Practical Design Issues for PFC Circuits

James P. Noon and Dhaval Dalal

Unitrode Corporation, 7 Continental Blvd., Merrimack, NH-03054.
Phone : (603)429-8547.Fax : (603)424-3460.
E-mail : noon@uicc.com,dalal@uicc.com

-
Abstract Many difficult design issues are faced by
designers trying to optimize the performance of boost PFC
circuits. This paper addresses common design challenges and
provides analytical techniques for developing practical
solutions. The issues covered include line filtering, loop
compensation alternatives, input voltage feedforward,
protection circuits, and synchronization.

I. INTRODUCTION

The harmonic reduction requirements imposed by

regulatory agencies (IEC 1000-3-2) have accelerated interest
in active power factor corrected preregulators for switching
power supplies. Many new topologies have been discussed in
recent literature for achieving the required power factor
correction. Some of the newer techniques are promising for
the long term objectives of cost reduction and performance Figure 1 Average Current Mode PFC Boost Converter
enhancements. However, the majority of the PFC circuit
distortion. Below are some of the common causes of current
implementations in the industry are centered around a boost
distortion.
preregulator with average current mode control using
commonly available monolithic control ICs (Fig. 1). General
operation of the boost preregulator is well understood and A. Noise
average current mode control has been described in detail in
the existing literature [1,2]. However, design of the power As with all switching circuits, good layout and noise
factor corrected boost preregulator is far from reduction are critical for proper circuit operation. Early
straightforward and the designer is faced with many design generations of average current mode controllers had a
limited bandwidth current loop error amplifier. This had the
issues which impact the ultimate performance of the
converter. Unfortunately, there is a lack of sufficient effect of attenuating noise in the current loop. In some
respects, these circuits were a little more forgiving.
reference material that addresses these practical issues and
However, the limited bandwidth can lead to cross-over
the designer is forced to resort to empirical methods or
develop homegrown analytical approaches to these problems. distortion since the current loop needs to follow a rapidly
changing waveform. Higher bandwidth error amplifiers
The aim of this paper is to collectively present these issues
allow the current loop to track better but they are more
along with analytical approaches for solving them.
Interrelationships between certain design choices are susceptible to noise. It is always better to eliminate noise
highlighted and the trade-offs are quantified where with proper layout than to try and filter it later. When
appropriate. filtering is needed, the physical as well as electrical location
of filtering capacitors is critical.
11. LINECURRENT DISTORTION
Whenever possible, ground planes should be used. As a
Distortion in the input current waveform can be caused by minimum, running ground around and under the IC is
many different factors. Where the distortion is occurring recommended. Bypass capacitors should be placed as close
within the line cycle can often point to the cause of the to the IC as possible. A few inches of trace can add as much
as 25nH of inductance between the capacitor and the pin,

0-7803-3704-2/97 $10.00 0 1 997 IEEE 51

 Rsense
Amplifier input offset voltage will also contribute to
B
distortion at the zero crossings of the line. The distortion
occurs here since this is where the voltage on the sense
resistor is at its minimum. The offset voltage mainly
contributes to distortion at light load. This effect can be
reduced by using a larger full scale voltage on the sense
I Current WA
resistor. This will cause the ratio of offset voltage to current
signal to be smaller. However, this will only lower the
power level at which the problem occurs. Matching input
resistors will also help to cancel input offset currents which
Figure 2 Current error amplifier configuration
contribute to the input error.
reducing the effectiveness of the capacitor. The ground
connection of bypass capacitors should also be as close to the C. Input Filter
IC ground as possible.
In order to attenuate the high frequency ripple and noise
Referring to Figure 2, it is clear that any noise at node A generated by the switching converter an input filter is usually
will be attenuated by the error amplifier noise filter pole. needed. The requirement of high power factor places a limit
The gain from node B to the output of the error amplifier on the maximum capacitance that can be placed across the
however, is 1+ Zf/Zi. So, the noise will not be attenuated by line. The inductor is sized to attenuate high frequency
the error amplifier. It is important then, to add filtering at switching and therefore rarely causes a phase shift at the line
the appropriate place. Adding capacitance at the + input of frequency. The maximum capacitance is a function of how
the current amplifier will help attenuate noise and effectively much phase shift that can be tolerated.
reduce the high frequency gain of the amplifier from that
node. The impedances at each amplifier input should be
cm,, =- I *tan0
kept approximately equal, otherwise the CMRR of the O*V
amplifier will be reduced. Again, the ground connection of
this capacitor should be to the IC ground pin or at least to Where o is 2*n* (the line frequency), I is the rms line
the ground plane around the IC.
current, V is the line voltage, and 8 is the phase angle.
Placing too large of a capacitor on the dc side of the
Usually, the best place to ground the capacitor is directly at
bridge rectifier must also be avoided. At light load
the IC ground. Connecting a bypass capacitor to a noisy part
conditions around the zero crossing of the line, the boost
of ground will actually make the problem worse, since this
converter doesn’t need to draw much current. The capacitor
will couple the noise directly into the IC pin. The exception
can then supply all the energy needed to support the load
to this is power stage filtering where keeping the circulating
without drawing any current from the line. This leads to flat
current loops as small as possible is most important. For
spots around the zero crossings of the line current.
example, it is common to place a high frequency, low ESR,
low ESL capacitor in parallel with the bulk output capacitor. Another cause of line current distortion is interaction of
This high frequency capacitor should be connected as close
the input filter andor the ac source impedance with the
as possible to the cathode of the boost diode and returned to
power converter 13, 41 . This distortion usually manifests
the source of the MOSFET. In addition, gate drive
itself as a high frequency oscillation at the mid to peak of the
connections should also be as short as possible. These
line. The instability is similar to what is seen with dc-dc
connections see very high di/dt and running separate drive
converters [5] and occurs when the impedance of the filter
and return traces for the gate drive can reduce noise.
(or ac source ) approaches the input impedance of the PFC
Keeping power ground separate from signal ground will help
converter. Typically the ac source has a much lower
control noise.
impedance than the converter. However, the PFC converter
looks like a negative impedance below 60 Hz so the source
The boost diode can also be a source of noise in the circuit.
must have a lower positive impedance at frequencies below
Choosing a diode with soft recovery characteristics can
this.
minimize the noise associated with the reverse recovery of
the diode.
An interaction with the output impedance of the input
filter and the input impedance of the converter will usually
B. Amplifier Offset Voltage
occur at much higher frequencies than the line. Proper

52
damping of the input filter will prevent its output impedance larger than necessary. Near zero crossings, the current
from interacting with the PFC converter’s input impedance drawn from the line is mainly limited by the current slewing
[6, 7, 81. The key is to keep the output impedance of the in the inductor.
input filter much lower than the input impedance of the
converter. E. Duty Cycle Limitations

In most PFC circuits there are practical limitations on

duty cycle range. These limitations have effects on different
An easy way of determining if a potential problem exists portions of the line cycle. Maximum duty cycle (D)
is to use PSPICE (or equivalent) to plot the impedances of limitations will show up as distortion around the zero
interest. Another easy way to determine if a problem exists is crossings of the line. If the duty cycle commanded is greater
to look at the current loop gain. An average model of the than the controller is capable of, the line current will be
Iimited and the current waveform will linearly move through
PFC stage ,as presented in [9] lends itself to this quite easily.
the zero crossing until the line voltage is such that a lower
Although plotting the current loop won’t directly revel how
much margin is in the design, looking at the current loop duty cycle is commanded. The current will then continue on
gain either by simulation or actually measuring it, will reveal a sinusoidal path.
if there is an interaction problem. Filter interaction with the
converter will show up as peaking (a complex pole pair will Another area where maximum duty cycle comes into play
exist) in the current loop. The peaking will occur at the is when current sensing is done with current sense
frequency where the impedances cross. If peaking is seen, transformers. If the control IC is capable of duty cycles of
about 90% and greater, transformer reset needs to be
further investigation of the impedances is required.
considered. Obviously no transformer can be operated with
D. Current Loop Design 100% duty cycle. If the IC is capable of achieving a D
greater than the transformer can support, the usual solution
Several excellent references exist on current loop design is to clamp the duty cycle below the onset of saturation. This
[9,10]. No attempt will be made to review them, however a can usually be implemented with a clamp on the output of
couple of general observations will be made. While it is true the current error amplifier.
the current loop’s job is to track a reference waveform (IMO)
The minimum duty cycle limitation can cause distortion at
whose fundamental frequency is 120Hz, the bandwidth of the
the peaks of the line. All controllers will allow 0% duty
current loop obviously needs to be much greater than that.
The reference signal has a high dv/dt (corresponding to the cycle, but there can often be a discontinuity between 0 and 2-
current di/dt), around the zero crossings of the line. 3%, due to propagation delays in the PWM circuitry, and is
Therefore the loop needs gain at frequencies corresponding often exacerbated by noise coupling in to the PWM
to the higher order Fourier coefficients needed to recreate the comparitor. The duty cycle required at any line voltage can
reference waveform. This implies high bandwidth for the be found by solving the boost converter dc transfer function
current loop. For a 50 - 60Hz input frequency, a l0kHz for D.
current loop bandwidth is usually adequate. This is easily
achieved with switching frequencies above SOkHz. One
thing to keep in mind is that the converter enters the
discontinuous conduction mode (DCM) around the line
crossings, even with high loads. A converter operating in A possible solution to reduce distortion due to minimum
DCM has reduced loop gain, since the power stage gain controllable duty cycle limitations is to raise the nominal
reduces. The lower loop gain lowers the bandwidth of the output voltage. Unfortunately this is usually unacceptable
converter and therefore can make it more difficult to track due to the output capacitor voltage rating, since considerable
the reference waveform. This is another reason for reduced cost savings can be achieved if 400V capacitors can be used.
performance under light load conditions. Another solution is to lower the switching frequency. The
minimum fixed ON time will be a smaller percent of the
The solution to the current tracking issue is to keep the duty cycle at a lower switching frequency.
current loop bandwidth as high as possible. As pointed out
in [9] operating the current loop with less than the typical 45 E. Quantifying Distortion
degrees of phase margin is quite acceptable and can result in
improved performance. Large signal behavior must also be Although there are many sources of error conspiring to
considered. In particular, the boost inductor should not be cause line distortion, the actual harmonic currents present in

53
a distorted waveform will normally still be well below the good references exist on voltage loop compensation
requirement. This is especially true of distortion around the[10,12,13]. There are some trade-offs inherent in the voltage
zero crossings, due to the fact that the energy at the zero loop design that are particular to PFC applications. The
fundamental requirement of power balance on the line
crossings is relatively low compared to the rest of the period.
frequency time scale within the PFC circuit requires that the
Although it is true that discontinuities in the waveform cause
high order harmonics, these harmonics can be low energy. voltage loop’s bandwidth must be less than the line
The waveform in Fig. 3 was created and analyzed using frequency (actually less than 1/2 the line frequency). If not,
MATHCAD, and the THD calculated. This is relatively the voltage loop will distort the line current in order to
easily done by using the relationship between power factor regulate the output voltage. This creates a trade-off between
and THD. Average and apparent power can be calculated by power factor and transient response.
multiplying the current waveform with a pure sinusoidal Since the loop bandwidth is low to begin with, it is
voltage waveform. Average power (P) is the instantaneous normally advised to avoid integral Compensation due to the
further reduction in transient response that the relatively
product of the voltage and current averaged over a line cycle,
while apparent power (VA) is the product of the RMS large feedback capacitor will cause. The large feedback
current and voltages. Power factor (PF) is given by the ratiocapacitor required for integral compensation will limit the
PNA. THD can be related to PF by [ 1 11: slew rate of the error amplifier. This is especially
troublesome at start up when the poor transient response can
cause a large overvoltage condition. The dc regulation of the
(4) output voltage is proportional to the loop gain. With the
voltage loop gain set relatively low, the output voltage will
vary widely with line and load. Since the load of a PFC
An alternate approach is to actually calculate the Fourier
circuit is typically another converter, dc regulation is
coefficients of the waveform and the THD by:
normally not an issue, and start up transient response can be
more of a concern (due to the voltage stress on the output
capacitors).

However, in some applications where the downstream

THD=KF converter is optimized for a narrow input voltage range or
when maximum hold up time is required, dc regulation is
The first approach has the advantage of simplicity and fast more of an issue. Additionally, some PFC controllers
computation times. For the example waveform in Fig. 3 the employ a transconductance type amplifier. This is often
THD is 8%. Again this is an extreme waveshape which done so that multiple functions, such as over voltage
would still meet most requirements. detection, can be incorporated on one IC pin. The
traditional voltage type error amplifier precludes this since
in a closed loop system the Vsense pin is not proportional to
111. VOLTAGE LOOP COMPENSATION Vout. A transconductance amplifier’s sense pin gives a true
measure of output voltage whether the loop is in regulation
As with current loop design and compensation, several or not. However, transconductance amplifiers are
compensated by connecting an impedance between the
amplifier’s output and ground. Usually the amplifier’s
output current capability is insufficient to drive a resistive
load unless the desired gain is very high. This implies
capacitive loading and hence integral gain. In both cases
then (transconductance amplifier or needing tighter dc
regulation) integral compensation can be used. Integral
compensation will of course provide zero dc error. However,
since the power stage has a single pole roll-off and the
integrator adds another 90 degrees of phase shift at low
frequency, a zero is needed before the loop cross-over
frequency. Since a zero in the compensation network
0 0.2 0.4 0.6 0.8 becomes a pole in the closed loop gain, this zero will
t
become the dominant pole in the system and placing this
Figure 3 Line current with cross over distortion zero as high as possible in frequency will improve the

54
transient response. Since the loop has such poor bandwidth, switching cycle depends on the status of the switches Q1 and
any improvement is welcome. Q2 and is shown in Fig. 5 . It can be seen that the greatest
ripple current cancellation is achieved when the overlap of
Previous design criteria for the voltage loop stressed Q1 off-time and Q2 on-time is maximized. For an arbitrary
reduction of the 120Hz ripple component being fed back to waveform shown in Fig. 5, the capacitor current RMS value
the multiplier [lo]. This is due to the fact that the ripple at is given by:
the output of the voltage error amplifier is a major
contributor to 3rd order harmonics in the line current.
However, in some cases some increased 3rd order harmonic
distortion can be tolerated and traded-off for improvements
in transient response. Alternatively, even if 3rd order
harmonic reduction is the main criteria, improvements in
transient response can be achieved when using integral where iACis the input inductor current at a given instant in
compensation. For example, one alternative is to first select the line cycle (and can be assumed to be constant for a
the frequency to cross-over the voltage loop (10 - 15Hz) and switching cycle), IL is the reflected output inductor current,
place the zero of the compensation network at that T, is the switching period and tl,t2,t3,t4 are as shown in Fig.
frequency. This will give 45" of phase margin. The second 5.
pole frequency can then be placed either at lOOHz plus, if
3rd order harmonic reduction is adequate, or slightly lower From (6), it is clear that IC-RMSis minimized when tl and
to further attenuate the 120Hz ripple. The lower the pole is t3 are maximized relative to t2 and t4. One method of
placed, the greater the 120Hz attenuation, and the lower the achieving this is to synchronize the turn-on of the boost
phase margin, this will tend to speed up the transient diode (Dl) with the turn-on of 42. If D1 conducts longer
response while increasing the overshoot. Another alternative than Q2, t4 is eliminated and if Q2 conducts longer than D 1 ,
is lo have the cross over frequency symmetrically between t2 is eliminated. This approach implies that the boost
the pole and zero frequencies. Keeping the distance about converter's leading edge is pulse width modulated while the
6:l is a good trade-off between 120Hz attenuation, and forward converter is modulated with traditional trailing edge
transient response. This method can give a little better PWM. To see the effect of ripple reduction achieved in a
transient response for the same attenuation. The point is you PFC circuit, (6) can be extended to cover half a line cycle
can trade off response using similar techniques as typically with instantaneous values of iAC and tl-t4 computed as the
used when designing voltage loops, with the added input voltage varies. IL and the duty cycle of Q2, D(Q2), can
specification being 3rd order harmonic reduction. be assumed to be constant for all practical purposes. The
results of such computations for a 200W power system with
IV. SYNCHRONIZATION
St14+tz++t3+t4 3-
For a power system where the PFC boost converter is
followed by a DC-DC converter stage, there are benefits to
synchronizing the two converters. In addition to the usual
advantages such as noise reduction and stability, proper
42 j
synchronization can significantly reduce the ripple currents
in the boost circuit's output capacitor. Fig. 4 helps illustrate
the impact of proper synchronization by showing a PFC
boost converter together with simplified input stage of a . .

forward converter. The capacitor current during a single

i Q 2 r 1L - 3
iQ2 j
1

Figure 5 Capacitor current for arbitrary overlap of conduction

Figure 4 Simplified representation of a 2-stage PFC power
system interval

55
 TABLE 1. EFFECTS ON BWST CAPACITOR
OF SYNCHROMZA~ON CURRENT a proportional representation of input voltage and is given by
I Vin= 85V I Vin = 1 2 0 ~ I Vin= 240V 1
nm?\
"\Y'I
I
II -
01/02
~
DUO2
1
I 0-~
1/02 D1/02
I
I 0-1 / 0-2 Dl102 I
0.35 I 1.491A 0.835A I 1.341A 0.663A I 1.024A 0.731A (7)
0.45 I 1,432A 0.93A I 1.276A 0.664A I 0.897A 0.614A
a VBsT of 385V are summarized in Table I. The table
compares the IC-RMSfor Dl/Q2 synchronization as described During the next half cycle, Vcms is converted into a digital
above vs. the same for the other extreme of synchronizing word and processed further. Crms is then discharged to be
the turn-ons of Q1 and Q2 . ready for integration of the input voltage again for the next
cycle. Thus, the dynamic response of this scheme is much
Table I illustrates that the boost capacitor ripple current improved (60 Hz bandwidth vs. 10 Hz typical for the 2-pole
can be reduced by about 50% at nominal line and about 30% LPF). It also minimizes the ripple current (ideally to zero)
at high line with the synchronization scheme described because of the digital sampling scheme. This novel scheme
above. The output capacitance value can be significantly lends itself well to integration in a logic-dense BCDMOS
reduced if the ripple current is limited or the capacitor life process and is incorporated in some of the recently
can be increased as a result. In cost sensitive designs where introduced PFC controllers[ 151. The improved feedforward
hold-up time is not critical, this is a significant advantage. performance can be translated into both higher voltage loop
bandwidth and lower input current THD.
An alternative method of synchronization to achieve the
same ripple reduction is to synchronize the turn-on of Q1 to
the turn-off of 42. While this method yields almost identical VI. PROTECTION
CIRCUITS
ripple reduction and maintains trailing edge modulation on
both converters, the synchronization is much more difficult The boost topology used in PFC circuits presents a unique
to achieve and the circuit can become susceptible to noise as problem for protecting the circuit components during start-
the synchronizing edge itself is being modulated. up. The combination of large output capacitance and a
relatively small (high frequency) input inductor presents a
very low impedance path during start-up. This path can not
V. INPUT
VOLTAGE
FEEDFORWARD be interrupted by turning the boost switch off. A high
current surge can lead to saturation of the boost inductor and
Input RMS voltage sensing and feedforward is performed damage the high speed diode. A common practice is to put a
in many PFC circuits in order to achieve a constant loop gain bypass.diode from input to output which acts only during
over varying input voltages and to provide input voltage start-up and input voltage transients.
correction to the line current. The average value of the
rectified AC input is computed by low pass filtering (LPF) The inrush situation can be complicated if the boost
and then squared before being used as a divider term in switch is allowed to turn on during start-up. A peak current
deriving the current programming signal as shown in Fig. 1. limiting circuit which directly shuts off the switch (without
Voltage feedforward results i n voltage loop bandwidth relying on the average current loop) when a preset threshold
optimization and a constant power limiting function by is crossed is essential. The average loop does not help
making the output of the voltage error amplifier proportional
to the output power [10,161.

Traditionally, the filtering of Vin is performed using a

passive 2-pole filter. It has been shown that a trade-off
between a fast response to input voltage dynamics and
attenuation of second harmonic contribution from the
feedforward path is forced with this approach [lo]. The
passive filter also slows the recovery from a line dropout due
to slow charging of the capacitors. One method to get
around this problem is to offset the harmonic contributions
to the current reference signal from the input feedforward
and voltage feedback loop [14]. Another approach for
improved performance is shown in Fig. 6. With this
approach, the sinusoidal reference input (IAC) current is Figure 6 Novel scheme for input voltage RMS detection
integrated over a half cycle and held. This voltage (VC,,,~) is

56
during start-up because the feedback capacitor needs time to
charge before the loop is effective. In essence, this is a large
signal phenomenon and the effectiveness of the average
current loop to control currents during small perturbations is
irrelevant.

Many monolithic PFC controllers available today provide

the peak current limiting feature. If this feature is not
available, it is often desirable to add external circuitry to
compare the instantaneous inductor/switch current to a set
threshold and terminate the gate drive signal when the
threshold is crossed. Fig. 7 provides an example of how the
peak current limiting can be achieved with a simple 8-pin
controller (UC3853) which does not have peak current Figure 8 Peak current limiting circuit
limiting. R1 and R2 set the threshold for Vsense. When the
threshold is crossed, Q1 turns ON, which turns ON Q2. As a Another important protection feature is the power limiting
result, the FB pin of UC3853 is pulled up and the function. With average current mode control and input RMS
overvoltage comparator is tripped, leading to drive pulse voltage feedforward implementation, the output of the
termination. The current sensing circuit should have good voltage error amplifier (V,,) is a reasonably accurate
layout and short loops in order to prevent the switching noise representation of the output power level. The current
from triggering the peak current limiting circuit reference value iMOis -
inadvertently. The peak threshold can be set much higher
than the nominal maximum current because it is necessary
only during start-up.
' FF
Overvoltage protection is another essential feature in PFC
circuits particularly if integral voltage loop compensation is where K, is the multiplier constant, iAc is the current
used. If the minimum controllable duty cycle is not proportional to the rectified input voltage and VFF is the
sufficiently low, the output capacitor can be overcharged feedforward voltage. It can be shown using (8) that VEA
under light or no load conditions. The slow response of the remains fixed for a given load (power) irrespective of the
voltage feedback loop mandates a faster shutdown path when line voltage variations. Since most PFC controller error
the output voltage exceeds a certain value. The penalty for amplifiers have output voltage clamping, this feature can be
not having the overvoltage protection or having a high used to limit the maximum power drawn for a given design.
threshold level is a higher stress level on components (both If the feedforward is not used, the inherent power limiting
in the boost stage and follow-on converters) and the function is lost. Without power limiting, the circuit can draw
associated cost and loss of efficiency. On the other hand, a high power from the line under fault conditions. Since peak
low overvoltage threshold forces a tighter regulation of the current limiting must be set up for the low line condition,
boost voltage and necessitates a high output capacitance
value.
Vbias
For universal input voltage operation, the output of the
boost voltage has to be above the peak of the maximum input
voltage (-375V). With the minimum duty cycle limitations
inherent to practical circuits, the actual output voltage has to
be above 385-390V for a 3-4% minimum duty cycle. Since
PFC circuits have a high second harmonic ripple on the
output voltage, the actual output peaks can easily exceed
400V. If an output capacitor rated at 450V is to be used, the
overvoltage circuit should have a tight tolerance.

Figure 7 Bias voltage generation

thus the power drawn can be 3x nominal power at high line.

57
 The multiplier limit levels can also be exploited to achieve ACKNOWLEDGMENT
power scaling when a line voltage brown out occurs. In
many commercially available PFC controllers (e.g. The authors would like to thank John O’Connor of
3854A/B), the multiplier output current (IMo) is limited to a Unitrode for his helpful discussions on the practical aspects
fixed multiple of IAC. If the multiplier is set-up so that IMOis of PFC circuit design. We would also like to thank Laszlo
close to this limit at low line full load operating point, the Balogh of Unitrode for his helpful suggestions.
IMo will hit the above mentioned limit under brownout
conditions[ 161. Below that voltage, the input current
REFERENCES
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reached a certain level, the load on the PFC stage is November 1993
minimized and prevents starting hiccups in the bias circuit. [9] C. Zhou and M.M. Jovanovic’, “Design Trade-offs in
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[11]J.G. Kassakian, M.F. Schlect, G.C. Verghese, Principles of
The under-voltage lockout levels of the two controllers must
Power Electronics, (Addison-Wesley, 1991)
be similar for this scheme to work. Low start-up and [12] J.B. Williams “Design of Feedback Loop in Unity Power
operating currents on the PWM controllers (as available with Factor AC to DC Converters,” PESC 1989
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September I989
VIII. SUMMARY [14] A. Abramovitch and S. Ben-Yaakov, “Analysis and Design of
the Feedback and Feedforward Paths of Active Power Factor
Some of the more common issues involving PFC circuits Correction Systems for Minimum Input Current Distortion,” PESC
have been discussed. Factors contributing to line current 1995
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[ 161 L. Balogh, Unitrode-UC3854AE3 and UC3855AA3 Provide
converters, providing over stress protection and biasing have
Power Limiting with Sinusoidal Input Current for PFC Front
been identified. Where possible, solutions to these issues Ends,” Design Note DN-66, Unitrode Corporation
have been suggested. [I71 W. Andreycak, “Optimizing Performance in UC3854 Power
Factor Correction Applications Design Note DN-39E, Unitrode
”

Corporation

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