CMOS, 330 MHz

Triple 10-Bit high Speed Video DAC

ADV7123
FEATURES FUNCTIONAL BLOCK DIAGRAM
VAA
330 MSPS throughput rate
Triple 10-bit digital-to-analog converters (DACs)
BLANK BLANK AND
SFDR SYNC LOGIC
SYNC
−70 dB at fCLK = 50 MHz; fOUT = 1 MHz
−53 dB at fCLK = 140 MHz; fOUT = 40 MHz DATA IOR
R9 TO R0 10 REGISTER 10 DAC
RS-343A-/RS-170-compatible output IOR
Complementary outputs IOG
DATA
DAC output current range: 2.0 mA to 26.5 mA G9 TO G0 10 REGISTER 10 DAC
IOG
TTL-compatible inputs
IOB
Internal reference (1.235 V) B9 TO B0 10
DATA
10 DAC
REGISTER
IOB
Single-supply 5 V/3.3 V operation
48-lead LQFP package POWER-DOWN VOLTAGE
PSAVE MODE REFERENCE VREF
Low power dissipation (30 mW minimum @ 3 V) CIRCUIT
Low power standby mode (6 mW typical @ 3 V) CLOCK
ADV7123

00215-001
Industrial temperature range (−40°C to +85°C)
GND RSET COMP
Pb-free (lead-free) package
Figure 1.
APPLICATIONS
Digital video systems (1600 × 1200 @ 100 Hz)
High resolution color graphics
Digital radio modulation
Image processing
Instrumentation
Video signal reconstruction

GENERAL DESCRIPTION
The ADV7123 (ADV®) is a triple high speed, digital-to-analog The ADV7123 is fabricated in a 5 V CMOS process. Its
converter on a single monolithic chip. It consists of three high monolithic CMOS construction ensures greater functionality
speed, 10-bit, video DACs with complementary outputs, a with lower power dissipation. The ADV7123 is available in a
standard TTL input interface, and a high impedance, analog 48-lead LQFP package.
output current source.
PRODUCT HIGHLIGHTS
The ADV7123 has three separate 10-bit-wide input ports. A 1. 330 MSPS throughput.
single 5 V/3.3 V power supply and clock are all that are required 2. Guaranteed monotonic to 10 bits.
to make the part functional. The ADV7123 has additional video 3. Compatible with a wide variety of high resolution color
control signals, composite SYNC and BLANK. graphics systems, including RS-343A and RS-170.
The ADV7123 also has a power save mode.

ADV is a registered trademark of Analog Devices, Inc.

Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com
Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved.
ADV7123

TABLE OF CONTENTS
Features .............................................................................................. 1 3 V Typical Performance Characteristics ................................ 14
Applications ....................................................................................... 1 Terminology .................................................................................... 16
Functional Block Diagram .............................................................. 1 Circuit Description and Operation .............................................. 17
General Description ......................................................................... 1 Digital Inputs .............................................................................. 17
Product Highlights ........................................................................... 1 Clock Input.................................................................................. 17
Revision History ............................................................................... 2 Video Synchronization and Control ........................................ 18
Specifications..................................................................................... 3 Reference Input........................................................................... 18
5 V Specifications ......................................................................... 3 DACs ............................................................................................ 18
3.3 V Specifications ...................................................................... 4 Analog Outputs .......................................................................... 18
5 V Dynamic Specifications ........................................................ 5 Gray Scale Operation ................................................................. 19
3.3 V Dynamic Specifications ..................................................... 6 Video Output Buffers................................................................. 19
5 V Timing Specifications ........................................................... 7 PCB Layout Considerations ...................................................... 19
3.3 V Timing Specifications ........................................................ 8 Digital Signal Interconnect ....................................................... 19
Absolute Maximum Ratings............................................................ 9 Analog Signal Interconnect....................................................... 20
ESD Caution .................................................................................. 9 Outline Dimensions ....................................................................... 21
Pin Configuration and Function Descriptions ........................... 10 Ordering Guide .......................................................................... 21
Typical Performance Characteristics ........................................... 12
5 V Typical Performance Characteristics ................................ 12

REVISION HISTORY
3/09—Rev. B to Rev. C 10/02—Rev. A to Rev. B
Updated Format .................................................................. Universal Change in Title...................................................................................1
Changes to Features Section............................................................ 1 Change to Feature..............................................................................1
Changes to Table 5 ............................................................................ 7 Change to Product Highlights .........................................................1
Changes to Table 6 ............................................................................ 8 Change Specifications .......................................................................3
Changes to Table 8 .......................................................................... 10 Change to Pin Function Descriptions ......................................... 10
Changed fCLOCK to fCLK ..................................................................... 12 Change to Reference Input section .............................................. 18
Changes to Figure 6, Figure 7, and Figure 8................................ 12 Change to Figure 28 ....................................................................... 22
Changes to Figure 13 and Figure 17 ............................................. 14 Updated Outline Dimensions ....................................................... 23
Deleted Ground Planes Section, Power Planes Section, and Change to Ordering Guide............................................................ 23
Supply Decoupling Section ........................................................... 15
Changes to Figure 23 ...................................................................... 17
Changes to Table 9, Analog Outputs Section, Figure 24, and
Figure 25 .......................................................................................... 18
Changes to Video Output Buffers Section and PCB Layout
Considerations Section .................................................................. 19
Changes to Analog Signal Interconnect Section and
Figure 28 .......................................................................................... 20
Updated Outline Dimensions ....................................................... 21
Changes to Ordering Guide .......................................................... 21

Rev. C | Page 2 of 24
 ADV7123

SPECIFICATIONS
5 V SPECIFICATIONS
VAA = 5 V ± 5%, VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX,1 unless otherwise noted, TJ MAX = 110°C.

Table 1.
Parameter Min Typ Max Unit Test Conditions1
STATIC PERFORMANCE
Resolution (Each DAC) 10 Bits
Integral Nonlinearity (BSL) −1 ±0.4 +1 LSB
Differential Nonlinearity −1 ±0.25 +1 LSB Guaranteed Monotonic
DIGITAL AND CONTROL INPUTS
Input High Voltage, VIH 2 V
Input Low Voltage, VIL 0.8 V
Input Current, IIN −1 +1 μA VIN = 0.0 V or VDD
PSAVE Pull-Up Current 20 μA
Input Capacitance, CIN 10 pF
ANALOG OUTPUTS
Output Current 2.0 26.5 mA Green DAC, SYNC = high
2.0 18.5 mA RGB DAC, SYNC = low
DAC-to-DAC Matching 1.0 5 %
Output Compliance Range, VOC 0 1.4 V
Output Impedance, ROUT 100 kΩ
Output Capacitance, COUT 10 pF IOUT = 0 mA
Offset Error −0.025 +0.025 % FSR Tested with DAC output = 0 V
Gain Error2 −5.0 +5.0 % FSR FSR = 17.62 mA
VOLTAGE REFERENCE, EXTERNAL AND
INTERNAL
Reference Range, VREF 1.12 1.235 1.35 V
POWER DISSIPATION
Digital Supply Current3 3.4 9 mA fCLK = 50 MHz
10.5 15 mA fCLK = 140 MHz
18 25 mA fCLK = 240 MHz
Analog Supply Current 67 72 mA RSET = 560 Ω
8 mA RSET = 4933 Ω
Standby Supply Current4 2.1 5.0 mA PSAVE = low, digital, and control inputs at VDD
Power Supply Rejection Ratio 0.1 0.5 %/%
1
Temperature range TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz and 330 MHz.
2
Gain error = {(Measured (FSC)/Ideal (FSC) − 1) × 100}, where Ideal = VREF /RSET × K × (0x3FFH) and K = 7.9896.
3
Digital supply is measured with a continuous clock that has data input corresponding to a ramp pattern and with an input level at 0 V and VDD.
4
These maximum/minimum specifications are guaranteed by characterization to be over the 4.75 V to 5.25 V range.

Rev. C | Page 3 of 24
ADV7123
3.3 V SPECIFICATIONS
VAA = 3.0 V to 3.6 V, VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX,1 unless otherwise noted, TJ MAX = 110°C.

Table 2.
Parameter2 Min Typ Max Unit Test Conditions1
STATIC PERFORMANCE
Resolution (Each DAC) 10 Bits RSET = 680 Ω
Integral Nonlinearity (BSL) −1 +0.5 +1 LSB RSET = 680 Ω
Differential Nonlinearity −1 +0.25 +1 LSB RSET = 680 Ω
DIGITAL AND CONTROL INPUTS
Input High Voltage, VIH 2.0 V
Input Low Voltage, VIL 0.8 V
Input Current, IIN −1 +1 μA VIN = 0.0 V or VDD
PSAVE Pull-Up Current 20 μA
Input Capacitance, CIN 10 pF
ANALOG OUTPUTS
Output Current 2.0 26.5 mA Green DAC, SYNC = high
2.0 18.5 mA RGB DAC, SYNC = low
DAC-to-DAC Matching 1.0 %
Output Compliance Range, VOC 0 1.4 V
Output Impedance, ROUT 70 kΩ
Output Capacitance, COUT 10 pF
Offset Error 0 0 % FSR Tested with DAC output = 0 V
Gain Error3 0 % FSR FSR = 17.62 mA
VOLTAGE REFERENCE, EXTERNAL
Reference Range, VREF 1.12 1.235 1.35 V
VOLTAGE REFERENCE, INTERNAL
Voltage Reference, VREF 1.235 V
POWER DISSIPATION
Digital Supply Current4 2.2 5.0 mA fCLK = 50 MHz
6.5 12.0 mA fCLK = 140 MHz
11 15 mA fCLK = 240 MHz
16 mA fCLK = 330 MHz
Analog Supply Current 67 72 mA RSET = 560 Ω
8 mA RSET = 4933 Ω
Standby Supply Current 2.1 5.0 mA PSAVE = low, digital, and control inputs at VDD
Power Supply Rejection Ratio 0.1 0.5 %/%
1
Temperature range TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz and 330 MHz.
2
These maximum/minimum specifications are guaranteed by characterization to be over the 3.0 V to 3.6 V range.
3
Gain error = {(Measured (FSC)/Ideal (FSC) − 1) × 100}, where Ideal = VREF/RSET × K × (0x3FFH) and K = 7.9896.
4
Digital supply is measured with a continuous clock that has data input corresponding to a ramp pattern and with an input level at 0 V and VDD.

Rev. C | Page 4 of 24
 ADV7123
5 V DYNAMIC SPECIFICATIONS
VAA = 5 V ± 5%,1 VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications are TA = 25°C, unless otherwise noted, TJ MAX = 110°C.

Table 3.
Parameter1 Min Typ Max Unit
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist2
Single-Ended Output
fCLK = 50 MHz; fOUT = 1.00 MHz 67 dBc
fCLK = 50 MHz; fOUT = 2.51 MHz 67 dBc
fCLK = 50 MHz; fOUT = 5.04 MHz 63 dBc
fCLK = 50 MHz; fOUT = 20.2 MHz 55 dBc
fCLK = 100 MHz; fOUT = 2.51 MHz 62 dBc
fCLK = 100 MHz; fOUT = 5.04 MHz 60 dBc
fCLK = 100 MHz; fOUT = 20.2 MHz 54 dBc
fCLK = 100 MHz; fOUT = 40.4 MHz 48 dBc
fCLK = 140 MHz; fOUT = 2.51 MHz 57 dBc
fCLK = 140 MHz; fOUT = 5.04 MHz 58 dBc
fCLK = 140 MHz; fOUT = 20.2 MHz 52 dBc
fCLK = 140 MHz; fOUT = 40.4 MHz 41 dBc
Double-Ended Output
fCLK = 50 MHz; fOUT = 1.00 MHz 70 dBc
fCLK = 50 MHz; fOUT = 2.51 MHz 70 dBc
fCLK = 50 MHz; fOUT = 5.04 MHz 65 dBc
fCLK = 50 MHz; fOUT = 20.2 MHz 54 dBc
fCLK = 100 MHz; fOUT = 2.51 MHz 67 dBc
fCLK = 100 MHz; fOUT = 5.04 MHz 63 dBc
fCLK = 100 MHz; fOUT = 20.2 MHz 58 dBc
fCLK = 100 MHz; fOUT = 40.4 MHz 52 dBc
fCLK = 140 MHz; fOUT = 2.51 MHz 62 dBc
fCLK = 140 MHz; fOUT = 5.04 MHz 61 dBc
fCLK = 140 MHz; fOUT = 20.2 MHz 55 dBc
fCLK = 140 MHz; fOUT = 40.4 MHz 53 dBc
Spurious-Free Dynamic Range Within a Window
Single-Ended Output
fCLK = 50 MHz; fOUT = 1.00 MHz; 1 MHz Span 77 dBc
fCLK = 50 MHz; fOUT = 5.04 MHz; 2 MHz Span 73 dBc
fCLK = 140 MHz; fOUT = 5.04 MHz; 4 MHz Span 64 dBc
Double-Ended Output
fCLK = 50 MHz; fOUT = 1.00 MHz; 1 MHz Span 74 dBc
fCLK = 50 MHz; fOUT = 5.00 MHz; 2 MHz Span 73 dBc
fCLK = 140 MHz; fOUT = 5.00 MHz; 4 MHz Span 60 dBc
Total Harmonic Distortion
fCLK = 50 MHz; fOUT = 1.00 MHz
TA = 25°C 66 dBc
TMIN to TMAX 65 dBc
fCLK = 50 MHz; fOUT = 2.00 MHz 64 dBc
fCLK = 100 MHz; fOUT = 2.00 MHz 63 dBc
fCLK = 140 MHz; fOUT = 2.00 MHz 55 dBc

Rev. C | Page 5 of 24
ADV7123
Parameter1 Min Typ Max Unit
DAC PERFORMANCE
Glitch Impulse 10 pV-sec
DAC-to-DAC Crosstalk3 23 dB
Data Feedthrough4, 5 22 dB
Clock Feedthrough4, 5 33 dB
1
These maximum/minimum specifications are guaranteed by characterization over the 4.75 V to 5.25 V range.
2
Note that the ADV7123 exhibits high performance when operating with an internal voltage reference, VREF.
3
DAC-to-DAC crosstalk is measured by holding one DAC high while the other two are making low-to-high and high-to-low transitions.
4
Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough.
5
TTL input values are 0 V to 3 V, with input rise/fall times of −3 ns, measured from the 10% and 90% points. Timing reference points are 50% for inputs and outputs.

3.3 V DYNAMIC SPECIFICATIONS

VAA = 3.0 V to 3.6 V1, VREF = 1.235 V, RSET = 680 Ω, CL = 10 pF. All specifications are TA = 25°C, unless otherwise noted, TJ MAX = 110°C.

Table 4.
Parameter Min Typ Max Unit
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist2
Single-Ended Output
fCLK = 50 MHz; fOUT = 1.00 MHz 67 dBc
fCLK = 50 MHz; fOUT = 2.51 MHz 67 dBc
fCLK = 50 MHz; fOUT = 5.04 MHz 63 dBc
fCLK = 50 MHz; fOUT = 20.2 MHz 55 dBc
fCLK = 100 MHz; fOUT = 2.51 MHz 62 dBc
fCLK = 100 MHz; fOUT = 5.04 MHz 60 dBc
fCLK = 100 MHz; fOUT = 20.2 MHz 54 dBc
fCLK = 100 MHz; fOUT = 40.4 MHz 48 dBc
fCLK = 140 MHz; fOUT = 2.51 MHz 57 dBc
fCLK = 140 MHz; fOUT = 5.04 MHz 58 dBc
fCLK = 140 MHz; fOUT = 20.2 MHz 52 dBc
fCLK = 140 MHz; fOUT = 40.4 MHz 41 dBc
Double-Ended Output
fCLK = 50 MHz; fOUT = 1.00 MHz 70 dBc
fCLK = 50 MHz; fOUT = 2.51 MHz 70 dBc
fCLK = 50 MHz; fOUT = 5.04 MHz 65 dBc
fCLK = 50 MHz; fOUT = 20.2 MHz 54 dBc
fCLK = 100 MHz; fOUT = 2.51 MHz 67 dBc
fCLK = 100 MHz; fOUT = 5.04 MHz 63 dBc
fCLK = 100 MHz; fOUT = 20.2 MHz 58 dBc
fCLK = 100 MHz; fOUT = 40.4 MHz 52 dBc
fCLK = 140 MHz; fOUT = 2.51 MHz 62 dBc
fCLK = 140 MHz; fOUT = 5.04 MHz 61 dBc
fCLK = 140 MHz; fOUT = 20.2 MHz 55 dBc
fCLK = 140 MHz; fOUT = 40.4 MHz 53 dBc
Spurious-Free Dynamic Range Within a Window
Single-Ended Output
fCLK = 50 MHz; fOUT = 1.00 MHz; 1 MHz Span 77 dBc
fCLK = 50 MHz; fOUT = 5.04 MHz; 2 MHz Span 73 dBc
fCLK = 140 MHz; fOUT = 5.04 MHz; 4 MHz Span 64 dBc
Double-Ended Output
fCLK = 50 MHz; fOUT = 1.00 MHz; 1 MHz Span 74 dBc
fCLK = 50 MHz; fOUT = 5.00 MHz; 2 MHz Span 73 dBc
fCLK = 140 MHz; fOUT = 5.00 MHz; 4 MHz Span 60 dBc

Rev. C | Page 6 of 24
 ADV7123
Parameter Min Typ Max Unit
Total Harmonic Distortion
fCLK = 50 MHz; fOUT = 1.00 MHz
TA = 25°C 66 dBc
TMIN to TMAX 65 dBc
fCLK = 50 MHz; fOUT = 2.00 MHz 64 dBc
fCLK = 100 MHz; fOUT = 2.00 MHz 64 dBc
fCLK = 140 MHz; fOUT = 2.00 MHz 55 dBc
DAC PERFORMANCE
Glitch Impulse 10 pV-sec
DAC-to-DAC Crosstalk3 23 dB
Data Feedthrough4, 5 22 dB
Clock Feedthrough4, 5 33 dB
1
These maximum/minimum specifications are guaranteed by characterization over the 3.0 V to 3.6 V range.
2
Note that the ADV7123 exhibits high performance when operating with an internal voltage reference, VREF.
3
DAC-to-DAC crosstalk is measured by holding one DAC high while the other two are making low-to-high and high-to-low transitions.
4
Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough.
5
TTL input values are 0 V to 3 V, with input rise/fall times of −3 ns, measured at the 10% and 90% points. Timing reference points are 50% for inputs and outputs.

5 V TIMING SPECIFICATIONS
VAA = 5 V ± 5%,1 VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX,2 unless otherwise noted, TJ MAX = 110°C.

Table 5.
Parameter3 Symbol Min Typ Max Unit Conditions
ANALOG OUTPUTS
Analog Output Delay t6 5.5 ns
Analog Output Rise/Fall Time4 t7 1.0 ns
Analog Output Transition Time5 t8 15 ns
Analog Output Skew6 t9 1 2 ns
CLOCK CONTROL
CLOCK Frequency7 fCLK 0.5 50 MHz 50 MHz grade
0.5 140 MHz 140 MHz grade
0.5 240 MHz 240 MHz grade
Data and Control Setup t1 0.5 ns
Data and Control Hold t2 1.5 ns
CLOCK Period t3 4.17 ns
CLOCK Pulse Width High t4 1.875 ns fCLK_MAX = 240 MHz
CLOCK Pulse Width Low t5 1.875 ns fCLK_MAX = 240 MHz
CLOCK Pulse Width High t4 2.85 ns fCLK_MAX = 140 MHz
CLOCK Pulse Width Low t5 2.85 ns fCLK_MAX = 140 MHz
CLOCK Pulse Width High t4 8.0 ns fCLK_MAX = 50 MHz
CLOCK Pulse Width Low t5 8.0 ns fCLK_MAX = 50 MHz
Pipeline Delay6 tPD 1.0 1.0 1.0 Clock cycles
PSAVE Up Time6 t10 2 10 ns
1
These maximum and minimum specifications are guaranteed over this range.
2
Temperature range: TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz.
3
Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) 0 for both 5 V and 3.3 V supplies.
4
Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
5
Measured from 50% point of full-scale transition to 2% of final value.
6
Guaranteed by characterization.
7
fCLK maximum specification production tested at 125 MHz; 5 V limits specified here are guaranteed by characterization.

Rev. C | Page 7 of 24
ADV7123
3.3 V TIMING SPECIFICATIONS
VAA = 3.0 V to 3.6 V,1 VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX,2 unless otherwise noted, TJ MAX = 110°C.

Table 6.
Parameter3 Symbol Min Typ Max Unit Conditions
ANALOG OUTPUTS
Analog Output Delay t6 7.5 ns
Analog Output Rise/Fall Time4 t7 1.0 ns
Analog Output Transition Time5 t8 15 ns
Analog Output Skew6 t9 12 ns
CLOCK CONTROL
CLOCK Frequency7 fCLK 50 MHz 50 MHz grade
140 MHz 140 MHz grade
240 MHz 240 MHz grade
330 MHz 330 MHz grade
Data and Control Setup t1 0.2 ns
Data and Control Hold t2 1.5 ns
CLOCK Period t3 3 ns
CLOCK Pulse Width High6 t4 1.4 ns fCLK_MAX = 330 MHz
CLOCK Pulse Width Low6 t5 1.4 ns fCLK_MAX = 330 MHz
CLOCK Pulse Width High t4 1.875 ns fCLK_MAX = 240 MHz
CLOCK Pulse Width Low t5 1.875 ns fCLK_MAX = 240 MHz
CLOCK Pulse Width High t4 2.85 ns fCLK_MAX = 140 MHz
CLOCK Pulse Width Low t5 2.85 ns fCLK_MAX = 140 MHz
CLOCK Pulse Width High t4 8.0 ns fCLK_MAX = 50 MHz
CLOCK Pulse Width Low t5 8.0 ns fCLK_MAX = 50 MHz
Pipeline Delay6 tPD 1.0 1.0 1.0 Clock cycles
PSAVE Up Time6 t10 4 10 ns
1
These maximum and minimum specifications are guaranteed over this range.
2
Temperature range: TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz and 330 MHz.
3
Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) 0 for both 5 V and 3.3 V supplies.
4
Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
5
Measured from 50% point of full-scale transition to 2% of final value.
6
Guaranteed by characterization.
7
fCLK maximum specification production tested at 125 MHz; 5 V limits specified here are guaranteed by characterization.

t3

t4
t5

CLOCK
t2
DIGITAL INPUTS
(R9 TO R0, G9 TO G0, B9 TO B0,
SYNC, BLANK)
t1
t6
t8

ANALOG INPUTS
(IOR, IOR, IOG, IOG, IOB, IOB)
t7

NOTES
1. OUTPUT DELAY (t6) MEASURED FROM THE 50% POINT OF THE RISING EDGE OF CLOCK TO THE 50% POINT
OF FULL-SCALE TRANSITION.
2. OUTPUT RISE/FALL TIME (t7) MEASURED BETWEEN THE 10% AND 90% POINTS OF FULL-SCALE TRANSITION.
00215-002

3. TRANSITION TIME (t8) MEASURED FROM THE 50% POINT OF FULL-SCALE TRANSITION TO WITHIN 2% OF THE
FINAL OUTPUT VALUE.

Figure 2. Timing Diagram

Rev. C | Page 8 of 24
 ADV7123

ABSOLUTE MAXIMUM RATINGS

Table 7. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
Parameter Rating
rating only; functional operation of the device at these or any
VAA to GND 7V
other conditions above those indicated in the operational
Voltage on Any Digital Pin GND − 0.5 V to VAA + 0.5 V
section of this specification is not implied. Exposure to absolute
Ambient Operating Temperature (TA) −40°C to +85°C
maximum rating conditions for extended periods may affect
Storage Temperature (TS) −65°C to +150°C
device reliability.
Junction Temperature (TJ) 150°C
Lead Temperature (Soldering, 10 sec) 300°C
Vapor Phase Soldering (1 Minute) 220°C ESD CAUTION
IOUT to GND1 0 V to VAA
1
Analog output short circuit to any power supply or common GND can be of
an indefinite duration.

Rev. C | Page 9 of 24
ADV7123

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PSAVE
RSET
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
48 47 46 45 44 43 42 41 40 39 38 37

G0 1 36 VREF
PIN 1
G1 2 INDICATOR 35 COMP
G2 3 34 IOR
G3 4 33 IOR
G4 5 32 IOG
G5 6 ADV7123 31 IOG
G6 7 TOP VIEW 30 VAA
(Not to Scale)
G7 8 29 VAA
G8 9 28 IOB
G9 10 27 IOB
BLANK 11 26 GND
SYNC 12 25 GND

13 14 15 16 17 18 19 20 21 22 23 24

CLOCK
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
VAA

00215-003
Figure 3. Pin Configuration

Table 8. Pin Function Descriptions

Pin No. Mnemonic Description
1 to 10, G0 to G9, Red, Green, and Blue Pixel Data Inputs (TTL Compatible). Pixel data is latched on the rising edge of CLOCK. R0,
14 to 23, B0 to B9, G0, and B0 are the least significant data bits. Unused pixel data inputs should be connected to either the
39 to 48 R0 to R9 regular printed circuit board (PCB) power or ground plane.
11 BLANK Composite Blank Control Input (TTL Compatible). A Logic 0 on this control input drives the analog outputs,
IOR, IOB, and IOG, to the blanking level. The BLANK signal is latched on the rising edge of CLOCK. While
BLANK is a Logic 0, the R0 to R9, G0 to G9, and B0 to B9 pixel inputs are ignored.
12 SYNC Composite Sync Control Input (TTL Compatible). A Logic 0 on the SYNC input switches off a 40 IRE current
source. This is internally connected to the IOG analog output. SYNC does not override any other control or
data input; therefore, it should only be asserted during the blanking interval. SYNC is latched on the rising
edge of CLOCK. If sync information is not required on the green channel, the SYNC input should be tied to
Logic 0.
13, 29, 30 VAA Analog Power Supply (5 V ± 5%). All VAA pins on the ADV7123 must be connected.
24 CLOCK Clock Input (TTL Compatible). The rising edge of CLOCK latches the R0 to R9, G0 to G9, B0 to B9, SYNC, and
BLANK pixel and control inputs. It is typically the pixel clock rate of the video system. CLOCK should be driven
by a dedicated TTL buffer.
25, 26 GND Ground. All GND pins must be connected.
27, 31, 33 IOB, IOG, IOR Differential Red, Green, and Blue Current Outputs (High Impedance Current Sources). These RGB video
outputs are specified to directly drive RS-343A and RS-170 video levels into a doubly terminated 75 Ω load. If
the complementary outputs are not required, these outputs should be tied to ground.
28, 32, 34 IOB, IOG, IOR Red, Green, and Blue Current Outputs. These high impedance current sources are capable of directly driving a
doubly terminated 75 Ω coaxial cable. All three current outputs should have similar output loads whether or
not they are all being used.
35 COMP Compensation Pin. This is a compensation pin for the internal reference amplifier. A 0.1 μF ceramic capacitor
must be connected between COMP and VAA.
36 VREF Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).

Rev. C | Page 10 of 24
 ADV7123
Pin No. Mnemonic Description
37 RSET A resistor (RSET) connected between this pin and GND controls the magnitude of the full-scale video signal.
Note that the IRE relationships are maintained, regardless of the full-scale output current. For nominal video
levels into a doubly terminated 75 Ω load, RSET = 530 Ω. The relationship between RSET and the full-scale
output current on IOG (assuming ISYNC is connected to IOG) is given by:
RSET (Ω) = 11,445 × VREF (V)/IOG (mA)
The relationship between RSET and the full-scale output current on IOR, IOG, and IOB is given by:
IOG (mA) = 11,445 × VREF (V)/RSET (Ω) (SYNC being asserted)
IOR, IOB (mA) = 7989.6 × VREF (V)/RSET (Ω)
The equation for IOG is the same as that for IOR and IOB when SYNC is not being used, that is, SYNC tied
permanently low.
38 PSAVE Power Save Control Pin. Reduced power consumption is available on the ADV7123 when this pin is active.

Rev. C | Page 11 of 24
ADV7123

TYPICAL PERFORMANCE CHARACTERISTICS

5 V TYPICAL PERFORMANCE CHARACTERISTICS
VAA = 5 V, VREF = 1.235 V, IOUT = 17.62 mA, 50 Ω doubly terminated load, differential output loading, TA = 25°C, unless otherwise noted.
70 76

SFDR (DE) SECOND

74 HARMONIC
60
72
SFDR (SE)
50 THIRD
70 FOURTH
HARMONIC HARMONIC
SFDR (dBc)

THD (dBc)
40 68

30 66

64
20
62
10
60

0 58
00215-004

0.1 1 2.51 5.04 20.2 40.4 100 0 50 100 140 160

00215-007
fOUT (MHz) fCLK (MHz)

Figure 4. SFDR vs. fOUT @ fCLK = 140 MHz (Single-Ended and Differential) Figure 7. THD vs. fCLK @ fOUT = 2 MHz (Second, Third, and Fourth Harmonics)

80 1.0
SFDR (DE) 0.9
70

SFDR (SE) 0.8

60
0.7
LINEARITY (LSB)

50
0.6
SFDR (dBc)

40 0.5

0.4
30
0.3
20
0.2
10
0.1

0 0
0.1 1 2.51 5.04 20.2 40.4 100 2 17.62

00215-008
00215-005

fOUT (MHz) IOUT (mA)

Figure 5. SFDR vs. fOUT @ fCLK = 50 MHz (Single-Ended and Differential) Figure 8. Linearity vs. IOUT

72.0
1.0
71.8
0.75
71.6
0.5
71.4
SFDR (dBc)

ERROR (LSB)

71.2
0 1023
71.0
–0.16

70.8
–0.5
70.6

70.4
–10 5 25 45 65 85
00215-006

00215-009

–1.0
TEMPERATURE (°C) CODE (INL)
Figure 6. SFDR vs. Temperature @ fCLK = 50 MHz (fOUT = 1 MHz) Figure 9. Typical Linearity (INL)

Rev. C | Page 12 of 24
 ADV7123
–5 –5
SFDR (dBm)

SFDR (dBm)
–45 –45

00215-012
–85 –85

00215-010
0kHz 35MHz 70MHz 0kHz 35MHz 70MHz
START STOP START STOP

Figure 10. Single-Tone SFDR @ fCLK = 140 MHz (fOUT = 2 MHz) Figure 12. Dual-Tone SFDR @ fCLK = 140 MHz (fOUT1 = 13.5 MHz, fOUT2 = 14.5 MHz)
–5
SFDR (dBm)

–45

–85
00215-011

0kHz 35MHz 70MHz

START STOP

Figure 11. Single-Tone SFDR @ fCLK = 140 MHz (fOUT = 20 MHz)

Rev. C | Page 13 of 24
ADV7123
3 V TYPICAL PERFORMANCE CHARACTERISTICS
VAA = 3 V, VREF = 1.235 V, IOUT = 17.62 mA, 50 Ω doubly terminated load, differential output loading, TA = 25°C.
70 76
SECOND HARMONIC
60 SFDR (DE) 74

SFDR (SE) 72 FOURTH

50 HARMONIC

70
SFDR (dBc)

40 THIRD HARMONIC

THD (dBc)
68

30 66

64
20
62
10
60

0 58
1.0 2.51 5.04 20.2 40.4 100
00215-013

00215-016
0 50 100 140 160
fOUT (MHz) FREQUENCY (MHz)
Figure 13. SFDR vs. fOUT @ fCLK = 140 MHz (Single-Ended and Differential) Figure 16. THD vs. fCLK @ fOUT = 2 MHz (Second, Third, and Fourth Harmonics)

80 1.0
SFDR (DE)
70 0.9

SFDR (SE) 0.8

60
0.7
LINEARITY (LSB)

50
0.6
SFDR (dBc)

40 0.5

30 0.4

0.3
20
0.2
10
0.1

0 0
0.1 1 2.51 5.04 20.2 40.4 100 2 17.62
00215-014

00215-017
fOUT (MHz) IOUT (mA)

Figure 14. SFDR vs. fOUT @ fCLK = 140 MHz (Single-Ended and Differential) Figure 17. Linearity vs. IOUT

72.0
1.0
71.8
0.75
71.6
0.5
71.4
SFDR (dBc)

LINEARITY (LSB)

71.2
0 1023
71.0

70.8
–0.42
–0.5
70.6

70.4
00215-015

00215-018

0 20 85 145 165
–1.0
TEMPERATURE (°C) CODE (INL)
Figure 15. SFDR vs. Temperature @ fCLK = 50 MHz, (fOUT = 1 MHz) Figure 18. Typical Linearity

Rev. C | Page 14 of 24
 ADV7123

–5 –5

SFDR (dBm)
SFDR (dBm)

–45 –45

–85 –85

00215-021
00215-019
0kHz 35MHz 70MHz 0kHz 35MHz 70MHz
START STOP START STOP

Figure 19. Single-Tone SFDR @ fCLK = 140 MHz (fOUT = 2 MHz) Figure 21. Dual-Tone SFDR @ fCLK = 140 MHz (fOUT1 = 13.5 MHz, fOUT2 = 14.5 MHz)

–5
SFDR (dBm)

–45

–85
00215-020

0kHz 35MHz 70MHz

START STOP

Figure 20. Single-Tone SFDR @ fCLK = 140 MHz (fOUT = 20 MHz)

Rev. C | Page 15 of 24
ADV7123

TERMINOLOGY
Blanking Level Raster Scan
The level separating the SYNC portion from the video portion The most basic method of sweeping a CRT one line at a time to
generate and display images.
of the waveform. Usually referred to as the front porch or back
porch. At 0 IRE units, it is the level that shuts off the picture Reference Black Level
tube, resulting in the blackest possible picture. The maximum negative polarity amplitude of the video signal.
Color Video (RGB) Reference White Level
This refers to the technique of combining the three primary The maximum positive polarity amplitude of the video signal.
colors of red, green, and blue to produce color pictures within Sync Level
the usual spectrum. In RGB monitors, three DACs are required, The peak level of the SYNC signal.
one for each color.
Video Signal
Sync Signal (SYNC) The portion of the composite video signal that varies in gray
The position of the composite video signal that synchronizes scale levels between reference white and reference black. Also
the scanning process. referred to as the picture signal, this is the portion that can be
Gray Scale visually observed.
The discrete levels of video signal between reference black and
reference white levels. A 10-bit DAC contains 1024 different
levels, while an 8-bit DAC contains 256.

Rev. C | Page 16 of 24
 ADV7123

CIRCUIT DESCRIPTION AND OPERATION

The ADV7123 contains three 10-bit DACs, with three input Table 9 details the resultant effect on the analog outputs of
channels, each containing a 10-bit register. Also integrated BLANK and SYNC.
on board the part is a reference amplifier. The CRT control
All these digital inputs are specified to accept TTL logic levels.
functions, BLANK and SYNC, are integrated on board the
ADV7123. CLOCK INPUT
The CLOCK input of the ADV7123 is typically the pixel clock
DIGITAL INPUTS
rate of the system. It is also known as the dot rate. The dot rate,
There are 30 bits of pixel data (color information), R0 to R9, G0 and thus the required CLOCK frequency, is determined by the
to G9, and B0 to B9, latched into the device on the rising edge on-screen resolution, according to the following equation:
of each clock cycle. This data is presented to the three 10-bit
DACs and then converted to three analog (RGB) output Dot Rate = (Horiz Res) × (Vert Res) × (Refresh Rate)/
waveforms (see Figure 22). (Retrace Factor)
where:
CLOCK
Horiz Res is the number of pixels per line.
DIGITAL INPUTS Vert Res is the number of lines per frame.
(R9 TO R0, G9 TO G0,
DATA
B9 TO B0, Refresh Rate is the horizontal scan rate. This is the rate at which
SYNC, BLANK)
the screen must be refreshed, typically 60 Hz for a noninterlaced
ANALOG INPUTS system, or 30 Hz for an interlaced system.
00215-022

(IOR, IOR, IOG, IOG, Retrace Factor is the total blank time factor. This takes into
IOB, IOB)
account that the display is blanked for a certain fraction of the
Figure 22. Video Data Input/Output
total duration of each frame (for example, 0.8).
The ADV7123 has two additional control signals that are latched
Therefore, for a graphics system with a 1024 × 1024 resolution,
to the analog video outputs in a similar fashion. BLANK and
a noninterlaced 60 Hz refresh rate, and a retrace factor of 0.8,
SYNC are each latched on the rising edge of CLOCK to maintain
synchronization with the pixel data stream. Dot Rate = 1024 × 1024 × 60/0.8 = 78.6 MHz

The BLANK and SYNC functions allow for the encoding of The required CLOCK frequency is thus 78.6 MHz.
these video synchronization signals onto the RGB video output. All video data and control inputs are latched into the ADV7123
This is done by adding appropriately weighted current sources on the rising edge of CLOCK, as described in the Digital Inputs
to the analog outputs, as determined by the logic levels on the section. It is recommended that the CLOCK input to the
ADV7123 be driven by a TTL buffer (for example, 74F244).
BLANK and SYNC digital inputs. Figure 23 shows the analog
output, RGB video waveform of the ADV7123. The influence of
SYNC and BLANK on the analog video waveform is illustrated.

RED AND BLUE GREEN

mA V mA V

18.62 0.7 26.67 1.000 WHITE LEVEL

0 0 8.05 0.3 BLANK LEVEL

0 0 SYNC LEVEL

NOTES
1. OUTPUTS CONNECTED TO A DOUBLY TERMINATED 75Ω LOAD.
00215-023

2. VREF = 1.235V, RSET = 530Ω.

3. RS-343 LEVELS AND TOLERANCES ASSUMED ON ALL LEVELS.

Figure 23. RGB Video Output Waveform

Rev. C | Page 17 of 24
ADV7123
Table 9. Video Output Truth Table (RSET = 530 Ω, RLOAD = 37.5 Ω)
Video Output Level IOG (mA) IOG (mA) IOR/IOB (mA) IOR/IOB (mA) SYNC BLANK DAC Input Data
White Level 26.67 0 18.62 0 1 1 0x3FFH
Video Video + 8.05 18.62 − Video Video 18.62 − Video 1 1 Data
Video to BLANK Video 18.62 − Video Video 18.62 − Video 0 1 Data
Black Level 8.05 18.62 0 18.62 1 1 0x000H
Black to BLANK 0 18.62 0 18.62 0 1 0x000H
BLANK Level 8.05 18.62 0 18.62 1 0 0xXXXH (don’t care)
SYNC Level 0 18.62 0 18.62 0 0 0xXXXH (don’t care)

VIDEO SYNCHRONIZATION AND CONTROL sources in a monolithic design guarantees monotonicity and
low glitch. The on-board operational amplifier stabilizes the
The ADV7123 has a single composite sync (SYNC) input
full-scale output current against temperature and power supply
control. Many graphics processors and CRT controllers have the
variations.
ability of generating horizontal sync (HSYNC), vertical sync
(VSYNC), and composite SYNC. ANALOG OUTPUTS
In a graphics system that does not automatically generate a The ADV7123 has three analog outputs, corresponding to the
composite SYNC signal, the inclusion of some additional logic red, green, and blue video signals.
circuitry enables the generation of a composite SYNC signal. The red, green, and blue analog outputs of the ADV7123 are
The sync current is internally connected directly to the IOG high impedance current sources. Each one of these three RGB
output, thus encoding video synchronization information onto current outputs is capable of directly driving a 37.5 Ω load, such
the green video channel. If it is not required to encode sync as a doubly terminated 75 Ω coaxial cable. Figure 24 shows
information onto the ADV7123, the SYNC input should be tied the required configuration for each of the three RGB outputs
connected into a doubly terminated 75 Ω load. This arrangement
to logic low.
develops RS-343A video output voltage levels across a 75 Ω
REFERENCE INPUT monitor.
The ADV7123 contains an on-board voltage reference. The VREF A suggested method of driving RS-170 video levels into a 75 Ω
pin is normally terminated to VAA through a 0.1 μF capacitor. monitor is shown in Figure 25. The output current levels of the
Alternatively, the part can, if required, be overdriven by an DACs remain unchanged, but the source termination resistance,
external 1.23 V reference (AD1580). ZS, on each of the three DACs is increased from 75 Ω to 150 Ω.
A resistance, RSET, connected between the RSET pin and GND, IOR, IOG, IOB
Z0 = 75Ω
determines the amplitude of the output video level according to DACs
Equation 1 and Equation 2 for the ADV7123. (CABLE)
ZS = 75Ω
ZL = 75Ω
(SOURCE
IOG (mA) = 11,445 × VREF (V)/RSET (Ω) (1) TERMINATION)
(MONITOR)

IOR, IOB (mA) = 7989.6 × VREF (V)/RSET (Ω) (2)

00215-024
Equation 1 applies to the ADV7123 only, when SYNC is being TERMINATION REPEATED THREE TIMES
FOR RED, GREEN, AND BLUE DACs
used. If SYNC is not being encoded onto the green channel,
Figure 24. Analog Output Termination for RS-343A
Equation 1 is similar to Equation 2.
IOR, IOG, IOB
Z0 = 75Ω
Using a variable value of RSET allows for accurate adjustment of
DACs
the analog output video levels. Use of a fixed 560 Ω RSET resistor (CABLE)
ZS = 150Ω
yields the analog output levels quoted in the Specifications section. (SOURCE
ZL = 75Ω
(MONITOR)
These values typically correspond to the RS-343A video wave- TERMINATION)

form values, as shown in Figure 23.

00215-025

DACs TERMINATION REPEATED THREE TIMES

FOR RED, GREEN, AND BLUE DACs
The ADV7123 contains three matched 10-bit DACs. The DACs Figure 25. Analog Output Termination for RS-170
are designed using an advanced, high speed, segmented architec-
More detailed information regarding load terminations for
ture. The bit currents corresponding to each digital input are
various output configurations, including RS-343A and RS-170,
routed to either the analog output (bit = 1) or GND (bit = 0)
is available in the AN-205 Application Note, Video Formats and
by a sophisticated decoding scheme. Because all this circuitry is
Required Load Terminations, available from Analog Devices, at
on one monolithic device, matching between the three DACs is
www.analog.com.
optimized. As well as matching, the use of identical current
Rev. C | Page 18 of 24
 ADV7123
Z2 Z1
Figure 23 shows the video waveforms associated with the three
RGB outputs driving the doubly terminated 75 Ω load of Figure 24. +VS 0.1µF

As well as the gray scale levels, black level to white level, Figure 23 7
2 Z0 = 75Ω
also shows the contributions of SYNC and BLANK for the IOR, IOG, IOB
AD848 6
75Ω

ADV7123. These control inputs add appropriately weighted DACs 3 (CABLE) ZL = 75Ω
4 0.1µF
currents to the analog outputs, producing the specific output (MONITOR)
ZS = 75Ω –VS
level requirements for video applications. Table 9 details how (SOURCE

00215-027
TERMINATION) Z1
the SYNC and BLANK inputs modify the output levels. GAIN (G) = 1 +
Z2

GRAY SCALE OPERATION Figure 27. AD848 As an Output Buffer

The ADV7123 can be used for standalone, gray scale (mono- PCB LAYOUT CONSIDERATIONS
chrome), or composite video applications (that is, only one The ADV7123 is optimally designed for lowest noise perfor-
channel used for video information). Any one of the three mance, both radiated and conducted noise. To complement the
channels, red, green, or blue, can be used to input the digital excellent noise performance of the ADV7123, it is imperative
video data. The two unused video data channels should be tied that great care be given to the PCB layout. Figure 28 shows a
to Logic 0. The unused analog outputs should be terminated recommended connection diagram for the ADV7123.
with the same load as that for the used channel; that is, if the
red channel is used and IOR is terminated with a doubly The layout should be optimized for lowest noise on the
terminated 75 Ω load (37.5 Ω), IOB and IOG should be ADV7123 power and ground lines. This can be achieved by
terminated with 37.5 Ω resistors (see Figure 26). shielding the digital inputs and providing good decoupling.
Shorten the lead length between groups of VAA and GND pins
DOUBLY
VIDEO R0 IOR TERMINATED to minimize inductive ringing.
7.5Ω LOAD
OUTPUT
R9 IOG
ADV7123 37.5Ω It is recommended to use a 4-layer printed circuit board with a
G0 single ground plane. The ground and power planes should
G9 IOB separate the signal trace layer and the solder side layer. Noise
37.5Ω

B0
on the analog power plane can be further reduced by using
multiple decoupling capacitors (see Figure 28). Optimum
00215-026

GND
B9
performance is achieved by using 0.1 μF and 0.01 μF ceramic
Figure 26. Input and Output Connections for Standalone Gray Scale or capacitors. Individually decouple each VAA pin to ground by
Composite Video
placing the capacitors as close as possible to the device with the
VIDEO OUTPUT BUFFERS capacitor leads as short as possible, thus minimizing lead
The ADV7123 is specified to drive transmission line loads. The inductance. It is important to note that while the ADV7123
analog output configuration to drive such loads is described in contains circuitry to reject power supply noise, this rejection
the Analog Outputs section and illustrated in Figure 27. However, decreases with frequency. If a high frequency switching power
in some applications it may be required to drive long transmis- supply is used, pay close attention to reducing power supply
sion line cable lengths. Cable lengths greater than 10 meters can noise. A dc power supply filter (Murata BNX002) provides EMI
attenuate and distort high frequency analog output pulses. The suppression between the switching power supply and the main
inclusion of output buffers compensates for some cable distortion. PCB. Alternatively, consideration can be given to using a 3-
Buffers with large full power bandwidths and gains between terminal voltage regulator.
two and four are required. These buffers also need to be able to DIGITAL SIGNAL INTERCONNECT
supply sufficient current over the complete output voltage swing. Isolate the digital signal lines to the ADV7123 as much as
Analog Devices produces a range of suitable op amps for such possible from the analog outputs and other analog circuitry.
applications. These include the AD843, AD844, AD847, and Digital signal lines should not overlay the analog power plane.
AD848 series of monolithic op amps. In very high frequency
applications (80 MHz), the AD8061 is recommended. More Due to the high clock rates used, long clock lines to the
information on line driver buffering circuits is given in the ADV7123 should be avoided to minimize noise pickup.
relevant op amp data sheets. Connect any active pull-up termination resistors for the digital
Use of buffer amplifiers also allows implementation of other inputs to the regular PCB power plane (VCC) and not the analog
video standards besides RS-343A and RS-170. Altering the gain power plane.
components of the buffer circuit results in any desired video level.

Rev. C | Page 19 of 24
ADV7123
ANALOG SIGNAL INTERCONNECT For optimum performance, the analog outputs should each
Place the ADV7123 as close as possible to the output connec- have a source termination resistance to ground of 75 Ω (doubly
tors, thus minimizing noise pickup and reflections due to terminated 75 Ω configuration). This termination resistance
impedance mismatch. should be as close as possible to the ADV7123 to minimize
reflections.
The video output signals should overlay the ground plane and
not the analog power plane, thereby maximizing the high Additional information on PCB design is available in the
frequency power supply rejection. AN-333 Application Note, Design and Layout of a Video
Graphics System for Reduced EMI, which is available from
Analog Devices at www.analog.com.

POWER SUPPLY DECOUPLING

(0.1µF AND 0.01µF CAPACITOR
FOR EACH VAA GROUP)

0.1µF 0.01µF
13, 29,
0.1µF 30
VAA 35 COMP VAA VAA

39 TO 48 VAA
1kΩ
VREF 36
R9 TO R0 1
AD1580 1µF
2
1 TO 10 RSET 37
VIDEO RSET
DATA G9 TO G0 530Ω COAXIAL CABLE MONITOR (CRT)
INPUTS 75Ω
IOR 34
14 TO 23 75Ω
B9 TO B0
IOG 32
75Ω
ADV7123
IOB 28
75Ω 75Ω 75Ω 75Ω

BNC
12 SYNC IOR 33 CONNECTORS

11 BLANK
COMPLEMENTARY
IOG 31
24 CLOCK OUTPUTS

IOB 27
38 PSAVE

GND
00215-028
25, 26

Figure 28. Typical Connection Diagram

Rev. C | Page 20 of 24
 ADV7123

OUTLINE DIMENSIONS
9.20
0.75 9.00 SQ
1.60
0.60 MAX 8.80
0.45 48 37
1 36

PIN 1
7.20
1.45 TOP VIEW 7.00 SQ
0.20 (PINS DOWN) 6.80
1.40
0.09
1.35
7°
3.5° 12 25
0.15 0° 13 24
0.05 SEATING 0.08
PLANE VIEW A 0.50
0.27
COPLANARITY
BSC 0.22
LEAD PITCH 0.17
VIEW A
ROTATED 90° CCW

051706-A
COMPLIANT TO JEDEC STANDARDS MS-026-BBC

Figure 29. 48-Lead Low Profile Quad Flat Package [LQFP]

(ST-48)
Dimensions shown in millimeters

ORDERING GUIDE
Model Temperature Range Speed Option Package Description Package Option
ADV7123KSTZ501 −40°C to +85°C 50 MHz 48-Lead LQFP ST-48
ADV7123KSTZ1401 −40°C to +85°C 140 MHz 48-Lead LQFP ST-48
ADV7123KST140-RL1 −40°C to +85°C 140 MHz 48-Lead LQFP ST-48
ADV7123JSTZ2401 0°C to 70°C 240 MHz 48-Lead LQFP ST-48
ADV7123JSTZ240-RL1 0°C to 70°C 240 MHz 48-Lead LQFP ST-48
ADV7123JSTZ3301, 2 0°C to 70°C 330 MHz 48-Lead LQFP ST-48
1
Z = RoHS Compliant Part.
2
Available in 3.3 V version only.

Rev. C | Page 21 of 24
ADV7123

NOTES

Rev. C | Page 22 of 24
 ADV7123

NOTES

Rev. C | Page 23 of 24
ADV7123

NOTES

©2009 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D00215-0-3/09(C)

Rev. C | Page 24 of 24