FLEXIBLE AC TRANSMISSION SYSTEMS

UNIT-V
SERIES COMPENSATION
Concept of Series Capacitive Compensation:

The basic idea behind series capacitive compensation is to decrease the overall effective series
transmission impedance from the sending end to the receiving end, i.e., X in the P = (V2/X) sin δ
relationship characterizing the power transmission over a single line.

Consider the simple two-machine model, assumed to be composed of two identical segments, as
illustrated in Figure 6.1(a). The corresponding voltage and current phasors are shown in Figure 6.1(b).
Note that for the same end voltages the magnitude of the total voltage across the series line inductance,
Vx=2Vx/2 is increased by the magnitude of the opposite voltage, V C, developed across the series
capacitor; this results from an increase in the line current.

The effective transmission impedance XT with the series capacitive compensation is given by

where k is the degree of series compensation, i.e,

Assuming Vs=Vr=V in figure 6.1(b), the current in the compensated line, and the corresponding real
power transmitted can be derived as follows

The reactive power supplied by the series capacitor can be expressed as follows:

The relationship between the real power P, series capacitor reactive power Q C, and angle δ is shown
plotted at various values of the degree of series compensation k in Figure 6.1(c). It can be observed
that the transmittable power rapidly increases with the degree of series compensation k. Similarly, the
reactive power supplied by the series capacitor also increases sharply with k and varies with angle δ in
a similar manner as the line reactive power.

Voltage Stability:
 Series capacitive compensation can be used to reduce the series reactive impedance to minimize
the receiving-end voltage variation and the possibility of voltage collapse.
 A simple radial system with feeder line reactance X, series compensating reactance Xs, and load
impedance Z is shown in Figure. The corresponding normalized terminal voltage V r, versus power
 P plots, with unity power factor load at 0, 50 and 75% series capacitive compensation, are shown
in Figure.
 The "nose point" at each plot given for a specific compensation level represents the corresponding
voltage instability.
 Both shunt and series capacitive compensation can effectively increase the voltage stability limit.
Shunt compensation does it by supplying the reactive load demand and regulating the terminal
voltage. Series capacitive compensation does it by cancelling a portion of the line reactance and
thereby, in effect, providing a "stiff" voltage source for the load.
 For increasing the voltage stability limit of overhead transmission, series compensation is much
more effective than shunt compensation of the same MVA rating.

Power Oscillation Damping:

 Controlled series compensation can be applied effectively to damp power oscillations.
 For power oscillation damping it is necessary to vary the applied compensation to counteract the
accelerating and decelerating swings of the disturbed machine(s).
 When the rotationally oscillating generator accelerates and angle δ increases (dδ/dt > 0), then
electric power transmitted must be increased to compensate for the excess mechanical input
power.
 When the generator decelerates and angle δ decreases (dδ/dt < 0), then electric power must be
decreased to balance the insufficient mechanical input power.
 The required variation of the degree of series compensation, together with the corresponding
variation of the transmission angle δ and transmitted power P versus time of an under-damped
oscillating system are shown for an illustrative hypothetical case in Figure.
 Waveforms in Figure show the undamped and damped oscillations of angle δ around the steady
state value δ0 . Waveforms in Figure shows the corresponding undamped and damped
oscillations of the electric power P around the steady-state value P 0, following an assumed fault
(sudden drop in P) that initiated the oscillation.
 Waveform C shows the applied variation of the degree of series capacitive compensation, k,
applied. As shown, k is maximum when dδ/dt > 0, and it is zero when dδ/dt < 0.
 With maximum k, the effective line impedance is minimum and consequently, the electric power
transmitted over the line is maximum. When k is zero, the effective line impedance is maximum
and the power transmitted is minimum.
  The k is controlled in a "bang-bang" manner i.e, output of the series compensator is varied
between the minimum and maximum values. This type of control is the most effective for
damping large oscillations.

Improvement of Transient Stability:

Consider the simple system with the series compensated line shown in Figure 6.1(a). Suppose that the
system of Figure 6.1(a), with and without series capacitive compensation, transmits the same power
Pm. Assume that both the uncompensated and the series compensated systems are subjected to the same
fault for the same period of time.

The dynamic behaviour of these systems is illustrated in Figures 6.3(a) and (b). As seen, prior to the
fault both of them transmit power P, at angles δ1 and δS1, respectively.

During the fault, the transmitted electric power becomes zero while the mechanical input power to the
generators remains constant, Pm. Therefore, the sending-end generator accelerates from the steady-state
angles δ1 and δS1 to angles δ2 and δS2, respectively, when the fault clears.

The accelerating energies are represented by areas A1 and AS1.

After fault clearing, the transmitted electric power exceeds the mechanical input power and therefore
the sending-end machine decelerates. However, the accumulated kinetic energy further increases until
a balance between the accelerating and decelerating energies, represented by areas A 1, AS1 and A2 AS2,
respectively, is reached at the maximum angular swings, δ 3 and δS3, respectively. The areas between
the P versus δ curve and the constant Pm line over the intervals defined by angles δ 3 and δcrit, and δS3
and δScrit, respectively, determine the margin of transient stability, represented by areas A margin and
Asmargin.

Comparison of Figures 6.3(a) and (b) clearly shows a substantial increase in the transient stability
margin the series capacitive compensation can provide by partial cancellation of the series impedance
of the transmission line. The increase of transient stability margin is proportional to the degree of
series compensation.

Variable Impedance Type Series Compensators:

Variable impedance type series compensators are composed of thyristor-switched/controlled-

capacitors or thyristor-controlled reactors with fixed capacitors. The variable impedance series
compensators are

 GTO Thyristor-Controlled Series Capacitor (GCSC)

 Thyristor-Switched Series Capacitor (TSSC)

 Thyristor-Controlled Series Capacitor (TCSC)

GTO Thyristor-Controlled Series Capacitor (GCSC):

A GCSC consists of a fixed capacitor in parallel with a GTO Thyristor valve which can be turned on or
off upon command. The GCSC controls the voltage across the capacitor (Vc) for a given line current.
In other words, when the GTO is closed the voltage across the capacitor is zero and when the GTO is
open the voltage across the capacitor is at its maximum value. The magnitude of the capacitor voltage
can be varied continuously by the method of delayed angle control.

The turn-off instant of the valve in each half-cycle is controlled by a (turn-off) delay angle γ (0 < γ <
π/2), with respect to the peak of the line current. Refer to Figure 6.5(b), where the line current i, and
the capacitor voltage Vc(γ) are shown at γ = 0 (valve open) and at an arbitrary turn-off delay angle γ,
for a positive and a negative half-cycle. When the valve sw is opened at the crest of the (constant) line
current (γ=0), the resultant capacitor voltage V c will be the same as that obtained in steady state with a
permanently open switch. When the opening of the valve is delayed by the angle γ with respect to the
crest of the line current, the capacitor voltage can be expressed with a defined line current, i(t) = I cos
ωt, as follows:

In the above equation the term (I/ωC) sin γ is simply a γ dependent constant by which the sinusoidal
voltage obtained at γ = 0 is offset, shifted down for positive, and up for negative voltage half-cycles, as
illustrated in Figure 6.5(b). Since the GTO valve automatically turns on at the instant of voltage zero
crossing (which is symmetrical on the time axis to the instant of turn-off with respect to the peak of the
capacitor voltage), this process controls the nonconducting (blocking) interval (or angle) of the GTO
valve. That is, the turn-off delay angle γ defines the prevailing blocking angle ξ: ξ = π - 2γ. Thus, as
the turn-off delay angle γ increases, the correspondingly increasing offset results in the reduction of the
blocking angle ξ of the valve, and the consequent reduction of the capacitor voltage. At the maximum
delay of γ=π/2, the offset also reaches its maximum of I/ωC, at which both the blocking angle and the
capacitor voltage become zero.

It is evident that the magnitude of the capacitor voltage can be varied continuously by this method of
turn-off delay angle control from maximum (γ = 0) to zero (γ = π/2), as illustrated in Figure 6.5(c),
where the capacitor voltage VC(γ), together with its fundamental component V CF(γ), are shown at
various turn-off delay angles, γ.

The amplitude VCF(γ) of the fundamental capacitor voltage can be expressed as a function of angle γ:

where I is the amplitude of the line current, C is the capacitance of the GTO thyristor controlled
capacitor, and ω is the angular frequency of the ac system. The V-I characteristics of GCSC are as
follows.

V-I characteristics:

In a practical application the GCSC can be operated either to control the compensating voltage, V CF(γ),
or the compensating reactance, XC(γ).

Voltage Compensation mode:

In the voltage compensation mode, the GCSC is to maintain the rated compensating voltage in face of

decreasing line current over a defined interval , as illustrated in Figure 6.7(a1). In this
compensation mode the capacitive reactance Xc, is selected so as to produce the rated compensating

voltage with I=Imin i.e. As current is increased toward , the turn-off delay
angle γ is increased to reduce the duration of the capacitor injection and thereby maintain the
compensating voltage with increasing line current. The loss, as percent of the rated var output, versus
line current characteristic of the GCSC operated in the voltage compensation mode is shown in Figure
6.7(a2) for zero voltage injection and for maximum rated voltage injection.
Impedance compensation mode:

In the impedance compensation mode, the GCSC is to maintain the maximum rated compensating
reactance at any line current up to the rated maximum, as illustrated in Figure 6.7(b1). In this
compensation mode the capacitive impedance is chosen so as to provide the maximum series

compensation at rated current, , that the GCSC can vary in the range

by controlling the effective capacitor voltage , i.e., . The loss versus line
current characteristic of the GCSC for this operating mode is shown in Figure 6.7 (b2) for zero
compensating impedance (capacitor is bypassed by the GTo valve) and for maximum compensating
impedance.

Thyristor-Switched Series Capacitor (TSSC):

The basic circuit arrangement of the thyristor-switched series capacitor is shown in Figure 6.10. It
consists of a number of capacitors, each shunted by an appropriately rated bypass valve composed of a
string of reverse parallel connected thyristors, in series.

The operating principle of the TSSC is straightforward: the degree of series compensation is controlled
in a step-like manner by increasing or decreasing the number of series capacitors inserted. A capacitor
is inserted by turning off, and it is bypassed by turning on the corresponding thyristor valve.

A thyristor valve commutates "naturally," that is, it turns off when the current crosses zero. Thus a
capacitor can be inserted into the line by the thyristor valve only at the zero crossings of the line
current. Since the insertion takes place at line current zero, a full half-cycle of the line current will
charge the capacitor from zero to maximum and the successive, opposite polarity half-cycle of the line
current will discharge it from this maximum to zero, as illustrated in Figure 6.11

As can be seen, the capacitor insertion at line current zero, necessitated by the switching limitation of
the thyristor valve, results in a dc offset voltage which is equal to the amplitude of the ac capacitor
voltage. In order to minimize the initial surge current in the valve, and the corresponding circuit
transient, the thyristor valve should be turned on for bypass only when the capacitor voltage is zero.
With the prevailing dc offset, this requirement can cause a delay of up to one full cycle, which would
set the theoretical limit for the attainable response time of the TSSC.

V-I Characteristics:

The basic V-I characteristic of the TSSC with four series connected compensator modules operated to
control the compensating voltage is shown in Figure 6.12(aI). For this compensating mode the
reactance of the capacitor banks is chosen so as to produce, on the average, the rated compensating

voltage, , in the face of decreasing line current over a defined interval .

As current is increased toward , the capacitor banks are progressively bypassed by the related
thyristor valves to reduce the overall capacitive reactance in a step-like manner and thereby maintain
the compensating voltage with increasing line current. The loss, as percent of the rated var output,
versus line current characteristic of the TSSC operated in the voltage compensating mode is shown in
Figure 6.72(a2) for zero voltage injection (all capacitors are bypassed) and for maintaining maximum
rated voltage injection (capacitors are progressively bypassed).

In the impedance compensation mode, the TSSC is applied to maintain the maximum rated
compensating reactance at any line current up to the rated maximum, as illustrated in Figure 6.12(bI).
In this compensation mode the capacitive impedance is chosen so as to provide the maximum series

compensation at rated current, , that the TSSC can vary in a step-like manner by
bypassing one or more capacitor banks. The loss versus line current characteristic for this
compensation mode is shown in Figure 6.12(b2) for zero compensating impedance (all capacitor banks
are bypassed by the thyristor valves) and for maximum compensating impedance (all thyristor valves
are off and all capacitors are inserted).

Thyristor Controlled Series Capacitor (TCSC):

The Thyristor-Controlled Series Capacitor consists of the series compensating capacitor shunted by a
Thyristor-Controlled Reactor. The basic idea behind the TCSC scheme is to provide a continuously
variable capacitor by means of partially cancelling the effective compensating capacitance by the TCR.
Since, the TCR at the fundamental system frequency is a continuously variable reactive impedance,
controllable by delay angle α, the steady-state impedance of the TCSC is that of a parallel LC circuit,
consisting of a fixed capacitive impedance, XC, and a variable inductive impedance, XL(α), that is,

Where

The TCSC thus presents a tuneable parallel LC circuit to the line current that is substantially a constant
alternating current source.

As the impedance of the controlled reactor, X L(α), is varied from its maximum (infinity) toward its

minimum (ωL), the TCSC increases its minimum capacitive impedance, , until
parallel resonance at XC = XL(α) is established and XTCSCmin, theoretically becomes infinite.

Decreasing XL(α) further, the impedance of the TCSC, Xtcsc(α) becomes inductive, reaching its
minimum value of XLXC/(XL-XC) at α=0, where the capacitor is in effect bypassed by the TCR.

Therefore, with the usual TCSC arrangement in which the impedance of the TCR reactor, X L, is
smaller than that of the capacitor, X C, the TCSC has two operating ranges around its internal circuit

resonance: one is the range, where Xtcsc(α) is capacitive, and the other is the

range, where Xtcsc(α) is inductive, as illustrated in Figure 6.14.

Process of changing Capacitor Voltage:

Assume that the thyristor valve, SW, is initially open and the prevailing line current i produces voltage
Vco across the fixed series compensating capacitor, as illustrated in Figure 6.15(a). Suppose that the
TCR is to be turned on at , measured from the negative peak of the capacitor voltage.

As seen, at this instant of turn-on, the capacitor voltage is negative, the line current is positive and thus
charging the capacitor in the positive direction.

During this first half-cycle (and all similar subsequent half-cycles) of TCR operation, the thyristor
valve can be viewed as an ideal switch, closing at , in series with a diode of appropriate polarity to
stop the conduction as the current crosses zero, as shown at the bottom of Figure 6.15(b).

At the instant of closing switch SW, two substantially independent events will take place:

One is that the line current, being a constant current source, continues to (dis)charge the capacitor.

The other is that the charge of the capacitor will be reversed during the resonant half-cycle of the LC
circuit formed by the switch closing. (assume that XL < Xc.)
 6.15 Illustration of capacitor voltage reversal by TCR: (a) line current and corresponding capacitor
voltage, (b) equivalent circuit of the TCSC at the firing instant , and (c) the resulting capacitor
voltage and related TCR current.

The resonant charge reversal produces a dc offset for the next (positive) half-cycle of the capacitor
voltage, as illustrated in Figure 6.15(c).

In the subsequent (negative) half-cycle, this dc offset can be reversed by maintaining the same , and
thus a voltage waveform symmetrical to the zero axis can be produced, as illustrated in Figure 6.16,
where the relevant current and voltage waveforms of the TCSC operated in the capacitive region are
shown.

6.16 Capacitor voltage and current waveforms, together with TCR voltage and current waveforms,
characterizing the TCSC in the capacitive region under steady-state operation.
V-I Characteristics of TCSC:

The compensating voltage versus line current (V-I) characteristic of a basic TCSC is shown in Figure
6.20(a1).

As illustrated, in the capacitive region the minimum delay angle , sets the limit for the maximum

compensating voltage up to a value of line current ( ) at which the maximum rated voltage, ,

constrains the operation until the rated maximum current, , is reached.

In the inductive region, the maximum delay angle, , limits the voltage at low line currents and the
maximum rated thyristor current at high line currents. The loss, as a percent of the rated var output,
versus line current for voltage compensation mode in the capacitive operating region is shown in
Figure 6.20(a2) for maximum and minimum compensating voltages as well as for bypass operation
(thyristor valve is fully on). The losses are almost entirely due to the TCR, which include the
conduction and switching losses of the thyristor valve and the I2R losses of the reactor.

Note that the loss characteristic of the TCSC shown in Figure 6.20(a2) correlates with its voltage
compensation characteristic shown in Figure 6-20(a1). That is, the losses increase in proportion with
the line current at the fixed maximum TCR conduction angle obtained with the minimum delay angle,

and then they decline as the conduction angle is continuously decreased with increasing α to
keep the capacitor voltage constant, below the maximum voltage constraint.
In the impedance compensation mode, the TCSC is applied to maintain the maximum rated
compensating reactance at any line current up to the rated maximum. For this operating mode the
TCSC capacitor and thyristor-controlled reactor are chosen so that at ag\^ the maximum capacitive
reactance can be maintained at and below the maximum rated line current, as illustrated in Figure
6.20(b1). The minimum capacitive compensating impedance the TCSC can provide is, of course, the
impedance of the capacitor itself, theoretically obtained at α = 90 o (with nonconducting thyristor
valve). The loss versus line current characteristic for this operating mode is shown in Figure 6.20(b2)
for maximum and minimum capacitive compensating reactances.

Mechanism of controlling the dc offset by charge reversal:

Mechanism of controlling the dc offset by charge reversal is illustrated for the increase and decrease of
the capacitor voltage in Figures 6.19(a) and (b), respectively. For the clarity of illustration, the
theoretically ideal case of instantaneous voltage reversal is assumed. In Figure 6.19(a), initially the
TCR is gated on at α=π/2, at which the TCR current is zero and the capacitor voltage is entirely due to
the line current. To produce a dc offset, the periodically repeated gating in the second cycle is
advanced by a small angle ε i.e., the prevailing half period is reduced by ε to π - ε. This action
produces a phase advance for the capacitor voltage with respect to the line current and, as a result, the
capacitor absorbs energy from the line, charging it to a higher voltage.
6.19(a). Increase of the capacitor voltage by advancing the voltage reversal from α = π to α = π - ε.

In a similar manner, periodically repeated gating in the second cycle is delayed by a small angle ε, as
a result, the capacitor dissipate energy into the line, discharging it to a lower voltage as shown in figure
6.19(b).
6.19 (b) Decrease of the capacitor voltage by retarding the voltage reversal from α = π to α = π + ε.
Internal control scheme for GCSC:

It has four basic functions.

The first function is synchronous timing, provided by a phase-locked loop circuit that runs in
synchronism with the line current.

The second function is the reactive voltage or impedance to turn-off delay angle conversion according
to the relationship given in (6.8a) or (6.8b), respectively.

The third function is the determination of the instant of valve turn-on when the capacitor voltage
becomes zero. (This function may also include the maintenance of a minimum on time at voltage zero
crossings to ensure immunity to sub-synchronous resonance.)

The fourth function is the generation of suitable turn-off and turn-on pulses for the GTO valve.

Inspection of these waveforms show that, with a "black box" viewpoint, the basic GCSC (power circuit
plus internal control) can be considered as a controllable series capacitor which, in response to the
transmission line current, will reproduce (within a given frequency band and specified rating) the
compensating impedance (or voltage) defined by the reference input. The dynamic performance of the
GCSC is like that of the TCR, both having a maximum transport lag of one half of a cycle.

Functional internal control scheme for TCSC

The main consideration for the structure of the internal control operating the power circuit of the
TCSC is to ensure immunity to sub-synchronous resonance. The approach follows two basic control
philosophies. One is to operate the basic phase locked loop (PLL) from the fundamental component of
the line current. In order to achieve this, it is necessary to provide substantial filtering to remove the
super- and, in particular, the sub-synchronous components from the line current and, at the same time,
maintain correct phase relationship for proper synchronization. A possible internal control scheme of
this type is shown in Figure 6.27. In this arrangement the

conventional technique of converting the demanded TCR current into the corresponding delay angle,
which is measured from the peak (or, with a fixed 90 o shift, from the zero crossing) of the fundamental
line current, is used. The reference for the demanded TCR current is, as illustrated in Figure 6.27,
usually provided by a regulation loop of the external control, which compares the actual capacitive
impedance or compensating voltage to the reference given for the desired system operation.