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HW4, q + a - Homework assignment 4

Digital Logic and Microprocessor Design (Oakland University)

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ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY

ECE-378: Digital Logic and Microprocessor Design Winter 2015

Homework 4
(Due date: April 2nd @ 5:30 pm)
Presentation and clarity are very important! Show your procedure!

PROBLEM 1 (20 PTS)

resetn
 Design a counter using a Finite State Machine (FSM):
Counter features: E 3
E Q
 Count: 000, 001, 010, 011, 111, 110, 101, 100, 000, …
 𝑟𝑒𝑠𝑒𝑡𝑛: Asynchronous active-low input signal. It initializes the count to “000”
 Input 𝐸: Synchronous input that increases the count when it is set to ‘1’. clock z
 output 𝑧: It becomes ‘1’ when the count is 111 or 100.
Counter

 Provide the State Diagram (any representation), State Table, and the Excitation Table. Is this a Mealy or a Moore machine?
Why? (10 pts)
 Provide the excitation equations (simplify your circuit using K-maps or the Quine-McCluskey algorithm) (5 pts)
 Sketch the circuit. (5 pts)

PROBLEM 2 (15 PTS) resetn

 Sequence detector (with overlap):
Draw the state diagram (both normal FSM representation and ASM chart) of a x z
circuit (with an input 𝑥) that detects the following sequence: 00110101. The FINITE STATE
MACHINE
detector must assert an output 𝑧 when the sequence is detected.
clock

PROBLEM 3 (30 PTS)

 Complete the timing diagram of the following FSM (represented as an ASM chart). (10 pts)

resetn=0
S1
sclr  1 clock

0 resetn
s
1 s
S2

0
z E1 sclr
1

sclr  1
E

S3
state
wt  1

wt
1
z
0 done
S4
done  1

0 1
s

1 Instructor: Daniel Llamocca

Downloaded by ?? ? (pinelee98@gmail.com)
 lOMoARcPSD|43202152

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY

ECE-378: Digital Logic and Microprocessor Design Winter 2015

 Complete the timing diagram of the following FSM. Is this a Mealy or a Moore machine? Why? (5 pts)
resetn = 0
x/z
1/0 clock

1/1
0/1 resetn
S1 S2
0/0 x
1/0 0/0
state S1
S4 S3 0/1
1/1
z

 Provide the state diagram (in ASM form) and complete the timing diagram of the FSM whose VHDL description is listed
below. (15 pts)

library ieee; architecture behavioral of circ is

use ieee.std_logic_1164.all; type state is (S1, S2, S3);
signal y: state;
entity circ is begin
port ( clk, resetn: in std_logic; Transitions: process (resetn, clk, a, b)
a, b: in std_logic; begin
x,w,z: out std_logic); if resetn = '0' then y <= S1;
end circ; elsif (clk'event and clk = '1') then
case y is
when S1 =>
if a = '1' then
if b = ‘1’ then y <= S3; else y <= S1; end if;
else
y <= S2;
end if;

when S2 =>
if a = '1' then y <= S3; else y <= S2; end if;

when S3 =>
if b = '1' then y <= S1; else y <= S3; end if;
end case;
end if;
end process;

Outputs: process (y, a, b)

begin
x <= ‘0’; w <= ‘0’; z <= ‘0’;
case y is
when S1 => if a = ‘0’ then z <= ‘1’; end if;
when S2 => w <= ‘1’;
when S3 => if b = ‘1’ then x <= '1'; end if;
end case;
end process;
end behavioral;

clk

resetn

state

2 Instructor: Daniel Llamocca

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 lOMoARcPSD|43202152

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY

ECE-378: Digital Logic and Microprocessor Design Winter 2015

PROBLEM 4 (20 PTS)

 Complete the timing diagram of the following digital circuit that includes an FSM (in ASM form) and a datapath circuit.
resetn=0
data 0010 S1
4 E1

1 0
0
4 4 s sclr  1

0
+ p 1

resetn 4 S2
E1
E
sclr
0
z

4 1
Q sclr: synchronous clear
If E=sclr=1, then Q = 0 sclr  1
p E sclr
S3
z done  1
s FINITE STATE
MACHINE done
clock
0 1
s

clock

resetn

data 0101 0011 1000

Q 0000

sclr

state

done

PROBLEM 5 (15 PTS)

 Attach a printout of your Project Status Report (no more than three pages, single-spaced, 2 columns). This report should
contain the current status of the project. You MUST use the provided template (Final Project – Report
Template.docx).

3 Instructor: Daniel Llamocca

Downloaded by ?? ? (pinelee98@gmail.com)
 lOMoARcPSD|43202152

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY

ECE-378: Digital Logic and Microprocessor Design Winter 2015

Solutions - Homework 4
(Due date: April 2nd @ 5:30 pm)
Presentation and clarity are very important! Show your procedure!

PROBLEM 1 (20 PTS)

resetn
 Design a counter using a Finite State Machine (FSM):
Counter features: E 3
E Q
 Count: 000, 001, 010, 011, 111, 110, 101, 100, 000, …
 𝑟𝑒𝑠𝑒𝑡𝑛: Asynchronous active-low input signal. It initializes the count to “000”
 Input 𝐸: Synchronous input that increases the count when it is set to ‘1’. clock z
 output 𝑧: It becomes ‘1’ when the count is 111 or 100.
Counter

 Provide the State Diagram (any representation), State Table, and the Excitation Table. Is this a Mealy or a Moore machine?
Why? (10 pts)
 Provide the excitation equations (simplify your circuit using K-maps or the Quine-McCluskey algorithm) (5 pts)
 Sketch the circuit. (5 pts)

 State Diagram and State Table:

PRESENT NEXT
E STATE STATE z
E=1 E=1 E=1 0 S1 S1 0
resetn = '0'
E=0 0 S2 S2 0
0 S3 S3 0
S1 S2 S3 S4 0 S4 S4 0
Q=0,z=0 Q=1,z=0 Q=2,z=0 Q=3,z=0 0 S5 S5 1
E=0 0 S6 S6 0
E=1 E=0 E=0 E=1 0 S7 S7 0
E=0 E=0 E=0 S8 S8 1
0
1 S1 S2 0
S8 S7 S6 S5 1 S2 S3 0
Q=4,z=0 Q=5,z=0 Q=6,z=0 Q=7,z=0 1 S3 S4 0
1 S4 S5 0
E=0
1 S5 S6 1
E=1 E=1 E=1 1 S6 S7 0
1 S7 S8 0
1 S8 S1 1
The output ‘z’ only depends on the present state  Moore FSM

 State Assignment:  Excitation Table: PRESENT STATE NEXTSTATE

 S1: Q = 000
 S2: Q = 001 E Q2Q1Q0(t) Q2Q1Q0(t+1) z
 S3: Q = 010 0 0 0 0 0 0 0 0
 S4: Q = 011 0 0 0 1 0 0 1 0
 S5: Q = 111 0 0 1 0 0 1 0 0
 S6: Q = 110 0 0 1 1 0 1 1 0
 S7: Q = 101
0 1 1 1 1 1 1 1
 S8: Q = 100
0 1 1 0 1 1 0 0
0 1 0 1 1 0 1 0
0 1 0 0 1 0 0 1
1 0 0 0 0 0 1 0
1 0 0 1 0 1 0 0
1 0 1 0 0 1 1 0
1 0 1 1 1 1 1 0
1 1 1 1 1 1 0 1
1 1 1 0 1 0 1 0
1 1 0 1 1 0 0 0
1 1 0 0 0 0 0 1
1 Instructor: Daniel Llamocca
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 lOMoARcPSD|43202152

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY

ECE-378: Digital Logic and Microprocessor Design Winter 2015

 Excitation equations and minimization: Q2(t+1) Q1(t+1)

EQ2 EQ2
00 01 11 10 00 01 11 10
𝑄2 (𝑡 + 1) = 𝐸̅ 𝑄2 + 𝑄1 𝑄2 + 𝑄0 𝑄2 + 𝐸𝑄1 𝑄0 Q1 Q0 Q1 Q0
00 0 1 0 0 00 0 0 0 0
̅̅̅2̅𝑄1 + 𝐸𝑄
𝑄1 (𝑡 + 1) = 𝐸̅ 𝑄1 + 𝑄1 𝑄0 + 𝑄 ̅̅̅2̅𝑄0

𝑄0 (𝑡 + 1) = 𝐸̅ 𝑄0 + 𝐸𝑄1 ̅𝑄̅̅0̅ + 𝐸𝑄
̅̅̅2̅(𝑄1 + 𝑄
̅̅̅0̅) 01 0 1 1 0 01 0 0 0 1

̅̅̅1 𝑄
𝑧=𝑄 ̅̅̅0̅𝑄2 + 𝑄1 𝑄0 𝑄2 = 𝑄2 (𝑄
̅̅̅̅̅̅̅̅̅
1 𝑄0 )
11 0 1 1 1 11 1 1 1 1

10 0 1 1 0 10 1 1 0 1

Q0(t+1) z
EQ2 EQ2
00 01 11 10 00 01 11 10
Q1 Q0 Q 1 Q0
00 0 0 0 1 00 0 1 1 0

01 1 1 0 0 01 0 0 0 0

11 1 1 0 1 11 0 1 1 0

10 0 0 1 1 10 0 0 0 0

 Circuit Implementation:
resetn
clk
E

D Q Q2

D Q Q1

D Q Q0

2 Instructor: Daniel Llamocca

Downloaded by ?? ? (pinelee98@gmail.com)
 lOMoARcPSD|43202152

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY

ECE-378: Digital Logic and Microprocessor Design Winter 2015

PROBLEM 2 (15 PTS) resetn

 Sequence detector (with overlap):
Draw the state diagram (both normal FSM representation and ASM chart) of a x z
circuit (with an input 𝑥) that detects the following sequence: 00110101. The FINITE STATE
MACHINE
detector must assert an output 𝑧 when the sequence is detected.
clock

resetn=0
S1

1 resetn = 0 x/z 1/0 0/0

x 0/0
0
S2 0/0 0/0 1/0
S1 S2 S3 S4
1/0
1 1/0 0/0
x 1/1 1/0 1/0
0/0
0
S3 S8 S7 S6 S5
0/0 1/0 0/0

0
x
1
S4

0
x
1
S5

1
x
0
S6

0
x
1
S7

1
x
0
S8

0 1
x z1

3 Instructor: Daniel Llamocca

Downloaded by ?? ? (pinelee98@gmail.com)
 lOMoARcPSD|43202152

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY

ECE-378: Digital Logic and Microprocessor Design Winter 2015

PROBLEM 3 (30 PTS)

 Complete the timing diagram of the following FSM (represented as an ASM chart). (10 pts)

resetn=0
S1
sclr  1 clock

0 resetn
s
1 s
S2

0
z E1 sclr
1

sclr  1
E

S3
wt  1
state S1 S1 S1 S2 S2 S2 S3 S4 S4 S1 S2 S2 S2 S3

wt
1
z
0 done
S4
done  1

0 1
s

4 Instructor: Daniel Llamocca

Downloaded by ?? ? (pinelee98@gmail.com)
 lOMoARcPSD|43202152

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY

ECE-378: Digital Logic and Microprocessor Design Winter 2015

 Complete the timing diagram of the following FSM. Is this a Mealy or a Moore machine? Why? (5 pts)
resetn = 0
x/z
1/0 clock

1/1
0/1 resetn
S1 S2
0/0 x
1/0 0/0
state S1 S1 S1 S2 S3 S4 S1 S2 S1 S1
S4 S3 0/1
1/1
z
The output ‘z’ does not depend on the input ‘x’  It is a Moore-type FSM.

 Provide the state diagram (in ASM form) and complete the timing diagram of the FSM whose VHDL description is listed
below. (15 pts)

library ieee; architecture behavioral of circ is

use ieee.std_logic_1164.all; type state is (S1, S2, S3);
signal y: state;
entity circ is begin
port ( clk, resetn: in std_logic; Transitions: process (resetn, clk, a, b)
a, b: in std_logic; begin
x,w,z: out std_logic); if resetn = '0' then y <= S1;
end circ; elsif (clk'event and clk = '1') then
resetn=0 case y is
S1 when S1 =>
if a = '1' then
if b = ‘1’ then y <= S3; else y <= S1; end if;
else
y <= S2;
1 0 end if;
a b

0 1 when S2 =>
if a = '1' then y <= S3; else y <= S2; end if;
z1
when S3 =>
S2 if b = '1' then y <= S1; else y <= S3; end if;
end case;
w1 end if;
end process;

0 Outputs: process (y, a, b)

a begin
1 x <= ‘0’; w <= ‘0’; z <= ‘0’;
S3 case y is
when S1 => if a = ‘0’ then z <= ‘1’; end if;
when S2 => w <= ‘1’;
when S3 => if b = ‘1’ then x <= '1'; end if;
1 0 end case;
x1 b end process;
end behavioral;

clk

resetn

state S1 S1 S2 S2 S3 S1 S2 S3 S1 S1 S3 S1 S2 S2 S3 S3 S1

5 Instructor: Daniel Llamocca

Downloaded by ?? ? (pinelee98@gmail.com)
 lOMoARcPSD|43202152

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY

ECE-378: Digital Logic and Microprocessor Design Winter 2015

PROBLEM 4 (20 PTS)

 Complete the timing diagram of the following digital circuit that includes an FSM (in ASM form) and a datapath circuit.
resetn=0
data 0010 S1
4 E1

1 0
0
4 4 s sclr  1

0
+ p 1

resetn 4 S2
E1
E
sclr
0
z

4 1
Q sclr: synchronous clear
If E=sclr=1, then Q = 0 sclr  1
p E sclr
S3
z done  1
s FINITE STATE
MACHINE done
clock
0 1
s

clock

resetn

data 0101 0011 1000

Q 0000 0000 0101 0111 1001 1011 1101 1111 0000 0000 0000 1000 1010 1100 1110 0000 0010

sclr

state S1 S1 S2 S2 S2 S2 S2 S2 S3 S3 S1 S2 S2 S2 S2 S2 S2

done

PROBLEM 5 (15 PTS)

 Attach a printout of your Project Status Report (no more than three pages, single-spaced, 2 columns). This report should
contain the current status of the project. You MUST use the provided template (Final Project – Report
Template.docx).

6 Instructor: Daniel Llamocca

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