Enpirion® Power Datasheet

EN5322QI 2A PowerSoC
Synchronous Buck DC-DC Converter
with Integrated Inductor
General Description Ordering Information
The EN5322 is a high efficiency synchronous Part Number Temp Rating (°C) Package
buck converter with integrated inductor, PWM EN5322QI -40 to +85 24-pin QFN T&R
EVB-EN5322QI QFN Evaluation Board
controller, MOSFETS, and compensation
providing the smallest possible solution size.
Features
The 4 MHz operation allows for the use of tiny
MLCC capacitors. It also enables a very wide • Revolutionary Integrated Inductor
control loop bandwidth providing excellent • Total Solution Footprint as Small as 50 mm2
transient performance and reduced output • 4 mm x 6 mm x 1.1 mm QFN Package
impedance. The internal compensation is • 4 MHz Fixed Switching Frequency
designed for unconditional stability across all
operating conditions. • High Efficiency, up to 95 %
• Low Ripple Voltage; 8 mVP-P Typical
Three VID output voltage select pins provide • 2% Initial VOUT Accuracy with VID Codes
seven pre-programmed output voltages along • 2% Initial 0.6 V Feedback Voltage Accuracy
with an option for external resistor divider.
Output voltage can be programmed on-the-fly to • 2.4 V to 5.5 V Input Voltage Range
provide fast, dynamic voltage scaling with • 2 A Continuous Output Current Capability
smooth transitions between VID programmed • Fast Transient Response
output voltages. • Low Dropout Operation: 100 % Duty Cycle
• Power OK Signal with 5 mA Sink Capability
Applications • Dynamic Voltage Scaling with VID Codes
• Point of Load Regulation for Low Power • 17 A Typical Shutdown Current
Processors, Network Processors, DSPs’ • Under Voltage Lockout, Over Current, Short
FPGAs and ASICs
Circuit, and Thermal Protection
• Replacement of LDOs
• Noise Sensitive Applications such as A/V and • RoHS Compliant; MSL 3 260 °C Reflow
RF
• Computing, Computer Peripherals, Storage, Application Circuit
Networking, and Instrumentation
• DSL, STB, DVR, DTV, and iPC ON

VIN OFF ENABLE

VSENSE VOUT
PVIN VOUT
CIN VS0
VS1 EN5322 POK COUT
10 uF VS2 47 uF
PGND PGND
AVIN AGND

1 uF

Figure 1. Typical Application Circuit

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Absolute Maximum Ratings

CAUTION: Absolute maximum ratings are stress ratings only. Functional operation beyond recommended operating
conditions is not implied. Stress beyond absolute maximum ratings may cause permanent damage to the device.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability.

Absolute Maximum Electrical Ratings MIN MAX

Voltages on: PVIN, AVIN, VOUT -0.3 V 6.5 V
Voltages on: VSENSE, VS0, VS1, VS2, ENABLE, POK -0.3 V VIN
Voltage on: VFB -0.3 V 2.7 V
ESD Rating (Human Body Model) 2 kV
ESD Rating (Charge Device Model) 500 V
Absolute Maximum Thermal Ratings
Ambient Operating Range -40 °C +85 °C
Storage Temperature Range -65 °C +150 °C
Reflow Peak Body Temperature MSL3 (10 s) +260 °C

Thermal Characteristics
PARAMETER SYMBOL MIN TYP MAX UNITS
Thermal Shutdown TSD 155 °C
Thermal Shutdown Hysteresis TSDH 15 °C
Thermal Resistance: Junction to Case (0 LFM) JC 6 °C/W
Thermal Resistance: Junction to Ambient (0 LFM)* JA 36 °C/W
* Based on a 2 oz. copper board and proper thermal design in line with JEDEC EIJ-JESD51 standards

Recommended Operating Conditions

PARAMETER SYMBOL MIN MAX UNITS
Input Voltage Range VIN 2.4 5.5 V
Output Voltage Range VOUT 0.6 VIN - VDROPOUT V
Output Current ILOAD 0 2 A
Operating Junction Temperature TJ -45 +125 °C
Note: VDROPOUT is defined as (ILOAD x Dropout Resistance) including temperature effect.

Electrical Characteristics
VIN = 5 V and TA = 25 °C, unless otherwise noted.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Operating Input Voltage VIN 2.4 5.5 V
Under Voltage Lockout VUVLO VIN going low to high 2.2 V
UVLO Hysteresis 0.15 V
Output Voltage with VID TA = 25 °C; VIN = 5V
Codes (Note 1) ILOAD = 100 mA
VS2 VS1 VS0 VOUT (V)
0 0 0 3.3 -2.0 +2.0
0 0 1 2.5 -2.0 +2.0
VOUT
0 1 0 1.8 -2.0 +2.0
%
0 1 1 1.5 -2.0 +2.0
1 0 0 1.25 -2.0 +2.0
1 0 1 1.2 -2.0 +2.0
1 1 0 0.8 -2.0 +2.0

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PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

TA = 25 °C; VIN = 5V
VFB Voltage VFB 0.588 0.600 0.612 V
ILOAD = 100 mA, VS0 = VS1 = VS2 = 1
Output Voltage with VID
Codes (Note 1) 2.4 V  VIN  5.5 V, ILOAD = 0 ~ 2 A,
-40°C  TA  +85°C
VS2 VS1 VS0 VOUT (V)
0 0 0 3.3 -3.0 +3.0
0 0 1 2.5 -3.0 +3.0
VOUT
0 1 0 1.8 +3.0
%
-3.0
0 1 1 1.5 -3.0 +3.0
1 0 0 1.25 -3.0 +3.0
1 0 1 1.2 -3.0 +3.0
1 1 0 0.8 -3.5 +3.0

2.4 V  VIN  5.5 V, ILOAD = 0 ~ 2 A,

VFB Voltage VFB VS0 = VS1 = VS2 = 1, 0.582 0.600 0.618 V
-40°C  TA  +85°C
Dynamic Voltage Slew Rate Switching between VID settings 0.975 1.5 2.025 V/ms
Soft Start Slew Rate VID Mode VOUT Programming 0.975 1.5 2.025 V/ms
Soft Start Time VFB Mode VOUT Programming 0.78 1.2 1.62 ms
VFB, ENABLE, VS0-VS2
-40°C  TA  +85°C +/-40 nA
Pin Input Current (Note 2)
ENABLE, VS0-VS2 Voltage Logic Low 0.0 0.4
V
Threshold Logic High 1.4 VIN
POK Upper Threshold VOUT Rising 111 %
POK Upper Threshold VOUT Falling 102 %
POK Lower Threshold VOUT Rising 92 %
POK Lower Threshold VOUT Falling 90 %
POK Low Voltage ISINK = 5 mA, -40°C  TA  +85°C 0.15 0.4 V
POK Pin VOH Leakage
POK High, -40°C  TA  +85°C 500 nA
Current
Shutdown Current ENABLE Low 17 A
Quiescent Current No Switching 800 A
Quiescent Current Switching, VOUT = 1.2 V 15 mA
2.4 V  VIN  5.5 V,
Current Limit Threshold 2.1 3.0 A
-40°C  TA  +85°C
PFET On Resistance 160 m
NFET On Resistance 60 m
Dropout Resistance 200 300 m
Operating Frequency FOSC 4 MHz
COUT = 1 x 47 F 1206 X5R MLCC,
14 mVP-P
VOUT = 1.2 V, ILOAD = 2 A
Output Ripple Voltage VRIPPLE
COUT = 2 x 22 F 0805 X5R MLCC,
8 mVP-P
VOUT = 1.2 V, ILOAD = 2 A
Note 1: The tolerances hold true only if VIN is greater than (VOUT + VDROPOUT).
Note 2: VFB, ENABLE, VS0-VS2 pin input current specification is guaranteed by design.

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Pin Configuration

Figure 2. Pin Diagram, Top View.

Pin Description

PIN NAME FUNCTION

No Connect. These pins are internally connected to the common drain output of the internal
MOSFETs. NC(SW) pins are not to be electrically connected to any external signal, ground, or
1, 21-24 NC(SW)
voltage. However, they must be soldered to the PCB. Failure to follow this guideline may result
in part malfunction or damage.
Input/Output Power Ground. Connect these pins to the ground electrode of the input and
2-3, 8-9 PGND
output filter capacitors. Refer to Layout Considerations section for details.
4-7 VOUT Voltage and Power Output. Connect these pins to output capacitor(s).
Output Voltage Select. These pins set one of seven preset output voltages and the external
10-12 VS2-0 divider option (refer to Electrical Characteristics table for more details), and can be directly
pulled up to VIN or pulled down to GND; these pins must not be left floating.
Sense Pin for Internally Programmed Output Voltages with VID Codes. For either VID code or
13 VSENSE external resistor divider applications, connect this pin to the last local output filter capacitor for
internal compensation.
Feedback Pin for External Voltage Divider Network. Connect a resistor divider to this pin to set
14 VFB
the output voltage. Use 340 k, 1% or better for the upper resistor.
15 AGND Analog Ground for the Controller Circuits
Analog Voltage Input for the Controller Circuits. Connect this pin to the input power supply.
16 AVIN
Use a 1 F bypass capacitor on this pin.
17 POK Power OK with an Open Drain Output. Refer to Power OK section.
Input Enable. A logic high signal on this pin enables the output and initiates a soft start. A
logic low signal disables the output and discharges the output to GND. The ENABLE pin
18 ENABLE should not be left floating as it could be in an unknown and random state. It is recommended
to enable the device after both PVIN and AVIN is in regulation. See ENABLE operation for
details.

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PIN NAME FUNCTION
19-20 PVIN Input Power Supply. Connect to input supply. Decouple with input capacitor(s) to PGND.

Functional Block Diagram

POK PVIN

UVLO
POK
Thermal Limit

Current Limit

ENABLE Soft Start NC (SW)

P-Drive

(-) Logic VOUT

PWM
Comp N-Drive
(+)
PGND

VSENSE
Sawtooth
Generator
Compensation
Network

(-) Switch
Error VFB
Amp
(+)

DAC

Voltage
BIAS VREF
Select

Package Boundary
AVIN AGND
VS0 VS1 VS2

Figure 3. Functional Block Diagram.

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RPOK* 100k
ON
POK
OFF
VIN ENABLE
VSENSE VOUT
PVIN VOUT
CIN VS0
VS1 EN5322 POK COUT
10 uF VS2 47 uF
PGND PGND
AVIN AGND

1 uF

* Leave RPOK open if the POK function is not used.

Figure 4. Typical Application Circuit with VID Codes.
(NOTE: Enable can be separated from PVIN if the application requires it)

Typical Performance Characteristics

Circuit of Figure 4, VIN = 5 V, VOUT = 1.2 V and TA = 25°C, unless otherwise noted.

Efficiency vs. Load Current (Vin = 5.0V) Efficiency vs. Load Current (Vin = 3.3V)

95 95
90 90
85 85
Efficiency (%)

Efficiency (%)

80 80
75 75
70 70
65 65
60 60
55 55
50 50
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00

Load Current (A) Load Current (A)

Top to Bottom: VOUT = 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V,
0.8 V Top to Bottom: VOUT = 2.5 V, 1.8 V, 1.5 V, 1.2 V, 0.8 V

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Quiescent Current (No Switching) vs. Quiescent Current (Switching) vs.

Input Voltage Input Voltage

Quiescent Current (mA)

840 18
Quiescent Current (uA)

820 16

800 14

780 12

760 10

740 8
2 3 4 5 6 2 3 4 5 6

Input Voltage (V) Input Voltage (V)

Load Regulation (Vin = 5 V) Load Regulation (Vin = 5 V)

1.208 3.304
Output Voltage (V)

1.204
Output Voltage (V)

3.300
1.200
3.296
1.196
3.292
1.192

1.188 3.288

1.184 3.284
0 0.4 0.8 1.2 1.6 2 0 0.4 0.8 1.2 1.6 2
Load Current (A) Load Current (A)

Output Ripple at 2 A Load (CH2: VOUT) Output Ripple at 2 A Load (CH2: VOUT)
VIN = 3.3 V, VOUT = 1.2 V, COUT = 1 x 47 F VIN = 3.3 V, VOUT = 1.2 V, COUT = 2 x 22 F

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Transient Response at VIN = 5 V Transient Response at VIN = 5 V

VOUT = 1.2V, COUT = 1 x 47 F VOUT = 3.3V, COUT = 1 x 47 F
(0-2 A Load Step, slew rate ≥ 10A/uS) (0-2 A Load Step, slew rate ≥ 10A/uS)
CH1: VOUT, CH4: ILOAD CH1: VOUT, CH4: ILOAD

VOUT Scaling with VID Codes at VIN = 5 V VOUT Scaling with VID Codes at VIN = 3.3 V
(VOUT = 1.2 V – 2.5 V, IOUT = 0 – 2 A) (VOUT = 1.2 V – 2.5 V, IOUT = 0 – 2 A)
CH1: VS2, CH2: VOUT, CH3: POK CH1: VS2, CH2: VOUT, CH3: POK

Power Up/Down at No Load (VIN = 5 V, VOUT = 1.2 V) Power Up/Down at 0.6  Load (VIN = 5 V, VOUT = 1.2 V)
CH1: ENABLE, CH2: VOUT, CH3: POK, CH4: IINDUCTOR CH1: ENABLE, CH2: VOUT, CH3: POK, CH4: IINDUCTOR

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Output Over Load at No Load (VIN = 5 V, VOUT = 1.2 V) Output Over Load at 2 A Load (VIN = 5 V, VOUT = 1.2 V)
CH2: VOUT, CH3: POK, CH4: IINDUCTOR CH2: VOUT, CH3: POK, CH4: IINDUCTOR

Output Over Load at No Load (VIN = 5 V, VOUT = 1.2 V) Output Over Load at 2 A Load (VIN = 5 V, VOUT = 1.2 V)
CH2: VOUT, CH3: POK, CH4: IINDUCTOR CH2: VOUT, CH3: POK, CH4: IINDUCTOR

Functional Description
The EN5322 leverages advanced CMOS The converter uses voltage mode control to
technology to provide high switching provide high noise immunity, low output
frequency, while also maintaining high impedance and excellent load transient
efficiency. response. No external compensation
components are needed for most applications.
Packaged in a 4 mm x 6 mm x 1.1 mm QFN,
the EN5322 provides a high degree of flexibility Output voltage is chosen from one of seven
in circuit design while maintaining a very small preset values via a three-pin VID voltage select
footprint. High switching frequency allows for scheme. An external divider option enables the
the use of very small MLCC input and output selection of any output voltage  0.6 V. The
filter capacitors. VID pins can be toggled dynamically to

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implement glitch-free dynamic voltage scaling Excess bulk capacitance on the output of the
between any two VID preset values. device can cause an over-current condition at
startup.
POK monitors the output voltage and signals if When operating in VID mode, the maximum
it is within ±10% of nominal. Protection total capacitance on the output, including the
features include under voltage lockout (UVLO), output filter capacitor and bulk and decoupling
over current protection, short circuit protection, capacitance, at the load, is given as:
and thermal overload protection.
COUT_TOTAL_MAX = COUT_Filter + COUT_BULK =
Stability over Wide Range of Operating 1000uF
Conditions
The EN5322 utilizes an internal compensation When the EN5322QI output voltage is
network and is designed to provide stable programmed using and external resistor divider
operation over a wide range of operating the maximum total capacitance on the output is
conditions. To improve transient performance given as:
or reduce output voltage ripple with dynamic
COUT_TOTAL_MAX = 1.867x10-3/VOUT Farads
loads you have the option to add
supplementary capacitance to the output.
When programming VOUT using the VID pins, The above number and formula assume a no
the EN5322 is stable with up to 60 F of output load condition at startup.
capacitance without compensation adjustment.
Additional output capacitance above 60 F can Over Current/Short Circuit Protection
be accommodated with compensation When an over current condition occurs, VOUT is
adjustment depending on the application. pulled low. This condition is maintained for a
When programming VOUT with the resistor period of 1.2 ms and then a normal soft start
divider option, the maximum output cycle is initiated. If the over current condition
capacitance may be limited. Please refer to still persists, this cycle will repeat.
the section on soft start for more details. The
high switching frequency allows for a wide Under Voltage Lockout
control loop bandwidth.
An under voltage lockout circuit will hold off
switching during initial power up until the input
Soft Start
voltage reaches sufficient level to ensure
The EN5322QI has an internal soft-start circuit proper operation. If the voltage drops below the
that controls the ramp of the output voltage. UVLO threshold the lockout circuitry will again
The control circuitry limits the VOUT ramp rate to disable switching. Hysteresis is included to
levels that are safe for the Power MOSFETS prevent chattering between UVLO high and low
and the integrated inductor. states.

The EN5322QI has two soft start operating

Enable
modes. When VOUT is programmed using a The ENABLE pin provides means to shut down
preset voltage in VID mode, the device has a the converter or initiate normal operation. A
constant slew rate. When the EN5322QI is logic high will enable the converter to go
configured in external resistor divider mode, through the soft start cycle and regulate the
the device has a constant VOUT ramp time. output voltage to the desired value. A logic low
Output voltage slew rate and ramp time is will allow the device to discharge the output
given in the Electrical Characteristics Table. and go into shutdown mode for minimal power
consumption. When the output is discharged,
an auxiliary NFET turns on and limits the

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discharge current to 300 mA or below. In Thermal Shutdown
shutdown mode, the device typically drains When excessive power is dissipated in the
17A. The ENABLE pin should not be left device, its junction temperature rises. Once the
floating as it could be in an unknown and junction temperature exceeds the thermal
random state. It is recommended to enable the shutdown temperature 155 °C, the thermal
device after both PVIN and AVIN is in shutdown circuit turns off the converter,
regulation. At extremely cold conditions below allowing the device to cool. When the junction
-30°C, the controller may not be properly temperature drops 15 °C, the device will be re-
powered if ENABLE is tied directly to AVIN enabled and go through a normal startup
during startup. It is recommended to use an process.
external RC circuit to delay the ENABLE
voltage rise so that the internal controller has Power OK
time to startup into regulation (see circuit The EN5322 provides an open drain output to
below). The RC circuit may be adjusted so that indicate if the output voltage stays within 92%
AVIN and PVIN are above UVLO before to 111% of the set value. Within this range, the
ENABLE is high. The startup time will be POK output is allowed to be pulled high.
delayed by the extra time it takes for the Outside this range, POK remains low.
capacitor voltage to reach the ENABLE However, during transitions such as power up,
threshold. power down, and dynamic voltage scaling, the
POK output will not change state until the
AVIN
transition is complete for enhanced noise
immunity.

The POK has 5 mA sink capability for events

1k where it needs to feed a digital controller with
standard CMOS inputs. When POK is pulled
ENABLE high, the pin leakage current is as low as 500
nA maximum over temperature. This allows a
large pull up resistor such as 100 k to be
used for minimal current consumption in
1µF shutdown mode.

The POK output can also be conveniently used

as an ENABLE input of the next stage for
power sequencing of multiple converters.
Figure 5: ENABLE Delay Circuit

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RPOK* 100k
POK
ON

VIN OFF ENABLE

VSENSE VOUT
PVIN VOUT
CIN VS0
VS1 EN5322 POK Ra COUT
10 uF 340k
VS2 47 uF
PGND VFB

AVIN AGND PGND

1 uF Rb

* Leave RPOK open if the POK function is not used.

Figure 6. Typical Application Circuit with External Resistor Divider.
(NOTE: Enable can be separated from PVIN if the application requires it)

Application Information
values is indeterminate. These pins must not
Setting the Output Voltage be left floating.
To provide the highest degree of flexibility in
choosing output voltage, the EN5322QI uses a Table 1. VID voltage select settings.
3 pin VID (Voltage ID) output voltage select
arrangement. This allows the designer to VS2 VS1 VS0 VOUT
choose one of seven preset voltages, or to use 0 0 0 3.3V
an external voltage divider. Figure 4 shows a 0 0 1 2.5V
typical application circuit with VID codes. 0 1 0 1.8V
Internally, the output of the VID multiplexer 0 1 1 1.5V
sets the value for the voltage reference DAC, 1 0 0 1.25V
which in turn is connected to the non-inverting 1 0 1 1.2V
input of the error amplifier. This allows the use 1 1 0 0.8V
of a single feedback divider with constant loop User
1 1 1
gain and optimum compensation, independent Selectable
of the output voltage selected.

Table 1 shows the various VS0-VS2 pin logic External Voltage Divider
states and the associated output voltage As described above, the external voltage
levels. A logic “1” indicates a connection to VIN divider option is chosen by connecting the
or to a “high” logic voltage level. A logic “0” VS0, VS1, and VS2 pins to VIN or logic “high”.
indicates a connection to ground or to a “low” The EN5322QI uses a separate feedback pin,
logic voltage level. These pins can be either VFB, when using the external divider. VSENSE
hardwired to VIN or GND or alternatively can be must be connected to VOUT as indicated in
driven by standard logic levels. Logic low is Figure 6.
defined as VLOW  0.4V. Logic high is defined
as VHIGH  1.4V. Any level between these two If the external voltage divider option is chosen,
use 340 k, 1% or better for the upper resistor
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Ra. Then the value of the bottom resistor Rb in A 10 F, 10 V, 0805 MLC capacitor is needed
k is given as: on PVIN for all applications. A 1 F, 10 V, 0402
MLC capacitor on AVIN is needed for high
204 frequency bypass to ensure clean chip supply
Rb  k
VOUT  0.6 for optimal performance.

Where VOUT is the output voltage. Rb should A 47 F, 6.3 V, 1206 MLC capacitor is
also be a 1% or better resistor. recommended on the output for most
applications. The output ripple can be reduced
Power-Up/Down Sequencing by approximately 50% by using 2 x 22 F,
6.3V, 0805 MLC capacitors rather than 1 x 47
During power-up, ENABLE should not be
F.
asserted before PVIN, and PVIN should not be
asserted before AVIN. The PVIN should never
As described in the Soft Start section, there is
be powered when AVIN is off. During power
a limitation on the maximum bulk capacitance
down, the AVIN should not be powered down
that can be placed on the output of this device.
before the PVIN. It is recommended to follow
Please refer to that section for more details.
the power-up and power-down sequencing to
ensure that the EN5322QI is always sufficiently
powered before the device begins operation.

Pre-Bias Start-up Table 2. Recommended input and output capacitors

Description Mfg. P/N
The EN5322QI does not support startup into a CIN 10F, 10V, Taiyo Yuden LMK212BJ106KG
pre-biased condition. Be sure the output X5R, 10%, Murata GRM21BR71A106KE51L
0805 Panasonic ECJ-2FB1A106K
capacitors are not charged or the output of the COUT 47F, 6.3V, Taiyo Yuden JMK316BJ476ML
EN5322QI is not pre-biased when the X5R, 20%, Murata GRM31CR60J476ME19L
1206 Kemet C1206C476M9PACTU
EN5322QI is first enabled.

Input and Output Capacitor Selection

POK Pull Up Resistor Selection
Low ESR MLC capacitors with X5R or X7R or
POK can be pulled up through a resistor to any
equivalent dielectric should be used for input
voltage source as high as VIN. The simplest
and output capacitors. Y5V or equivalent
way is to connect POK to the power input of
dielectrics lose too much capacitance with
frequency, DC bias, and temperature. the converter through a resistor. A 100 k pull
Therefore, they are not suitable for switch- up resistor is typically recommended for most
mode DC-DC converter filtering, and must be applications for minimal current drain from the
avoided. voltage source and good noise immunity. POK
can sink up to 5mA.

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Layout Recommendations
spokes to connect the vias to the ground plane.
This connection provides the path for heat
dissipation from the converter.
Recommendation 4: Multiple small vias (the same
size as the thermal vias discussed in
recommendation 3) should be used to connect
ground terminal of the input capacitor and output
capacitors to the system ground plane. It is
preferred to put these vias along the edge of the
GND copper closest to the +V copper. These vias
connect the input/output filter capacitors to the
GND plane, and help reduce parasitic inductances
in the input and output current loops.
Recommendation 5: AVIN is the power supply for
the small-signal control circuits. It should be
connected to the input voltage at a quiet point. In
Figure 7 this connection is made at the input
Figure 7. Optimized Layout Recommendations
capacitor. Connect a 1µF capacitor from the AVIN
pin to AGND.
Recommendation 6: The layer 1 metal under the
Recommendation 1: Input and output filter device must not be more than shown in Figure 7.
capacitors should be placed on the same side of See the section regarding exposed metal on bottom
the PCB, and as close to the EN5322QI package of package. As with any switch-mode DC/DC
as possible. They should be connected to the converter, try not to run sensitive signal or control
device with very short and wide traces. Do not use lines underneath the converter package on other
thermal reliefs or spokes when connecting the layers.
capacitor pads to the respective nodes. The +V and
Recommendation 7: The VOUT sense point should
GND traces between the capacitors and the
be just after the last output filter capacitor. Keep the
EN5322QI should be as close to each other as
sense trace short in order to avoid noise coupling
possible so that the gap between the two nodes is
into the node.
minimized, even under the capacitors.
Recommendation 8: Keep RA, RB close to the VFB
Recommendation 2: The system ground plane
pin (See Figures 7). The VFB pin is a high-
should be the first layer immediately below the
impedance, sensitive node. Keep the trace to this
surface layer. This ground plane should be
pin as short as possible. Whenever possible,
continuous and un-interrupted below the converter
connect RB directly to the AGND pin instead of
and the input/output capacitors.
going through the GND plane.
Recommendation 3: The thermal pad underneath
Recommendation 9: Altera provides schematic
the component must be connected to the system
and layout reviews for all customer designs. Please
ground plane through as many vias as possible.
contact local sales representatives for references to
The drill diameter of the vias should be 0.33mm,
Power Applications Engineering support
and the vias must have at least 1 oz. copper plating
(www.altera.com/mysupport).
on the inside wall, making the finished hole size
around 0.20-0.26mm. Do not use thermal reliefs or

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 EN5322QI

Design Considerations for Lead-Frame Based Modules

Exposed Metal Pads on Package Bottom

QFN lead-frame based package technology utilizes exposed metal pads on the bottom of the
package that provide improved thermal dissipation and low package thermal resistance,
smaller package footprint and thickness, large lead size and pitch, and excellent lead co-
planarity. As the EN5322 package is a fully integrated module consisting of multiple internal
devices, the lead-frame provides circuit interconnection and mechanical support of these
devices resulting in multiple exposed metal pads on the package bottom.

Only the two large thermal pads and the perimeter leads are to be mechanically/electrically
connected to the PCB through a SMT soldering process. All other exposed metal is to remain
free of any interconnection to the PCB. Figure 8 shows the recommended PCB metal layout
for the EN5322 package. A GND pad with a solder mask "bridge" to separate into two pads
and 24 signal pads are to be used to match the metal on the package. The PCB should be
clear of any other metal, including traces, vias, etc., under the package to avoid electrical
shorting.

Figure 8. Recommended Footprint for PCB.

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 EN5322QI

Package and Mechanical

Figure 9. EN5322QI Package Dimensions

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 EN5322QI

Revision History

Change(s) from Datasheet Rev F to Rev G in February 2014

- ENABLE functional description has been rewritten and updated to include delay circuit…………… Page 11

Change(s) from Datasheet Rev G to Rev H in February 2014

- Updated Typical Application Circuits to show that ENABLE is best toggled after PVIN is stable…......Page 1
- Updated Power Up/Down Sequencing description……………………….……………………..………...Page 13

Contact Information
Altera Corporation
101 Innovation Drive
San Jose, CA 95134
Phone: 408-544-7000
www.altera.com

© 2014 Altera Corporation—Confidential. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, HARDCOPY, MAX, MEGACORE, NIOS,
QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other
countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's
standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or
liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera.
Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders
for products or services.

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