A brief history of electronics

M.B. Patil
Department of Electrical Engineering
IIT Bombay

(images taken from internet)

M.B.Patil, IIT Bombay

Superposition

* Consider a circuit made up of elements of the following types:

- Resistor (V = R I )
- VCVS (V = ↵ Vc )
- VCCS (I = G Vc )
- CCVS (V = R Ic )
- CCCS (I = Ic )
and independent sources of the following types:
- Independent DC voltage source (V = V0 (constant))
- Independent DC current source (I = I0 (constant))
* Such a circuit is linear, and we can use superposition to obtain its response (currents and voltages) when multiple
independent sources are involved.
* Superposition enables us to consider the independent sources one at a time (with the others deactivated), compute the
desired quantity of interest in each case, and get the net result by adding the individual contributions.
This procedure is generally simpler than considering all independent sources simultaneously.

* What do we mean by “deactivating” an independent source?

- Deactivating an independent current source ) I0 = 0, i.e., replace the current source with an open circuit.
- Deactivating an independent voltage source ) V0 = 0, i.e., replace the voltage source with a short circuit.

M. B. Patil, IIT Bombay

Example 1

2⌦
i1

18 V 4⌦ 3A
Example 1

Case 1: Keep Vs , deactivate Is .

2⌦

2⌦ i1
(1)
i1 4⌦ i1 = 3 A
18 V
18 V 4⌦ 3A

Case 2: Keep Is , deactivate Vs .

2⌦
i1
(1) (2)
inet
1 = i1 + i1 = 3 + 1 = 4 A 2⌦
(2)
4⌦ 3A i1 = 3 A ⇥ = 1A
2⌦+4⌦

M. B. Patil, IIT Bombay

Example 2

12 V
i v 3⌦
1⌦ 6A

2i
Example 2

Case 1: Keep Vs , deactivate Is .

12 V
i v 3⌦
KVL: 12 + 3 i + 2 i + i = 0
1⌦
12 V ) i = 2 A , v(1) = 6 V .
i v 3⌦
2i
1⌦ 6A

2i

Case 2: Keep Is , deactivate Vs .

vnet = v(1) + v(2) = 6 + 9 = 15 V i v 3⌦

KVL: i + (6 + i) 3 + 2 i = 0
1⌦ 6A
)i= 3 A , v(2) = ( 3 + 6) ⇥ 3 = 9 V .
2i

(SEQUEL file: ee101 superposition 2.sqproj)

M. B. Patil, IIT Bombay

SEQUEL Circuit Simulator

www.ee.iitb.ac.in/~sequelnew

M. B. Patil, IIT Bombay

Example 3

Find V1 using superposition.

R1 R2

VS1 V1 VS2

VS1 alone: VS2 alone:

R1 R2 R1 R2

VS1 V1 V1 VS2

(1) R2 (2) R1
V1 = VS1 V1 = VS2
R1 + R2 R1 + R2

(net) (1) (2) R2 R1

V1 = V1 + V1 = VS1 + VS2
R1 + R2 R1 + R2
M. B. Patil, IIT Bombay
Example 3 (again)

Find V1 using superposition.

R1 R2

VS1 V1 VS2
Example 3 (again)

Find V1 using superposition.

R1 R2

R1 R2
VS1 V1 VS2 VS1 VS2
V1

VS1 alone: VS2 alone:

R1 R2 R1 R2
VS1 VS2
V1 V1

(1) R2 (2) R1
V1 = VS1 V1 = VS2
R1 + R2 R1 + R2

(net) (1) (2) R2 R1

V1 = V1 + V1 = VS1 + VS2
R1 + R2 R1 + R2

M. B. Patil, IIT Bombay

Superposition: Why does it work?

R1 V1 R3 V2
A B

Vs R2 Is

M. B. Patil, IIT Bombay

Superposition: Why does it work?

R1 V1 R3 V2
A B

Vs R2 Is

KCL at nodes A and B (taking current leaving a node as positive):

1 1 1
(V1 Vs ) + V1 + (V1 V2 ) = 0 ,
R1 R2 R3
1
Is + (V2 V1 ) = 0 .
R3

Writing in a matrix form, we get (using G1 = 1/R1 , etc.),

  
G1 + G2 + G3 G3 V1 G1 Vs
=
G3 G3 V2 Is

   
V1 G 1 Vs V1 1 G1 Vs
i.e., A = ! =A .
V2 Is V2 Is

M. B. Patil, IIT Bombay

Superposition: Why does it work?

R1 V1 R3 V2
A B

Vs R2 Is

     
V1 1 G1 V s m11 m12 G1 Vs m11 G1 m12 Vs
=A ⌘ = .
V2 Is m21 m22 Is m21 G1 m22 Is

We are now in a position to see why superposition works.

     " (1) # " (2) #

V1 m11 G1 m12 Vs m11 G1 m12 0 V1 V1
= + ⌘ + .
V2 m21 G1 m22 0 m21 G1 m22 Is (1)
V2 V2
(2)

The first vector is the response due to Vs alone (and Is deactivated).

The second vector is the response due to Is alone (and Vs deactivated).
All other currents and voltages are linearly related to V1 and V2
) Any voltage (node voltage or branch voltage) or current can also be computed using superposition.

M. B. Patil, IIT Bombay

Thevenin’s theorem

V1 R2 V2
A B

R1 I0 RL V

C 0
V3 R3

How is V related to the circuit parameters?

Assign node voltages with respect to a reference node.
Let G1 ⌘ 1/R1 , etc. Write KCL equation at each node, taking current leaving the node as positive.

KCL at A : G1 (V1 V3 ) + G2 (V1 V2 ) I0 = 0 ,

KCL at B : G2 (V2 V1 ) + GL (V2 0) = 0,
KCL at C : G1 (V3 V1 ) + G 3 V 3 + I0 = 0.

Write in a matrix form: 2 32 3 2 3

G1 + G2 G2 G1 V1 I0
4 G2 G2 + GL 0 5 4 V2 5 = 4 0 5 ,
G1 0 G1 + G3 V3 I0

i.e., G V = Is . We can solve this matrix equation to get V2 , i.e., the voltage across RL .

M. B. Patil, IIT Bombay

Thevenin’s theorem

V1 R2 V2
A B

R1 I0 RL V

C 0
V3 R3
2 3
G1 + G2 I0 G1
det 4 G2 0 0 5
G1 I0 G1 + G3 1
V2 can be found using Cramer’s rule: V2 = ⌘
det(G) det(G)
2 3
G1 + G2 G2 G1
det(G) = det 4 G2 G2 + GL 0 5
G1 0 G1 + G3
2 3 2 3
G1 + G2 G2 G1 G1 + G2 0 G1
= det 4 G2 G2 0 5 + det 4 G2 GL 0 5
G1 0 G 1 + G3 G1 0 G1 + G3
2 3
G1 + G2 0 G1
= + GL 2 where 2 = det 4 G2 1 0 5.
G1 0 G1 + G3

1 1
i.e., V2 = = (Note: , 1, and 2 are independent of GL ).
det(G) + GL 2
M. B. Patil, IIT Bombay
Thevenin’s theorem

V1 R2 V2
A B

R1 I0 RL V

C 0
V3 R3

1 1
V2 = = .
det(G) + GL 2

1
The “open-circuit” value of V2 is obtained by substituting RL = 1, i.e., GL = 0, leading to V2OC = .

1/ V2OC RL OC
We can now write V2 = = = V2 .
1 + GL 2 / 2 2
1+ RL +
RL
Note that 2 / has units of resistance. Define RTh = 2/ (Thevenin resistance). Then we have
STOP
RL OC
V2 = V .
RL + RTh 2

M. B. Patil, IIT Bombay

Thevenin’s theorem

RL OC
V2 = V .
RL + RTh 2

This is simply a voltage division formula, corresponding to the following “Thevenin equivalent circuit” (with VTh = V2OC ).

RTh

VTh RL V2

This allows us to replace the original circuit with an equivalent, simpler circuit.

R2 RTh

R1 I0 RL VTh RL

R3

M. B. Patil, IIT Bombay

Thevenin’s theorem: RTh
Method 1:
RTh
Circuit A A Is
A
(resistors,
voltage sources,
VTh Vs
current sources,
CCVS, CCCS,
VCVS, VCCS) B B
B
RTh A
Circuit A A
(resistors,
voltage sources, Vs Is
current sources,
CCVS, CCCS,
VCVS, VCCS) B B
B

* Deactivate all independent sources. This amounts to making VTh = 0 in the Thevenin equivalent circuit.
* Often, RTh can be found by inspection of the original circuit (with independent sources deactivated).
* RTh can also be found by connecting a test source to the original circuit (with independent sources
deactivated): RTh = Vs /Is .

M. B. Patil, IIT Bombay

Thevenin’s theorem: RTh
Method 2:
A RTh A

Original Voc Voc

VTh
Circuit

B B

A RTh A

Original Isc Isc

VTh
Circuit

B B

VTh Voc Voc

* For the Thevenin equivalent circuit, Voc = VTh , Isc = = ! RTh = .
RTh RTh Isc
Voc
* In the original circuit, find Voc and Isc ! RTh = .
Isc
* Note: We do not deactivate any sources in this case.

M. B. Patil, IIT Bombay

Thevenin’s theorem: example

6⌦ 2⌦
A
R1 R3

3⌦ R2 RL
9V

B
Thevenin’s theorem: example

6⌦ 2⌦ RTh A 4⌦ A
A
R1 R3

9V
3⌦ R2 RL ⌘ VTh RL ⌘ 3V RL

B
B B

VTh : 6⌦ 2⌦ RTh : 6⌦ 2⌦
A A

3⌦ Voc 3⌦
9V

B B
3⌦
Voc = 9V⇥ RTh = (R1 ! R2 ) + R3 = (3 ! 6) + 2
6⌦ + 3⌦
✓ ◆
1 1×2
= 9V ⇥ = 3V =3× +2 = 4⌦
3 1+2

M. B. Patil, IIT Bombay

Thevenin’s theorem: example

4⌦ A B 4⌦

2⌦ 12 ⌦ 12 ⌦
6A 48 V
Thevenin’s theorem: example

4⌦ A B 4⌦
Voc :
4⌦ A B 4⌦
Voc
2⌦ 12 ⌦ 12 ⌦
6A 48 V 2⌦ 12 ⌦
12 ⌦ 6A 48 V
C i
RTh :
4⌦ A B 4⌦ Note: i = 0 (since there is no return path).
VAB = VA VB
= (VA VC ) + (VC VB )
2⌦ 12 ⌦ 12 ⌦
= VAC + VCB
C = 24 V + 36 V = 60 V
A B
A B
VTh = 60 V
7⌦
⌘ 4⌦
3⌦
) RTh = 7 ⌦ RTh = 7 ⌦
60 V
C

M. B. Patil, IIT Bombay

Graphical method for finding VTh and RTh

I
RTh VTh
I RTh

VTh V

V
VTh

VTh V
I= (Note: negative slope for I versus V plot)
RTh
I = 0 ! V = VTh (same as Voc )
VTh
V =0 ! I = (same as Isc )
RTh
i.e., a plot of I versus V can be used to find VTh and RTh .

(Instead of a voltage source, we could also connect a resistor load (R), vary R, and then plot I versus V .)

M. B. Patil, IIT Bombay

Graphical method for finding VTh and RTh
SEQUEL file: ee101 thevenin 1.sqproj

4⌦ A B 4⌦

2⌦ 12 ⌦ 12 ⌦
6A 48 V
Graphical method for finding VTh and RTh
SEQUEL file: ee101 thevenin 1.sqproj

4⌦ A B 4⌦
10
8

i (Amp)
2⌦ 12 ⌦ 12 ⌦ 6
6A 48 V
4
2
0
Connect a voltage source between A and B.
0 20 40 60
Plot i versus v. v (Volt)

4⌦ A B 4⌦ Voc = 60 V, Isc = 8.57 A

i RTh = Voc /Isc = 7 ⌦
v
2⌦ 12 ⌦ A B
12 ⌦
6A 48 V
VTh = 60 V
7⌦
RTh = 7 ⌦
Voc = intercept on the v-axis. 60 V
Isc = intercept on the i-axis.

M. B. Patil, IIT Bombay

Thevenin’s theorem: example

R1 I1
A
2⌦

2 I1 R2
4⌦

B
Thevenin’s theorem: example

R1 I1
A
2⌦

2 I1 R2
4⌦

VTh = Voc
R1 I1 R1
A A
2⌦ 2⌦

2 I1 R2 Voc R2 Voc VTh = 0

4⌦ 4⌦

B B

M. B. Patil, IIT Bombay

Thevenin’s theorem: example

R1 I1 RTh
A A A
2⌦ 8/3 ⌦
2 I1 R2 VTh 8/3 ⌦
4⌦ 0V

B B B

RTh : Deactivate independent sources, connect a test source.

I1 Vs
2 Is R1 Vs A We need to compute RTh = .
Is
2⌦ Vs Vs 2 Is
KCL: Is + + =0
2 I1 R2 Vs R2 R1
4⌦ Is
✓ ◆ ✓ ◆
1 1 2
! Vs + = Is 1 +
R1 R2 R1
0 B Vs 8
! RTh = = ⌦
Is 3

M. B. Patil, IIT Bombay

Norton equivalent circuit (source transformation)

RTh RTh
A A A A

VTh IN RN VTh Isc IN RN Isc

B B B B

* Consider the open circuit case.

Thevenin circuit: VAB = VTh .
Norton circuit: VAB = IN RN .
) VTh = IN RN .
* Consider the short circuit case.
Thevenin circuit: Isc = VTh /RTh .
Norton circuit: Isc = IN .
VTh
) VTh = RN ! RTh = RN .
RTh

VTh
RN = RTh , IN = RTh = RN , VTh = IN RN
RTh
M. B. Patil, IIT Bombay
Source transformation: example

16 ⌦ 20 ⌦ 6⌦
A

32 V 2A 12 ⌦

B
Source transformation: example

16 ⌦ 20 ⌦ 6⌦ 6⌦ 6⌦
A A A

16 16
32 V 2A 12 ⌦ A 12 ⌦ A 9⌦
9 36 ⌦ 9

B B B

20 ⌦ 6⌦ 36 ⌦ 6⌦ 9⌦ 6⌦
A A A

16 ⌦ 2A 12 ⌦ 64 V 12 ⌦ 16 V
2A

B B B

20 ⌦ 6⌦ 16 ⌦ 20 ⌦ 6⌦ 15 ⌦
A A A

16 ⌦ 12 ⌦ 64 V 12 ⌦ 16 V
4A

B B B
M. B. Patil, IIT Bombay
Maximum power transfer

A
iL
Circuit
(resistors,
voltage sources,
current sources, RL
CCVS, CCCS,
VCVS, VCCS)
B
Maximum power transfer

A
iL
Circuit
(resistors, * Power “transferred” to load is, PL = iL2 RL .
voltage sources,
current sources, RL
* For a given black box, what is the value of RL for
CCVS, CCCS,
VCVS, VCCS) which PL is maximum?
B
* Replace the black box with its Thevenin
RTh A iL equivalent.
VTh 2 ⇥ RL
* iL = , PL = VTh .
VTh RL RTh + RL (RTh + RL )2
dPL
* For = 0 , we need
B dRL
PL
(RTh + RL )2 RL ⇥ 2 (RTh + RL )
Pmax
L = 0,
(RTh + RL )4
i.e., RTh + RL = 2 RL ) RL = RTh .

RL
RL = RTh

M. B. Patil, IIT Bombay

Find RL for which PL is maximum.
3⌦ 2⌦
A
R1 R3
12 V R2 6⌦ RL
2A

B
Find RL for which PL is maximum.
3⌦ 2⌦ Voc : 3⌦ 2⌦
A A
R1 R3 R1 R3
12 V R2 6⌦ RL 12 V 6⌦ 2A
2A R2

B B
RTh : Use superposition to find Voc :
3⌦ 2⌦
A 3⌦ 2⌦ 3⌦ 2⌦
R1 R3 A A
R1 R3 R1 R3
R2 6⌦
12 V 6⌦ 6⌦
R2 R2 2A
B
RTh = (R1 ! R2 ) + R3 = (3 ! 6) + 2 B B
6
✓ ◆ V(1)
oc = 12 ⇥ =8V V(2)
oc = 4 ⌦ ⇥ 2 A = 8 V
1×2 9
=3× +2 = 4⌦ (1) (2)
Voc = Voc + Voc = 8 + 8 = 16 V
1+2

RTh A
PL is maximum when RL = RTh = 4 ⌦
iL

VTh RL ) iL = VTh /(2 RTh ) = 2 A

Pmax
L = 22 ⇥ 4 = 16 W .
B
M. B. Patil, IIT Bombay
Maximum power transfer: simulation results
SEQUEL file: ee101 maxpwr 1.sqproj

RTh A
4⌦ iL

VTh RL vL
16 V

M. B. Patil, IIT Bombay

Maximum power transfer (sinusoidal steady state)

ZTh I

VTh ZL

M. B. Patil, IIT Bombay

Maximum power transfer (sinusoidal steady state)

Let ZL = RL + jXL , ZTh = RTh + jXTh , and I = Im \ . ZTh I

The power absorbed by ZL is, VTh ZL

1
P = Im2 RL
2
2
1 VTh
= RL
2 ZTh + ZL
1 |VTh |2
= RL .
2 (RTh + RL )2 + (XTh + XL )2
For P to be maximum, (XTh + XL ) must be zero. ) XL = XTh .
With XL = XTh , we have,
1 |VTh |2
P= RL ,
2 (RTh + RL )2
which is maximum for RL = RTh .
Therefore, for maximum power transfer to the load ZL , we need,
RL = RTh , XL = XTh , i.e., ZL = Z⇤Th .

M. B. Patil, IIT Bombay

Impedance matching

Input Audio
signal Amp
Impedance matching

Input Audio
signal Amp

1k 1k

✓ ◆
N1 2
8⌦ ⇥ 8⌦
N2

N1 : N2

Calculate the turns ratio to provide maximum power transfer of the audio signal.
✓ ◆ r
N1 2 N1 1000
ZL = Z⇤Th ! ⇥ 8 ⌦ = 1 k⌦ ! = = 11.2
N2 N2 8

M. B. Patil, IIT Bombay

Sinusoidal steady state

t=0
Vm cos !t C Vc

M. B. Patil, IIT Bombay

Sinusoidal steady state

t=0
Vm cos !t C Vc

R (C Vc0 ) + Vc = Vm cos !t , t > 0. (1)

(h) (p)
The solution Vc (t) is made up of two components, Vc (t) = Vc (t) + Vc (t) .
(h)
Vc (t) satisfies the homogeneous di↵erential equation,
R C Vc0 + Vc = 0 , (2)
(h)
from which, Vc (t) = A exp( t/⌧ ) , with ⌧ = RC .
(p)
Vc (t) is a particular solution of (1). Since the forcing function is Vm cos !t, we try
(p)
Vc (t) = C1 cos !t + C2 sin !t .
Substituting in (1), we get,
!R C ( C1 sin !t + C2 cos !t) + C1 cos !t + C2 sin !t = Vm cos !t .

C1 and C2 can be found by equating the coefficients of sin !t and cos !t on the left and right sides.
M. B. Patil, IIT Bombay
Sinusoidal steady state

R Vc (V)
0.2

t=0 2 k⌦
Vm cos !t C Vc 0
Vm = 1 V 0.5 µF
f = 1 kHz
−0.2
0 2 4 6 8 10
(SEQUEL file: ee101 rc5.sqproj) time (ms)

* The complete solution is Vc (t) = A exp( t/⌧ ) + C1 cos !t + C2 sin !t .

* As t ! 1, the exponential term becomes zero, and we are left with Vc (t) = C1 cos !t + C2 sin !t .
* This is known as the “sinusoidal steady state” response since all quantities (currents and voltages) in the
circuit are sinusoidal in nature.
* Any circuit containing resistors, capacitors, inductors, sinusoidal voltage and current sources (of the same
frequency), dependent (linear) sources behaves in a similar manner, viz., each current and voltage in the
circuit becomes purely sinusoidal as t ! 1.

M. B. Patil, IIT Bombay

Sinusoidal steady state: phasors

* In the sinusoidal steady state, “phasors” can be used to represent currents and voltages.
* A phasor is a complex number,
X = Xm 6 ✓ = Xm exp(j✓) ,
with the following interpretation in the time domain.
⇥ ⇤
x(t) = Re X e j!t
⇥ ⇤
= Re Xm e j✓ e j!t
⇥ ⇤
= Re Xm e j(!t+✓)
= Xm cos (!t + ✓)
* Use of phasors substantially simplifies analysis of circuits in the sinusoidal steady state.
* Note that a phasor can be written in the polar form or rectangular form,
X = Xm 6 ✓ = Xm exp(j✓) = Xm cos ✓ + j Xm sin ✓ .
The term !t is always implicit.
Im (X)

X
Xm

✓
Re (X)

M. B. Patil, IIT Bombay

Phasors: examples

Time domain Frequency domain

v1 (t)=3.2 cos (!t+30◦ ) V V1 = 3.2 ! 30◦ = 3.2 exp (j⇡/6) V

i(t) = 1.5 cos (!t + 60◦ ) A I = 1.5 6 ( 2⇡/3) A

= 1.5 cos (!t + ⇡/3 ⇡) A
= 1.5 cos (!t 2⇡/3) A

v2 (t) = 0.1 cos (!t) V V2 = 0.1 6 ⇡ V

= 0.1 cos (!t + ⇡) V

i2 (t) = 0.18 sin (!t) A I2 = 0.18 6 ( ⇡/2) A

= 0.18 cos (!t ⇡/2) A
p
i3 (t) = 2 cos (!t + 45◦ ) A I3 = 1 + j 1 A
p
= 2 ! 45◦ A

M. B. Patil, IIT Bombay

Addition of phasors

Consider addition of two sinusoidal quantities:

v (t) = v1 (t) + v2 (t)
= Vm1 cos (!t + ✓1 ) + Vm2 cos (!t + ✓2 )
Now consider addition of the phasors corresponding to v1 (t) and v2 (t).
V = V1 + V2
= Vm1 e j✓1 + Vm2 e j✓2
In the time domain, V corresponds to ṽ (t), with
⇥ ⇤
ṽ (t) = Re Ve j!t
⇥ ⇤
= Re Vm1 e j✓1 + Vm2 e j✓2 e j!t
⇥ ⇤
= Re Vm1 e j(!t+✓1 ) + Vm2 e j(!t+✓2 )
= Vm1 cos (!t + ✓1 ) + Vm2 cos (!t + ✓2 )

which is the same as v (t).

M. B. Patil, IIT Bombay

Addition of phasors

* Addition of sinusoidal quantities in the time domain can be replaced by addition

of the corresponding phasors in the sinusoidal steady state.
* The KCL and KVL equations,
P
ik (t) = 0 at a node, and
P
vk (t) = 0 in a loop,
amount to addition of sinusoidal quantities and can therefore be replaced by the
corresponding phasor equations,
P
Ik = 0 at a node, and
P
Vk = 0 in a loop.

M. B. Patil, IIT Bombay

Impedance of a resistor

v(t) V

i(t) R I Z

M. B. Patil, IIT Bombay

Impedance of a resistor

v(t) V

i(t) R I Z

Let i(t) = Im cos (!t + ✓).

v (t) = R i(t)
= R Im cos (!t + ✓)
⌘ Vm cos (!t + ✓).
The phasors corresponding to i(t) and v (t) are, respectively,
I = Im 6 ✓ , V = R ⇥ Im 6 ✓ .
We have therefore the following relationship between V and I: V = R ⇥ I.
Thus, the impedance of a resistor, defined as, Z = V/I, is

Z=R +j0

M. B. Patil, IIT Bombay

Impedance of a capacitor

v(t) V

i(t) C I Z

M. B. Patil, IIT Bombay

Impedance of a capacitor

v(t) V

i(t) C I Z

Let v (t) = Vm cos (!t + ✓).

dv
i(t) = C = C ! Vm sin (!t + ✓).
dt
Using the identity, cos ( + ⇡/2) = sin , we get
i(t) = C ! Vm cos (!t + ✓ + ⇡/2).
In terms of phasors, V = Vm 6 ✓, I = !CVm 6 (✓+⇡/2).

I can be rewritten as,

I = !CVm e j(✓+⇡/2) = !CVm e j✓ e j⇡/2 = j!C Vm e j✓ = j!C V

Thus, the impedance of a capacitor, Z = V/I, is Z = 1/(j!C ) ,

and the admittance of a capacitor, Y = I/V, is Y = j!C .

M. B. Patil, IIT Bombay

Impedance of an inductor

v(t) V

i(t) L I Z

M. B. Patil, IIT Bombay

Impedance of an inductor

v(t) V

i(t) L I Z

Let i(t) = Im cos (!t + ✓).

di
v (t) = L = L ! Im sin (!t + ✓).
dt
Using the identity, cos ( + ⇡/2) = sin , we get
v (t) = L ! Im cos (!t + ✓ + ⇡/2).
In terms of phasors, I = Im 6 ✓, V = !LIm 6 (✓+⇡/2).

V can be rewritten as,

V = !LIm e j(✓+⇡/2) = !LIm e j✓ e j⇡/2 = j!L Im e j✓ = j!L I

Thus, the impedance of an indcutor, Z = V/I, is Z = j!L ,

and the admittance of an inductor, Y = I/V, is Y = 1/(j!L) .

M. B. Patil, IIT Bombay

Sources

is (t) Is vs (t) Vs

* An independent sinusoidal current source, is (t) = Im cos (!t + ✓), can be represented by the phasor Im 6 ✓
(i.e., a constant complex number).
* An independent sinusoidal voltage source, vs (t) = Vm cos (!t + ✓), can be represented by the phasor
Vm 6 ✓ (i.e., a constant complex number).
* Dependent (linear) sources can be treated in the sinusoidal steady state in the same manner as a resistor,
i.e., by the corresponding phasor relationship.
For example, for a CCVS, we have,
v (t) = r ic (t) in the time domain.
V = r Ic in the frequency domain.

M. B. Patil, IIT Bombay

Use of phasors in circuit analysis

P P P
* The
P time-domain KCL and KVL equations ik (t) = 0 and vk (t) = 0 can be written as Ik = 0 and
Vk = 0 in the frequency domain.
* Resistors, capacitors, and inductors can be described by V = Z I in the frequency domain, which is similar
to V = R I in DC conditions (except that we are dealing with complex numbers in the frequency domain).
* An independent sinusoidal source in the frequency domain behaves like a DC source, e.g., Vs = constant
(a complex number).
* For dependent sources, a time-domain relationship such as i(t) = ic (t) translates to I = Ic in the
frequency domain.
* Circuit analysis in the sinusoidal steady state using phasors is therefore very similar to DC circuits with
independent and dependent sources, and resistors.
* Series/parallel formulas for resistors, nodal analysis, mesh analysis, Thevenin’s and Norton’s theorems can
be directly applied to circuits in the sinusoidal steady state.

M. B. Patil, IIT Bombay

RL circuit

R I

V m ! 0◦ j!L
RL circuit

R I

V m ! 0◦ j!L

Vm \0
I= ⌘ Im \( ✓),
R + j!L
Vm 1 (!L/R).
where Im = p , and ✓ = tan
R 2 + ! 2 L2
In the time domain, i(t) = Im cos (!t ✓), which lags the source voltage since the peak (or zero) of i(t) occurs
t = ✓/! seconds after that of the source voltage.
For R = 1 ⌦, L = 1.6 mH, f = 50 Hz, ✓ = 26.6 , tlag = 1.48 ms.
(SEQUEL file: ee101 rl ac 1.sqproj)
RL circuit

R I
1
vs (t) (V)

0 R = 1⌦
V m ! 0◦ j!L
L = 1.6 mH
i(t) (A)
−1
0 10 20 30
time (ms)

Vm \0
I= ⌘ Im \( ✓),
R + j!L
Vm 1 (!L/R).
where Im = p , and ✓ = tan
R 2 + ! 2 L2
In the time domain, i(t) = Im cos (!t ✓), which lags the source voltage since the peak (or zero) of i(t) occurs
t = ✓/! seconds after that of the source voltage.
For R = 1 ⌦, L = 1.6 mH, f = 50 Hz, ✓ = 26.6 , tlag = 1.48 ms.
(SEQUEL file: ee101 rl ac 1.sqproj)

M. B. Patil, IIT Bombay

RL circuit

VR
Im (V)
R I VL
◦ Vs j!L VL
Vm ! 0 Re (V)
✓ Vs

VR

Vm \0
I= ⌘ Im \( ✓),
R + j!L
Vm 1 (!L/R).
where Im = p , and ✓ = tan
R + ! 2 L2
2

VR = I ⇥ R = R Im \( ✓) ,
VL = I ⇥ j!L = !Im L \( ✓ + ⇡/2) ,
The KVL equation, Vs = VR + VL , can be represented in the complex plane by a “phasor diagram.”
If R |j!L|, ✓ ! 0, |VR | ' |Vs | = Vm .
If R ⌧ |j!L|, ✓ ! ⇡/2, |VL | ' |Vs | = Vm .

M. B. Patil, IIT Bombay

RC circuit

R I

Vm ! 0◦ 1/j!C

Vm \0
I= ⌘ Im \✓,
R + 1/j!C
!CVm 1 (!RC ).
where Im = p , and ✓ = ⇡/2 tan
1 + (!RC )2
In the time domain, i(t) = Im cos (!t + ✓), which leads the source voltage since the peak (or zero) of i(t)
occurs t = ✓/! seconds before that of the source voltage.
For R = 1 ⌦, C = 5.3 mF, f = 50 Hz, ✓ = 31 , tlead = 1.72 ms.
(SEQUEL file: ee101 rc ac 1.sqproj)
RC circuit

R I
1 vs (t) (V)

0 R = 1⌦
Vm ! 0◦ 1/j!C
C = 5.3 mF

−1 i(t) (A)

0 10 20 30
time (ms)

Vm \0
I= ⌘ Im \✓,
R + 1/j!C
!CVm 1 (!RC ).
where Im = p , and ✓ = ⇡/2 tan
1 + (!RC )2
In the time domain, i(t) = Im cos (!t + ✓), which leads the source voltage since the peak (or zero) of i(t)
occurs t = ✓/! seconds before that of the source voltage.
For R = 1 ⌦, C = 5.3 mF, f = 50 Hz, ✓ = 31 , tlead = 1.72 ms.
(SEQUEL file: ee101 rc ac 1.sqproj)

M. B. Patil, IIT Bombay

RC circuit

VR
Im (V) VR
R I
✓
Vm ! 0 ◦ Vs VC Re (V)
1/j!C Vs
VC

Vm \0
I= ⌘ Im \✓,
R + 1/j!C
!CVm 1 (!RC ).
where Im = p , and ✓ = ⇡/2 tan
1 + (!RC )2
VR = I ⇥ R = R Im \✓ ,
VC = I ⇥ (1/j!C ) = (Im /!C ) \(✓ ⇡/2) ,
The KVL equation, Vs = VR + VC , can be represented in the complex plane by a “phasor diagram.”
If R |1/j!C |, ✓ ! 0, |VR | ' |Vs | = Vm .
If R ⌧ |1/j!C |, ✓ ! ⇡/2, |VC | ' |Vs | = Vm .

M. B. Patil, IIT Bombay

Series/parallel connections

A A

0.25 H Z1
Z
100 µF Z2
B B
(! = 100 rad/s)
Series/parallel connections

A A

Z1 = j ⇥ 100 ⇥ 0.25 = j 25 ⌦
0.25 H Z1
Z Z2 = j/(100 ⇥ 100 ⇥ 10 6 ) = j 100 ⌦
100 µF Z2 Z = Z1 + Z2 = j 75 ⌦
B B
(! = 100 rad/s)

Z1 Z2
A A Z=
Z1 + Z2
100 µF (j 25) ⇥ ( j 100)
0.25 H Z =
j 25 j 100
Z1 Z2
25 ⇥ 100
=
j 75
B B
= j 33.3 ⌦
(! = 100 rad/s)

M. B. Patil, IIT Bombay

Impedance example

Obtain Z in polar form.

A A

10 ⌦ j 10 ⌦ Z
Z1 Z2

B B
(! = 100 rad/s)
Impedance example

Method 1:
10 ⇥ j10 j10
Obtain Z in polar form. Z= =
10 + j10 1+j
j10 1 j
A A = ⇥
1+j 1 j
10 + j10
10 ⌦ j 10 ⌦ = = 5 + j5 ⌦
Z 2
Z1 Z2
Convert to polar form ! Z = 7.07 ! 45◦ ⌦

B B
(! = 100 rad/s) Method 2:
10 ⇥ j10 100 ! ⇡/2
Z= = p
10 + j10 10 2 ! ⇡/4
p
= 5 2 ! (⇡/2 ⇡/4) = 7.07 ! 45◦ ⌦

M. B. Patil, IIT Bombay

Circuit example

is 2⌦ 10 ⌦
iC iL
◦
10 ! 0 V
15 mH
f = 50 Hz 2 mF
Circuit example

is 2⌦ 10 ⌦ Is Z1 Z2 Is

iC iL IC IL
◦
10 ! 0 V Vs Z3 Z4 Vs
15 mH ZEQ
f = 50 Hz 2 mF

1
Z3 = 3
= j 1.6 ⌦
j ⇥ 2⇡ ⇥ 50 ⇥ 2 ⇥ 10
Z4 = j 2⇡ ⇥ 50 ⇥ 15 ⇥ 10 3 = j 4.7 ⌦
ZEQ = Z1 + Z3 k (Z2 + Z4 )
( j 1.6) ⇥ (10 + j 4.7)
= 2 + ( j 1.6) k (10 + j 4.7) = 2 +
j 1.6 + 10 + j 4.7
1.6\ ( 90 ) ⇥ 11.05\ (25.2 ) 17.7\ ( 64.8 )
=2+ =2+
10.47\ (17.2 ) 10.47\ (17.2 )
= 2 + 1.69\ ( 82 ) = 2 + (0.235 j 1.67)

= 2.235 j 1.67 = 2.79\ ( 36.8 ) ⌦

M. B. Patil, IIT Bombay
Circuit example (continued)

is 2⌦ 10 ⌦ Is Z1 Z2 Is

iC iL IC IL

10 ! 0◦ V Vs Z3 Z4 Vs
15 mH ZEQ
f = 50 Hz 2 mF

Vs 10 \ (0 )
Is = = = 3.58 \ (36.8 ) A
ZEQ 2.79 \ ( 36.8 ) 2
IC
(Z2 + Z4 )
IC = ⇥ Is = 3.79 \ (44.6 ) A Is

Im(I)
Z3 + (Z2 + Z4 ) 1

Z3
IL = ⇥ Is = 0.546 \ ( 70.6 ) A
Z3 + (Z2 + Z4 ) 0
IL

−1
0 1 2 3
Re(I)
M. B. Patil, IIT Bombay