EE 313 – LOGIC CIRCUITS AND SWITCHING THEORY

LEC 03 – SEQUENTIAL LOGIC

CIRCUITS
Flip-Flops and Latches
Registers and Counters (Synchronous and Asynchronous)
State Diagram and State Tables
Finite State Machines
Sequence Detectors
Mealy vs. Moore Machines

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3.1 Intro to Sequential Circuits

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What are sequential circuits?
▪ With sequential circuits, outputs depend not only on the present inputs,
but also on the past history of the system.
▪ With this, the system memorizes the state in which its is in.
▪ How does the circuit memorize its state?
▪ Using memory elements called latches and flip-flops.
▪ A state table gives the past, present, and future states at the output.

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Basic idea on how to store bits
▪ Sequential Circuit = Combinational Logic + Memory Elements
▪ Consider a cascade of two inverters with feedback:
▪ There is a stable state in the system.
▪ The circuit can memorize the output values as long as power is on.

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Basic Idea on How to Store Bits
▪ We use memory elements!
▪ A memory element a device which can remember value indefinitely, or change
value on command from its inputs.
▪ State table:
Command (at time t) Q(t) – current state Q(t+1) – next state
Set X 1
Reset X 0
No change 0 0
No change 1 1

▪ In practice,
▪ Output values should be set to 0 or 1, as per the requirement of digital circuits.
▪ Additional functionality distinguished between different types of flip-flops and latches.

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Sequential Circuits

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Sequential Circuits: Synchronous vs. Asynch?

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Synchronous Circuits: Notion of Clocks
▪ A clock is a continuous periodic signal (usually a square wave) that
alternates between two levels.
▪ It ensures that changes in the state of the circuit occur in a controlled
manner, preventing random behavior.
▪ Most synchronous circuits use edge-triggered devices to achieve precise
timing.
▪ Rising edge: low-to-high transition
▪ Falling edge: high-to-low transition
▪ What do we use for clock circuits?

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Multivibrators
▪ Multivibrators are fundamental circuits in electronics that produce
specific types of output waveforms, such as square waves or pulses.
▪ There are three types: bistable, monostable, or astable.
▪ They serve as basic building blocks for timing, waveform generation, and
memory elements, which are important to sequential circuits.

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Astable Multivibrator
▪ Behavior: Continuously oscillates between two states without requiring
external triggering.
▪ Applications: Acts as a clock source for synchronization.

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Monostable Multivibrator
▪ Behavior: Has one stable state and one quasi-stable state. An external
trigger forces it into the quasi-stable state temporarily before it returns
to the stable state.
▪ Applications: Generates precise time delays to ensure proper timing
between/among multiple events.

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Bistable Multivibrator
▪ Behavior: Has two stable states and can toggle between them based on
external inputs.
▪ Applications: Used in flip-flops.

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3.2 Flip-Flops and Latches

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Flip-Flop and Latch
▪ Flip-flops (FF) are digital circuits of two stable states at the output, with
a timing input that controls the instance at which the output changes:
▪ 1 – flip, 0 – flop
▪ These 1s and 0s are stable states that form as the smallest basic
memory unit. The two outputs are Q and Q’.
▪ What is a latch? A latch is simply a flip-flop without an edge-triggered
clocking mechanism.

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Latches and Flip-flops: What’s the difference?

LATCH FLIP-FLOP

Triggering Mechanism Level-triggered Edge-triggered

Controlled by enable; no clock
Clock dependency Requires a clock signal
required
Usage Used in asynchronous circuits Used in synchronous circuits
Complexity Simpler design More complex design
Examples SR latch D flip-flop (ff), JK, T

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Set-Reset (S-R) Latch
▪ Consists of a pair of cross-coupled NOR or NAND gates.
▪ There are two inputs (S and R) and two outputs (Q and Q’).
▪ The output can be set to 0 or 1 by applying suitable values on S and R
inputs.
▪ In creating a SR latch, we can cross-couple two NAND gates or two NOR
gates.

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Set-Reset (S-R) Latch

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Set-Reset (S-R) Latch
▪ NAND RS Latch

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Set-Reset (S-R) Latch
▪ NOR RS Latch

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Gated S-R Latch

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Set-Reset (S-R) Latch
▪ While S-R is considered a building block of FF, difficulty in using it lies in:
▪ The unstable condition when both input states are 0 (for a NAND RS) and 1 (for a
NOR RS)
▪ When we are interested in setting (i.e. forcing in logic state 1) Q from its reset
state (0) or resetting Q from the set state, there will be a certain time interval
taken in interchanging the R and S input states. During the intermediate time
interval (during the floating of the R and/or S inputs), what happens we cannot
predict.

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Set-Reset (S-R) Latch

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Gated S-R Latch
▪ Adding two NAND (or NOR) gates to the two cross-coupled NANDs (or
NORs) from the initial S-R latch produces a gated S-R. The gate acts as
an enable input, which controls whether the S-R latch responds to the
inputs of the S and R.
▪ E = 1: the latch responds to S and R inputs.
▪ E = 0: the latch ignores S and R; it retains its previous state.

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How about an S-R FF?

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Set-Reset (S-R) Flip-Flop
▪ S-R flip-flop is done by adding two NAND (or NOR) gates to the cross-
coupled NAND (or NOR) S-R latch. An edge-triggered clock input circuit
is also added.

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S-R Flip-flop
Clock Set Reset Q(t) Q(t+1)
inactive X X Q(t) Q(t) No change, since the clock is inactive

Active edge 0 0 0 0 Hold: Keeps state at 0

Active edge 0 0 1 1 Hold: Keeps state at 1

Active edge 1 0 X 1 Set: Forces next state to 1

Active edge 0 1 X 0 Reset: Forces next state to 0

Active edge 1 1 X invalid S = R = 1 is a forbidden state

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D Latch
▪ A D latch eliminates the undesirable condition of invalid state in the S-R
latch.

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D Latch

Enable Data Q(t) Q(t+1)

0 X Q(t) Q(t) Hold: No change.

1 0 X 0 Reset: Next state is 0.

1 1 X 1 Set: Next state is 1.

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D Flip-flop?

Clock Data Q(t) Q(t+1)

Inactive X Q(t) Q(t) Hold: No change.

Active 0 X 0 Reset: Next state is 0.

Edge
Active 1 X 1 Set: Next state is 1.
Edge

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J-K Flip-Flop

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J-K Flip-Flop

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J-K Flip-Flop
▪ In a J-K flip-flop, Q and Q' are fed back to the pulse-steering NAND
gates.
▪ There is no invalid state.
▪ It includes a toggle state.

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J-K Flip-flop
Clock J (Set) K (Reset) Q(t) Q(t+1)
inactive X X Q(t) Q(t) No change, since the clock is inactive

Active edge 0 0 0 0 Hold: Keeps state at 0

Active edge 0 0 1 1 Hold: Keeps state at 1

Active edge 1 0 X 1 Set: Forces next state to 1

Active edge 0 1 X 0 Reset: Forces next state to 0

Active edge 1 1 0 1 Toggle: Flips the current state to 1.

Active edge 1 1 1 0 Toggle: Flips the current state to 0.

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T Flip-flop
▪ This is a single-input version of the J-K flip-flop, formed by tying both
inputs together.

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T Flip-flop

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D Flip-flop

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D Flip-flop

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State Equations, Tables, and
Diagrams

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State Equations/Tables/Diagram
▪ A state equation is a mathematical representation that relates:
▪ The next state (Q(t+1)) of the system
▪ The current state (Q(t))
▪ The inputs (X) driving the system
▪ Q(t+1) = f(Q(t), X)
▪ A state table is a tabular representation of a sequential circuit’s
behavior.
▪ A state diagram represents states as nodes, and show transition from
one state (current state) to the next.

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Simplest Example: D Flip-flop
▪ State Equation: Q(t+1) = D
▪ State Table:

Q(t) D Q(t+1)
0 0 0 Hold at 0
0 1 1 Set to 1
1 0 0 Reset to 0
1 1 1 Hold at 1

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More Examples of State Equations, Tables, etc.

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Finite State Machines

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What are FSMs?
▪ A Finite State Machine (FSM) is a computational model used to design
and describe the behavior of systems that have a finite number of states.
It operates by transitioning between states based on inputs and produces
outputs, making it widely used in digital logic design.
▪ The components are:
▪ States (initial state is also identified)
▪ Inputs
▪ Outputs
▪ Transitions (and state transition logic)

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What are FSMs?
▪ Moore Machine:
▪ Outputs depend only on the current state.
▪ Outputs are constant as long as the FSM is in a given state.
▪ Simpler to design and analyze.
▪ Z = f(Q)
▪ Mealy Machine:
▪ Outputs depend only on the current state.
▪ Outputs are constant as long as the FSM is in a given state.
▪ Simpler to design and analyze.
▪ Z – f(Q,X)

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