Analog Electronics
Lecture 10
Field Effect Transistor
“JFFT”
Dr. Roaa Mubarak
Field Effect Transistor
• FET is a three terminal semiconductor device. It is unipolar transistor
i.e. depends only on one type of charge carrier, either electron or hole.
• FET is simple to fabricate and occupies less space on a chip than a BJT.
About 100000 FETs can be fabricated in a single chip. This makes them
useful in VLSI (Very Large Scale Integrate) system.
• FET is a voltage-sensitive device which has extremely high input
impedance ( 1014 Ω as well as high output impedance).
• There are two types of FET – the JFET (Junction Field Effect Transistor)
and MOSFET (Metal Oxide Semiconductor Field Effect Transistor)
Field Effect Transistor
• FET is a three terminal unipolar semiconductors device has a very similar
characteristics to BJT such as :
- High efficiency.
- Instant operation.
- Robust and cheap.
- Can be used in most electronic circuit applications.
• FET advantages over BJT:
- FET can be made much smaller than BJT.
- Their low power consumption and power dissipation makes them ideal for use
in integrated circuit.
- Rin is very high, makes them very sensitive to input voltage signal, but for this
sensitivity it will be damage easily by static electricity.
Field Effect Transistor
Junction Field Effect Transistor “JFET”
• It is of two types
- P-channel JFET
- n-channel JFET
• The n- channel JFET consists of a bar of n-type semiconductor with two islands
of p- type material embedded in the sides. The drain and source terminals are
made by ohmic contacts at the end of semiconductor bar.
Junction Field Effect Transistor “JFET”
• Majority charge carrier i.e. electrons can be cause to flow along length of bar by
means of a voltage applied between the source and drain. The third terminal,
known as the gate is formed by electrically connecting the two p-type regions.
Symbol & Structure of n-channel JFET
Junction Field Effect Transistor “JFET”
The circuit symbol of p- channel JFET is similar to that of an n-channel
JFET except that the gate arrow points outward as shown in below.
Symbol & Structure of p-channel JFET
JFET Operation and Circuit analysis (N Channel)
JFET Operation and Circuit analysis
JFET Operation and Circuit analysis
JFET Operation and Circuit analysis
➢The Gate and channel constitute a PN junction diode which is reverse
biased by the gate to the source voltage.
➢A depletion layer is developed in the channel as reverse bias increases
the width of depletion layer increases.
➢For a fixed drain to source voltage, the drain current will be a function
of reverse bias voltage across the gate junction.
➢ At a gate-to-source voltage VGS known as the “Pinch- off” voltage
which eliminates the channel, the channel width is reduces to zero.
➢The term Field Effect is used to describe this device because of
mechanism to control current using reverse bias voltage VGS.
Drain characteristics (N channel)
• Ohmic Region
When 𝑉𝐺𝑆 = 0 the depletion layer is very small and
JFET as voltage controlled resistor.
• Saturation or Active region
JFET become good conductor and controlled by 𝑉𝐺𝑆
which 𝑉𝐷𝑆 has little or no effect.
• Cutoff region “ pinch off region”
𝑉𝐺𝑆 is sufficient to cause the JFET to act as open
circuit as channel resistance is maximum.
• Breakdown region
𝑉𝐷𝑆 is high enough to cause JFET resistive channel
to breakdown and pass uncontrolled maximum
current
Drain characteristics
• 𝑉𝑝 “ pinch off voltage”, the voltage that pinches off the channel connection
between drain and source.
• Ohmic region
2
𝑉𝐺𝑆
𝑉𝐷𝑆 < 𝑉𝑝 , 𝐼𝐷 = 𝐼𝐷𝑆𝑆 1 − 𝐼𝐷𝑆𝑆 is the maximum current
𝑉𝑝
• Saturation region
𝑉𝐷𝑆 ≥𝑉𝑝 , 𝐼𝐷 remains constant
• Breakdown
𝑉𝐷𝑆 >>> 𝑉𝑝
Transfer characteristics
Transfer characteristics
• 𝐃𝐫𝐚𝐢𝐧 − 𝐒𝐨𝐮𝐫𝐜𝐞 𝐜𝐡𝐚𝐧𝐧𝐞𝐥 𝐫𝐞𝐬𝐢𝐬𝐭𝐚𝐧𝐜𝐞: The rate of change of VDS with
respect to change of ID at a constant value of VGS (R DS ≈ 100kΩ to1MΩ)
△ 𝑉𝐷𝑆
𝑅𝐷𝑆 =
△ 𝐼𝐷
Transconductance gm : The rate of change of ID with respect to change of VGS
at a constant value of VDS (gm ≈ 0.1 to 20 mA/V)
Where gm0 is the transconductance when 𝑉𝐺𝑆 = 0
Current Equations of JFET
2
𝑉𝐺𝑆
𝐼𝐷 = 𝐼𝐷𝑆𝑆 1−
𝑉𝑝
ID = IS
IG =0
JFET Biasing
• There are several different ways of biasing the JFET, for many
configurations 𝐼𝐷𝑆𝑆 and 𝑉𝐺𝑆 (off) “𝑉𝑝 ” will be needed.
➢Fixed-Bias.
➢Self Bias.
➢Combination Bias.
➢Constant current Bias.
➢Voltage Divider Bias.
Fixed-Bias JFET
• The simplest form of bias is the constant voltage bias.
Using KVL in Gate –Source loop
IG is approximately zero
Using KVL in Drain–Source loop
Example
Determine 𝐼𝐷 and 𝑉𝐷𝑆 . Assume 𝐼𝐷𝑆𝑆 = 10 mA , 𝑉𝐺𝑆 (off) = -5V.
• Solution
Self Bias
• Self bias using a small number of components and only a single power supply, it offers
a better stability than fixed voltage bias.
IG =0 , and ID = IS
Constant current Bias
• The most stable bias of JFET relies on a current source made with BJT.
• An NPN BJT is used for an N-channel JFET and a PNP would be used
with a P-channel JFET.
Voltage Divider Bias
JFET small signal model (Hybrid Model)
𝛑 Model T- Model
JFET Hybrid 𝛑 Model
△𝑽𝑫𝑺 𝟏
𝒓𝒐 = 𝒓𝒅 = =
△𝑰𝑫 𝒈𝒐𝒔
𝒁𝒊 = ∞
𝒁𝒐 = 𝒓𝒅
JFET different configuration
Fixed biased CS Configuration
Voltage Divider CS Configuration
