CURRICULUM VITAE

P.Vasu Ramesh E-mail: vasuramesh424@gmail.com

Mobile: +91-9000774365

CAREER OBJECTIVE:
9+ years of experience in Embedded Hardware board design. Have proficiency in all phases of
hardware development cycle covering from engineering specification, high level & detailed level
design and Validation testing. Design and development of embedded system hardware for a variety of
state-of-the-art in Automotive and Defense.
PROFESSIONAL EXPERIENCE:

 Working as Senior Hardware Design Engineer in People Tech Group, Hyderabad from March 25th
2024 to Till date.
 Working as Senior Hardware Design Engineer in Wipro Limited, Hyderabad from March 29th 2022
to February 25th 2024.
 Working as Senior Hardware Design Engineer in Tata Consultancy Services (TCS), Hyderabad
from July 17th 2019 to March 28th 2022.
 Working as Hardware Design Engineer in L&T Technology Services, Chennai from December 4th
2017 to March 29th 2019.
 Worked as Hardware Design Engineer in Vrinda Technologies Pvt. Ltd, Hyderabad from December
29th 2014 to November 23rd 2017.
FUNCTIONAL SKILLS:
 9+ Years of experience in electronics Hardware Design, Development &Testing which involves
architecture study, component research, schematic design, layout analysis, validation and support.
 Experience in Designing high speed boards and handling all kinds of design issues like Signal &
Power Integrity, timing, EMI/EMC and Thermal Issues.
 Handful experience in power supply Design, Development &testing, understanding their stability,
efficiency and various design issues and trouble shoot the problem with route cause analysis.
 Hands on knowledge of Oscilloscopes, Function Generator, Vector Network Analyzer, Spectrum
Analyzers and Signal Generators.
 Excellent working experience with seeker hardware like Xilinx FPGA's(Zynq Ultra Scale+ MPSOC,
Zynq 7000, Virtex-7, Airtex-7), Mediatek Processor, iMX8 Processor, Flash memory, USB Interface,
DDRx memory, Gigabit Ethernet, C-PHY, TFT Display, RGB Interface, LVDS, MIPI, eMMC,
CAN, LIN, 4G GPS module, Clock buffers, Transceivers and other embedded hardware.
 Having knowledge in the areas of High-Speed board design and Mixed Signal Board Design.
 Having knowledge in High-Speed Signal integrity, Power integrity and Thermal analysis.
 Hands on experience in Automotive Infotainment, Cluster Meter and Defense products.
 Having Experience of Requirements Capture Tools, such as IBM Rational Doors
 Providing status reporting of the progress of ongoing tasks through the JIRA/Task tool.
 Designed 6U VPX Backplane chassis, Motherboards.
 Hands on knowledge in CADENCE/ORCAD, Mentor Graphics Dx Designer, SVC Filter Design
Tool, RF Sim, Multi-sim, Else Filter tools.
 Proficient in generation of Design document PDR, HDD, ICD, BOM, ATP reports as per AS9100
standards.
 Experience in WCCA analysis.
 Knowledge of Functional Safety life cycle as per ISO26262
  Experience in EMI/EMC Certification Testing as per CISPR-25, Electrical pulse testing as per
ISO16750-2 and ISO 7637-2
 Experience in designing of RF filters(LPF,HPF,BPF)
 Development & Testing of both active and passive filters.
 Able to guide PCB designer for Placement and Routing.
 Performing Worst case Circuit Analysis for Power Supply Modules.
 Experience in Testing at laboratories like DLRL, RCI, BEL Hyderabad using high end Oscilloscopes
and Network Analyzers.
 Attended electrical, environmental (ESS & SOF), QT & EMI/EMC Tests Conducted on High Speed
Boards and LRU Level.

TECHNICAL SKILLS & IT PROFICIENCY:

Cadence 17.2, Cadance16.6, Mentor Graphics Dx
Schematic Design, Layout Tools
Designer VX2.5, Altium Designer19,20.
PSpice, RF Sim, Mathcad15, MultiSim, HyperLynx,
Simulation Tools
SVC Filter Design, Else Filter tools
EDA Tools / Platforms (Basic
Xilinx(ISE, SDK),Chip Scope(Xilinx)
Knowledge)
Digital Storage Oscilloscope, Network Analyzer up to
Equipment’s 20GHz, Function Generator, Signal generator and
Spectrum Analyzer

ACADEMICS:
 Bachelor of Technology (B.Tech) specializing in Electronics & Communication Engineering., in
2014, Pragati Engineering College, Surampalem, affiliated to JNTU Kakinada.
 Diploma Engineering (D.E) specializing in Electronics & Communication Engineering, in 2011 from
Sri Y.V.S & B.R.M Polytechnic College, Mukteswaram, affiliated to Board of Technical Education.
 Secondary School Certificate (SSC) from Z.P. High School, Injaram, Andhra Pradesh, Secondary
Education Examination Board in 2008.

PROJECTS SUMMARY:
Project #1: Instrument Cluster
Role : Design Engineer

Project Summary: It is a E-Bike Cluster meter with Mediatek SOM module. It has 7 inch color TFT
display with capacitive touch.
Display is driven by LVDS channels from the processor.
Interfaces Used: 2GB LPDDR4, 32GB eMMC, 4G LTE, WiFi/Bluetooth, Audio Amplifier, Speaker, MIC,
Audio Jack, CAN 2.0 Interface, USB Type-C.
Responsibilities Handled: Schematic Design, Power calculation, components selection. BOM
preparation, Technical Documents Preparation.

Project #2: Audio Infotainment

Role : Design Engineer

Project Summary: It is a car audio Infotainment system with Qualcomm Snapdragon SIP module. It
has 17.1 inch color TFT display with capacitive touch.
Display is driven by LVDS channels from the processor. Interfaces Used: LPDDR4, NXP Safety MCU,
PMIC, Gigabit Ethernet, USB to UART interface,A2B transceiver, Wifi/BT module, USB type C, GSML
serializer and desterilizer.
Responsibilities Handled: Power Tree review, Schematic Design, components selection. BOM
preparation, Technical Documents Preparation, Signal and Power Integrity

Project #3: Digital Tracking Receiver

Role : Design Engineer

Project Summary: Digital Tracking Receiver Unit is based on Xilinx Zynq Ultra scale+ FPGA.
Interfaces Used: XCZU7EV (Zynq Ultra scale+ MPSOC), DDR4, Gigabit Ethernet (1000/100/10 Base-T),
4G GSM module, WiFi/BT Module, USB 2.0, SD Card, QSPI Flash, RS232, USB-UART Bridg.

Responsibilities Handled: Block Diagram, Components Selection, Schematic Design, Technical

Documents Preparation, BOM preparation, Layout verification, Signal Integrity, Power Integrity, Thermal
Analysis, and Power Calculation.

Project #4: Automotive Breaking System

Role : Functional Test Engineer

Project Summary: Automotive Breaking System is based on Aurix Micro, BLDC Driver, Auriga
(DC/DC CONVERTER), Capella, CAN, Sensor Interfaces.

Responsibilities Handled: Functional Testing, Technical Documents Preparation, WCCA analysis,

upload results in Integrity, Doors usage for requirements.

Project #5: Audio Infotainment

Role : Design Engineer

Project Summary: It is a car audio Infotainment system with i.MX8 Dual processor from NXP. It has
10.25inch color TFT display with capacitive touch.
Display is driven by LVDS channels from the processor.4 channel class AB amplifier is used as Audio
Amplifier. Interfaces Used: DDR3L, NAND Flash, NOR Flash, USB, High Speed CAN, MIC, Tuner
(FM/DAB), BT/Wi-fi, GPS.

Responsibilities Handled: Schematic Design, Technical Documents Preparation, and Power

Calculation, Board bring up, Testing and WCCA Analysis.

Project#6: Quad Digital Receiver (QDR500)

Role: Design Engineer

Project Summary: The Quad Digital Receiver (QDR500) is a sub-system of an ESM/ELINT system and
measures the pulse parameters of radar in real time. The radar signal of 0.5 – 18GHz will be down
converted to an IF using suitable Front-End Receiver and fed to Quad Digital Receiver. This sub-system is
built around Texas Instrument’s Ultra High speed, Low Power, High Performance 10-bit ADC’s and
Xilinx 7 series FPGAs. The 4 IF inputs in various bandwidths will be amplified and passed through
switched filter i.e. DC-1250MHz (LPF) or 980 -1020MHz (BPF). Interfaces Used: High speed 10 bit
@1350MSPS, Two Virtex-7 & One Artix-7 FPGA’s, 2 Gb DDR2 SDRAM, 1Gb Flash, Three 1 Mb
EEPROMs, Gigabit Ethernet (1000/100/10 Base-T), High Speed RIO interfaces between FPGAs as well as
to VPX at 3.125Gbps, VPX Backplane. Dimension: 6U

Basically, Quad Digital Receiver (QDR500) Hardware is configured into two modules i.e.
1) IF Section
2) Quad Digital Rx Main Board.
IF Section: IF Section module to be developed as a separate Board and after through testing, this will be
integrated with the main Quad Digital Receiver Board. IF Section consists of Amplifier, Switch,
BPF, LPF and Programmable attenuator in all the four IF chains. Phase and Gain critical
requirement of the IF Section.

Responsibilities Handled: Schematic Design, Development &testing, Component Selection, preparing

BOM, Preparation of Technical Documents, Conducting Electrical, environmental Tests and Support to the
Client for the Integration of the unit in their sub-system.
 Involved in Development and Testing of All Interfaces, Major Thing is Gain and Phase
Matching.
 Phase matching between channels was adjusted for ±4 degrees using length matching cables
while interfacing with Rx board.

Project #7: VLF Processor

Role: Design Engineer

Project Summary: The FPGA cum processor card (base band hardware) with following hardware
capability is required for VLF communication. This baseband hardware will have capability to work as a
complete receiver. This will be able to take direct signals from antenna and will produce digital output and
audio output. Signals Integrity of card is important aspect since card has an RF Front end with mixed-
signal baseband section.
Internal noise floor of the board should be very low level (less than -130dBm) as it has to handle RF signal
(of bandwidth as low as 100 Hz also) at sensitivity level.

Responsibilities Handled: Schematic Design, Development & testing, Component Selection, preparing
BOM, Preparation of Technical Documents, Testing, and Conducting ATP.

Project #8: Receiver Processor LRU

Role : Design Engineer

Project Summary: The “Receiver Processor LRU” shall be developed as Air cooled chassis.
The Receiver processor LRU contains 10-slot space inside, consisting of 8 boards in total
and two power distribution modules. The back plane of RP LRU shall be custom designed with VPX
connector terminations.

Responsibilities Handled: Schematic Design, Development & testing, take inputs from Clint, Circular
Connectors selection, preparing BOM, Preparation of Technical Documents, Testing, Conducting
electrical, environmental (ESS & SOF) & EMI/EMC Tests.
ACHIEVEMENTS &EXTRA CURRICULAR ACTIVITIES:
 Got First prize in Project Presentation under EJIVE -2K12 at Pragati Engineering College.
 Participated in two NSS Special Camps focusing the theme on “Youth for Rural development”
conducted by the NSS Unit of Pragati Engineering College.
 Attended a Seminar on NSIC-Technical Service Centre.
 Participated in Project Presentation conducted by S.R.K.R Engineering College Bhimavaram
 Participated in the Circuit Building competition in VEDA-2K12 at Aditya Group of Engineering
Colleges

DECLARATION:
I hereby declare that all the information furnished above are true to the best of my knowledge.

PERSONAL DATA:

Name : P.Vasu Ramesh

Date of Birth : 12 –july-1993
Gender : Male
Marital Status : Married
Languages Known : English and Telugu

(P.VASU RAMESH)