Assignment 5

### 1. **Major Components of CPU**

1. **Arithmetic Logic Unit (ALU):**
- Performs arithmetic operations (e.g., addition, subtraction).
- Executes logical operations (e.g., AND, OR, NOT).

2. **Control Unit (CU):**

- Directs and coordinates the CPU’s operations.
- Decodes instructions and sends control signals to other
components.

3. **Registers:**
- High-speed storage areas within the CPU.
- Temporarily hold data, instructions, or addresses.

4. **Cache Memory:**
- Small-sized, fast memory close to the processor.
- Stores frequently accessed data and instructions.

5. **Clock:**
- Synchronizes the operations of the CPU.
- Determines the speed of instruction execution.

6. **Bus Interface Unit:**

- Manages communication between the CPU, memory, and I/O
devices.
- Includes address, data, and control buses.

---
### 2. **General Register Organization (With Diagram)**
- **Concept:**
- A system where multiple general-purpose registers are connected
to the CPU.
- Provides fast storage and retrieval of data for computation,
reducing dependency on main memory.
- Helps with arithmetic operations, logical decisions, and program
control.

- **Key Registers:**
1. Accumulator (A): For arithmetic and logic operations.
2. Data Registers (R1, R2,...): Store operands and results.
3. Address Registers: Store memory addresses.
4. Program Counter (PC): Points to the next instruction.

- **Diagram:**
A typical diagram shows:
- Multiple general-purpose registers connected to the ALU.
- Decoders and multiplexers facilitate data movement.
```plaintext

---
### 3. **Register Stack and Memory Stack**
- **Register Stack:**
- **Definition:** A set of registers organized as a stack.
- **Operations:** Push (store) and pop (retrieve) values in LIFO
order.
- **Uses:**
- Fast access for temporary storage.
- Efficient in recursive procedures.
- **Limitations:** Limited capacity due to small size.

- **Memory Stack:**
- **Definition:** A region in memory used to manage function calls
and local variables.
- **Operations:** Push and pop values in LIFO order.
- **Uses:**
- Stores return addresses, function parameters, and local variables.
- Supports dynamic memory allocation.
- **Advantages:** Large storage capacity.
- **Disadvantages:** Slower access compared to register stack.

---
### 4. **Instruction Format**
**Instruction formats** define the layout of binary instruction codes in
memory.

#### **One-Address Instruction**

- **Format:** `OP <operand>`
- **Example:** `LOAD A`
- **Explanation:**
- Uses an implicit accumulator register for operations.
- Suitable for simple architectures.

#### **Two-Address Instruction**

- **Format:** `OP <destination>, <source>`
- **Example:** `ADD R1, R2`
- **Explanation:**
- One operand is the destination, and the other is the source.
- Reduces memory references.

#### **Three-Address Instruction**

- **Format:** `OP <destination>, <source1>, <source2>`
- **Example:** `ADD R1, R2, R3`
- **Explanation:**
- Specifies two source operands and a destination.
- Suitable for complex architectures.

#### **Zero-Address Instruction**

- **Format:** `OP`
- **Example:** `PUSH A, PUSH B, ADD`
- **Explanation:**
- Operates on stack-based architectures.
- Instructions implicitly reference the stack top.
1. Addressing Modes with Examples

Addressing modes define how the operands of an instruction are

accessed.

1. Immediate Addressing Mode:

○ Operand is part of the instruction.
○ Example: MOV R1, #5 (Load the value 5 into register
R1).
2. Direct Addressing Mode:
○ The address of the operand is specified in the instruction.
○ Example: LOAD A (Load the value at memory location A).
3. Indirect Addressing Mode:
○ The instruction specifies a pointer to the operand.
○ Example: MOV R1, @R2 (Load the value from the address
in R2 into R1).
4. Register Addressing Mode:
○ Operand is stored in a register.
○ Example: ADD R1, R2 (Add values in R1 and R2).
5. Indexed Addressing Mode:
○ The effective address is the sum of a base address and an
index.
○ Example: MOV R1, A[R2] (Load value at address A +
R2).
6. Relative Addressing Mode:
○ Address is calculated relative to the program counter.
○ Example: JMP OFFSET (Jump to an address relative to the
current instruction).
7. Base Addressing Mode:
○ Address is the sum of a base register and an offset.
○ Example: MOV R1, 100(BR) (Load value from address
BR + 100).
2. Data Manipulation Instructions

These instructions perform operations on data.

1. Arithmetic Instructions:
○ Perform basic arithmetic operations.
○ Examples:
■ ADD R1, R2 (Add R2 to R1).
■ SUB R1, R2 (Subtract R2 from R1).
2. Logical Instructions:
○ Perform bitwise operations.
○ Examples:
■ AND R1, R2 (Bitwise AND of R1 and R2).
■ OR R1, R2 (Bitwise OR of R1 and R2).
3. Shift Instructions:
○ Shift bits left or right.
○ Examples:
■ SHL R1 (Shift bits of R1 left).
■ SHR R1 (Shift bits of R1 right).
4. Comparison Instructions:
○ Compare two values and set condition flags.
○ Example: CMP R1, R2 (Compare R1 and R2).
5. Increment/Decrement Instructions:
○ Increase or decrease a value.
○ Examples:
■ INC R1 (Increment R1).
■ DEC R1 (Decrement R1).
3. Program Control Instructions

These instructions control the sequence of execution.

1. Unconditional Branch Instructions:

○ Transfer control to a specific location.
○ Example: JMP 200 (Jump to address 200).
2. Conditional Branch Instructions:
○ Transfer control based on a condition.
○ Examples:
■ JZ 100 (Jump if zero flag is set).
■ JNZ 100 (Jump if zero flag is not set).
3. Procedure Call Instructions:
○ Save the return address and transfer control to a
subroutine.
○ Example: CALL SUBR (Call the subroutine SUBR).
4. Return Instructions:
○ Return control to the calling program.
○ Example: RET (Return to the instruction after the
subroutine).
5. Halt Instructions:
○ Stop program execution.
○ Example: HLT (Halt the CPU).
6. Interrupt Instructions:
○ Trigger a software or hardware interrupt.
○ Example: INT N (Generate interrupt N).
4. Flag Processor Status Word (PSW)

The Processor Status Word (PSW) is a special register that holds

the status of the CPU and flags indicating the results of operations.

● Components of PSW:
○ Zero Flag (Z): Set if the result of an operation is zero.
○ Carry Flag (C): Set if there is a carry out from the most
significant bit.
○ Sign Flag (S): Set if the result is negative.
○ Overflow Flag (O): Set if an arithmetic operation generates
an overflow.
○ Parity Flag (P): Set if the number of 1s in the result is
even.
○ Auxiliary Carry Flag (AC): Used for binary-coded decimal
(BCD) arithmetic.
● Uses of PSW:
○ Helps in decision-making for branching instructions.
○ Indicates the status of arithmetic and logical operations.
○ Used for debugging and program analysis.

1. Six Conditional Branch Instructions

1. Jump if Zero (JZ): Branches if the zero flag is set.

○ Example: JZ LABEL (Jump to LABEL if result is zero).
2. Jump if Not Zero (JNZ): Branches if the zero flag is not set.
○ Example: JNZ LABEL (Jump to LABEL if result is not
zero).
3. Jump if Carry (JC): Branches if the carry flag is set.
○ Example: JC LABEL (Jump to LABEL if carry flag is set).
4. Jump if Not Carry (JNC): Branches if the carry flag is not set.
 ○ Example: JNC LABEL (Jump to LABEL if carry flag is not
set).
5. Jump if Greater (JG): Branches if the result is greater than
zero.
○ Example: JG LABEL (Jump to LABEL if the result is
positive).
6. Jump if Less (JL): Branches if the result is less than zero.
○ Example: JL LABEL (Jump to LABEL if the result is
negative).

2. Interrupt

An interrupt is a signal sent to the CPU to temporarily halt the current

execution and perform a specific task. After the task, the CPU
resumes normal execution.
Types of Interrupts

1. Hardware Interrupts:
○ Triggered by external hardware devices (e.g., keyboard,
mouse).
○ Examples:
■ I/O Interrupts (e.g., keypress detection).
■ Timer Interrupts (e.g., periodic tasks).
2. Software Interrupts:
○ Generated by a program or operating system.
○ Example: System calls like INT 21H.
3. Maskable Interrupts:
○ Can be enabled or disabled by the CPU using control
registers.
○ Example: Interrupts that can be ignored during critical
sections.
 4. Non-Maskable Interrupts (NMI):
○ Cannot be disabled and are of high priority.
○ Example: Power failure alerts.
5. Vector Interrupts:
○ The address of the interrupt service routine (ISR) is
predefined.
○ Example: Interrupt table used in x86 architecture.
6. Non-Vector Interrupts:
○ ISR address is not predefined and must be provided during
the interrupt.

3. Difference Between RISC and CISC

Feature RISC CISC

Instruction Simple and fewer Complex and many

Set instructions. instructions.

Instruction Executes one May take multiple cycles per

Execution instruction per cycle instruction.
(pipeline).

Memory Accessed only for load Can directly manipulate

Access and store operations. memory.

Code Size Larger, as complex Smaller, as single

tasks need more instructions can perform
instructions. complex tasks.

Control Unit Hardwired for Microprogrammed for

simplicity and speed. flexibility.

Examples ARM, MIPS x86, Intel Pentium

4. Overlapped Register Window (With Diagram)

Concept:

● Used in RISC processors to optimize procedure calls and reduce

memory access.
● A set of registers is divided into overlapping windows, where:
1. Registers in the current window hold local variables.
2. Overlapping registers act as communication buffers
between procedures.
Advantages:

1. Eliminates the need to store and load parameters from memory

during function calls.
2. Improves efficiency in recursive calls.
Diagram:
 ● Explanation of Diagram:
○ Each register window has private and shared registers.
○ When a function is called, the shared registers pass
parameters to the next window.
○ This reduces the overhead of memory access.

Assignment 4

Definitions:

1. Control Word:
○ A control word is a binary-encoded instruction used to specify the
control signals for the execution of a micro-operation in a computer
system.
○ It activates various components like ALU, memory, or I/O devices
during a clock cycle.
2. Sequencer:
○ A sequencer is a component that generates the sequence of control
signals for the execution of instructions.
○ It determines the order in which micro-operations are performed by
fetching and decoding instructions.
3. Control Memory:
○ Control memory is a small, high-speed memory that stores the
microprogram for a control unit.
○ It is accessed to fetch microinstructions that guide the execution of a
computer program.
4. Micro-program:
○ A micro-program is a sequence of microinstructions stored in control
memory to define the control signals required for executing
machine-level instructions.
 ○ It acts as a layer between the hardware and machine-level
instructions.
5. Micro-Instruction:
○ A micro-instruction is a single-level instruction in a micro-program
that specifies one or more control signals for performing
micro-operations.
○ It is the smallest unit of instruction in a micro-program.

Block Diagram of Computer Hardware Configuration

Micro-Instruction Format

Definition:

● The micro-instruction format is the structure or layout of bits in a

micro-instruction that specifies the control signals for the execution of a
micro-operation.

Components of a Micro-Instruction Format:

1. Control Field:
 ○ Specifies control signals to activate hardware units like ALU,
memory, or registers.
2. Address Field:
○ Specifies the next microinstruction or provides the address of the
control memory.
3. Condition Field:
○ Specifies conditional branching based on the status of flags or
external inputs.
4. Opcode Field:
○ Specifies the type of operation to be performed.

Block Diagram:

Decoding ALU Control Information

Explanation:

The ALU (Arithmetic Logic Unit) performs arithmetic and logical operations based
on the control signals provided by the control unit. The decoding of ALU control
information involves translating binary control inputs into specific operations.

Steps in Decoding:

1. The Opcode from the instruction specifies the desired operation.

 2. The control unit decodes the opcode to generate ALU control signals.
3. ALU control signals determine the operation to perform (e.g., addition,
subtraction, AND, OR).

Components in Decoding ALU Control Information:

1. Instruction Decoder: Converts opcodes into binary control lines.

2. Control Signals: Determines the ALU operation (e.g., ALUOp).
3. Multiplexers: Select operands or routes for processing.

Diagram:

Block Diagram of Micro-program Sequencer in Control Unit

A micro-program sequencer determines the address of the next

microinstruction in the control memory.

Components:

1. Control Address Register (CAR): Stores the address of the current

microinstruction.
2. Control Memory (CM): Stores microinstructions.
3. Address Multiplexer: Selects the next address based on branching
conditions.
 4. Sequencing Logic: Generates the next address.

Diagram:

+------------------+ +------------------+
| Control Address | -----> | Control Memory |
| Register (CAR) | | (Microinstructions)|
+------------------+ +------------------+
| |
v |
+------------------+ +------------------+
| Address | <----- | Branching Logic |
| Multiplexer | | (Condition Flags)|
+------------------+ +------------------+
Symbol Representations of Branching (BR) and Condition (CD) Fields in
Microinstructions

1. Branching Field (BR):

Specifies the type of control transfer.

Symb Meaning
ol

000 Next sequential

microinstruction

001 Branch unconditionally

010 Branch if a condition is true

011 Branch if a condition is false

100 Indirect address in control

memory

2. Condition Field (CD):

Specifies the conditions to test for branching.

Symb Meaning
ol

00 No condition (default
branching)

01 Zero flag condition

10 Carry flag condition

11 Overflow flag condition

These fields together help the micro-program sequencer manage program flow
efficiently.

Assignment 3

What is an Assembler?

An assembler is a system program that converts assembly language code into

machine code. Assembly language is a low-level programming language that uses
symbolic representations for operations and memory locations, while machine code
consists of binary instructions that the CPU understands directly.

First Pass Assembler

Explanation:

The first pass of an assembler scans the assembly language program and performs the
following tasks:

1. Symbol Table Creation:

○ Identifies all symbols (labels) and assigns their memory addresses.
2. Address Assignment:
○ Allocates memory for each instruction and data in the program.
3. Detection of Syntax Errors:
○ Checks for invalid syntax but does not generate machine code.
4. Intermediate Code Generation:
○ Produces an intermediate file with partially processed information.

Diagram for First Pass Assembler:

 +-----------------------+

Second Pass Assembler

Explanation:

The second pass of an assembler takes the intermediate file generated in the first pass
and:

1. Generates Machine Code:

○ Converts the intermediate instructions into machine language.
2. Symbol Resolution:
○ Resolves all symbols by referencing the symbol table.
3. Error Detection:
○ Identifies errors related to unresolved symbols or invalid opcodes.
What is Machine Language?

Machine language is the lowest-level programming language, consisting of

binary code (0s and 1s) that the computer's CPU directly executes.

● It represents instructions and data in binary format.

 ● Machine language instructions are processor-specific, meaning they vary
for different CPUs.

Key Characteristics:

1. Directly understood by the hardware.

2. Difficult to write and debug due to its binary format.
3. Faster execution compared to higher-level languages.

Fields Required to Write an Assembly Language Program

An assembly language program consists of the following fields:

1. Label Field (Optional):

○ Used to identify a memory location with a symbolic name.
○ Example: START:
2. Opcode Field (Required):
○ Specifies the operation to perform (e.g., ADD, SUB, MOV).
○ Example: MOV
3. Operand Field (Required):
○ Contains data or addresses on which the operation is performed.
○ Example: AX, BX
4. Comment Field (Optional):
○ Used for documentation and improving program readability.
○ Example: ; This adds two numbers

Structure of an Assembly Language Statement:

plaintext
Copy code
LABEL: OPCODE OPERANDS ; COMMENT

Assembly Language Program to Perform Addition of Two Numbers

Problem: Add two numbers stored in memory and store the result in a register.
Program:
assembly
Copy code
; Program to Add Two Numbers
START: MOV AX, [NUM1] ; Load the first number into
AX
MOV BX, [NUM2] ; Load the second number into
BX
ADD AX, BX ; Add AX and BX, result in AX
MOV [RESULT], AX ; Store the result in memory
HLT ; Halt the program

; Data Section
NUM1 DW 10 ; First number (10)
NUM2 DW 20 ; Second number (20)
RESULT DW 0 ; Memory to store the result

Explanation of Code:

1. MOV AX, [NUM1]: Loads the first number (NUM1) into register AX.
2. MOV BX, [NUM2]: Loads the second number (NUM2) into register BX.
3. ADD AX, BX: Adds the values of AX and BX, storing the result in AX.
4. MOV [RESULT], AX: Stores the result from AX into memory at the location
labeled RESULT.
5. HLT: Stops program execution.

Output:

Conversions Between Number

Systems
1. Binary to Octal

To convert binary to octal:

1. Group binary digits into sets of 3 bits (from right to left).

2. Convert each group into its equivalent octal value.

Example: Convert 110101 to Octal

● Binary: 110101 → Group as 000 110 101 (add leading zeros if needed).
● Octal: (110) = 6, (101) = 5 → Octal: 65

2. Octal to Hexadecimal

To convert octal to hexadecimal:

1. Convert octal to binary (each octal digit to 3 binary bits).

2. Group binary digits into sets of 4 bits (for hexadecimal).
3. Convert each group into its hexadecimal equivalent.

Example: Convert 65 (Octal) to Hexadecimal

1. Convert Octal to Binary:

○ 6 → 110, 5 → 101 → Binary: 110101
2. Group into 4 bits: 0001 1010 (add leading zeros).
3. Convert to Hexadecimal: (0001) = 1, (1010) = A → Hexadecimal: 1A

3. Hexadecimal to Decimal

To convert hexadecimal to decimal:

1. Multiply each digit by 16n16^n16n, where nnn is the position from the right
(starting at 0).
2. Sum the results.

Example: Convert 1A (Hexadecimal) to Decimal

 ● 1×161+A×1601 \times 16^1 + A \times 16^01×161+A×160
● 1×16+10×1=16+10=261 \times 16 + 10 \times 1 = 16 + 10 =
261×16+10×1=16+10=26 → Decimal: 26

4. Binary to Decimal

To convert binary to decimal:

1. Multiply each bit by 2n2^n2n, where nnn is the position from the right
(starting at 0).
2. Sum the results.

Example: Convert 110101 (Binary) to Decimal

● 1×25+1×24+0×23+1×22+0×21+1×201 \times 2^5 + 1 \times 2^4 + 0 \times

2^3 + 1 \times 2^2 + 0 \times 2^1 + 1 \times
2^01×25+1×24+0×23+1×22+0×21+1×20
● 32+16+0+4+0+1=5332 + 16 + 0 + 4 + 0 + 1 = 5332+16+0+4+0+1=53 →
Decimal: 53

5. Octal to Decimal

To convert octal to decimal:

1. Multiply each digit by 8n8^n8n, where nnn is the position from the right
(starting at 0).
2. Sum the results.

Example: Convert 65 (Octal) to Decimal

● 6×81+5×806 \times 8^1 + 5 \times 8^06×81+5×80

● 6×8+5×1=48+5=536 \times 8 + 5 \times 1 = 48 + 5 = 536×8+5×1=48+5=53
→ Decimal: 53

Summary of Examples:
 Input Conversion Outp
ut

110101 Binary to Octal 65

(Binary)

65 (Octal) Octal to 1A
Hexadecimal

1A Hexadecimal to 26
(Hexadecimal) Decimal

110101 Binary to Decimal 53

(Binary)

65 (Octal) Octal to Decimal 53

Number System Conversion Table

Binary Numbers Octal Numbers Decimal Numbers Hexadecimal Numbers

0000 0 0 0

0001 1 1 1

0010 2 2 2

0011 3 3 3
0100 4 4 4

0101 5 5 5

0110 6 6 6

0111 7 7 7

1000 10 8 8

1001 11 9 9

1010 12 10 A

1011 13 11 B

1100 14 12 C

1101 15 13 D

1110 16 14 E

1111 17 15 F