Chapter 9: 8086/8088 Hardware Specifications
9–1 PIN-OUTS AND THE PIN
FUNCTIONS
• In this section, we explain the function and
the multiple functions of each of the
microprocessor’s pins.
• In addition, we discuss the DC characteristics
to provide a basis for understanding the later
sections on buffering and latching.
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
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Barry B. Brey
The Pin-Out
• Figure 9–1 illustrates pin-outs of 8086.
– packaged in 40-pin dual in-line packages (DIPs)
• 8086 is a 16-bit microprocessor with a 16-bit
data bus;
– 8086 has pin connections AD0–AD15
– thus 8086 transfers 16-bit data more efficiently
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
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Barry B. Brey
Figure 9–1 (a) The pin-out of the 8086 in maximum mode; (b)
the pin-out of the 8086 in minimum mode.
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
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Barry B. Brey
Pin Connections
AD7 - AD0
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
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Barry B. Brey
Pin Connections
AD15 - AD8
• 8086 address/data bus lines compose upper
multiplexed address/data bus on the 8086.
• These lines contain address bits A15–A8
whenever ALE is a logic 1, and data bus
connections D15–D8 when ALE is a logic 0.
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Pin Connections A19/S6 - A16/S3
• Address/status bus bits are multiplexed to
provide address signals A19–A16 and status
bits S6–S3.
– status bit S6 is always logic 0,
– bit S5 indicates the condition of the IF flag bit
• S4 and S3 show which segment is accessed
during the current bus cycle.
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Pin Connections RD
• When read signal is logic 0, the data bus is
receptive to data from memory or I/O devices
– pin floats high-impedance state during a hold
acknowledge
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Pin Connections INTR
• Interrupt request is used to request a
hardware interrupt.
– If INTR is held high when IF = 1, 8086/8088
enters an interrupt acknowledge cycle after the
current instruction has completed execution
NMI
• The non-maskable interrupt input is similar
to INTR.
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Pin Connections RESET
• Causes the microprocessor to reset itself if
held high a minimum of four clocking periods.
– when 8086/8088 is reset, it executes instructions
at memory location FFFFOH
– also disables future interrupts by clearing IF flag
CLK
• The clock pin provides the basic timing signal.
– must have a duty cycle of 33 % (high for one third
of clocking period, low for two thirds) to provide
proper internal timing
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Pin Connections VCC
• This power supply input provides a +5.0 V,
±10 % signal to the microprocessor.
GND
• The ground connection is the return for the
power supply.
– 8086/8088 microprocessors have two pins
labeled GND—both must be connected to
ground for proper operation
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Pin Connections MN/MX
• Minimum/maximum mode pin selects either
minimum or maximum mode operation.
– if minimum mode selected, the MN/MX pin must
be connected directly to +5.0 V
BHE S7
• The bus high enable pin is used in 8086 to
enable the most-significant data bus bits
(D15–D8) during a read or a write operation.
• The state of S7 is always a logic 1.
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Minimum Mode Pins
• Minimum mode operation is obtained by
connecting the MN/MX pin directly to +5.0 V.
– do not connect to +5.0 V through a pull-up register;
it will not function correctly
IO/M or M/IO
• The IO/M (8088) or M/IO (8086) pin selects
memory or I/O.
– indicates the address bus contains either a
memory address or an I/O port address.
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Minimum Mode Pins WR
• Write line indicates 8086/8088 is outputting
data to a memory or I/O device.
– during the time WR is a logic 0, the data bus
contains valid data for memory or I/O
– high-impedance during a hold acknowledge
INTA
• The interrupt acknowledge signal is a
response to the INTR input pin.
– normally used to gate the interrupt vector number
onto the data bus in response to an interrupt
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Minimum Mode Pins ALE
• Address latch enable shows the 8086/8088
address/data bus contains an address.
– can be a memory address or an I/O port number
– ALE signal doesn’t float during hold acknowledge
DT/R
• The data transmit/receive signal shows that
the microprocessor data bus is transmitting
(DT/R = 1) or receiving (DT/R = 0) data.
– used to enable external data bus buffers
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Minimum Mode Pins DEN
• Data bus enable activates external data bus
buffers.
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
9–3 BUS BUFFERING AND
LATCHING
• Before 8086/8088 can be used with memory
or I/O interfaces, their multiplexed buses must
be demultiplexed.
• This section provides detail required to
demultiplex the buses and illustrates how
the buses are buffered for very large systems.
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Demultiplexing the Buses
• The address/data bus of the 8086/8088 is
multiplexed (shared) to reduce the number
of pins required for the integrated circuit
– the hardware designer must extract or
demultiplex information from these pins
• Memory & I/O require the address remain
valid and stable throughout a read/write cycle.
• If buses are multiplexed, the address changes
at the memory and I/O, causing them to read
or write data in the wrong locations
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
• All computer systems have three buses:
– an address bus that provides memory and I/O
with the memory address or the I/O port number
– a data bus that transfers data between the
microprocessor and the memory and I/O
– a control bus that provides control signals to
the memory and I/O
• These buses must be present in order to
interface to memory and I/O.
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Demultiplexing the 8086
• Fig 9–6 illustrates a demultiplexed 8086 with
all three buses:
• address (A19–A0 and BHE )
• data (D15–D0),
• control (M/IO,RD, and WR )
• Here, the memory and I/O system see the
8086 as a device with:
– a 20-bit address bus;16-bit data bus
– and a three-line control bus
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Figure 9–6 The 8086 microprocessor shown with a demultiplexed address
bus. This is the model used to build many 8086-based systems.
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
9–4 BUS TIMING
• It is essential to understand system bus timing
before choosing memory or I/O devices for
interfacing to 8086 or 8088 microprocessors.
• This section provides insight into operation
of the bus signals and the basic read/write
timing of the 8086/8088.
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Basic Bus Operation
• The three buses of 8086 function the same
way as any other microprocessor.
• If data are read from the memory the
microprocessor:
– outputs the memory address on the address bus
– issues a read memory signal (RD)
– and accepts the data via the data bus
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Simplified 8086/8088 read bus cycle.
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
Basic Bus Operation
• If data are written to memory the processor:
– outputs the memory address on the address bus
– outputs the data to be written on the data bus
– issues a write (WR) to memory
– and IO/M = 1 for 8086
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey
