Spartan-3E Starter Kit

Board User Guide

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Revision History
The following table shows the revision history for this document.

Date Version Revision

03/09/06 1.0a Initial release.

Spartan-3E Starter Kit Board User Guide www.xilinx.com UG230 (v1.0) March 9, 2006
Table of Contents

Preface: About This Guide

Acknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Chapter 1: Introduction and Overview

Choose the Starter Kit Board for Your Needs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Spartan-3E FPGA Features and Embedded Processing Functions . . . . . . . . . . . . . . . . 11
Learning Xilinx FPGA, CPLD, and ISE Development Software Basics . . . . . . . . . . . . 11
Advanced Spartan-3 Generation Development Boards . . . . . . . . . . . . . . . . . . . . . . . . . 11
Key Components and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Design Trade-Offs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Configuration Methods Galore! . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Voltages for all Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Related Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Chapter 2: Switches, Buttons, and Knob

Slide Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Locations and Labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Push-Button Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Locations and Labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Rotary Push-Button Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Locations and Labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Push-Button Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Rotary Shaft Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Discrete LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Locations and Labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Related Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Chapter 3: Clock Sources

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Clock Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Voltage Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
50 MHz On-Board Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

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Auxiliary Clock Oscillator Socket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

SMA Clock Input or Output Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
UCF Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Clock Period Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Related Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Chapter 4: FPGA Configuration Options

Configuration Mode Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PROG Push Button. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DONE Pin LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Programming the FPGA, CPLD, or Platform Flash PROM via USB . . . . . . . . . . . 28
Connecting the USB Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Programming via iMPACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Programming Platform Flash PROM via USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Generating the FPGA Configuration Bitstream File . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Generating the PROM File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Programming the Platform Flash PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Chapter 5: Character LCD Screen

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Character LCD Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Voltage Compatibility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Interaction with Intel StrataFlash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
LCD Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
DD RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
CG ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
CG RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Clear Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Return Cursor Home . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Entry Mode Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Display On/Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Cursor and Display Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Function Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Set CG RAM Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Set DD RAM Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Read Busy Flag and Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Write Data to CG RAM or DD RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Read Data from CG RAM or DD RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Four-Bit Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Transferring 8-Bit Data over the 4-Bit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Initializing the Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Power-On Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Display Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

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Writing Data to the Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Disabling the Unused LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Related Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Chapter 6: VGA Display Port

Signal Timing for a 60 Hz, 640x480 VGA Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
VGA Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Related Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Chapter 7: RS-232 Serial Ports

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Chapter 8: PS/2 Mouse/Keyboard Port

Keyboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Mouse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Voltage Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Related Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Chapter 9: Digital to Analog Converter (DAC)

SPI Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Disable Other Devices on the SPI Bus to Avoid Contention . . . . . . . . . . . . . . . . . . . . . 68
SPI Communication Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Communication Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Specifying the DAC Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
DAC Outputs A and B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
DAC Outputs C and D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Related Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Chapter 10: Analog Capture Circuit

Digital Outputs from Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Programmable Pre-Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Programmable Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
SPI Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Analog to Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
SPI Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Disable Other Devices on the SPI Bus to Avoid Contention . . . . . . . . . . . . . . . . . . 79

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Connecting Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Related Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Chapter 11: Intel StrataFlash Parallel NOR Flash PROM

StrataFlash Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Shared Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Character LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Xilinx XC2C64A CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
SPI Data Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Setting the FPGA Mode Select Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Related Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Chapter 12: SPI Serial Flash

UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Configuring from SPI Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Setting the FPGA Mode Select Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Creating an SPI Serial Flash PROM File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Setting the Configuration Clock Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Formatting an SPI Flash PROM File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Downloading the Design to SPI Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Downloading the SPI Flash using XSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Download and Install the XSPI Programming Utility. . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Attach a JTAG Parallel Programming Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Insert Jumper on JP8 and Hold PROG_B Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Programming the SPI Flash with the XSPI Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Additional Design Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Shared SPI Bus with Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Other SPI Flash Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Variant Select Pins, VS[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Jumper Block J11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Programming Header J12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Multi-Package Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Related Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Chapter 13: DDR SDRAM

DDR SDRAM Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Reserve FPGA VREF Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Related Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

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Chapter 14: 10/100 Ethernet Physical Layer Interface

Ethernet PHY Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
MicroBlaze Ethernet IP Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Related Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Chapter 15: Expansion Connectors

Hirose 100-pin FX2 Edge Connector (J3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Voltage Supplies to the Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Connector Pinout and FPGA Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Compatible Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Mating Receptacle Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Differential I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Using Differential Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Using Differential Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Six-Pin Accessory Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Header J1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Header J2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Header J4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Connectorless Debugging Port Landing Pads (J6) . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Related Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Chapter 16: XC2C64A CoolRunner-II CPLD

UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
FPGA Connections to CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Related Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Chapter 17: DS2432 1-Wire SHA-1 EEPROM

UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Related Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Appendix A: Schematics
FX2 Expansion Header, 6-pin Headers, and Connectorless Probe Header . . . . 132
RS-232 Ports, VGA Port, and PS/2 Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Ethernet PHY, Magnetics, and RJ-11 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
FPGA Configurations Settings, Platform Flash PROM, SPI Serial Flash, JTAG
Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
FPGA I/O Banks 0 and 1, Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
FPGA I/O Banks 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
XC2C64A CoolRunner-II CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

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Linear Technology ADC and DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Intel StrataFlash Parallel NOR Flash Memory and Micron DDR SDRAM . . . 152
Buttons, Switches, Rotary Encoder, and Character LCD . . . . . . . . . . . . . . . . . . . . . 154
DDR SDRAM Series Termination and FX2 Connector Differential Termination 156

Appendix B: Example User Constraints File (UCF)

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Preface

About This Guide

This user guide provides basic information on the Spartan-3E Starter Kit board
capabilities, functions, and design. It includes general information on how to use the
various peripheral functions included on the board. For detailed reference designs,
including VHDL or Verilog source code, please visit the following web link.
• Spartan™-3E Starter Kit Board Reference Page
http://www.xilinx.com/s3estarter

Acknowledgements
Xilinx wishes to thank the following companies for their support of the Spartan-3E Starter
Kit board:
• Intel Corporation for the 128 Mbit StrataFlash memory
• Linear Technology for the SPI-compatible A/D and D/A converters, the
programmable pre-amplifier, and the power regulators for the non-FPGA
components
• Micron Technology, Inc. for the 32M x 16 DDR SDRAM
• SMSC for the 10/100 Ethernet PHY
• STMicroelectronics for the 16M x 1 SPI serial Flash PROM
• Texas Instruments Incorporated for the three-rail TPS75003 regulator supplying most
of the FPGA supply voltages
• Xilinx, Inc. Configuration Solutions Division for the XCF04S Platform Flash PROM
and their support for the embedded USB programmer
• Xilinx, Inc. CPLD Division for the XC2C64A CoolRunner™-II CPLD

Guide Contents
This manual contains the following chapters:
• Chapter 1, “Introduction and Overview,” provides an overview of the key features of
the Spartan-3E Starter Kit board.
• Chapter 2, “Switches, Buttons, and Knob,” defines the switches, buttons, and knobs
present on the Spartan-3E Starter Kit board.
• Chapter 3, “Clock Sources,” describes the various clock sources available on the
Spartan-3E Starter Kit board.
• Chapter 4, “FPGA Configuration Options,” describes the configuration options for
the FPGA on the Spartan-3E Starter Kit board.

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Preface: About This Guide

• Chapter 5, “Character LCD Screen,” describes the functionality of the character LCD
screen.
• Chapter 6, “VGA Display Port,” describes the functionality of the VGA port.
• Chapter 7, “RS-232 Serial Ports,” describes the functionality of the RS-232 serial ports.
• Chapter 8, “PS/2 Mouse/Keyboard Port,” describes the functionality of the PS/2
mouse and keyboard port.
• Chapter 9, “Digital to Analog Converter (DAC),” describes the functionality of the
DAC.
• Chapter 10, “Analog Capture Circuit,” describes the functionality of the A/D
converter with a programmable gain pre-amplifier.
• Chapter 11, “Intel StrataFlash Parallel NOR Flash PROM,” describes the functionality
of the StrataFlash PROM.
• Chapter 12, “SPI Serial Flash,” describes the functionality of the SPI Serial Flash
memory.
• Chapter 13, “DDR SDRAM,” describes the functionality of the DDR SDRAM.
• Chapter 14, “10/100 Ethernet Physical Layer Interface,” describes the functionality of
the 10/100Base-T Ethernet physical layer interface.
• Chapter 15, “Expansion Connectors,” describes the various connectors available on
the Spartan-3E Starter Kit board.
• Chapter 16, “XC2C64A CoolRunner-II CPLD” describes how the CPLD is involved in
FPGA configuration when using Master Serial and BPI mode.
• Chapter 17, “DS2432 1-Wire SHA-1 EEPROM” provides a brief introduction to the
SHA-1 secure EEPROM for authenticating or copy-protecting FPGA configuration
bitstreams.
• Appendix A, “Schematics,” lists the schematics for the Spartan-3E Starter Kit board.
• Appendix B, “Example User Constraints File (UCF),” provides example code from a
UCF.

Additional Resources
To find additional documentation, see the Xilinx website at:
http://www.xilinx.com/literature.
To search the Answer Database of silicon, software, and IP questions and answers, or to
create a technical support WebCase, see the Xilinx website at:
http://www.xilinx.com/support.

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Chapter 1

Introduction and Overview

Thank you for purchasing the Xilinx Spartan™-3E Starter Kit. You will find it useful in
developing your Spartan-3E FPGA application.

Choose the Starter Kit Board for Your Needs

Depending on specific requirements, choose the Xilinx development board that best suits
your needs.

Spartan-3E FPGA Features and Embedded Processing Functions

The Spartan-3E Starter Kit board highlights the unique features of the Spartan-3E FPGA
family and provides a convenient development board for embedded processing
applications. The board highlights these features:
• Spartan-3E specific features
♦ Parallel NOR Flash configuration
♦ MultiBoot FPGA configuration from Parallel NOR Flash PROM
♦ SPI serial Flash configuration
• Embedded development
♦ MicroBlaze™ 32-bit embedded RISC processor
♦ PicoBlaze™ 8-bit embedded controller
♦ DDR memory interfaces

Learning Xilinx FPGA, CPLD, and ISE Development Software Basics

The Spartan-3E Starter Kit board is more advanced and complex compared to other
Spartan development boards. To learn the basics of Xilinx FPGA or CPLD design and how
to use the Xilinx ISE development software, consider using the High Volume Starter Kit
Bundle, which includes both a Spartan-3 FPGA development board and a Xilinx
CoolRunner™-II/XC9500XL CPLD development board at a very affordable price.
• High Volume Starter Kit Bundle (HW-SPAR3-CPLD-DK)
http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?
key=HW-SPAR3-CPLD-DK

Advanced Spartan-3 Generation Development Boards

The Spartan-3E Starter Kit board demonstrates the basic capabilities of the MicroBlaze
embedded processor and the Xilinx Embedded Development Kit (EDK). For more

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Chapter 1: Introduction and Overview

advanced development on a board with additional peripherals and FPGA logic, consider
the SP-305 Development Board:
• Spartan-3 SP-305 Development Board (HW-SP305-xx)
http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=
HW-SP305-US
Also consider the capable boards offered by Xilinx partners:
• Spartan-3 and Spartan-3E Board Interactive Search
http://www.xilinx.com/products/devboards/index.htm

Key Components and Features

The key features of the Spartan-3E Starter Kit board are:
• Xilinx XC3S500E Spartan-3E FPGA
♦ Up to 232 user-I/O pins
♦ 320-pin FBGA package
♦ Over 10,000 logic cells
• Xilinx 4 Mbit Platform Flash configuration PROM
• Xilinx 64-macrocell XC2C64A CoolRunner CPLD
• 64 MByte (512 Mbit) of DDR SDRAM, x16 data interface, 100+ MHz
• 16 MByte (128 Mbit) of parallel NOR Flash (Intel StrataFlash)
♦ FPGA configuration storage
♦ MicroBlaze code storage/shadowing
• 16 Mbits of SPI serial Flash (STMicro)
♦ FPGA configuration storage
♦ MicroBlaze code shadowing
• 2-line, 16-character LCD screen
• PS/2 mouse or keyboard port
• VGA display port
• 10/100 Ethernet PHY (requires Ethernet MAC in FPGA)
• Two 9-pin RS-232 ports (DTE- and DCE-style)
• On-board USB-based FPGA/CPLD download/debug interface
• 50 MHz clock oscillator
• SHA-1 1-wire serial EEPROM for bitstream copy protection
• Hirose FX2 expansion connector
• Three Digilent 6-pin expansion connectors
• Four-output, SPI-based Digital-to-Analog Converter (DAC)
• Two-input, SPI-based Analog-to-Digital Converter (ADC) with programmable-gain
pre-amplifier
• ChipScope™ SoftTouch debugging port
• Rotary-encoder with push-button shaft
• Eight discrete LEDs
• Four slide switches

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Design Trade-Offs

• Four push-button switches

• SMA clock input
• 8-pin DIP socket for auxiliary clock oscillator

Design Trade-Offs
A few system-level design trade-offs were required in order to provide the Spartan-3E
Starter Kit board with the most functionality.

Configuration Methods Galore!

A typical FPGA application uses a single non-volatile memory to store configuration
images. To demonstrate new Spartan-3E capabilities, the starter kit board has three
different configuration memory sources that all need to function well together. The extra
configuration functions make the starter kit board more complex than typicalSpartan-3E
applications.
The starter kit board also includes an on-board USB-based JTAG programming interface.
The on-chip circuitry simplifies the device programming experience. In typical
applications, the JTAG programming hardware resides off-board or in a separate
programming module, such as the Xilinx Platform USB cable.

Voltages for all Applications

The Spartan-3E Starter Kit board showcases a triple-output regulator developed by Texas
Instruments, the TPS75003 specifically to power Spartan-3 and Spartan-3E FPGAs. This
regulator is sufficient for most stand-alone FPGA applications. However, the starter kit
board includes DDR SDRAM, which requires its own high-current supply. Similarly, the
USB-based JTAG download solution requires a separate 1.8V supply.

Related Resources
• Xilinx MicroBlaze Soft Processor
http://www.xilinx.com/microblaze
• Xilinx PicoBlaze Soft Processor
http://www.xilinx.com/picoblaze
• Xilinx Embedded Development Kit
http://www.xilinx.com/ise/embedded_design_prod/platform_studio.htm
• Xilinx software tutorials
http://www.xilinx.com/support/techsup/tutorials/
• Texas Instruments TPS75003
http://focus.ti.com/docs/prod/folders/print/tps75003.html

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Chapter 1: Introduction and Overview

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Chapter 2

Switches, Buttons, and Knob

Slide Switches

Locations and Labels

The Spartan-3E Starter Kit board has four slide switches, as shown in Figure 2-1. The slide
switches are located in the lower right corner of the board and are labeled SW3 through
SW0. Switch SW3 is the left-most switch, and SW0 is the right-most switch.

HIGH

LOW

SW3 SW2 SW1 SW0

(N17) (H18) (L14) (L13) UG230_c2_01_021206

Figure 2-1: Four Slide Switches

Operation
When in the UP or ON position, a switch connects the FPGA pin to 3.3V, a logic High.
When DOWN or in the OFF position, the switch connects the FPGA pin to ground, a logic
Low. The switches typically exhibit about 2 ms of mechanical bounce and there is no active
debouncing circuitry, although such circuitry could easily be added to the FPGA design
programmed on the board.

UCF Location Constraints

Figure 2-2 provides the UCF constraints for the four slide switches, including the I/O pin
assignment and the I/O standard used. The PULLUP resistor is not required, but it defines
the input value when the switch is in the middle of a transition.

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Chapter 2: Switches, Buttons, and Knob

NET "SW<0>" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;

NET "SW<1>" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;
NET "SW<2>" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ;
NET "SW<3>" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ;

Figure 2-2: UCF Constraints for Slide Switches

Push-Button Switches

Locations and Labels

The Spartan-3E Starter Kit board has four momentary-contact push-button switches,
shown in Figure 2-3. The push buttons are located in the lower left corner of the board and
are labeled BTN_NORTH, BTN_EAST, BTN_SOUTH, and BTN_WEST. The FPGA pins
that connect to the push buttons appear in parentheses in Figure 2-3 and the associated
UCF appears in Figure 2-5.

Rotary Push Button Switch

ROT_A: (K18) Requires an internal pull-up
BTN_NORTH ROT_B: (G18) Requires an internal pull-up
(V4) ROT_CENTER: (V16) Requires an internal pull-down

BTN_WEST BTN_EAST
(D18) (H13)

BTN_SOUTH
(K17) UG230_c2_02_021206
Notes:
1. All BTN_* push-button inputs require an internal pull-down resistor.
2. BTN_SOUTH is also used as a soft reset in some FPGA applications.

Figure 2-3: Four Push-Button Switches Surround Rotary Push-Button Switch

Operation
Pressing a push button connects the associated FPGA pin to 3.3V, as shown in Figure 2-4.
Use an internal pull-down resistor within the FPGA pin to generate a logic Low when the
button is not pressed. Figure 2-5 shows how to specify a pull-down resistor within the
UCF. There is no active debouncing circuitry on the push button.

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Rotary Push-Button Switch

Push Button FPGA I/O Pin

3.3V

BTN_* Signal

UG230_c2_03_021206

Figure 2-4: Push-Button Switches Require an Internal Pull-Down Resistor in FPGA

Input Pin
In some applications, the BTN_SOUTH push-button switch is also a soft reset that
selectively resets functions within the FPGA.

UCF Location Constraints

Figure 2-5 provides the UCF constraints for the four push-button switches, including the
I/O pin assignment and the I/O standard used, and defines a pull-down resistor on each
input.

NET "BTN_EAST" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN ;

NET "BTN_NORTH" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN ;
NET "BTN_SOUTH" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ;
NET "BTN_WEST" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN ;

Figure 2-5: UCF Constraints for Push-Button Switches

Rotary Push-Button Switch

Locations and Labels

The rotary push-button switch is located in the center of the four individual push-button
switches, as shown in Figure 2-3. The switch produces three outputs. The two shaft
encoder outputs are ROT_A and ROT_B. The center push-button switch is ROT_CENTER.

Operation
The rotary push-button switch integrates two different functions. The switch shaft rotates
and outputs values whenever the shaft turns. The shaft can also be pressed, acting as a
push-button switch.

Push-Button Switch
Pressing the knob on the rotary/push-button switch connects the associated FPGA pin to
3.3V, as shown in Figure 2-6. Use an internal pull-down resistor within the FPGA pin to
generate a logic Low. Figure 2-9 shows how to specify a pull-down resistor within the UCF.
There is no active debouncing circuitry on the push button.

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Chapter 2: Switches, Buttons, and Knob

Rotary / Push Button

FPGA I/O Pin

3.3V

ROT_CENTER Signal

UG230_c2_05_021206

Figure 2-6: Push-Button Switches Require Internal Pull-up Resistor in FPGA Input
Pin

Rotary Shaft Encoder

In principal, the rotary shaft encoder behaves much like a cam, connected to central shaft.
Rotating the shaft then operates two push-button switches, as shown in Figure 2-7.
Depending on which way the shaft is rotated, one of the switches opens before the other.
Likewise, as the rotation continues, one switch closes before the other. However, when the
shaft is stationary, also called the detent position, both switches are closed.

A pull-up resistor in each input pin

generates a ‘1’ for an open switch. FPGA
See the UCF file for details on
Vcco
specifying the pull-up resistor.

A=‘0’

Vcco

Rotary Shaft
Encoder

B=‘1’ UG230_c2_06_030606
GND

Figure 2-7: Basic example of rotary shaft encoder circuitry

Closing a switch connects it to ground, generating a logic Low. When the switch is open, a
pull-up resistor within the FPGA pin pulls the signal to a logic High. The UCF constraints
in Figure 2-9 describe how to define the pull-up resistor.
The FPGA circuitry to decode the ‘A’ and ‘B’ inputs is simple, but must consider the
mechanical switching noise on the inputs, also called chatter. As shown in Figure 2-8, the
chatter can falsely indicate extra rotation events or even indicate rotations in the opposite

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Discrete LEDs

direction! See the Rotary Encoder Interface reference design in“Related Resources” for an
example.

Rising edge on ‘A’ when ‘B’ is Low indicates RIGHT (clockwise) rotation
Switch opening chatter on ‘A’
Rotating RIGHT injects false “clicks” to the RIGHT

Detent
Detent

Switch closing chatter on ‘B’

injects false “clicks” to the LEFT
(’B’ rising edge when ‘A’ is Low)
UG230_c2_07_030606

Figure 2-8: Outputs from Rotary Shaft Encoder May Include Mechanical Chatter

UCF Location Constraints

Figure 2-9 provides the UCF constraints for the four push-button switches, including the
I/O pin assignment and the I/O standard used, and defines a pull-down resistor on each
input.

NET "ROT_A" LOC = "K18" | IOSTANDARD = LVTTL | PULLUP ;

NET "ROT_B" LOC = "G18" | IOSTANDARD = LVTTL | PULLUP ;
NET "ROT_CENTER" LOC = "V16" | IOSTANDARD = LVTTL | PULLDOWN ;

Figure 2-9: UCF Constraints for Rotary Push-Button Switch

Discrete LEDs

Locations and Labels

The Spartan-3E Starter Kit board has eight individual surface-mount LEDs located above
the slide switches as shown in Figure 2-10. The LEDs are labeled LED7 through LED0.
LED7 is the left-most LED, LED0 the right-most LED.
LED5: (D11)
LED4: (C11)

LED2: (E11)
LED1: (E12)
LED3: (F11)

LED0: (F12)
LED6: (E9)
LED7: (F9)

UG230_c2_04_021206

Figure 2-10: Eight Discrete LEDs

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Chapter 2: Switches, Buttons, and Knob

Operation
Each LED has one side connected to ground and the other side connected to a pin on the
Spartan-3E device via a 390Ω current limiting resistor. To light an individual LED, drive
the associated FPGA control signal High.

UCF Location Constraints

Figure 2-11 provides the UCF constraints for the four push-button switches, including the
I/O pin assignment, the I/O standard used, the output slew rate, and the output drive
current.

NET "LED<7>" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "LED<6>" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<5>" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<4>" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

Figure 2-11: UCF Constraints for Eight Discrete LEDs

Related Resources
• Rotary Encoder Interface for Spartan-3E Starter Kit (Reference Design)
http://www.xilinx.com/s3estarter

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Chapter 3

Clock Sources
Overview
As shown in Figure 3-1, the Spartan-3E Starter Kit board supports three primary clock
input sources, all of which are located below the Xilinx logo, near the Spartan-3E logo.
• The board includes an on-board 50 MHz clock oscillator.
• Clocks can be supplied off-board via an SMA-style connector. Alternatively, the FPGA
can generate clock signals or other high-speed signals on the SMA-style connector.
• Optionally install a separate 8-pin DIP-style clock oscillator in the supplied socket.

Bank 0, Oscillator Voltage 8-Pin DIP Oscillator Socket

Controlled by Jumper JP9 CLK_AUX: (B8)

On-Board 50 MHz Oscillator SMA Connector

CLK_50MHz: (C9) CLK_SMA: (A10)
UG230_c3_01_030306

Figure 3-1: Available Clock Inputs

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Chapter 3: Clock Sources

Clock Connections
Each of the clock inputs connect directly to a global buffer input in I/O Bank 0, along the
top of the FPGA. As shown in Table 3-1, each of the clock inputs also optimally connects to
an associated DCM.

Table 3-1: Clock Inputs and Associated Global Buffers and DCMs
Clock Input FPGA Pin Global Buffer Associated DCM
CLK_50MHZ C9 GCLK10 DCM_X0Y1
CLK_AUX B8 GCLK8 DCM_X0Y1
CLK_SMA A10 GCLK7 DCM_X1Y1

Voltage Control
The voltage for all I/O pins in FPGA I/O Bank 0 is controlled by jumper JP9.
Consequently, these clock resources are also controlled by jumper JP9. By default, JP9 is set
for 3.3V. The on-board oscillator is a 3.3V device and might not perform as expected when
jumper JP9 is set for 2.5V.

50 MHz On-Board Oscillator

The board includes a 50 MHz oscillator with a 40% to 60% output duty cycle. The oscillator
is accurate to ±2500 Hz or ±50 ppm.

Auxiliary Clock Oscillator Socket

The provided 8-pin socket accepts clock oscillators that fit the 8-pin DIP footprint. Use this
socket if the FPGA application requires a frequency other than 50 MHz. Alternatively, use
the FPGA’s Digital Clock Manager (DCM) to generate or synthesize other frequencies from
the on-board 50 MHz oscillator.

SMA Clock Input or Output Connector

To provide a clock from an external source, connect the input clock signal to the SMA
connector. The FPGA can also generate a single-ended clock output or other high-speed
signal on the SMA clock connector for an external device.

UCF Constraints
The clock input sources require two different types of constraints. The location constraints
define the I/O pin assignments and I/O standards. The period constraints define the clock
period—and consequently the clock frequency—and the duty cycle of the incoming clock
signal.

Location
Figure 3-2 provides the UCF constraints for the three clock input sources, including the
I/O pin assignment and the I/O standard used. The settings assume that jumper JP9 is set
for 3.3V. If JP9 is set for 2.5V, adjust the IOSTANDARD settings accordingly.

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Related Resources

NET "CLK_50MHZ" LOC = "C9" | IOSTANDARD = LVCMOS33 ;

NET "CLK_SMA" LOC = "A10" | IOSTANDARD = LVCMOS33 ;
NET "CLK_AUX" LOC = "B8" | IOSTANDARD = LVCMOS33 ;
Figure 3-2: UCF Location Constraints for Clock Sources

Clock Period Constraints

The Xilinx ISE development software uses timing-driven logic placement and routing. Set
the clock PERIOD constraint as appropriate. An example constraint appears in Figure 3-3
for the on-board 50 MHz clock oscillator. The CLK_50MHZ frequency is 50 MHz, which
equates to a 20 ns period. The output duty cycle from the oscillator ranges between 40% to
60%.

# Define clock period for 50 MHz oscillator

NET "CLK_50MHZ" PERIOD = 20.0ns HIGH 40%;

Figure 3-3: UCF Clock PERIOD Constraint

Related Resources
• Epson SG-8002JF Series Oscillator Data Sheet (50 MHz Oscillator)
http://www.eea.epson.com/go/Prod_Admin/Categories/EEA/QD/Crystal_Oscillators/
prog_oscillators/go/Resources/TestC2/SG8002JF

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Chapter 3: Clock Sources

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Chapter 4

FPGA Configuration Options

The Spartan-3E Starter Kit board supports a variety of FPGA configuration options:
• Download FPGA designs directly to the Spartan-3E FPGA via JTAG, using the on-
board USB interface. The on-board USB-JTAG logic also provides in-system
programming for the on-board Platform Flash PROM and the Xilinx XC2C64A CPLD.
SPI serial Flash and StrataFlash programming are performed separately.
• Program the on-board 4 Mbit Xilinx XCF04S serial Platform Flash PROM, then
configure the FPGA from the image stored in the Platform Flash PROM using Master
Serial mode.
• Program the on-board 16 Mbit ST Microelectronics SPI serial Flash PROM, then
configure the FPGA from the image stored in the SPI serial Flash PROM using SPI
mode.
• Program the on-board 128 Mbit Intel StrataFlash parallel NOR Flash PROM, then
configure the FPGA from the image stored in the Flash PROM using BPI Up or BPI
Down configuration modes. Further, an FPGA application can dynamically load two
different FPGA configurations using the Spartan-3E FPGA’s MultiBoot mode. See the
Spartan-3E data sheet (DS312) for additional details on the MultiBoot feature.
Figure 4-1 indicates the position of the USB download/programming interface and the on-
board non-volatile memories that potentially store FPGA configuration images.Figure 4-2
provides additional details on configuration options.

16 Mbit ST Micro SPI Serial Flash

Serial Peripheral Interface (SPI) mode

USB-based Download/Debug Port Configuration Options

Uses standard USB cable PROG_B button, Platform Flash PROM, mode pins

128 Mbit Intel StrataFlash

Parallel NOR Flash memory
Byte Peripheral Interface (BPI) mode

UG230_c4_01_022006

Figure 4-1: Spartan-3E Starter Kit FPGA Configuration Options

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Chapter 4: FPGA Configuration Options

Configuration Mode Jumper Settings (Header J30)

Select between three on-board configuration sources

DONE Pin LED PROG_B Push Button Switch

Lights up when FPGA successfully configured Press and release to restart configuration

64 Macrocell Xilinx XC2C64A CoolRunner CPLD

4 Mbit Xilinx Platform Flash PROM Controller upper address lines in BPI mode and
Configuration storage for Master Serial mode Platform Flash chip select (User programmable)
UG230_c4_02_030906

Figure 4-2: Detailed Configuration Options

The configuration mode jumpers determine which configuration mode the FPGA uses
when power is first applied, or whenever the PROG button is pressed.
The DONE pin LED lights when the FPGA successfully finishes configuration.
Pressing the PROG button forces the FPGA to restart its configuration process.
The 4 Mbit Xilinx Platform Flash PROM provides easy, JTAG-programmable configuration
storage for the FPGA. The FPGA configures from the Platform Flash using Master Serial
mode.
The 64-macrocell XC2C64A CoolRunner II CPLD provides additional programming
capabilities and flexibility when using the BPI Up, BPI Down, or MultiBoot configuration
modes and loading the FPGA from the StrataFlash parallel Flash PROM. The CPLD is user-
programmable.

Configuration Mode Jumpers

As shown in Table 4-1, the J30 jumper block settings control the FPGA’s configuration
mode. Inserting a jumper grounds the associated mode pin. Insert or remove individual
jumpers to select the FPGA’s configuration mode and associated configuration memory
source.

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PROG Push Button

Table 4-1: Spartan-3E Configuration Mode Jumper Settings (Header J30 in

Figure 4-2)
Configuration Mode Pins
Mode M2:M1:M0 FPGA Configuration Image Source Jumper Settings
Master Serial 0:0:0 Platform Flash PROM
M0
M1
M2
J30

SPI 1:1:0 SPI Serial Flash PROM starting at

(see address 0 M0
Chapter 12, M1
“SPI Serial M2
Flash”)
J30

BPI Up 0:1:0 StrataFlash parallel Flash PROM,

(see starting at address 0 and M0
Chapter 11, incrementing through address M1
“Intel space. The CPLD controls address M2
StrataFlash lines A[24:20] during BPI
configuration. J30
Parallel NOR
Flash
PROM”)
BPI Down 0:1:1 StrataFlash parallel Flash PROM,
(see starting at address 0x1FF_FFFF and M0
Chapter 11, decrementing through address M1
“Intel space. The CPLD controls address M2
StrataFlash lines A[24:20] during BPI
configuration. J30
Parallel NOR
Flash
PROM”)
JTAG 0:1:0 Downloaded from host via USB-
JTAG port M0
M1
M2
J30

PROG Push Button

The PROG push button, shown in Figure 4-2, page 26, forces the FPGA to reconfigure from
the selected configuration memory source. Press and release this button to restart the
FPGA configuration process at any time.

DONE Pin LED

The DONE pin LED, shown in Figure 4-2, page 26, lights whenever the FPGA is
successfully configured. If this LED is not lit, then the FPGA is not configured.

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Chapter 4: FPGA Configuration Options

Programming the FPGA, CPLD, or Platform Flash PROM via USB

As shown in Figure 4-1, page 25, the Spartan-3E Starter Kit includes embedded USB-based
programming logic and an USB endpoint with a Type B connector. Via a USB cable
connection with the host PC, the iMPACT programming software directly programs the
FPGA, the Platform Flash PROM, or the on-board CPLD. Direct programming of the
parallel or serial Flash PROMs is not presently supported.

Connecting the USB Cable

The kit includes a standard USB Type A/Type B cable, similar to the one shown in
Figure 4-3. The actual cable color might vary from the picture.

USB Type B Connector

Connects to Starter Kit's USB connector

USB Type A Connector

Connects to computer's USB connector
UG230_c4_04_030306

Figure 4-3: Standard USB Type A/Type B Cable

The wider and narrower Type A connector fits the USB connector at the back of the
computer.
After installing the Xilinx software, connect the square Type B connector to the Spartan-3E
Starter Kit board, as shown in Figure 4-4. The USB connector is on the left side of the board,
immediately next to the Ethernet connector. When the board is powered on, the Windows
operating system should recognize and install the associated driver software.

UG230_c4_05_030306

Figure 4-4: Connect the USB Type B Connector to the Starter Kit Board Connector
When the USB cable driver is successfully installed and the board is correctly connected to
the PC, a green LED lights up, indicating a good connection.

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Programming the FPGA, CPLD, or Platform Flash PROM via USB

Programming via iMPACT

After successfully compiling an FPGA design using the Xilinx development software, the
design can be downloaded using the iMPACT programming software and the USB cable.
To begin programming, connect the USB cable to the starter kit board and apply power to
the board. Then, double-click Configure Device (iMPACT) from within Project
Navigator, as shown in Figure 4-5.

UG230_c4_06_022406

Figure 4-5: Double-Click to Invoke iMPACT

If the board is connected properly, the iMPACT programming software automatically
recognizes the three devices in the JTAG programming file, as shown in Figure 4-6. If not
already prompted, click the first device in the chain, the Spartan-3E FPGA, to highlight it.
Right-click the FPGA and select Assign New Configuration File. Select the desired
FPGA configuration file and click OK.

UG230_c4_07_022406

Figure 4-6: Right-Click to Assign a Configuration File to the Spartan-3E FPGA

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Chapter 4: FPGA Configuration Options

If the original FPGA configuration file used the default StartUp clock source, CCLK,
iMPACT issues the warning message shown in Figure 4-7. This message can be safely
ignored. When downloading via JTAG, the iMPACT software must change the StartUP
clock source to use the TCK JTAG clock source.

UG230_c4_08_022406

Figure 4-7: iMPACT Issues a Warning if the StartUp Clock Was Not CCLK
To start programming the FPGA, right-click the FPGA and select Program. The iMPACT
software reports status during programming process. Direct programming to the FPGA
takes a few seconds to less than a minute, depending on the speed of the PC’s USB port and
the iMPACT settings.

UG230_c4_09_022406

Figure 4-8: Right-Click to Program the Spartan-3E FPGA

When the FPGA successfully programs, the iMPACT software indicates success, as shown
in Figure 4-9. The FPGA application is now executing on the board and the DONE pin LED
(see Figure 4-2) lights up.

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Programming the FPGA, CPLD, or Platform Flash PROM via USB

UG230_c4_10_022406

Figure 4-9: iMPACT Programming Succeeded, the FPGA’s DONE Pin is High

Programming Platform Flash PROM via USB

The on-board USB-JTAG circuitry also programs the Xilinx XCF04S serial Platform Flash
PROM. The steps provided in this section describe how to set up the PROM file and how
to download it to the board to ultimately program the FPGA.

Generating the FPGA Configuration Bitstream File

Before generating the PROM file, create the FPGA bitstream file. The FPGA provides an
output clock, CCLK, when loading itself from an external PROM. The FPGA’s internal
CCLK oscillator always starts at its slowest setting, approximately 1.5 MHz. Most external
PROMs support a higher frequency. Increase the CCLK frequency as appropriate to reduce
the FPGA’s configuration time. The Xilinx XCF04S Platform Flash supports a 25 MHz
CCLK frequency.
Right-click Generator Programming File in the Processes pane, as shown in
Figure 4-10. Left-click Properties.

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Chapter 4: FPGA Configuration Options

UG230_c4_11_022706

Figure 4-10: Set Properties for Bitstream Generator

Click Configuration Options as shown in Figure 4-11. Using the Configuration
Rate drop list, choose 25 to increase the internal CCLK oscillator to approximately
25 MHz, the fastest frequency when using an XCF04S Platform Flash PROM. Click OK
when finished.

UG230_c4_12_022706

Figure 4-11: Set CCLK Configuration Rate under Configuration Options

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Programming the FPGA, CPLD, or Platform Flash PROM via USB

To regenerate the programming file, double-click Generate Programming File, as

shown in Figure 4-12.

UG230_c4_13_022706

Figure 4-12: Double-Click Generate Programming File

Generating the PROM File

After generating the program file, double-click Generate PROM, ACE, or JTAG File
to launch the iMPACT software, as shown in Figure 4-13.

UG230_c4_14_022706

Figure 4-13: Double-Click Generate PROM, ACE, or JTAG File

After iMPACT starts, double-click PROM File Formatter, as shown in Figure 4-14.

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Chapter 4: FPGA Configuration Options

UG230_c4_15_022706

Figure 4-14: Double-Click PROM File Formatter

Choose Xilinx PROM as the target PROM type, as shown in Figure 4-15. Select from any
of the PROM File Formats; the Intel Hex format (MCS) is popular. Enter the Location of
the directory and the PROM File Name. Click Next > when finished.

UG230_c4_16_022706

Figure 4-15: Choose the PROM Target Type, the, Data Format, and File Location

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Programming the FPGA, CPLD, or Platform Flash PROM via USB

The Spartan-3E Starter Kit board has an XCF04S Platform Flash PROM. Select xcf04s
from the drop list, as shown in Figure 4-16. Click Add, then click Next >.

UG230_c4_17_022706

Figure 4-16: Choose the XCF04S Platform Flash PROM

The PROM Formatter then echoes the settings, as shown in Figure 4-17. Click Finish.

UG230_c4_18_022706

Figure 4-17: Click Finish after Entering PROM Formatter Settings

The PROM Formatter then prompts for the name(s) of the FPGA configuration bitstream
file. As shown in Figure 4-18, click OK to start selecting files. Select an FPGA bitstream file
(*.bit). Choose No after selecting the last FPGA file. Finally, click OK to continue.

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Chapter 4: FPGA Configuration Options

UG230_c4_19_022706

Figure 4-18: Enter FPGA Configuration Bitstream File(s)

When PROM formatting is complete, the iMPACT software presents the present settings
by showing the PROM, the select FPGA bitstream(s), and the amount of PROM space
consumed by the bitstream. Figure 4-19 shows an example for a single XC3S500E FPGA
bitstream stored in an XCF04S Platform Flash PROM.

UG230_c4_20_022706

Figure 4-19: PROM Formatting Completed

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Programming the FPGA, CPLD, or Platform Flash PROM via USB

To generate the actual PROM file, click Operations Æ Generate File as shown in
Figure 4-20.

UG230_c4_21_022706

Figure 4-20: Click Operations Æ Generate File to Create the Formatted PROM File
The iMPACT software indicates that the PROM file was successfully created, as shown in
Figure 4-21.

UG230_c4_22_022706

Figure 4-21: PROM File Formatter Succeeded

Programming the Platform Flash PROM

To program the formatted PROM file into the Platform Flash PROM via the on-board USB-
JTAG circuitry, follow the steps outlined in this subsection.
Place the iMPACT software in the JTAG Boundary Scan mode, either by choosing
Boundary Scan in the iMPACT Modes pane, as shown in Figure 4-22, or by clicking on
the Boundary Scan tab.

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Chapter 4: FPGA Configuration Options

UG230_c4_23_022706

Figure 4-22: Switch to Boundary Scan Mode

Assign the PROM file to the XCF04S Platform Flash PROM on the JTAG chain, as shown in
Figure 4-23. Right-click the PROM icon, then click Assign New Configuration File.
Select a previously generated PROM format file and click OK.

UG230_c4_24_022806

Figure 4-23: Assign the PROM File to the XCF04S Platform Flash PROM
To start programming the PROM, right-click the PROM icon and then click Program..

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Programming the FPGA, CPLD, or Platform Flash PROM via USB

UG230_c4_25_022806

Figure 4-24: Program the XCF04S Platform Flash PROM

The programming software again prompts for the PROM type to be programmed. Select
xcf04s and click OK, as shown in Figure 4-25.

UG230_c4_26_022806

Figure 4-25: Select XCF04S Platform Flash PROM

Before programming, choose the programming options available in Figure 4-26. Checking
the Erase Before Programming option erases the Platform Flash PROM completely
before programming, ensuring that no previous data lingers. The Verify option checks
that the PROM was correctly programmed and matches the downloaded configuration
bitstream. Both these options are recommended even though they increase overall
programming time.
The Load FPGA option immediately forces the FPGA to reconfigure after programming
the Platform Flash PROM. The FPGA’s configuration mode pins must be set for Master
Serial mode, as defined in Table 4-1, page 27. Click OK when finished.

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Chapter 4: FPGA Configuration Options

UG230_c4_27_022806

Figure 4-26: PROM Programming Options

The iMPACT software indicates if programming was successful or not. If programming
was successful and the Load FPGA option was left unchecked, push the PROG_B push-
button switch shown in Figure 4-2, page 26 to force the FPGA to reconfigure from the
newly programmed Platform Flash PROM. If the FPGA successfully configures, the DONE
LED, also shown in Figure 4-2, lights up.

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Chapter 5

Character LCD Screen

Overview
The Spartan-3E Starter Kit board prominently features a 2-line by 16-character liquid
crystal display (LCD). The FPGA controls the LCD via the 4-bit data interface shown in
Figure 5-1. Although the LCD supports an 8-bit data interface, the Starter Kit board uses a
4-bit data interface to remain compatible with other Xilinx development boards and to
minimize total pin count.

Spartan-3E FPGA Character LCD

SF_D<11> 390Ω
(M15) DB7
SF_D<10> 390Ω
(P17) DB6 Four-bit data
SF_D<9> 390Ω interface
(R16) DB5
SF_D<8> 390Ω
(R15) DB4

DB[3:0] Unused
LCD_E
(M18) E
LCD_RS
(L18) RS
LCD_RW
(L17) R/W

Intel StrataFlash

D[11:8]
‘1’
SF_CE0 CE0

UG230_c5_01_022006

Figure 5-1: Character LCD Interface

Once mastered, the LCD is a practical way to display a variety of information using
standard ASCII and custom characters. However, these displays are not fast. Scrolling the
display at half-second intervals tests the practical limit for clarity. Compared with the
50 MHz clock available on the board, the display is slow. A PicoBlaze processor efficiently
controls display timing plus the actual content of the display.

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Chapter 5: Character LCD Screen

Character LCD Interface Signals

Table 5-1 shows the interface character LCD interface signals.

Table 5-1: Character LCD Interface

Signal Name FPGA Pin Function
SF_D<11> M15 Data bit DB7 Shared with StrataFlash pins
SF_D<10> P17 Data bit DB6 SF_D<11:8>
SF_D<9> R16 Data bit DB5
SF_D<8> R15 Data bit DB4
LCD_E M18 Read/Write Enable Pulse
0: Disabled
1: Read/Write operation enabled
LCD_RS L18 Register Select
0: Instruction register during write operations. Busy
Flash during read operations
1: Data for read or write operations
LCD_RW L17 Read/Write Control
0: WRITE, LCD accepts data
1: READ, LCD presents data

Voltage Compatibility
The character LCD is power by +5V. The FPGA I/O signals are powered by 3.3V.
However, the FPGA’s output levels are recognized as valid Low or High logic levels by the
LCD. The LCD controller accepts 5V TTL signal levels and the 3.3V LVCMOS outputs
provided by the FPGA meet the 5V TTL voltage level requirements.
The 390Ω series resistors on the data lines prevent overstressing on the FPGA and
StrataFlash I/O pins when the character LCD drives a High logic value. The character LCD
drives the data lines when LCD_RW is High. Most applications treat the LCD as a write-
only peripheral and never read from from the display.

Interaction with Intel StrataFlash

As shown in Figure 5-1, the four LCD data signals are also shared with StrataFlash data
lines SF_D<11:8>. As shown in Table 5-2, the LCD/StrataFlash interaction depends on the
application usage in the design. When the StrataFlash memory is disabled (SF_CE0 =
High), then the FPGA application has full read/write access to the LCD. Conversely, when
LCD read operations are disabled (LCD_RW = Low), then the FPGA application has full
read/write access to the StrataFlash memory

Table 5-2: LCD/StrataFlash Control Interaction

SF_CE0 SF_BYTE LCD_RW Operation
1 X X StrataFlash disabled. Full read/write access to LCD.
X X 0 LCD write access only. Full access to StrataFlash.
X 0 X StrataFlash in byte-wide (x8) mode. Upper data lines
are not used. Full access to both LCD and StrataFlash.
Notes:
1. ‘X’ indicates a don’t care, can be either 0 or 1.

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UCF Location Constraints

If the StrataFlash memory is in byte-wide (x8) mode (SF_BYTE = Low), the FPGA
application has full simultaneous read/write access to both the LCD and the StrataFlash
memory. In byte-wide mode, the StrataFlash memory does not use the SF_D<15:8> data
lines.

UCF Location Constraints

Figure 5-2 provides the UCF constraints for the Character LCD, including the I/O pin
assignment and the I/O standard used.

NET "LCD_E" LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET "LCD_RS" LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "LCD_RW" LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

# The LCD four-bit data interface is shared with the StrataFlash.

NET "SF_D<8>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<9>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<10>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<11>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

Figure 5-2: UCF Location Constraints for the Character LCD

LCD Controller
The 2 x 16 character LCD has an internal Sitronix ST7066U graphics controller that is
functionally equivalent with the following devices.
• Samsung S6A0069X or KS0066U
• Hitachi HD44780
• SMOS SED1278

Memory Map
The controller has three internal memory regions, each with a specific purpose. The
display must be initialized before accessing any of these memory regions.

DD RAM
The Display Data RAM (DD RAM) stores the character code to be displayed on the screen.
Most applications interact primarily with DD RAM. The character code stored in a DD
RAM location references a specific character bitmap stored either in the predefined CG
ROM character set or in the user-defined CG RAM character set.
Figure 5-3shows the default address for the 32 character locations on the display. The
upper line of characters is stored between addresses 0x00 and 0x0F. The second line of
characters is stored between addresses 0x40 and 0x4F.

Undisplayed
Character Display Addresses
Addresses
1 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 … 27
2 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 … 67
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 … 40

Figure 5-3: DD RAM Hexadecimal Addresses (No Display Shifting)

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Chapter 5: Character LCD Screen

Physically, there are 80 total character locations in DD RAM with 40 characters available
per line. Locations 0x10 through 0x27 and 0x50 through 0x67 can be used to store other
non-display data. Alternatively, these locations can also store characters that can only
displayed using controller’s display shifting functions.
The Set DD RAM Address command initializes the address counter before reading or
writing to DD RAM. Write DD RAM data using the Write Data to CG RAM or DD RAM
command, and read DD RAM using the Read Data from CG RAM or DD RAM command.
The DD RAM address counter either remains constant after read or write operations, or
auto-increments or auto-decrements by one location, as defined by the I/D set by the Entry
Mode Set command.

CG ROM
The Character Generator ROM (CG ROM) contains the font bitmap for each of the
predefined characters that the LCD screen can display, shown in Figure 5-4. The character
code stored in DD RAM for each character location subsequently references a position with
the CG ROM. For example, a hexadecimal character code of 0x53 stored in a DD RAM
location displays the character ‘S’. The upper nibble of 0x53 equates to DB[7:4]=”0101”
binary and the lower nibble equates to DB[3:0] = “0011” binary. As shown in Figure 5-4, the
character ‘S’ appears on the screen.
English/Roman characters are stored in CG ROM at their equivalent ASCII code address.

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LCD Controller

Upper Data Nibble

DB7
DB6
DB5
DB4

Lower Data Nibble

DB3
DB2
DB1
DB0

UG230_c5_02_030306

Figure 5-4: LCD Character Set

The character ROM contains the ASCII English character set and Japanese kana characters.
The controller also provides for eight custom character bitmaps, stored in CG RAM. These
eight custom characters are displayed by storing character codes 0x00 through 0x07 in a
DD RAM location.

CG RAM
The Character Generator RAM (CG RAM) provides space to create eight custom character
bitmaps. Each custom character location consists of a 5-dot by 8-line bitmap, as shown in
Figure 5-5.
The Set CG RAM Address command initializes the address counter before reading or
writing to CG RAM. Write CG RAM data using the Write Data to CG RAM or DD RAM
command, and read CG RAM using the Read Data from CG RAM or DD RAM command.

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Chapter 5: Character LCD Screen

The CG RAM address counter can either remain constant after read or write operations, or
auto-increments or auto-decrements by one location, as defined by the I/D set by the Entry
Mode Set command.
Figure 5-5 provides an example, creating a special checkerboard character. The custom
character is stored in the fourth CG RAM character location, which is displayed when a
DD RAM location is 0x03. To write the custom character, the CG RAM address is first
initialized using the Set CG RAM Address command. The upper three address bits point to
the custom character location. The lower three address bits point to the row address for the
character bitmap. The Write Data to CG RAM or DD RAM command is used to write each
character bitmap row. A ‘1’ lights a bit on the display. A ‘0’ leaves the bit unlit. Only the
lower five data bits are used; the upper three data bits are don’t care positions. The eighth
row of bitmap data is usually left as all zeros to accommodate the cursor.

Upper Nibble Lower Nibble

Write Data to CG RAM or DD RAM
A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Character Address Row Address Don’t Care Character Bitmap
0 1 1 0 0 0 - - - 0 1 0 1 0
0 1 1 0 0 1 - - - 1 0 1 0 1
0 1 1 0 1 0 - - - 0 1 0 1 0
0 1 1 0 1 1 - - - 1 0 1 0 1
0 1 1 1 0 0 - - - 0 1 0 1 0
0 1 1 1 0 1 - - - 1 0 1 0 1
0 1 1 1 1 0 - - - 0 1 0 1 0
0 1 1 1 1 1 - - - 0 0 0 0 0
Figure 5-5: Example Custom Checkerboard Character with Character Code 0x03

Command Set
Table 5-3 summarizes the available LCD controller commands and bit definitions. Because
the display is set up for 4-bit operation, each 8-bit command is sent as two 4-bit nibbles.
The upper nibble is transferred first, followed by the lower nibble.

Table 5-3: LCD Character Display Command Set

Upper Nibble Lower Nibble
LCD_RW
LCD_RS

Function
DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Clear Display 0 0 0 0 0 0 0 0 0 1
Return Cursor Home 0 0 0 0 0 0 0 0 1 -
Entry Mode Set 0 0 0 0 0 0 0 1 I/D S
Display On/Off 0 0 0 0 0 0 1 D C B
Cursor and Display Shift 0 0 0 0 0 1 S/C R/L - -

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LCD Controller

Table 5-3: LCD Character Display Command Set (Continued)

Upper Nibble Lower Nibble

LCD_RW
LCD_RS
Function

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0
Function Set 0 0 0 0 1 0 1 0 - -
Set CG RAM Address 0 0 0 1 A5 A4 A3 A2 A1 A0
Set DD RAM Address 0 0 1 A6 A5 A4 A3 A2 A1 A0
Read Busy Flag and Address 0 1 BF A6 A5 A4 A3 A2 A1 A0
Write Data to CG RAM or DD RAM 1 0 D7 D6 D5 D4 D3 D2 D1 D0
Read Data from CG RAM or DD RAM 1 1 D7 D6 D5 D4 D3 D2 D1 D0

Disabled
If the LCD_E enable signal is Low, all other inputs to the LCD are ignored.

Clear Display
Clear the display and return the cursor to the home position, the top-left corner.
This command writes a blank space (ASCII/ANSI character code 0x20) into all DD RAM
addresses. The address counter is reset to 0, location 0x00 in DD RAM. Clears all option
settings. The I/D control bit is set to 1 (increment address counter mode) in the Entry Mode
Set command.
Execution Time: 82 μs – 1.64 ms

Return Cursor Home

Return the cursor to the home position, the top-left corner. DD RAM contents are
unaffected. Also returns the display being shifted to the original position, shown in
Figure 5-3.
The address counter is reset to 0, location 0x00 in DD RAM. The display is returned to its
original status if it was shifted. The cursor or blink move to the top-left character location.
Execution Time: 40 μs – 1.6 ms

Entry Mode Set

Sets the cursor move direction and specifies whether or not to shift the display.
These operations are performed during data reads and writes.
Execution Time: 40 μs

Bit DB1: (I/D) Increment/Decrement

0 Auto-decrement address counter. Cursor/blink moves to left.

1 Auto-increment address counter. Cursor/blink moves to right.

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Chapter 5: Character LCD Screen

This bit either auto-increments or auto-decrements the DD RAM and CG RAM address
counter by one location after each Write Data to CG RAM or DD RAM or Read Data from
CG RAM or DD RAM command. The cursor or blink position moves accordingly.

Bit DB0: (S) Shift

0 Shifting disabled
1 During a DD RAM write operation, shift the entire display value in the direction
controlled by Bit DB1 (I/D). Appears as though the cursor position remains constant
and the display moves.

Display On/Off
Display is turned on or off, controlling all characters, cursor and cursor position character
(underscore) blink.
Execution Time: 40 μs

Bit DB2: (D) Display On/Off

0 No characters displayed. However, data stored in DD RAM is retained

1 Display characters stored in DD RAM

Bit DB1: (C) Cursor On/Off

The cursor uses the five dots on the bottom line of the character. The cursor appears as a
line under the displayed character.

0 No cursor
1 Display cursor

Bit DB0: (B) Cursor Blink On/Off

0 No cursor blinking
1 Cursor blinks on and off approximately every half second

Cursor and Display Shift

Moves the cursor and shifts the display without changing DD RAM contents. Shift cursor
position or display to the right or left without writing or reading display data.
This function positions the cursor in order to modify an individual character, or to scroll
the display window left or right to reveal additional data stored in the DD RAM, beyond
the 16th character on a line. The cursor automatically moves to the second line when it
shifts beyond the 40th character location of the first line. The first and second line displays
shift at the same time.
When the displayed data is shifted repeatedly, both lines move horizontally. The second
display line does not shift into the first display line.
Execution Time: 40 μs

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LCD Controller

Table 5-4: Shift Patterns According to S/C and R/L Bits

DB3 DB2
Operation
(S/C) (R/L)
0 0 Shift the cursor position to the left. The address counter is decremented by one.
0 1 Shift the cursor position to the right. The address counter is incremented by one.
Shift the entire display to the left. The cursor follows the display shift. The
1 0
address counter is unchanged.
Shift the entire display to the right. The cursor follows the display shift. The
1 1
address counter is unchanged.

Function Set
Sets interface data length, number of display lines, and character font.
The Starter Kit board supports a single function set with value 0x28.
Execution Time: 40 μs

Set CG RAM Address

Set the initial CG RAM address.
After this command, all subsequent read or write operations to the display are to or from
CG RAM.
Execution Time: 40 μs

Set DD RAM Address

Set the initial DD RAM address.
After this command, all subsequentsubsequent read or write operations to the display are
to or from DD RAM. The addresses for displayed characters appear in Figure 5-3.
Execution Time: 40 μs

Read Busy Flag and Address

Read the Busy flag (BF) to determine if an internal operation is in progress, and read the
current address counter contents.
BF = 1 indicates that an internal operation is in progress. The next instruction is not
accepted until BF is cleared or until the current instruction is allowed the maximum time to
execute.
This command also returns the present value of address counter. The address counter is
used for both CG RAM and DD RAM addresses. The specific context depends on the most
recent Set CG RAM Address or Set DD RAM Address command issued.
Execution Time: 1 μs

Write Data to CG RAM or DD RAM

Write data into DD RAM if the command follows a previous Set DD RAM Address
command, or write data into CG RAM if the command follows a previous Set CG RAM
Address command.

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Chapter 5: Character LCD Screen

After the write operation, the address is automatically incremented or decremented by 1

according to the Entry Mode Set command. The entry mode also determines display shift.
Execution Time: 40 μs

Read Data from CG RAM or DD RAM

Read data from DD RAM if the command follows a previous Set DD RAM Address
command, or read data from CG RAM if the command follows a previous Set CG RAM
Address command.
After the read operation, the address is automatically incremented or decremented by 1
according to the Entry Mode Set command. However, a display shift is not executed
during read operations.
Execution Time: 40 μs

Operation

Four-Bit Data Interface

The board uses a 4-bit data interface to the character LCD.
Figure 5-6 illustrates a write operation to the LCD, showing the minimum times allowed
for setup, hold, and enable pulse length relative to the 50 MHz clock (20 ns period)
provided on the board.

CLOCK

LCD_RS 0 = Command, 1 = Data

SF_D[11:8] Valid Data

LCD_RW

LCD_E

230 ns

40 ns 10 ns

Upper Lower
4 bits 4 bits
LCD_RS
SF_D[11:8]
LCD_RW
LCD_E

1 μs 40 μs
UG230_c5_03_022006

Figure 5-6: Character LCD Interface Timing

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Operation

The data values on SF_D<11:8>, and the register select (LCD_RS) and the read/write
(LCD_RW) control signals must be set up and stable at least 40 ns before the enable LCD_E
goes High. The enable signal must remain High for 230 ns or longer—the equivalent of 12
or more clock cycles at 50 MHz.
In many applications, the LCD_RW signal can be tied Low permanently because the FPGA
generally has no reason to read information from the display.

Transferring 8-Bit Data over the 4-Bit Interface

After initializing the display and establishing communication, all commands and data
transfers to the character display are via 8 bits, transferred using two sequential 4-bit
operations. Each 8-bit transfer must be decomposed into two 4-bit transfers, spaced apart
by at least 1 μs, as shown in Figure 5-6. The upper nibble is transferred first, followed by
the lower nibble. An 8-bit write operation must be spaced least 40 μs before the next
communication. This delay must be increased to 1.64 ms following a Clear Display
command.

Initializing the Display

After power-on, the display must be initialized to establish the required communication
protocol. The initialization sequence is simple and ideally suited to the highly-efficient 8-
bit PicoBlaze embedded controller. After initialization, the PicoBlaze controller is available
for more complex control or computation beyond simply driving the display.

Power-On Initialization
The initialization sequence first establishes that the FPGA application wishes to use the
four-bit data interface to the LCD as follows:
• Wait 15 ms or longer, although the display is generally ready when the FPGA finishes
configuration. The 15 ms interval is 750,000 clock cycles at 50 MHz.
• Write SF_D<11:8> = 0x3, pulse LCD_E High for 12 clock cycles.
• Wait 4.1 ms or longer, which is 205,000 clock cycles at 50 MHz.
• Write SF_D<11:8> = 0x3, pulse LCD_E High for 12 clock cycles.
• Wait 100 μs or longer, which is 5,000 clock cycles at 50 MHz.
• Write SF_D<11:8> = 0x3, pulse LCD_E High for 12 clock cycles.
• Wait 40 μs or longer, which is 2,000 clock cycles at 50 MHz.
• Write SF_D<11:8> = 0x2, pulse LCD_E High for 12 clock cycles.
• Wait 40 μs or longer, which is 2,000 clock cycles at 50 MHz.

Display Configuration
After the power-on initialization is completed, the four-bit interface is now established.
The next part of the sequence configures the display:
• Issue a Function Set command, 0x28, to configure the display for operation on the
Spartan-3E Starter Kit board.
• Issue an Entry Mode Set command, 0x06, to set the display to automatically
increment the address pointer.
• Issue a Display On/Off command, 0x0C, to turn the display on and disables the
cursor and blinking.

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Chapter 5: Character LCD Screen

• Finally, issue a Clear Display command. Allow at least 1.64 ms (82,000 clock cycles)
after issuing this command.

Writing Data to the Display

To write data to the display, specify the start address, followed by one or more data values.
Before writing any data, issue a Set DD RAM Address command to specify the initial 7-bit
address in the DD RAM. See Figure 5-3 for DD RAM locations.
Write data to the display using a Write Data to CG RAM or DD RAM command. The 8-bit
data value represents the look-up address into the CG ROM or CG RAM, shown in
Figure 5-4. The stored bitmap in the CG ROM or CG RAM drives the 5 x 8 dot matrix to
represent the associated character.
If the address counter is configured to auto-increment, as described earlier, the application
can sequentially write multiple character codes and each character is automatically stored
and displayed in the next available location.
Continuing to write characters, however, eventually falls off the end of the first display
line. The additional characters do not automatically appear on the second line because the
DD RAM map is not consecutive from the first line to the second.

Disabling the Unused LCD

If the FPGA application does not use the character LCD screen, drive the LCD_E pin Low
to disable it. Also drive the LCD_RW pin Low to prevent the LCD screen from presenting
data.

Related Resources
• Initial Design for Spartan-3E Starter Kit (Reference Design)
http://www.xilinx.com/s3estarter
• PowerTip PC1602-D Character LCD (Basic Electrical and Mechanical Data)
http://www.powertipusa.com/pdf/pc1602d.pdf
• Sitronix ST7066U Character LCD Controller
http://www.sitronix.com.tw/sitronix/product.nsf/Doc/ST7066U?OpenDocument
• Detailed Data Sheet on PowerTip Character LCD
http://www.rapidelectronics.co.uk/images/siteimg/57-0910e.PDF
• Samsung S6A0069X Character LCD Controller
http://www.samsung.com/Products/Semiconductor/DisplayDriverIC/MobileDDI/BWSTN
/S6A0069X/S6A0069X.htm

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Chapter 6

VGA Display Port

The Spartan-3E Starter Kit board includes a VGA display port via a DB15 connector.
Connect this port directly to most PC monitors or flat-panel LCDs using a standard
monitor cable. As shown in Figure 6-1, the VGA connector is the left-most connector along
the top of the board.

Pin 5 Pin 1
Pin 10
Pin 6

Pin 15 Pin 11
DB15 VGA Connector
(front view)
DB15
Connector
270Ω
Red
1 (H14) VGA_RED
6 270Ω
11 Green
2 (H15) VGA_GREEN
7
12 270Ω
Blue
3 (G15) VGA_BLUE
8 Horizontal Sync 82.5Ω
13 (F15) VGA_HSYNC
4
9 Vertical Sync 82.5Ω
14 (F14) VGA_VSYNC
5
10 (xx) = FPGA pin number
15

GND UG230_c6_01_021706

Figure 6-1: VGA Connections from Spartan-3E Starter Kit Board

The Spartan-3E FPGA directly drives the five VGA signals via resistors. Each color line has
a series resistor, with one bit each for VGA_RED, VGA_GREEN, and VGA_BLUE. The
series resistor, in combination with the 75Ω termination built into the VGA cable, ensures
that the color signals remain in the VGA-specified 0V to 0.7V range. The VGA_HSYNC
and VGA_VSYNC signals using LVTTL or LVCMOS33 I/O standard drive levels. Drive
the VGA_RED, VGA_GREEN, and VGA_BLUE signals High or Low to generate the eight
colors shown in Table 6-1.

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Chapter 6: VGA Display Port

Table 6-1: 3-Bit Display Color Codes

VGA_RED VGA_GREEN VGA_BLUE Resulting Color
0 0 0 Black
0 0 1 Blue

0 1 0 Green

0 1 1 Cyan

1 0 0 Red

1 0 1 Magenta

1 1 0 Yellow

1 1 1 White

VGA signal timing is specified, published, copyrighted, and sold by the Video Electronics
Standards Association (VESA). The following VGA system and timing information is
provided as an example of how the FPGA might drive VGA monitor in 640 by 480 mode.
For more precise information or for information on higher VGA frequencies, refer to
documents available on the VESA website or other electronics websites (see “Related
Resources,” page 57).

Signal Timing for a 60 Hz, 640x480 VGA Display

CRT-based VGA displays use amplitude-modulated, moving electron beams (or cathode
rays) to display information on a phosphor-coated screen. LCDs use an array of switches
that can impose a voltage across a small amount of liquid crystal, thereby changing light
permittivity through the crystal on a pixel-by-pixel basis. Although the following
description is limited to CRT displays, LCDs have evolved to use the same signal timings
as CRT displays. Consequently, the following discussion pertains to both CRTs and LCDs.
Within a CRT display, current waveforms pass through the coils to produce magnetic fields
that deflect electron beams to transverse the display surface in a raster pattern, horizontally
from left to right and vertically from top to bottom. As shown in Figure 6-2, information is
only displayed when the beam is moving in the forward direction—left to right and top to
bottom—and not during the time the beam returns back to the left or top edge of the
display. Much of the potential display time is therefore lost in blanking periods when the
beam is reset and stabilized to begin a new horizontal or vertical display pass.

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Signal Timing for a 60 Hz, 640x480 VGA Display

pixel 0,0 pixel 0,639

640 pixels are displayed each

time the beam traverses the screen

VGA Display

Retrace: No
Current information
through the pixel 479,0 pixel 479,639 is displayed
horizontal during
deflection this time
coil

Stable current ramp: Information is

displayed during this time

Total horizontal time

Horizontal display time retrace time

time
"front porch" "front porch"

HS

Horizontal sync signal "back porch"

sets the retrace frequency
UG230_c6_02_021706

Figure 6-2: CRT Display Timing Example

The display resolution defines the size of the beams, the frequency at which the beam
traces across the display, and the frequency at which the electron beam is modulated.
Modern VGA displays support multiple display resolutions, and the VGA controller
dictates the resolution by producing timing signals to control the raster patterns. The
controller produces TTL-level synchronizing pulses that set the frequency at which current
flows through the deflection coils, and it ensures that pixel or video data is applied to the
electron guns at the correct time.
Video data typically comes from a video refresh memory with one or more bytes assigned
to each pixel location. The Spartan-3E Starter Kit board uses three bits per pixel, producing
one of the eight possible colors shown in Table 6-1. The controller indexes into the video
data buffer as the beams move across the display. The controller then retrieves and applies
video data to the display at precisely the time the electron beam is moving across a given
pixel.

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Chapter 6: VGA Display Port

As shown in Figure 6-2, the VGA controller generates the horizontal sync (HS) and vertical
sync (VS) timings signals and coordinates the delivery of video data on each pixel clock.
The pixel clock defines the time available to display one pixel of information. The VS signal
defines the refresh frequency of the display, or the frequency at which all information on the
display is redrawn. The minimum refresh frequency is a function of the display’s phosphor
and electron beam intensity, with practical refresh frequencies in the 60 Hz to 120 Hz
range. The number of horizontal lines displayed at a given refresh frequency defines the
horizontal retrace frequency.

VGA Signal Timing

The signal timings in Table 6-2 are derived for a 640-pixel by 480-row display using a
25 MHz pixel clock and 60 Hz ± 1 refresh. Figure 6-3 shows the relation between each of
the timing symbols. The timing for the sync pulse width (TPW) and front and back porch
intervals (TFP and TBP) are based on observations from various VGA displays. The front
and back porch intervals are the pre- and post-sync pulse times. Information cannot be
displayed during these times.
Table 6-2: 640x480 Mode VGA Timing
Vertical Sync Horizontal Sync
Symbol Parameter
Time Clocks Lines Time Clocks
TS Sync pulse time 16.7 ms 416,800 521 32 µs 800
TDISP Display time 15.36 ms 384,000 480 25.6 µs 640
TPW Pulse width 64 µs 1,600 2 3.84 µs 96
TFP Front porch 320 µs 8,000 10 640 ns 16
TBP Back porch 928 µs 23,200 29 1.92 µs 48

TS

Tfp
Tdisp

Tpw Tbp
UG230_c6_03_021706

Figure 6-3: VGA Control Timing

Generally, a counter clocked by the pixel clock controls the horizontal timing. Decoded
counter values generate the HS signal. This counter tracks the current pixel display
location on a given row.
A separate counter tracks the vertical timing. The vertical-sync counter increments with
each HS pulse and decoded values generate the VS signal. This counter tracks the current
display row. These two continuously running counters form the address into a video
display buffer. For example, the on-board DDR SDRAM provides an ideal display buffer.
No time relationship is specified between the onset of the HS pulse and the onset of the VS
pulse. Consequently, the counters can be arranged to easily form video RAM addresses, or
to minimize decoding logic for sync pulse generation.

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UCF Location Constraints

UCF Location Constraints

Figure 6-4 provides the UCF constraints for the VGA display port, including the I/O pin
assignment, the I/O standard used, the output slew rate, and the output drive current.

NET "VGA_RED" LOC = "H14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;

NET "VGA_GREEN" LOC = "H15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
NET "VGA_BLUE" LOC = "G15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
NET "VGA_HSYNC" LOC = "F15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
NET "VGA_VSYNC" LOC = "F14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;

Figure 6-4: UCF Constraints for VGA Display Port

Related Resources
• VESA
http://www.vesa.org
• VGA timing information
http://www.epanorama.net/documents/pc/vga_timing.html

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Chapter 6: VGA Display Port

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Chapter 7

RS-232 Serial Ports

Overview
As shown in Figure 7-1, the Spartan-3E Starter Kit board has two RS-232 serial ports: a
female DB9 DCE connector and a male DTE connector. The DCE-style port connects
directly to the serial port connector available on most personal computers and
workstations via a standard straight-through serial cable. Null modem, gender changers,
or crossover cables are not required.
Use the DTE-style connector to control other RS-232 peripherals, such as modems or
printers, or perform simple loopback testing with the DCE connector.

Standard Standard RS-232 Peripheral

9-pin serial cable 9-pin serial cable TALK/DATA

TALK RS CS TR RD TD CD

DCE DTE Pin 5 Pin 1

Pin 9 Pin 6

DB9 Serial Port Connector

(front view)
DCE DTE
Female DB9 Male DB9

5 4 3 2 1 5 4 3 2 1

9 8 7 6 9 8 7 6
J9 J10

GND GND

RS-232 Voltage Translator (IC2)

RS232_DCE_RXD

RS232_DCE_TXD

RS232_DTE_RXD

RS232_DTE_TXD

(R7) (M14) (U8) (M13)

Spartan-3E FPGA
UG230_c7_01_022006

Figure 7-1: RS-232 Serial Ports

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Chapter 7: RS-232 Serial Ports

Figure 7-1 shows the connection between the FPGA and the two DB9 connectors. The
FPGA supplies serial output data using LVTTL or LVCMOS levels to the Maxim device,
which in turn, converts the logic value to the appropriate RS-232 voltage level. Likewise,
the Maxim device converts the RS-232 serial input data to LVTTL levels for the FPGA. A
series resistor between the Maxim output pin and the FPGA’s RXD pin protects against
accidental logic conflicts.
Hardware flow control is not supported on the connector. The port’s DCD, DTR, and DSR
signals connect together, as shown in Figure 7-1. Similarly, the port’s RTS and CTS signals
connect together.

UCF Location Constraints

Figure 7-2 and Figure 7-3 provide the UCF constraints for the DTE and DCE RS-232 ports,
respectively, including the I/O pin assignment and the I/O standard used.

NET "RS232_DTE_RXD" LOC = "U8" | IOSTANDARD = LVTTL ;

NET "RS232_DTE_TXD" LOC = "M13" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;

Figure 7-2: UCF Location Constraints for DTE RS-232 Serial Port

NET "RS232_DCE_RXD" LOC = "R7" | IOSTANDARD = LVTTL ;

NET "RS232_DCE_TXD" LOC = "M14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;

Figure 7-3: UCF Location Constraints for DCE RS-232 Serial Port

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Chapter 8

PS/2 Mouse/Keyboard Port

The Spartan-3E Starter Kit board includes a PS/2 mouse/keyboard port and the standard
6-pin mini-DIN connector, labeled J14 on the board. Figure 8-1 shows the PS/2 connector,
and Table 8-1 shows the signals on the connector. Only pins 1 and 5 of the connector attach
to the FPGA.

270Ω
PS2_DATA: (G13)

2 1
4 3
6 5 270Ω
PS2_CLK: (G14)

UG230_c8_01_021806

Figure 8-1: PS/2 Connector Location and Signals

Table 8-1: PS/2 Connector Pinout

PS/2 DIN Pin Signal FPGA Pin
1 DATA (PS2_DATA) G13
2 Reserved G13

3 GND GND

4 +5V —

5 CLK (PS2_CLK) G14

6 Reserved G13

Both a PC mouse and keyboard use the two-wire PS/2 serial bus to communicate with a
host device, the Spartan-3E FPGA in this case. The PS/2 bus includes both clock and data.
Both a mouse and keyboard drive the bus with identical signal timings and both use 11-bit
words that include a start, stop and odd parity bit. However, the data packets are

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Chapter 8: PS/2 Mouse/Keyboard Port

organized differently for a mouse and keyboard. Furthermore, the keyboard interface
allows bidirectional data transfers so the host device can illuminate state LEDs on the
keyboard.
The PS/2 bus timing appears in Table 8-2 and Figure 8-2. The clock and data signals are
only driven when data transfers occur; otherwise they are held in the idle state at logic
High. The timing defines signal requirements for mouse-to-host communications and
bidirectional keyboard communications. As shown in Figure 8-2, the attached keyboard or
mouse writes a bit on the data line when the clock signal is High, and the host reads the
data line when the clock signal is Low.

Table 8-2: PS/2 Bus Timing

Symbol Parameter Min Max
TCK Clock High or Low Time 30 μs 50 μs
TSU Data-to-clock Setup Time 5 μs 25 μs
THLD Clock-to-data Hold Time 5 μs 25 μs

TCK TCK
Edge 0 Edge 10

CLK (PS2C)
THLD
TSU
DATA (PS2D)

'1' stop bit

'0' start bit
UG230_c8_02_021806

Figure 8-2: PS/2 Bus Timing Waveforms

Keyboard
The keyboard uses open-collector drivers so that either the keyboard or the host can drive
the two-wire bus. If the host never sends data to the keyboard, then the host can use simple
input pins.
A PS/2-style keyboard uses scan codes to communicate key press data. Nearly all
keyboards in use today are PS/2 style. Each key has a single, unique scan code that is sent
whenever the corresponding key is pressed. The scan codes for most keys appear in
Figure 8-3.
If the key is pressed and held, the keyboard repeatedly sends the scan code every 100 ms or
so. When a key is released, the keyboard sends an “F0” key-up code, followed by the scan
code of the released key. The keyboard sends the same scan code, regardless if a key has
different shift and non-shift characters and regardless whether the Shift key is pressed or
not. The host determines which character is intended.
Some keys, called extended keys, send an “E0” ahead of the scan code and furthermore,
they might send more than one scan code. When an extended key is released, an “E0 F0”
key-up code is sent, followed by the scan code.

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Keyboard

ESC F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12

76 05 06 04 0C 03 0B 83 0A 01 09 78 07 E0 75

`~ 1! 2@ 3# 4$ 5% 6^ 7& 8* 9( 0) -_ =+ Back Space

0E 16 1E 26 25 2E 36 3D 3E 46 45 4E 55 66 E0 74
TA B Q W E R T Y U I O P [{ ]} \|
0D 15 1D 24 2D 2C 35 3C 43 44 4D 54 5B 5D E0 6B
Caps Lock A S D F G H J K L ;: '" Enter
58 1C 1B 23 2B 34 33 3B 42 4B 4C 52 5A
E0 72
Shift Z X C V B N M ,< >. /? Shift
12 1Z 22 21 2A 32 31 3A 41 49 4A 59
Ctrl Alt Space Alt Ctrl
14 11 29 E0 11 E0 14
UG230_c8_03_021806

Figure 8-3: PS/2 Keyboard Scan Codes

The host can also send commands and data to the keyboard. Table 8-3 provides a short list
of some often-used commands.

Table 8-3: Common PS/2 Keyboard Commands

Command Description
ED Turn on/off Num Lock, Caps Lock, and Scroll Lock LEDs. The keyboard acknowledges receipt of an
“ED” command by replying with an “FA”, after which the host sends another byte to set LED status. The
bit positions for the keyboard LEDs are shown below. Write a ‘1’ to the specific bit to illuminate the
associated keyboard LED.

7 6 5 4 3 2 1 0
Ignored Caps Lock Num Lock Scroll Lock

EE Echo. Upon receiving an echo command, the keyboard replies with the same scan code “EE”.

F3 Set scan code repeat rate. The keyboard acknowledges receipt of an “F3” by returning an “FA”, after
which the host sends a second byte to set the repeat rate.

FE Resend. Upon receiving a resend command, the keyboard resends the last scan code sent.
FF Reset. Resets the keyboard.

The keyboard sends commands or data to the host only when both the data and clock lines
are High, the Idle state.
Because the host is the bus master, the keyboard checks whether the host is sending data
before driving the bus. The clock line can be used as a clear to send signal. If the host pulls
the clock line Low, the keyboard must not send any data until the clock is released.
The keyboard sends data to the host in 11-bit words that contain a ‘0’ start bit, followed by
eight bits of scan code (LSB first), followed by an odd parity bit and terminated with a ‘1’
stop bit. When the keyboard sends data, it generates 11 clock transitions at around 20 to
30 kHz, and data is valid on the falling edge of the clock as shown in Figure 8-2.

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Chapter 8: PS/2 Mouse/Keyboard Port

Mouse
A mouse generates a clock and data signal when moved; otherwise, these signals remain
High, indicating the Idle state. Each time the mouse is moved, the mouse sends three 11-bit
words to the host. Each of the 11-bit words contains a ‘0’ start bit, followed by 8 data bits
(LSB first), followed by an odd parity bit, and terminated with a ‘1’ stop bit. Each data
transmission contains 33 total bits, where bits 0, 11, and 22 are ‘0’ start bits, and bits 10, 21,
and 32 are ‘1’ stop bits. The three 8-bit data fields contain movement data as shown in
Figure 8-4. Data is valid at the falling edge of the clock, and the clock period is 20 to 30 kHz.

Mouse status byte X direction byte Y direction byte

1 0 L R 0 1 XS YS XV YV P 1 0 X0 X1 X2 X3 X4 X5 X6 X7 P 1 0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 P 1

Start bit Stop bit Stop bit Stop bit

Idle state Start bit Start bit Idle state
UG230_c8_04_021806

Figure 8-4: PS/2 Mouse Transaction

A PS/2-style mouse employs a relative coordinate system (see Figure 8-5), wherein
moving the mouse to the right generates a positive value in the X field, and moving to the
left generates a negative value. Likewise, moving the mouse up generates a positive value
in the Y field, and moving it down represents a negative value. The XS and YS bits in the
status byte define the sign of each value, where a ‘1’ indicates a negative value.

+Y values (YS=0)

-X values +X values
(XS=1) (XS=0)

-Y values (YS=1) UG230_c8_05_021806

Figure 8-5: The Mouse Uses a Relative Coordinate System to Track Movement
The magnitude of the X and Y values represent the rate of mouse movement. The larger the
value, the faster the mouse is moving. The XV and YV bits in the status byte indicate when
the X or Y values exceed their maximum value, an overflow condition. A ‘1’ indicates
when an overflow occurs. If the mouse moves continuously, the 33-bit transmissions repeat
every 50 ms or so.
The L and R fields in the status byte indicate Left and Right button presses. A ‘1’ indicates
that the associated mouse button is being pressed.

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Voltage Supply

Voltage Supply
The PS/2 port on the Spartan-3E Starter Kit board is powered by 5V. Although the
Spartan-3E FPGA is not a 5V-tolerant device, it can communicate with a 5V device using
series current-limiting resistors, as shown in Figure 8-1.

UCF Location Constraints

Figure 8-6 provides the UCF constraints for the PS/2 port connecting, including the I/O
pin assignment and the I/O standard used.

NET "PS2_CLK" LOC = "G14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;

NET "PS2_DATA" LOC = "G13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;

Figure 8-6: UCF Location Constraints for PS/2 Port

Related Resources
• PS/2 Mouse/Keyboard Protocol
http://www.computer-engineering.org/ps2protocol/
• PS/2 Keyboard Interface
http://www.computer-engineering.org/ps2keyboard/
• PS/2 Mouse Interface
http://www.computer-engineering.org/ps2mouse/

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Chapter 8: PS/2 Mouse/Keyboard Port

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Chapter 9

Digital to Analog Converter (DAC)

The Spartan-3E Starter Kit board includes an SPI-compatible, four-channel, serial Digital-
to-Analog Converter (DAC). The DAC device is a Linear Technology LTC2624 quad DAC
with 12-bit unsigned resolution. The four outputs from the DAC appear on the J5 header,
which uses the Digilent 6-pin Peripheral Module format. The DAC and the header are
located immediately above the Ethernet RJ-45 connector, as shown in Figure 9-1.

Linear Tech LTC2624 Quad DAC

6-pin DAC Header (J5) SPI_MOSI: (T4)
SPI_MISO: (N10)
SPI_SCK: (U16)
DAC_CS: (N8)
DAC_CLR: (P8)

UG230_c9_01_030906

Figure 9-1: Digital-to-Analog Converter and Associated Header

SPI Communication
As shown in Figure 9-2, the FPGA uses a Serial Peripheral Interface (SPI) to communicate
digital values to each of the four DAC channels. The SPI bus is a full-duplex, synchronous,
character-oriented channel employing a simple four-wire interface. A bus master—the
FPGA in this example—drives the bus clock signal (SPI_SCK) and transmits serial data
(SPI_MOSI) to the selected bus slave—the DAC in this example. At the same time, the bus
slave provides serial data (SPI_MISO) back to the bus master.

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Chapter 9: Digital to Analog Converter (DAC)

LTC 2624 DAC

Header J5
REF A
DAC A VOUTA
A
3.3V
12
REF B
DAC B VOUTB
B
12
REF C
DAC C VOUTC
C
2.5V
12
REF D
VOUTD
DAC D D
12
Spartan-3E FPGA
SPI_MOSI GND
(N10) (T4) SDI SDO
DAC_CS
(N8) CS/LD
SPI_SCK
(U16) SCK SPI Control Interface VCC
(3.3V)
DAC_CLR
(P8) CLR

SPI_MISO
UG230_c9_02_021806

Figure 9-2: Digital-to-Analog Connection Schematics

Interface Signals
Table 9-1 lists the interface signals between the FPGA and the DAC. The SPI_MOSI,
SPI_MISO, and SPI_SCK signals are shared with other devices on the SPI bus. The
DAC_CS signal is the active-Low slave select input to the DAC. The DAC_CLR signal is
the active-Low, asynchronous reset input to the DAC.
Table 9-1: DAC Interface Signals
Signal FPGA Pin Direction Description
SPI_MOSI T4 FPGAÆDAC Serial data: Master Output, Slave Input
DAC_CS N8 FPGAÆDAC Active-Low chip-select. Digital-to-analog
conversion starts when signal returns High.
SPI_SCK U16 FPGAÆDAC Clock
DAC_CLR P8 FPGAÆDAC Asynchronous, active-Low reset input
SPI_MISO N10 FPGAÅDAC Serial data: Master Input, Slave Output

The serial data output from the DAC is primarily used to cascade multiple DACs. This
signal can be ignored in most applications although it does demonstrate full-duplex
communication over the SPI bus.

Disable Other Devices on the SPI Bus to Avoid Contention

The SPI bus signals are shared by other devices on the board. It is vital that other devices
are disabled when the FPGA communicates with the DAC to avoid bus contention.
Table 9-2 provides the signals and logic values required to disable the other devices.
Although the StrataFlash PROM is a parallel device, its least-significant data bit is shared
with the SPI_MISO signal.

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SPI Communication

Table 9-2: Disabled Devices on the SPI Bus

Signal Disabled Device Disable Value
SPI_SS_B SPI serial Flash 1
AMP_CS Programmable pre-amplifier 1
AD_CONV Analog-to-Digital Converter (ADC) 0
SF_CE0 StrataFlash Parallel Flash PROM 1
FPGA_INIT_B Platform Flash PROM 1

SPI Communication Details

Figure 9-3 shows a detailed example of the SPI bus timing. Each bit is transmitted or
received relative to the SPI_SCK clock signal. The bus is fully static and supports clocks
rate up to the maximum of 50 MHz. However, check all timing parameters using the
LTC2624 data sheet if operating at or close to the maximum speed.

DAC_CS

SPI_MOSI 31 30 29

SPI_SCK

SPI_MISO Previous 31 Previous 30 Previous 29

UG230_c9_03_021806

Figure 9-3: SPI Communication Waveforms

After driving the DAC_CS slave select signal Low, the FPGA transmits data on the
SPI_MOSI signal, MSB first. The LTC2624 captures input data (SPI_MOSI) on the rising
edge of SPI_SCK; the data must be valid for at least 4 ns relative to the rising clock edge.
The LTC2624 DAC transmits its data on the SPI_MISO signal on the falling edge of
SPI_SCK. The FPGA captures this data on the next rising SPI_SCK edge. The FPGA must
read the first SPI_MISO value on the first rising SPI_SCK edge after DAC_CS goes Low.
Otherwise, bit 31 is missed.
After transmitting all 32 data bits, the FPGA completes the SPI bus transaction by
returning the DAC_CS slave select signal High. The High-going edge starts the actual
digital-to-analog conversion process within the DAC.

Communication Protocol
Figure 9-4 shows the communications protocol required to interface with the LTC2624
DAC. The DAC supports both a 24-bit and 32-bit protocol. The 32-bit protocol is shown.
Inside the D/A converter, the SPI interface is formed by a 32-bit shift register. Each 32-bit
command word consists of a command, an address, followed by data value. As a new
command enters the DAC, the previous 32-bit command word is echoed back to the
master. The response from the DAC can be ignored although it is a useful to confirm
correct communication.

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Chapter 9: Digital to Analog Converter (DAC)

SPI_MISO

0 Slave: LTC2624 DAC 31

SPI_MOSI
x x x x 0 1 2 3 4 5 6 7 8 9 10 11 a0 a1 a2 a3 c0 c1 c2 c3 x x x x x x x x
DAC_CS lsb msb
Master
Spartan-3E SPI_SCK
Don’t Care Don’t Care
FPGA 12-bit Unsigned
DATA
COMMAND
a3 a2 a1 a0 ADDRESS
0 0 0 0 DAC A
0 0 0 1 DAC B
0 0 1 0 DAC C
0 0 1 1 DAC D
1 1 1 1 All UG230_c9_04_021806

Figure 9-4: SPI Communications Protocol to LTC2624 DAC

The FPGA first sends eight dummy or “don’t care” bits, followed by a 4-bit command. The
most commonly used command with the board is COMMAND[3:0] = “0011”, which
immediately updates the selected DAC output with the specified data value. Following the
command, the FPGA selects one or all the DAC output channels via a 4-bit address field.
Following the address field, the FPGA sends a 12-bit unsigned data value that the DAC
converts to an analog value on the selected output(s). Finally, four additional dummy or
don’t care bits pad the 32-bit command word.

Specifying the DAC Output Voltage

As shown in Figure 9-2, each DAC output level is the analog equivalent of a 12-bit
unsigned digital value, D[11:0], written by the FPGA to the DAC via the SPI interface.
The voltage on a specific output is generally described in Equation 9-1. The reference
voltage, VREFERENCE, is different between the four DAC outputs. Channels A and B use a
3.3V reference voltage and Channels C and D use a 2.5V reference. The reference voltages
themselves have a ±5% tolerance, so there will be slight corresponding variances in the
output voltage.

D [ 11:0 ]
V OUT = --------------------- × V REFERENCE Equation 9-1
,
4096

DAC Outputs A and B

Equation 9-2 provides the output voltage equation for DAC outputs A and B. The
reference voltage associated with DAC outputs A and B is 3.3V ± 5%.

D [ 11:0 ]
V OUTA = --------------------- × ( 3.3V ± 5% ) Equation 9-2
,
4096

DAC Outputs C and D

Equation 9-3 provides the output voltage equation for DAC outputs A and B. The
reference voltage associated with DAC outputs A and B is 2.5V ± 5%.

D [ 11:0 ]
V OUTC = --------------------- × ( 2.5V ± 5% ) Equation 9-3
,
4096

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UCF Location Constraints

UCF Location Constraints

Figure 9-5 provides the UCF constraints for the DAC interface, including the I/O pin
assignment and the I/O standard used.

NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 ;

NET "SPI_MOSI" LOC = "T4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "SPI_SCK" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "DAC_CS" LOC = "N8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "DAC_CLR" LOC = "P8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;

Figure 9-5: UCF Location Constraints for the DAC Interface

Related Resources
• LTC2624 Quad DAC Data Sheet
http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1155,C1005,C1156,P2048,D2170

• PicoBlaze Based D/A Converter Control for the Spartan-3E Starter Kit (Reference
Design)
http://www.xilinx.com/s3estarter
• Xilinx PicoBlaze Soft Processor
http://www.xilinx.com/picoblaze
• Digilent, Inc. Peripheral Modules
http://www.digilentinc.com/Products/Catalog.cfm?Nav1=Products&Nav2=Peripheral&Cat=Peripheral

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Chapter 10

Analog Capture Circuit

The Spartan-3E Starter Kit board includes a two-channel analog capture circuit, consisting
of a programmable scaling pre-amplifier and an analog-to-digital converter (ADC), as
shown in Figure 10-1. Analog inputs are supplied on the J7 header.

6-pin ADC Header (J7) Linear Tech LTC1407A-1 Dual A/D

SPI_SCK: (U16)
AD_CONV: (P11)
SPI_MISO: (N10)

Linear Tech LTC6912-1 Dual Amp

SPI_MOSI: (T4)
AMP_CS: (N7)
SPI_SCK: (U16)
AMP_SHDN: (P7)
AMP_DOUT: (E18)

UG230_c10_01_030306

Figure 10-1: Two-Channel Analog Capture Circuit

The analog capture circuit consists of a Linear Technology LTC6912-1 programmable pre-
amplifier that scales the incoming analog signal on header J7 (see Figure 10-2). The output
of pre-amplifier connects to a Linear Technology LTC1407A-1 ADC. Both the pre-amplifier
and the ADC are serially programmed or controlled by the FPGA.

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Chapter 10: Analog Capture Circuit

Header J7

REFAB
(3.3V)

REFCD
(2.5V)
LTC 6912-1 AMP LTC 1407A-1 ADC

VINA
A A/D
Channel 0
14
VINB
B A/D
Channel 1
GND

VCC
(3.3V)
14
REF = 1.65V

Spartan-3E FPGA
SPI_MOSI
(N10) (T4) DIN 0 1 2 3 0 1 2 3 DOUT 0 ... 13 0 ... 13 SDO
(E18) (N7) AMP_CS CS/LD A GAIN B GAIN CHANNEL 1 CHANNEL 0
(U16) SPI_SCK SCK SPI Control Interface SCK SPI Control Interface

AMP_SHDN
(P7) SHDN CONV

AD_CONV
(P11)

AMP_DOUT
SPI_MISO
UG230_c10_02_022306

Figure 10-2: Detailed View of Analog Capture Circuit

Digital Outputs from Analog Inputs

The analog capture circuit converts the analog voltage on VINA or VINB and converts it to
a 14-bit digital representation, D[13:0], as expressed by Equation 10-1.

( V IN – 1.65V )
D [ 13:0 ] = GAIN × ------------------------------------ × 8192 Equation 10-1
1.25V
The GAIN is the current setting loaded into the programmable pre-amplifier. The various
allowable settings for GAIN and allowable voltages applied to the VINA and VINB inputs
appear in Table 10-2.
The reference voltage for the amplifier and the ADC is 1.65V, generated via a voltage
divider shown in Figure 10-2. Consequently, 1.65V is subtracted from the input voltage on
VINA or VINB.
The maximum range of the ADC is ±1.25V, centered around the reference voltage, 1.65V.
Hence, 1.25V appears in the denominator to scale the analog input accordingly.

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Programmable Pre-Amplifier

Finally, the ADC presents a 14-bit, two’s complement digital output. A 14-bit, two’s
complement number represents values between -213 and 213-1. Therefore, the quantity is
scaled by 8192, or 213.
See “Programmable Pre-Amplifier” to control the GAIN settings on the programmable
pre-amplifier.
The reference design files provide more information on converting the voltage applied on
VINA or VINB to a digital representation (see “Related Resources,” page 79).

Programmable Pre-Amplifier
The LTC6912-1 provides two independent inverting amplifiers with programmable gain.
The purpose of the amplifier is to scale the incoming voltage on VINA or VINB so that it
maximizes the conversion range of the DAC, namely 1.65 ± 1.25V.

Interface
Table 10-1 lists the interface signals between the FPGA and the amplifier. The SPI_MOSI,
SPI_MISO, and SPI_SCK signals are shared with other devices on the SPI bus. The
AMP_CS signal is the active-Low slave select input to the amplifier.

Table 10-1: AMP Interface Signals

Signal FPGA Pin Direction Description
SPI_MOSI T4 FPGAÆAD Serial data: Master Output, Slave Input.
Presents 8-bit programmable gain settings, as
defined in Table 10-2.
AMP_CS N7 FPGAÆAMP Active-Low chip-select. The amplifier gain is
set when signal returns High.
SPI_SCK U16 FPGAÆAMP Clock
AMP_SHDN P7 FPGAÆAMP Active-High shutdown, reset
AMP_DOUT E18 FPGAÅAMP Serial data. Echoes previous amplifier gain
settings. Can be ignored in most applications.

Programmable Gain
Each analog channel has an associated programmable gain amplifier (see Figure 10-2).
Analog signals presented on the VINA or VINB inputs on header J7 are amplified relative
to 1.65V. The 1.65V reference is generated using a voltage divider of the 3.3V voltage
supply.
The gain of each amplifier is programmable from -1 to -100, as shown in Table 10-2.

Table 10-2: Programmable Gain Settings for Pre-Amplifier

A3 A2 A1 A0 Input Voltage Range
Gain
B3 B2 B1 B0 Minimum Maximum
0 0 0 0 0
-1 0 0 0 1 0.4 2.9
-2 0 0 1 0 1.025 2.275

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Chapter 10: Analog Capture Circuit

Table 10-2: Programmable Gain Settings for Pre-Amplifier (Continued)

A3 A2 A1 A0 Input Voltage Range
Gain
B3 B2 B1 B0 Minimum Maximum
-5 0 0 1 1 1.4 1.9
-10 0 1 0 0 1.525 1.775
-20 0 1 0 1 1.5875 1.7125
-50 0 1 1 0 1.625 1.675
-100 0 1 1 1 1.6375 1.6625

SPI Control Interface

Figure 10-3 highlights the SPI-based communications interface with the amplifier. The gain
for each amplifier is sent as an 8-bit command word, consisting of two 4-bit fields. The
most-significant bit, B3, is sent first.

AMP_DOUT

0 Slave: LTC2624-1 7
SPI_MOSI
A0 A1 A2 A3 B0 B1 B2 B3
Spartan-3E AMP_CS
FPGA SPI_SCK
Master A Gain B Gain

UG230_c10_03_030306

Figure 10-3: SPI Serial Interface to Amplifier

The AMP_DOUT output from the amplifier echoes the previous gain settings. These
values can be ignored for most applications.
The SPI bus transaction starts when the FPGA asserts AMP_CS Low (see Figure 10-4). The
amplifier captures serial data on SPI_MOSI on the rising edge of the SPI_SCK clock signal.
The amplifier presents serial data on AMP_DOUT on the falling edge of SPI_SCK.

AMP_CS
30 50 50

SPI_SCK
30

SPI_MOSI 7 6 5 4 3 2
(from FPGA)
85 max

AMP_DOUT Previous 7 6 5 4 3 2
(from AMP)
All timing is minimum in nanoseconds unless otherwise noted. UG230_c10_04_022306

Figure 10-4: SPI Timing When Communicating with Amplifier

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Analog to Digital Converter (ADC)

The amplifier interface is relatively slow, supporting only about a 10 MHz clock frequency.

UCF Location Constraints

Figure 10-5 provides the User Constraint File (UCF) constraints for the amplifier interface,
including the I/O pin assignment and I/O standard used.

NET "SPI_MOSI" LOC = "T4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;

NET "AMP_CS" LOC = "N7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "SPI_SCK" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "AMP_SHDN" LOC = "P7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "AMP_DOUT" LOC = "E18" | IOSTANDARD = LVCMOS33 ;

Figure 10-5: UCF Location Constraints for the DAC Interface

Analog to Digital Converter (ADC)

The LTC1407A-1 provides two ADCs. Both analog inputs are sampled simultaneously
when the AD_CONV signal is applied.

Interface
Table 10-3 lists the interface signals between the FPGA and the ADC. The SPI_MOSI,
SPI_MISO, and SPI_SCK signals are shared with other devices on the SPI bus. The
DAC_CS signal is the active-Low slave select input to the DAC. The DAC_CLR signal is
the active-Low, asynchronous reset input to the DAC.

Table 10-3: ADC Interface Signals

Signal FPGA Pin Direction Description
SPI_SCK U16 FPGAÆADC Clock
AD_CONV P11 FPGAÆADC Active-High shutdown and reset.
SPI_MISO N10 FPGAÅADC Serial data: Master Input, Serial Output. Presents
the digital representation of the sample analog
values as two 14-bit two’s complement binary
values.

SPI Control Interface

Figure 10-6 provides an example SPI bus transaction to the ADC.
When the AD_CONV signal goes High, the ADC simultaneously samples both analog
channels. The results of this conversion are not presented until the next time AD_CONV is
asserted, a latency of one sample. The maxim sample rate is approximately 1.5 MHz.
The ADC presents the digital representation of the sampled analog values as a 14-bit, two’s
complement binary value.

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Chapter 10: Analog Capture Circuit

SPI_MISO
Slave: LTC1407A-1 A/D Converter
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13
AD_CONV
Spartan-3E
Z Z Z
FPGA SPI_SCK
Channel 1 Channel 0
Master
Converted data is presented with a latency of one sample.
The sampled analog value is converted to digital data 32 SPI_SCK cycles after asserting AD_CONV.
Sample The converted values is then presented after the next AD_CONV pulse. Sample
point point
AD_CONV

SPI_SCK
Channel 0 Channel 1 Channel 0
SPI_MISO 13 0 13 0 13

UG230_c10_05_030306

Figure 10-6: Analog-to-Digital Conversion Interface

Figure 10-7 shows detailed transaction timing. The AD_CONV signal is not a traditional
SPI slave select enable. Be sure to provide enough SPI_SCK clock cycles so that the ADC
leaves the SPI_MISO signal in the high-impedance state. Otherwise, the ADC blocks
communication to the other SPI peripherals. As shown in Figure 10-6, use a 34-cycle
communications sequence. The ADC 3-states its data output for two clock cycles before
and after each 14-bit data transfer.

4ns min

AD_CONV
19.6ns min
3ns

SPI_SCK 1 2 3 4 5 6
8ns

Channel 0
SPI_MISO High-Z
13 12 11

AD_CONV
45ns min

SPI_SCK 30 31 32 33 34
6ns

Channel 1
High-Z
SPI_MISO 3 2 1 0

The A/D converter sets its SDO output line to high impedance after 33 SPI_SCK clock cycles
UG230_c10_06_022306

Figure 10-7: Detailed SPI Timing to ADC

UCF Location Constraints

Figure 10-8 provides the User Constraint File (UCF) constraints for the amplifier interface,
including the I/O pin assignment and I/O standard used.

NET "AD_CONV" LOC = "P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;

NET "SPI_SCK" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 ;

Figure 10-8: UCF Location Constraints for the ADC Interface

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Disable Other Devices on the SPI Bus to Avoid Contention

Disable Other Devices on the SPI Bus to Avoid Contention

The SPI bus signals are shared by other devices on the board. It is vital that other devices
are disabled when the FPGA communicates with the AMP or ADC to avoid bus
contention. Table 10-4 provides the signals and logic values required to disable the other
devices. Although the StrataFlash PROM is a parallel device, its least-significant data bit is
shared with the SPI_MISO signal. The Platform Flash PROM is only potentially enabled if
the FPGA is set up for Master Serial mode configuration.

Table 10-4: Disable Other Devices on SPI Bus

Signal Disabled Device Disable Value
SPI_SS_B SPI Serial Flash 1
AMP_CS Programmable Pre-Amplifier 1
DAC_CS DAC 1
SF_CE0 StrataFlash Parallel Flash PROM 1
FPGA_INIT_B Platform Flash PROM 1

Connecting Analog Inputs

Connect AC signals to VINA or VINB via a DC blocking capacitor.

Related Resources
• Amplifier and A/D Converter Control for the Spartan-3E Starter Kit (Reference
Design)
http://www.xilinx.com/s3estarter
• Xilinx PicoBlaze Soft Processor
http://www.xilinx.com/picoblaze
• LTC6912 Dual Programmable Gain Amplifiers with Serial Digital Interface
http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1154,C1009,C1121,P7596,D5359

• LTC1407A-1 Serial 14-bit Simultaneous Sampling ADCs with Shutdown

http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1155,C1001,C1158,P2420,D1295

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Chapter 11

Intel StrataFlash Parallel NOR Flash

PROM
As shown in Figure 11-1, the Spartan-3E Starter Kit boards includes a 128 Mbit (16 Mbyte)
Intel StrataFlash parallel NOR Flash PROM. As indicated, some of the StrataFlash
connections are shared with other components on the board.

Intel StrataFlash
SPI Serial Flash
CE2
Spartan-3E FPGA
CE1 Q
SF_CE0
LDC0 CE0
SF_OE
LDC1 OE# ADC
SF_WE
HDC WE#
SF_BYTE SDO
LDC2 BYTE#
SF_STS
User I/O STS
SF_D<15:12> DAC
User I/O D[15:12]
SF_D<11:8>
User I/O D[11:8] SDO
SF_D<7:1>
D[7:1] D[7:1]
SPI_MISO
D[0] D[0]
SF_A<24:20> Platform Flash
User I/O A[24:20]
SF_A<19:0>
A[19:0] A[19:0] D0
A[23:20]

CoolRunner-II CPLD Character LCD

[7:4]
DB[7:4]
UG230_c11_01_030206

Figure 11-1: Connections to Intel StrataFlash Flash Memory

The StrataFlash PROM provides various functions:
• Stores a single FPGA configuration in the StrataFlash device.
• Stores two different FPGA configurations in the StrataFlash device and dynamically
switch between the two using the Spartan-3E FPGA’s MultiBoot feature.
• Stores and executes MicroBlaze processor code directly from the StrataFlash device.

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Chapter 11: Intel StrataFlash Parallel NOR Flash PROM

• Stores MicroBlaze processor code in the StrataFlash device and shadows the code into
the DDR memory before executing the code.
• Stores non-volatile data from the FPGA.

StrataFlash Connections
Table 11-1 shows the connections between the FPGA and the StrataFlash device.
Although the XC3S500E FPGA only requires just slightly over 2 Mbits per configuration
image, the FPGA-to-StrataFlash interface on the board support up to a 256 Mbit
StrataFlash. The Spartan-3E Starter Kit board ships with a 128 Mbit device. Address line
SF_A24 is not used.
In general, the StrataFlash device connects to the XC3S500E to support Byte Peripheral
Interface (BPI) configuration. The upper four address bits from the FPGA, A[23:19] do not
connect directly to the StrataFlash device. Instead, the XC2C64 CPLD controls the pins
during configuration. As described in Table 11-1 and Shared Connections, some of the
StrataFlash connections are shared with other components on the board.

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StrataFlash Connections

Table 11-1: FPGA-to-StrataFlash Connections

StrataFlash FPGA Pin
Category Signal Name Number Function
SF_A24 A11 Shared with XC2C64A CPLD. The CPLD
actively drives these pins during FPGA
SF_A23 N11
configuration, as described in Chapter 16,
SF_A22 V12 “XC2C64A CoolRunner-II CPLD”. Also
connects to FPGA user-I/O pins. SF_A24 is the
SF_A21 V13
same as FX2 connector signal FX2_IO<32>.
SF_A20 T12
SF_A19 V15 Connects to FPGA pins A[19:0] to support the
BPI configuration.
SF_A18 U15
SF_A17 T16
SF_A16 U18
SF_A15 T17
SF_A14 R18
SF_A13 T18
Address

SF_A12 L16
SF_A11 L15
SF_A10 K13
SF_A9 K12
SF_A8 K15
SF_A7 K14
SF_A6 J17
SF_A5 J16
SF_A4 J15
SF_A3 J14
SF_A2 J12
SF_A1 J13
SF_A0 H17

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Chapter 11: Intel StrataFlash Parallel NOR Flash PROM

Table 11-1: FPGA-to-StrataFlash Connections

StrataFlash FPGA Pin
Category Signal Name Number Function
SF_D15 T8 Upper 8 bits of a 16-bit
halfword when
SF_D14 R8
StrataFlash is -
SF_D13 P6 configured for x16
data
SF_D12 M16
(SF_BYTE=High).
SF_D11 M15 Connects to FPGA Signals SF_D<11:8>
user I/O. connect to character
SF_D10 P17
LCD pins DB[7:4].
SF_D9 R16
SF_D8 R15
SF_D7 N9 Upper 7 bits of a data byte or lower 8 bits of a
Data

16-bit halfword. Connects to FPGA pins D[7:1]

SF_D6 M9
to support the BPI configuration.
SF_D5 R9
SF_D4 U9
SF_D3 V9
SF_D2 R10
SF_D1 P10
SPI_MISO N10 Bit 0 of data byte and 16-bit halfword.
Connects to FPGA pin D0/DIN to support the
BPI configuration. Shared with other SPI
peripherals and Platform Flash PROM.
SF_CE0 D16 StrataFlash Chip Enable. Connects to FPGA
pin LDC0 to support the BPI configuration.
SF_WE D17 StrataFlash Write Enable. Connects to FPGA
pin HDC to support the BPI configuration.
SF_OE C18 StrataFlash Chip Enable. Connects to FPGA
Control

pin LDC1 to support the BPI configuration.

SF_BYTE C17 StrataFlash Byte Enable. Connects to FPGA pin
LDC2 to support the BPI configuration.
0: x8 data
1: x16 data
SF_STS B18 StrataFlash Status signal. Connects to FPGA
user-I/O pin.

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Shared Connections

Shared Connections
Besides the connections to the FPGA, the StrataFlash memory shares some connections to
other components.

Character LCD
The character LCD uses a four-bit data interface. The display data connections are also
shared with the SF_D<11:8> signals on the StrataFlash PROM. As shown in Table 11-2, the
FPGA controls access to the StrataFlash PROM or the character LCD using the SF_CE0 and
LCD_RW signals.

Table 11-2: FPGA Control for StrataFlash and LCD

SF_CE0 LCD_RW Function
1 1 The FPGA reads from the character LCD.
0 0 The FPGA accesses the StrataFlash PROM.

Xilinx XC2C64A CPLD

The Xilinx XC2C64A CoolRunner CPLD controls the five upper StrataFlash address lines,
SF_A<24:20> during configuration. The four upper BPI-mode address lines from the
FPGA, A<23:20> are not connected. Instead, four FPGA user-I/O pins connect to the
StrataFlash PROM upper address lines SF_A<23:0>. See Chapter 16, “XC2C64A
CoolRunner-II CPLD” for more information.
The most-significant address line, SF_A<24>, is not physically used on the 16 Mbyte
StrataFlash PROM. It is provided for upward migration to a larger StrataFlash PROM in
the same package footprint. Likewsie, the SF_A<24> signal is also connected to the
FX2_IO<32> signal on the FX2 expansion connector.

SPI Data Line

The least-significant StrataFlash data line, SF_D<0>, is shared with data output signals
from serial SPI peripherals, SPI_MISO, and the serial output from the Platform Flash
PROM as shown in Table 11-3. To avoid contention, the FPGA application must ensure that
only one data source is active at any time.
Table 11-3: Possible Contention on SPI_MISO (SF_D<0>) Data
Condition Function
FPGA_M2 = Low Platform Flash outputs data on D0.
FPGA_M1 = Low
FPGA_M0 = Low
INIT_B = High
SF_CE0 = Low StrataFlash outputs data.
SF_OE = Low
AD_CONV = High Serial data is clocked out of the A/D converter
SPI_SCK
DAC_CS = Low DAC outputs previous command in response to SPI_SCK transitions.
SPI_SCK

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Chapter 11: Intel StrataFlash Parallel NOR Flash PROM

UCF Location Constraints

Address
Figure 11-2 provides the UCF constraints for the StrataFlash address pins, including the
I/O pin assignment and the I/O standard used.

NET "SF_A<24>" LOC = "A11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET "SF_A<23>" LOC = "N11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<22>" LOC = "V12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<21>" LOC = "V13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<20>" LOC = "T12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<19>" LOC = "V15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<18>" LOC = "U15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<17>" LOC = "T16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<16>" LOC = "U18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<15>" LOC = "T17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<14>" LOC = "R18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<13>" LOC = "T18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<12>" LOC = "L16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<11>" LOC = "L15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<10>" LOC = "K13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<9>" LOC = "K12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<8>" LOC = "K15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<7>" LOC = "K14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<6>" LOC = "J17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<5>" LOC = "J16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<4>" LOC = "J15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<3>" LOC = "J14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<2>" LOC = "J12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<1>" LOC = "J13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<0>" LOC = "H17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

Figure 11-2: UCF Location Constraints for StrataFlash Address Inputs

Data
Figure 11-3 provides the UCF constraints for the StrataFlash data pins, including the I/O
pin assignment and the I/O standard used.

NET "SF_D<15>" LOC = "T8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET "SF_D<14>" LOC = "R8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<13>" LOC = "P6" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<12>" LOC = "M16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<11>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<10>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<9>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<8>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<7>" LOC = "N9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<6>" LOC = "M9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<5>" LOC = "R9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<4>" LOC = "U9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<3>" LOC = "V9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<2>" LOC = "R10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<1>" LOC = "P10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 | DRIVE = 6 | SLEW = SLOW ;

Figure 11-3: UCF Location Constraints for StrataFlash Data I/Os

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Setting the FPGA Mode Select Pins

Control
Figure 11-4 provides the UCF constraints for the StrataFlash control pins, including the
I/O pin assignment and the I/O standard used.

NET "SF_BYTE" LOC = "C17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET "SF_CE0" LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_OE" LOC = "C18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_STS" LOC = "B18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_WE" LOC = "D17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

Figure 11-4: UCF Location Constraints for StrataFlash Control Pins

Setting the FPGA Mode Select Pins

Set the FPGA configuration mode pins for either BPI Up or BPI down mode, as shown in
Table 11-4. See
Table 11-4: Selecting BPI-Up or BPI-Down Configuration Modes (Header J30 in
Figure 4-2)
Configuration Mode Pins FPGA Configuration Image in
Mode M2:M1:M0 StrataFlash Jumper Settings
BPI Up 0:1:0 FPGA starts at address 0 and
increments through address space. M0
The CPLD controls address lines M1
A[24:20] during BPI configuration. M2
J30

BPI Down 0:1:1 FPGA starts at address 0xFF_FFFF

and decrements through address M0
space. The CPLD controls address M1
lines A[24:20] during BPI M2
configuration.
J30

Related Resources
• Intel J3 StrataFlash Data Sheet
http://www.intel.com/design/flcomp/products/j3/techdocs.htm#datasheets
• Application Note 827, Intel StrataFlash® Memory (J3) to Xilinx Spartan-3E FPGA
Design Guide
http://www.intel.com/design/flcomp/applnots/307257.htm

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Chapter 11: Intel StrataFlash Parallel NOR Flash PROM

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Chapter 12

SPI Serial Flash

The Spartan-3E Starter Kit board includes a STMicroelectronics M25P16 16 Mbit SPI serial
Flash, useful in a variety of applications. The SPI Flash provides an alternative means to
configure the FPGA—a new feature of Spartan-3E FPGAs as shown in Figure 12-1. The SPI
Flash is also available to the FPGA after configuration for a variety of purposes, such as:
• Simple non-volatile data storage
• Storage for identifier codes, serial numbers, IP addresses, etc.
• Storage of MicroBlaze processor code that can be shadowed into DDR SDRAM.

STMicro M25P16
Spartan-3E FPGA SPI Serial Flash
SPI_MOSI
MOSI/CSI_B (T4) D
SPI_MISO
DIN/D0 (N10) Q
SPI_SCK
CCLK (U16) C
SPI_SS_B
CSO_B (U3) S
UG230_c15_01_030206

Figure 12-1: Spartan-3E FPGAs Have an Optional SPI Flash Configuration Interface

Table 12-1: SPI Flash Interface Signals

Signal FPGA Pin Direction Description
SPI_MOSI T4 FPGAÆSPI Serial data: Master Output, Slave Input
SPI_MISO N10 FPGAÅSPI Serial data: Master Input, Slave Output
SPI_SCK U16 FPGAÆSPI Clock
SPI_SS_B U3 FPGAÆSPI Asynchronous, active-Low slave select input

UCF Location Constraints

Figure 12-2 provides the UCF constraints for the SPI serial Flash PROM, including the I/O
pin assignment and the I/O standard used.

# some connections shared with SPI Flash, DAC, ADC, and AMP
NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 ;
NET "SPI_MOSI" LOC = "T4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "SPI_SCK" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "SPI_SS_B" LOC = "U3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "SPI_ALT_CS_JP11" LOC = "R12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;

Figure 12-2: UCF Location Constraints for SPI Flash Connections

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Chapter 12: SPI Serial Flash

Configuring from SPI Flash

To configure the FPGA from SPI Flash, the FPGA mode select pins must be set
appropriately and the SPI Flash must contain a valid configuration image.

Select SPI Mode using Jumper Settings Header J12 (XSPI Programming)
Remove the top jumper, insert the bottom two as shown
Jumper J11

DONE Pin LED

Lights up when FPGA successfully configured PROG_B Push Button Switch
Press and release to restart configuration
Jumper JP8 (XSPI)
When programming SPI Flash using XSPI
utility, insert jumper to hold PROG_B pin Low UG230_c15_02_030906

Figure 12-3: Configuration Options for SPI Mode

Setting the FPGA Mode Select Pins

Set the FPGA configuration mode pins for SPI mode, as shown in Figure 12-4. The location
of the configuration mode jumpers (J30) appears in Figure 12-3.

M0
M1
M2

J30
UG230_c15_03_030206

Figure 12-4: Set Mode Pins for SPI Mode

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Configuring from SPI Flash

Creating an SPI Serial Flash PROM File

The following steps describe how to format an FPGA bitstream for an SPI Serial Flash
PROM.

Setting the Configuration Clock Rate

The FPGA supports a 12 MHz configuration clock rate when connected to an M25P16 SPI
serial Flash. Set the Properties for Generate Programming File so that the
Configuration Rate is 12, as shown in Figure 12-5. See “Generating the FPGA
Configuration Bitstream File” in the FPGA Configuration Options chapter for a
more detailed description.
Regenerate the FPGA bitstream programming file with the new settings.

UG230_c15_04_030206

Figure 12-5: Set Configuration Rate to 12 MHz When Using the M25P16 SPI Flash

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Chapter 12: SPI Serial Flash

Formatting an SPI Flash PROM File

After generating the program file, double-click Generate PROM, ACE, or JTAG File
to launch the iMPACT software, as shown in Figure 12-6.

UG230_c15_05_030206

Figure 12-6: Double-Click Generate PROM, ACE, or JTAG File

After iMPACT starts, double-click PROM File Formatter, as shown in Figure 12-7.

UG230_c15_06_030206

Figure 12-7: Double-Click PROM File Formatter

Choose 3rd Party SPI PROM as the target PROM type, as shown in Figure 12-8. Select
from any of the PROM File Formats; the Intel Hex format (MCS) is popular. The PROM
Formatter automatically swaps the bit direction as SPI Flash PROMs shift out the most-
significant bit (MSB) first. Enter the Location of the directory and the PROM File Name.
Click Next > when finished.

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Configuring from SPI Flash

UG230_c15_07_030206

Figure 12-8: Choose the PROM Target Type, the, Data Format, and File Location
The Spartan-3E Starter Kit board has a 16 Mbit SPI serial Flash PROM. Select 16M from the
drop list, as shown in Figure 12-9. Click Next >.

UG230_c15_08_030206

Figure 12-9: Choose 16M

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Chapter 12: SPI Serial Flash

The PROM Formatter then echoes the settings, as shown in Figure 12-10. Click Finish.

UG230_c15_09_030206

Figure 12-10: Click Finish after Entering PROM Formatter Settings

The PROM Formatter then prompts for the name(s) of the FPGA configuration bitstream
file. As shown in Figure 12-11, click OK to start selecting files. Select an FPGA bitstream file
(*.bit). Choose No after selecting the last FPGA file. Finally, click OK to continue.

UG230_c15_10_030206

Figure 12-11: Enter FPGA Configuration Bitstream File(s)

When PROM formatting is complete, the iMPACT software presents the present settings
by showing the PROM, the select FPGA bitstream(s), and the amount of PROM space
consumed by the bitstream. Figure 12-12 shows an example for a single XC3S500E FPGA
bitstream stored in an XCF04S Platform Flash PROM.

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Configuring from SPI Flash

UG230_c15_11_030206

Figure 12-12: PROM Formatting Completed

To generate the actual PROM file, click Operations Æ Generate File as shown in
Figure 12-13.

UG230_c15_12_030206

Figure 12-13: Click Operations Æ Generate File to Create the Formatted PROM File
As shown in Figure 12-14, the iMPACT software indicates that the PROM file was
successfully created. The PROM Formatter creates an output file based on the settings
shown in Figure 12-8. In this example, the output file is called MySPIFlash.mcs.

UG230_c15_13_030206

Figure 12-14: PROM File Formatter Succeeded

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Chapter 12: SPI Serial Flash

Downloading the Design to SPI Flash

There multiple methods to program the SPI Flash, as listed below.
• Use the XSPI programming software provided with XAPP445. Download the SPI
Flash via the parallel port using a JTAG parallel programming cable (not provided
with the kit).
• Use the PicoBlaze based SPI Flash programmer reference designs. Use a terminal
emulator, such as Hyperlink, to download SPI Flash programming data via the PC’s
serial port to the FPGA. The embedded PicoBlaze processor then programs the
attached SPI serial Flash. See “Related Resources,” page 102.
• Via the FPGA’s JTAG chain, use a JTAG tool to program the SPI Flash connected to the
FPGA. See the link to the Universal Scan SPI Flash programming tutorial in “Related
Resources,” page 102.
• Additional programming support will be provided in the ISE 8.2i software.

Downloading the SPI Flash using XSPI

The following steps describe how to download the SPI Flash PROM using the XSPI
programming utility.

Download and Install the XSPI Programming Utility

Download application note XAPP445 and the associated XSPI programming software (see
“Related Resources,” page 102). Unzip the XSPI software onto the PC.

Attach a JTAG Parallel Programming Cable

The XSPI programming utility uses a JTAG parallel programming cable, such as:
• Xilinx Parallel Cable IV with flying leads
• Digilent JTAG3 programming cable
These cables are not provided with the Spartan-3E Starter Kit board but can be purchased
separately, either from the Xilinx Online Store or from Digilent, Inc. (see “Related
Resources,” page 102).
First, turn off the power on the Spartan-3E Starter Kit board.
If the USB cable is attached to the board, disconnect it. Simultaneously connecting both the
USB cable and the parallel cable to the PC confuses the iMPACT software.
Connect one end of the JTAG parallel programming cable to the parallel printer port of the
PC.
Connect the JTAG end of the cable to Header J12, as shown in Figure 12-15a. The physical
location of Header J12 is more clearly shown in Figure 12-3, page 90. The J12 header
connects directly to the SPI Flash pins; it is not connected to the JTAG chain.
The JTAG3 cable directly mounts to Header J12. The labels on the JTAG3 cable face toward
the J11 jumpers. If using flying leads, they must be connected as shown in Figure 12-15b
and Table 12-2. Note the color coding for the leads. The gray INIT lead is left unconnected.

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Configuring from SPI Flash

a) JTAG3 Parallel Connector b) Parallel Cable III or Parallel Cable IV

with Flying Leads
UG230_c15_14_030206

Figure 12-15: Attaching a JTAG Parallel Programming Cable to the Board

Table 12-2: Cable Connections to J12 Header

Cable and Labels Connections
J12 Header Label SEL SDI SDO SCK GND VCC
JTAG3 Cable Label TMS TDI TDO TCK GND VCC
Flying Leads Label TMS/ TDI/ TDO/ TCK/ GND/ VREF/
PROG DIN DONE CCLK GND VREF

Insert Jumper on JP8 and Hold PROG_B Low

The JTAG parallel programming cable directly accesses the SPI Flash pins. To avoid signal
contention with the FPGA, ensure that the connecting FPGA pins are high-impedance.
Force the FPGA’s PROG_B pin Low by installing a jumper on JP8, next to the PROG push
button, as shown in Figure 12-16. See Figure 12-3, page 90 to locate jumper JP8 and
surrounding landmarks.

JP8 JP8
NO JUMPER

NO JUMPER
DEFAULT

DEFAULT

PROG PROG
GND GND
PROG PROG

a) No Jumper: FPGA Operational (default) b) Jumper Installed: FPGA Held in

Configuration State, I/Os in High Impedance
UG230_c15_15_030206

Figure 12-16: Installing the JP8 Jumper Holds the FPGA in Configuration State
Re-apply power to the Spartan-3E Starter Kit board.

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Chapter 12: SPI Serial Flash

Programming the SPI Flash with the XSPI Software

Open a command prompt or DOS box and change to the XSPI installation directory.
The XSPI installation software also includes a short user guide, in addition to XAPP445.
Type xspi at the prompt to view quick help.
Type the following command at the prompt to program the SPI Flash using the SPI-
formatted Flash file generated earlier. This verifies that the SPI Flash is indeed an M25P16
SPI Flash and then erases, programs, and finally verifies the Flash.
C:\xspi>xspi -spi_dev m25p16 -spi_epv -mcs -i MySPIFlash.mcs -o output.txt

A disclaimer notice appears on the screen. Press the Enter key to continue. The entire
programming process takes slightly longer than a minute, as shown in Figure 12-17.

-==< Press ENTER to accept notice and continue >==-

Start : Mon Feb 27 13:37:07 2006

==> Checking SPI device [STMicro_M25P16_ver_00100] ID code(s)

- density = [2097152] bytes
= [16777216] bits
- mfg_code = [0x20]
- memory_type = [0x20]
- density_code = [0x15]
+-----------------------------------------+
| Device ID code(s) check ====> [ OK ] |
+-----------------------------------------+
=> Operation: Erase
=> Operation: Program and Verify using file [MySPIFlash.mcs]
Programmed [283776] of [283776] bytes (w/ polling)
Verified [283776] of [283776] bytes (0 errors)

--> Total byte mismatches [0] (see [temp.txt])

Finish : Mon Feb 27 13:38:22 2006
Elapsed clock time (00:01:15) = 75 seconds

Figure 12-17: Programming the M25P16 SPI Flash with the XSPI Programming
Utility

After programming the SPI Flash, remove jumper JP8, as shown in Figure 12-16a. If
properly programmed, the FPGA then configures itself from the SPI Flash PROM and the
DONE LED lights. The DONE LED is shown in Figure 12-3.

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Additional Design Details

Additional Design Details

Figure 12-18 provides additional details of the SPI Flash interface used on the Spartan-3E
Starter Kit board. In most applications, this interface is as simple as that shown in
Figure 12-1. The Spartan-3E Starter Kit board, however, supports of variety of
configuration options and demonstrates additional Spartan-3E capabilities.

3.3V

STMicro M25P16
Spartan-3E FPGA SPI Serial Flash
SPI_MOSI
MOSI/CSI_B (T4) D
SF_A<17> SPI_MISO
(T16) VS2/A17 DIN/D0 (N10) Q
SF_A<18> SPI_SCK
(U15) VS1/A18 CCLK (U16) C W
SF_A<19> SPI_SS_B
(V15) VS0/A19 CSO_B (U3) S HLD
SPI_ALT_CS_JP11
User-I/O (R12)

DAC

Other devices share SPI bus

Jumper J11
AMP

ROM_CS
CSO_B
SEL

CSO_B
ADC

Platform
Flash
Strata-
Flash

Programming
Header J12
SEL
SDI
SDO
SCK
GND
3.3V

UG230_c15_17_030306

Figure 12-18: Additional SPI Flash Interface Design Details

Shared SPI Bus with Peripherals

After configuration, the SPI Flash configuration pins are available to the application. On
the Spartan-3E Starter Kit board, the SPI bus is shared by other SPI-capable peripheral
devices, as shown in Figure 12-18. To access the SPI Flash memory after configuration, the
FPGA application must disable the other devices on the shared PCI bus. Table 12-3 shows
the signal names and disable values for the other devices.
Table 12-3: Disable Other Devices on SPI Bus
Signal Disabled Device Disable Value
DAC_CS Digital-to-Analog Converter (DAC) 1
AMP_CS Programmable Pre-Amplifier 1
AD_CONV Analog-to-Digital Converter (ADC) 0
SF_CE0 StrataFlash Parallel Flash PROM 1
FPGA_INIT_B Platform Flash PROM 1

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Chapter 12: SPI Serial Flash

Other SPI Flash Control Signals

The M25P16 SPI Flash has two additional control inputs. The active-Low write protect
input (W) and the active-Low bus hold input (HLD) are unused and pulled High via an
external pull-up resistor.

Variant Select Pins, VS[2:0]

When in SPI configuration mode, the FPGA samples the value on three pins, labeled
VS[2:0], to determine which SPI read command to issue to the SPI Flash. For the M25P16
Flash, VS[2:0]=<1:1:1> issues the correct command sequence. The VS[2:0] pins are pulled
High externally via pull-up resistors to 3.3V. The VS[2:0] pins are also parallel NOR Flash
address lines A[19:17] in the FPGA’s BPI configuration mode and these signals also
connect to the StrataFlash parallel Flash PROM. After SPI configuration, the VS[2:0] pins
become user-programmable I/O pins, allowing full access to the StrataFlash PROM,
despite that the FPGA configured from SPI Flash.

Jumper Block J11

In SPI configuration mode, the FPGA selects the attached SPI Flash by asserting the CSO_B
pin Low. On the Spartan-3E Starter Kit board, the CSO_B pin drives into the jumper J11
block. This jumper block provides the option to move the on-board SPI Flash to a different
select line (SPI_ALT_CS_JP11). This way, a different SPI Flash device can be tested by
changing the JP11 jumper settings and connecting the alternate SPI Flash on Header JP12.
By default, both jumpers are inserted on jumper block header J11.

Programming Header J12

As shown in Figure 12-15, page 97, Header J12 accepts a JTAG parallel programming cable
to program the on-board SPI Flash.

Multi-Package Layout
STMicroelectronics was rather clever when they defined the package layout for the
M25Pxx SPI serial Flash family. The Spartan-3E Starter Kit board supports all three of the
package types used for the 16 Mbit device, as shown in Figure 12-19. By default, the board
ships with the 8-lead, 8x6 mm MLP package. The multi-package layout also supports the 8-
pin SOIC package and the 16-pin SOIC package. Pin 1 for the 8-pin SOIC and MLP
packages is located in the top-left corner. However, pin 1 for the 16-pin SOIC package is
located in the top-right corner, because the package is rotated 90°. The 16-pin SOIC
package also have four pins on each side that do not connect on the board. These pins must
be left floating. Why support multiple packages? In a word, flexibility. The multi-package
layout provides ...
• Density migration between smaller- and larger-density SPI Flash PROMs. Not all
SPI Flash densities are available in all packages. The SPI Flash migration strategy
follows nicely with the pinout migration provided by Xilinx FPGAs.
• Consistent configuration PROM layout when migrating between FPGA densities.
The Spartan-3E FPGA’s FG320 package footprint supports the XC3S500E, the
XC3S1200E, and the XC3S1600E FPGA devices without modification. The SPI Flash
multi-package layout allows comparable flexibility in the associated configuration
PROM. Ship the optimally-sized SPI Flash memory for the FPGA mounted on the
board.

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Additional Design Details

• Supply security. If a certain SPI Flash density is not available in the desired package,
switch to a different package style or to a different density to secure availability.

HOLD
VCC
Q
S
Pin 1:
16-pin SOIC
Pin 1:
8-pin SOIC (Do not connect)
8-lead MLP
S VCC
Q HOLD
W C
GND D
GND (Do not connect)

D
C
W

UG230_c15_18_030606

Figure 12-19: Multi-Package Layout for the STMicroelectronics M25Pxx Family

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Chapter 12: SPI Serial Flash

Related Resources
• XAPP445: Configuring Spartan-3E Xilinx FPGAs with SPI Flash Memories
http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=
Application+Notes/FPGA+Features+and+Design/Configuration&show=xapp445.pdf
• XSPI SPI Flash Programming Utility
http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=
Application+Notes/FPGA+Features+and+Design/Configuration&show=xapp445.pdf
• Xilinx Parallel Cable IV with Flying Leads
http://www.xilinx.com/xlnx/xebiz/productview.jsp?sGlobalNavPick=&category=-19314

• Digilent JTAG3 Programming Cable

http://www.digilentinc.com/Products/Catalog.cfm?Nav1=Products&Nav2=Cables&Cat=Cable

• STMicroelectronics M25P16 SPI Serial Flash Data Sheet

http://www.st.com/stonline/books/pdf/docs/10027.pdf
• AN1579: Compatibility between the SO8 Package and the MLP Package for the
M25Pxx in Your Application
http://www.st.com/stonline/products/literature/an/9540.pdf
• PicoBlaze SPI Serial Flash Programmer, via RS-232 (Reference Design)
http://www.xilinx.com/s3estarter
• Using Serial Flash on the Spartan-3E Starter Kit Board (Reference Design)
http://www.xilinx.com/s3estarter
• Universal Scan SPI Flash Programming via JTAG Training Video
http://www.ricreations.com/JTAG-Software-Downloads.htm

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Chapter 13

DDR SDRAM
The Spartan-3E Starter Kit boards includes a 512 Mbit (32M x 16) Micron Technology DDR
SDRAM (MT46V32M16) with a 16-bit data interface, as shown in Figure 13-1. All DDR
SDRAM interface pins connect to the FPGA’s I/O Bank 3 on the FPGA. I/O Bank 3 and the
DDR SDRAM are both powered by 2.5V, generated by an LTC3412 regulator from the
board’s 5V supply input. The 1.25V reference voltage, common to the FPGA and DDR
SDRAM, is generated using a resistor voltage divider from the 2.5V rail.

5.0V

2.5V
LTC3412

1.25V
Spartan-3E FPGA Micron 512 Mb DDR SDRAM
SD_A<12:0>
See Table A[12:0]
SD_DQ<15:0>
VREF See Table DQ[15:0] VREF
SD_BA<1:0>
VCCO_3 See Table BA[1:0] VDD
SD_RAS
(C1) RAS# VDDQ
SD_CAS
(C2) CAS#
SD_WE
(D1) WE#
SD_UDM
(J1) UQM MT46V32M16
SD_LDM (32Mx16)
(J2) LQM
SD_UDQS
(G3) UDQS
SD_LDQS
(L6) LDQS
SD_CS
(K4) CS#
SD_CKE
(K3) CKE
SD_CK_N
(J4) CK#
SD_CK_P
(B9) GCLK9 (J5) CK

SD_CK_FB
UG230_c13_01_022406

Figure 13-1: FPGA Interface to Micron 512 Mbit DDR SDRAM

All DDR SDRAM interface signals are terminated.

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Chapter 13: DDR SDRAM

The differential clock pin SD_CK_P is fed back into FPGA pin B9 in I/O Bank 0 to have best
access to one of the FPGA’s Digital Clock Managers (DCMs). This path is required when
using the MicroBlaze OPB DDR controller. The MicroBlaze OPB DDR SDRAM controller
IP core documentation is also available from within the EDK 8.1i development software
(see “Related Resources,” page 107).

DDR SDRAM Connections

Table 13-1 shows the connections between the FPGA and the DDR SDRAM.

Table 13-1: FPGA-to-DDR SDRAM Connections

DDR SDRAM FPGA Pin
Category Signal Name Number Function
SD_A12 P2 Address inputs
SD_A11 N5
SD_A10 T2
SD_A9 N4
SD_A8 H2
SD_A7 H1
Address

SD_A6 H3
SD_A5 H4
SD_A4 F4
SD_A3 P1
SD_A2 R2
SD_A1 R3
SD_A0 T1

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DDR SDRAM Connections

Table 13-1: FPGA-to-DDR SDRAM Connections (Continued)

DDR SDRAM FPGA Pin
Category Signal Name Number Function
SD_DQ15 H5 Data input/output
SD_DQ14 H6
SD_DQ13 G5
SD_DQ12 G6
SD_DQ11 F2
SD_DQ10 F1
SD_DQ9 E1
SD_DQ8 E2
Data

SD_DQ7 M6
SD_DQ6 M5
SD_DQ5 M4
SD_DQ4 M3
SD_DQ3 L4
SD_DQ2 L3
SD_DQ1 L1
SD_DQ0 L2
SD_BA1 K6 Bank address inputs
SD_BA0 K5
SD_RAS C1 Command inputs
SD_CAS C2
SD_WE D1
SD_CK_N J4 Differential clock input
SD_CK_P J5
Control

SD_CKE K3 Active-High clock enable input

SD_CS K4 Active-Low chip select input
SD_UDM J1 Data Mask. Upper and Lower data masks
SD_LDM J2
SD_UDQS G3 Data Strobe. Upper and Lower data strobes
SD_LDQS L6
SD_CK_FB B9 SDRAM clock feedback into top DCM
within FPGA. Used by some DDR SDRAM
controller cores

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Chapter 13: DDR SDRAM

UCF Location Constraints

Address
Figure 13-2 provides the User Constraint File (UCF) constraints for the DDR SDRAM
address pins, including the I/O pin assignment and the I/O standard used.

NET "SD_A<12>" LOC = "P2" | IOSTANDARD = SSTL2_I ;

NET "SD_A<11>" LOC = "N5" | IOSTANDARD = SSTL2_I ;
NET "SD_A<10>" LOC = "T2" | IOSTANDARD = SSTL2_I ;
NET "SD_A<9>" LOC = "N4" | IOSTANDARD = SSTL2_I ;
NET "SD_A<8>" LOC = "H2" | IOSTANDARD = SSTL2_I ;
NET "SD_A<7>" LOC = "H1" | IOSTANDARD = SSTL2_I ;
NET "SD_A<6>" LOC = "H3" | IOSTANDARD = SSTL2_I ;
NET "SD_A<5>" LOC = "H4" | IOSTANDARD = SSTL2_I ;
NET "SD_A<4>" LOC = "F4" | IOSTANDARD = SSTL2_I ;
NET "SD_A<3>" LOC = "P1" | IOSTANDARD = SSTL2_I ;
NET "SD_A<2>" LOC = "R2" | IOSTANDARD = SSTL2_I ;
NET "SD_A<1>" LOC = "R3" | IOSTANDARD = SSTL2_I ;
NET "SD_A<0>" LOC = "T1" | IOSTANDARD = SSTL2_I ;

Figure 13-2: UCF Location Constraints for DDR SDRAM Address Inputs

Data
Figure 13-3 provides the User Constraint File (UCF) constraints for the DDR SDRAM data
pins, including the I/O pin assignment and I/O standard used.

NET "SD_DQ<15>" LOC = "H5" | IOSTANDARD = SSTL2_I ;

NET "SD_DQ<14>" LOC = "H6" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<13>" LOC = "G5" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<12>" LOC = "G6" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<11>" LOC = "F2" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<10>" LOC = "F1" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<9>" LOC = "E1" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<8>" LOC = "E2" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<7>" LOC = "M6" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<6>" LOC = "M5" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<5>" LOC = "M4" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<4>" LOC = "M3" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<3>" LOC = "L4" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<2>" LOC = "L3" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<1>" LOC = "L1" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<0>" LOC = "L2" | IOSTANDARD = SSTL2_I ;
Figure 13-3: UCF Location Constraints for DDR SDRAM Data I/Os

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Related Resources

Control
Figure 13-4 provides the User Constraint File (UCF) constraints for the DDR SDRAM
control pins, including the I/O pin assignment and the I/O standard used.

NET "SD_BA<0>" LOC = "K5" | IOSTANDARD = SSTL2_I ;

NET "SD_BA<1>" LOC = "K6" | IOSTANDARD = SSTL2_I ;
NET "SD_CAS" LOC = "C2" | IOSTANDARD = SSTL2_I ;
NET "SD_CK_N" LOC = "J4" | IOSTANDARD = SSTL2_I ;
NET "SD_CK_P" LOC = "J5" | IOSTANDARD = SSTL2_I ;
NET "SD_CKE" LOC = "K3" | IOSTANDARD = SSTL2_I ;
NET "SD_CS" LOC = "K4" | IOSTANDARD = SSTL2_I ;

NET "SD_LDM" LOC = "J2" | IOSTANDARD = SSTL2_I ;

NET "SD_LDQS" LOC = "L6" | IOSTANDARD = SSTL2_I ;
NET "SD_RAS" LOC = "C1" | IOSTANDARD = SSTL2_I ;
NET "SD_UDM" LOC = "J1" | IOSTANDARD = SSTL2_I ;
NET "SD_UDQS" LOC = "G3" | IOSTANDARD = SSTL2_I ;
NET "SD_WE" LOC = "D1" | IOSTANDARD = SSTL2_I ;
# Path to allow connection to top DCM connection
NET "SD_CK_FB" LOC = "B9" | IOSTANDARD = LVCMOS33 ;
Figure 13-4: UCF Location Constraints for DDR SDRAM Control Pins

Reserve FPGA VREF Pins

Five pins in I/O Bank 3 are dedicated as voltage reference inputs, VREF. These pins cannot
be used for general-purpose I/O in a design. Prohibit the software from using these pins
with the constraints provided in Figure 13-5.
5i

# Prohibit VREF pins

CONFIG PROHIBIT = D2;
CONFIG PROHIBIT = G4;
CONFIG PROHIBIT = J6;
CONFIG PROHIBIT = L5;
CONFIG PROHIBIT = R4;
Figure 13-5: UCF Location Constraints for StrataFlash Control Pins

Related Resources
• Xilinx Embedded Design Kit (EDK)
http://www.xilinx.com/ise/embedded_design_prod/platform_studio.htm
• MT46V32M16 (32M x 16) DDR SDRAM Data Sheet
http://download.micron.com/pdf/datasheets/dram/ddr/512MBDDRx4x8x16.pdf
• MicroBlaze OPB Double Data Rate (DDR) SDRAM Controller (v2.00b)
http://www.xilinx.com/bvdocs/ipcenter/data_sheet/opb_ddr.pdf

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Chapter 13: DDR SDRAM

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Chapter 14

10/100 Ethernet Physical Layer Interface

The Spartan-3E Starter Kit board includes a Standard Microsystems LAN83C185 10/100
Ethernet physical layer (PHY) interface and an RJ-45 connector, as shown in Figure 14-1.
With an Ethernet Media Access Controller (MAC) implemented in the FPGA, the board
can optionally connect to a standard Ethernet network. All timing is controlled from an
on-board 25 MHz crystal oscillator.

RJ-45 Ethernet Connector (J19)

SMSC LAN83C185 10/100 Ethernet PHY

25 MHz Crystal UG230_c14_01_022706

Figure 14-1: 10/100 Ethernet PHY with RJ-45 Connector

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Chapter 14: 10/100 Ethernet Physical Layer Interface

Ethernet PHY Connections

The FPGA connects to the LAN83C185 Ethernet PHY using a standard Media Independent
Interface (MII), as shown in Figure 14-2. A more detailed description of the interface
signals, including the FPGA pin number, appears in Table 14-1.

SMSC LAN83C185
Spartan-3E FPGA 10/100 Ethernet PHY
E_TXD<3:0>
See Table TXD[3:0]
E_TX_EN
(P15) TX_EN
E_TXD<4>
(R4) TXD4/TX_ER
E_TX_CLK
(T7) TX_CLK
E_RXD<3:0> RJ-45
See Table RXD[3:0]
Connector
E_RX_DV
(V2) RX_DV
E_RXD<4>
(U14) RXD4/RX_ER
E_RX_CLK
(V3) RX_CLK
E_CRS
(U13) CRS
25.000 MHz
E_COL
(U6) COL
E_MDC
(P9) MDC
E_MDIO
(U5) MDIO
UG230_c14_02_022706

Figure 14-2: FPGA Connects to Ethernet PHY via MII

Table 14-1: FPGA Connections to the LAN83C185 Ethernet PHY

FPGA Pin
Signal Name Number Function
E_TXD<4> R6 Transmit Data to the PHY. E_TXD<4> is also the MII
Transmit Error.
E_TXD<3> T5
E_TXD<2> R5
E_TXD<1> T15
E_TXD<0> R11
E_TX_EN P15 Transmit Enable.
E_TX_CLK T7 Transmit Clock. 25 MHz in 100Base-TX mode, and 2.5 MHz
in 10Base-T mode.
E_RXD<4> U14 Receive Data from PHY.
E_RXD<3> V14
E_RXD<2> U11
E_RXD<1> T11
E_RXD<0> V8
E_RX_DV V2 Receive Data Valid.

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MicroBlaze Ethernet IP Cores

Table 14-1: FPGA Connections to the LAN83C185 Ethernet PHY (Continued)

FPGA Pin
Signal Name Number Function
E_RX_CLK V3 Receive Clock. 25 MHz in 100Base-TX mode, and 2.5 MHz in
10Base-T mode.
E_CRS U13 Carrier Sense
E_COL U6 MII Collision Detect.
E_MDC P9 Management Clock. Serial management clock.
E_MDIO U5 Management Data Input/Output.

MicroBlaze Ethernet IP Cores

The Ethernet PHY is primarily intended for use with MicroBlaze applications. As such, an
Ethernet MAC is part of the EDK Platform Studio’s Base System Builder. Both the full
Ethernet MAC and the Lite version are available for evaluation, as shown in Figure 14-3.
The Ethernet Lite MAC controller core uses fewer FPGA resources and is ideal for
applications that do not require support for interrupts, back-to-back data transfers, and
statistics counters.

UG230_c14_03_022706

Figure 14-3: Ethernet MAC IP Cores for the Spartan-3E Starter Kit Board
The Ethernet MAC core requires design constraints to meet the required performance.
Refer to the OPB Ethernet MAC data sheet (v1.02) for details. The OPB bus clock frequency
must be 65 MHz or higher for 100 Mbps Ethernet operations and 6.5 MHz or faster for
10 Mbps Ethernet operations.

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Chapter 14: 10/100 Ethernet Physical Layer Interface

The hardware evaluation versions of the Ethernet MAC cores operate for approximately
eight hours in silicon before timing out. To order the full version of the core, visit the Xilinx
website at:
http://www.xilinx.com/ipcenter/processor_central/processor_ip/10-100emac/
10-100emac_order_register.htm

UCF Location Constraints

Figure 14-4 provides the UCF constraints for the 10/100 Ethernet PHY interface, including
the I/O pin assignment and the I/O standard used.

NET "E_COL" LOC = "U6" | IOSTANDARD = LVCMOS33 ;

NET "E_CRS" LOC = "U13" | IOSTANDARD = LVCMOS33 ;
NET "E_MDC" LOC = "P9" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "E_MDIO" LOC = "U5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "E_RX_CLK" LOC = "V3" | IOSTANDARD = LVCMOS33 ;
NET "E_RX_DV" LOC = "V2" | IOSTANDARD = LVCMOS33 ;
NET "E_RXD<0>" LOC = "V8" | IOSTANDARD = LVCMOS33 ;
NET "E_RXD<1>" LOC = "T11" | IOSTANDARD = LVCMOS33 ;
NET "E_RXD<2>" LOC = "U11" | IOSTANDARD = LVCMOS33 ;
NET "E_RXD<3>" LOC = "V14" | IOSTANDARD = LVCMOS33 ;
NET "E_RXD<4>" LOC = "U14" | IOSTANDARD = LVCMOS33 ;
NET "E_TX_CLK" LOC = "T7" | IOSTANDARD = LVCMOS33 ;
NET "E_TX_EN" LOC = "P15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "E_TXD<0>" LOC = "R11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "E_TXD<1>" LOC = "T15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "E_TXD<2>" LOC = "R5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "E_TXD<3>" LOC = "T5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "E_TXD<4>" LOC = "R6" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;

Figure 14-4: UCF Location Constraints for 10/100 Ethernet PHY Inputs

Related Resources
• Standard Microsystems SMSC LAN83C185 10/100 Ethernet PHY
http://www.smsc.com/main/catalog/lan83c185.html
• Xilinx OPB Ethernet Media Access Controller (EMAC) (v1.02a)
http://www.xilinx.com/bvdocs/ipcenter/data_sheet/opb_ethernet.pdf
• Xilinx OPB Ethernet Lite Media Access Controller (v1.01a)
The Ethernet Lite MAC controller core uses fewer FPGA resources and is ideal for
applications the do not require support for interrupts, back-to-back data transfers, and
statistics counters.
http://www.xilinx.com/bvdocs/ipcenter/data_sheet/opb_ethernetlite.pdf
• EDK 8.1i Documentation
http://www.xilinx.com/ise/embedded/edk_docs.htm

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Chapter 15

Expansion Connectors
The Spartan-3E Starter Kit board provides a variety of expansion connectors for easy
interface flexibility to other off-board components. The board includes the following I/O
expansion headers (see Figure 15-1):
• A Hirose 100-pin edge connector with 43 associated FPGA user-I/O pins, including
up to 15 differential LVDS I/O pairs and two Input-only pairs
• Three 6-pin Peripheral Module connections
• Landing pads for an Agilent or Tektronix connectorless probe

Jumper JP9, I/O Bank 0 Voltage

Default is 3.3V, set to 2.5V for differential I/O

Hirose 100-pin FX2 Connector, J3

43 I/O connections, high-performance

J1 6-pin Accessory Header

J6 Probe Landing Pads
Connectorless logic analyzer probes

J2 6-pin Accessory Header

J4 6-pin Accessory Header UG230_c12_01_030606

Figure 15-1: Expansion Headers

Hirose 100-pin FX2 Edge Connector (J3)

A 100-pin edge connector is located along the right edge of the board (see Figure 15-1). This
connector is a Hirose FX2-100P-1.27DS header with 1.27 mm pitch. Throughout the
documentation, this connector is called the FX2 connector.
As shown in Figure 15-2, 43 FPGA I/O pins interface to the FX2 connector. All but five of
these pins are true, bidirectional I/O pins capable of driving or receiving signals. Five pins,
FX2_IP<38:35> and FX2_IP<40> are Input-only pins on the FPGA. These pins are
highlighted in light green in Table 15-1 and cannot drive the FX2 connector but can receive
signals.

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Chapter 15: Expansion Connectors

Hirose 100-pin Expansion

Connector (J3)
Spartan-3E FPGA
FX2_IO<34:1>
(See Table) (See Table)
FX2_IP<38:35>
(See Table) (See Table)
FX2_IO<39>
(C3) (A.44)
FX2_IP<40>
(C15) (A.45)
FX2_CLKIN
(E10) (B.46)
FX2_CLKOUT
(D10) (A.47)
FX2_CLKIO
(D9) (B.48)

Bank 0 Supply
(JP9)
2.5V 3.3V

5.0V
GND
UG230_c12_02_022406

Figure 15-2: FPGA Connections to the Hirose 100-pin Edge Connector

Three signals are reserved primarily as clock signals between the board and FX2 connector,
although all three connect to full I/O pins.

Voltage Supplies to the Connector

The Spartan-3E Starter Kit board provides power to the Hirose 100-pin FX connector and
any attached board via two supplies (see Figure 15-2). The 5.0V supply provides a voltage
source for any 5V logic on the attached board or alternately provides power to any voltage
regulators on the attached board.
A separate supply provides the same voltage at that applied to the FPGA’s I/O Bank 0. All
FPGA I/Os that interface to the Hirose connector are in Bank 0. The I/O Bank 0 supply is
3.3V by default. However, the voltage level can be changed to 2.5V using jumper JP9. Some
FPGA I/O standards—especially the differential standards such as RSDS and LVDS—
require a 2.5V output supply voltage.
To support high-speed signals across the connector, a majority of pins on the B-side of the
FX2 connector are tied to GND.

Connector Pinout and FPGA Connections

Table 15-1 shows the pinout for the Hirose 100-pin FX2 connector and the associated FPGA
pin connections. The FX2 connect has two rows of connectors, both with 50 connections
each, shown in the table using light yellow shading.
Table 15-1 also highlights the shared connections to the eight discrete LEDs, the three 6-pin
Accessory Headers (J1, J2, and J4), and the connectorless debugging header (J6).

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Hirose 100-pin FX2 Edge Connector (J3)

Table 15-1: Hirose 100-pin FX2 Connector Pinout and FPGA Connections (J3)
Shared Header Connections FX2 Connector
A B
Signal Name FPGA Pin LED J1 J2 JP4 J6 (top) (bottom) FPGA Pin Signal Name
VCCO_0 1 1 SHIELD
VCCO_0 2 2 GND GND
TMS_B 3 3 TDO_XC2C
JTSEL 4 4 TCK_B
TDO_FX2 5 5 GND GND
FX2_IO1 B4 ‹ ‹ 6 6 GND GND
FX2_IO2 A4 ‹ ‹ 7 7 GND GND
FX2_IO3 D5 ‹ ‹ 8 8 GND GND
FX2_IO4 C5 ‹ ‹ 9 9 GND GND
FX2_IO5 A6 ‹ ‹ 10 10 GND GND
FX2_IO6 B6 ‹ ‹ 11 11 GND GND
FX2_IO7 E7 ‹ ‹ 12 12 GND GND
FX2_IO8 F7 ‹ ‹ 13 13 GND GND
FX2_IO9 D7 ‹ ‹ 14 14 GND GND
FX2_IO10 C7 ‹ ‹ 15 15 GND GND
FX2_IO11 F8 ‹ ‹ 16 16 GND GND
FX2_IO12 E8 ‹ ‹ 17 17 GND GND
FX2_IO13 F9 LD7 ‹ 18 18 GND GND
FX2_IO14 E9 LD6 ‹ 19 19 GND GND
FX2_IO15 D11 LD5 ‹ 20 20 GND GND
FX2_IO16 C11 LD4 ‹ 21 21 GND GND
FX2_IO17 F11 LD3 ‹ 22 22 GND GND
FX2_IO18 E11 LD2 ‹ 23 23 GND GND
FX2_IO19 E12 LD1 24 24 GND GND
FX2_IO20 F12 LD0 25 25 GND GND
FX2_IO21 A13 26 26 GND GND
FX2_IO22 B13 27 27 GND GND
FX2_IO23 A14 28 28 GND GND
FX2_IO24 B14 29 29 GND GND
FX2_IO25 C14 30 30 GND GND
FX2_IO26 D14 31 31 GND GND
FX2_IO27 A16 32 32 GND GND
FX2_IO28 B16 33 33 GND GND
FX2_IO29 E13 34 34 GND GND

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Chapter 15: Expansion Connectors

Table 15-1: Hirose 100-pin FX2 Connector Pinout and FPGA Connections (J3) (Continued)
Shared Header Connections FX2 Connector
A B
Signal Name FPGA Pin LED J1 J2 JP4 J6 (top) (bottom) FPGA Pin Signal Name
FX2_IO30 C4 35 35 GND GND
FX2_IO31 B11 36 36 GND GND
FX2_IO32 A11 37 37 GND GND
FX2_IO33 A8 38 38 GND GND
FX2_IO34 G9 39 39 GND GND
FX2_IP35 D12 40 40 GND GND
FX2_IP36 C12 41 41 GND GND
FX2_IP37 A15 42 42 GND GND
FX2_IP38 B15 43 43 GND GND
FX2_IO39 C3 44 44 GND GND
FX2_IP40 C15 45 45 GND GND
GND GND 46 46 E10 FX2_CLKIN
FX2_CLKOUT D10 47 47 GND GND
GND GND 48 48 D9 FX2_CLKIO
5.0V 49 49 5.0V
5.0V 50 50 SHIELD

Compatible Board
The following board is compatible with the FX2 connector on the Spartan-3E Starter Kit
board:
• VDEC1 Video Decoder Board from Digilent, Inc.
http://www.digilentinc.com/Products/Detail.cfm?Prod=VDEC1

Mating Receptacle Connectors

The Spartan-3E Starter Kit board uses a Hirose FX2-100P-1.27DS header connector. The
header mates with any compatible 100-pin receptacle connector, including board-mounted
and non-locking cable connectors.

Differential I/O
The Hirose FX2 connector, header J3, supports up to 15 differential I/O pairs and two
input-only pairs using either the LVDS or RSDS I/O standards, as listed in Table 15-2. All
I/O pairs support differential input termination (DIFF_TERM) as described in the
Spartan-3E data sheet. Select pairs have optional landing pads for external termination
resistors.
These signals are not routed with matched differential impedance, as would be required
for ultimate performance. However, all traces have similar lengths to minimize skew.

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Hirose 100-pin FX2 Edge Connector (J3)

Table 15-2: Differential I/O Pairs

External
Resistor
Differential Pair Signal Name FPGA Pins FPGA Pin Name Direction DIFF_TERM Designator
FX2_IO1 B4 IO_L24N_0 I/O Yes
1
FX2_IO2 A4 IO_L24P_0 I/O Yes
FX2_IO3 D5 IO_L23N_0 I/O Yes
2
FX2_IO4 C5 IO_L23P_0 I/O Yes
FX2_IO5 A6 IO_L20N_0 I/O Yes
3
FX2_IO6 B6 IO_L20P_0 I/O Yes
FX2_IO7 E7 IO_L19N_0 I/O Yes
4
FX2_IO8 F7 IO_L19P_0 I/O Yes
FX2_IO9 D7 IO_L18N_0 I/O Yes
5
FX2_IO10 C7 IO_L18P_0 I/O Yes
FX2_IO11 F8 IO_L17N_0 I/O Yes
6
FX2_IO12 E8 IO_L17P_0 I/O Yes
FX2_IO13 F9 IP_L15N_0 I/O Yes
7
FX2_IO14 E9 IP_L15P_0 I/O Yes
FX2_IO15 D11 IP_L09N_0 I/O Yes
8
FX2_IO16 C11 IP_L09P_0 I/O Yes
FX2_IO17 F11 IO_L08N_0 I/O Yes
9 R202
FX2_IO18 E11 IO_L08P_0 I/O Yes
FX2_IO19 E12 IO_L06N_0 I/O Yes
10 R203
FX2_IO20 F12 IO_L06P_0 I/O Yes
FX2_IO21 A13 IO_L05P_0 I/O Yes
11 R204
FX2_IO22 B13 IO_L05N_0 I/O Yes
FX2_IO23 A14 IO_L04N_0 I/O Yes
12 R205
FX2_IO24 B14 IO_L04P_0 I/O Yes
FX2_IO25 C14 IO_L03N_0 I/O Yes
13 R206
FX2_IO26 D14 IO_L03P_0 I/O Yes
FX2_IO27 A16 IO_L01N_0 I/O Yes
14 R207
FX2_IO28 B16 IO_L01P_0 I/O Yes
FX2_IP35 D12 IP_L07N_0 Input
15 R208
FX2_IP36 C12 IP_L07P_0 Input
FX2_IP37 A15 IP_L02N_0 Input
16 R209
FX2_IP38 B15 IP_L02P_0 Input
IO_L11N_0/
FX2_CLKIN E10 I/O Yes
GCLK5
17 R210
IO_L11P_0/
FX2_CLKOUT D10 I/O Yes
GCLK4

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Chapter 15: Expansion Connectors

Using Differential Inputs

LVDS and RSDS differential inputs require input termination. Two options are available.
The first option is to use external termination resistors, as shown in Figure 15-3a. The
board provides landing pads for external 100Ω termination resistors. The resistors are not
loaded on the board as shipped. The resistor reference designators are labeled on the
silkscreen, as listed in Table 15-2. The landing pads are located on both the top- and
bottom-side of the board, between the FPGA and the FX2 connector. The resistors are not
loaded on the board as shipped. External termination is always required when using
differential input pairs 15 and 16.
The second option, shown in Figure 15-3b, is a Spartan-3E feature called on-chip
differential termination, which uses the DIFF_TERM attribute available on differential I/O
signals. Each differential I/O pin includes a circuit that behaves like an internal
termination resistor of approximately 120Ω . On-chip differential termination is only
available on I/O pairs, not on Input-only pairs like pairs 15 and 16 in Table 15-2.

Pads for 100Ω Differential termination

surface-mount resistor (~120Ω)
FPGA FPGA
PAD PAD
LxxN_0 LxxN_0
Signal Signal
LxxP_0 LxxP_0

a) External 100Ω termination resistor b) On-chip differential termination

UG230_c12_03_022406

Figure 15-3: Differential Input Termination Options

Figure 15-4 and Figure 15-5 show the locations of the differential input termination resistor
landing pads on the top and bottom side of the board. Table 15-2 indicates which resistor is
associated with a specific differential pair.

UG230_c12_04_022406

Figure 15-4: Location of Termination Resistor Pads on Top Side of Board

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Hirose 100-pin FX2 Edge Connector (J3)

UG230_c12_05_022406

Figure 15-5: Location of Termination Resistor Pads on Bottom Side of Board

Using Differential Outputs

Differential input signals do not require any special voltage. LVDS and RSDS differential
outputs signals, on the other hand, require a 2.5V supply on I/O Bank 0. The board
provides the option to power I/O Bank 0 with either 3.3V or 2.5V. Figure 15-1, page 113
highlights the location of jumper JP9.
If using differential outputs on the FX2 connector, set jumper JP9 to 2.5V. If the jumper is
not set correctly, the outputs switch correctly but the signal levels are out of specification.

FPGA
PAD
LxxN_0
Signal
LxxP_0

UG230_c12_06_022406

Figure 15-6: Differential Outputs

UCF Location Constraints

Figure 15-7 provides the UCF constraints for the FX2 connector, including the I/O pin
assignment and the I/O standard used, assuming that all connections use single-ended
I/O standards. These header connections are shared with the 6-pin accessory headers, as
shown in Figure 15-11, page 122.

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Chapter 15: Expansion Connectors

# ==== FX2 Connector (FX2) ====

NET "FX2_CLKIN" LOC = "E10" | IOSTANDARD = LVCMOS33 ;
NET "FX2_CLKIO" LOC = "D9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_CLKOUT" LOC = "D10" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
# These four connections are shared with the J1 6-pin accessory header
NET "FX2_IO<1>" LOC = "B4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<2>" LOC = "A4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<3>" LOC = "D5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<4>" LOC = "C5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
# These four connections are shared with the J2 6-pin accessory header
NET "FX2_IO<5>" LOC = "A6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<6>" LOC = "B6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<7>" LOC = "E7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<8>" LOC = "F7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
# These four connections are shared with the J4 6-pin accessory header
NET "FX2_IO<9>" LOC = "D7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<10>" LOC = "C7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<11>" LOC = "F8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<12>" LOC = "E8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
# The discrete LEDs are shared with the following 8 FX2 connections
#NET "FX2_IO<13>" LOC = "F9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<14>" LOC = "E9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<15>" LOC = "D11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<16>" LOC = "C11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<17>" LOC = "F11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<18>" LOC = "E11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<19>" LOC = "E12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<20>" LOC = "F12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<21>" LOC = "A13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<22>" LOC = "B13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<23>" LOC = "A14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<24>" LOC = "B14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<25>" LOC = "C14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<26>" LOC = "D14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<27>" LOC = "A16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<28>" LOC = "B16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<29>" LOC = "E13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<30>" LOC = "C4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<31>" LOC = "B11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<32>" LOC = "A11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<33>" LOC = "A8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<34>" LOC = "G9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IP<35>" LOC = "D12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IP<36>" LOC = "C12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IP<37>" LOC = "A15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IP<38>" LOC = "B15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<39>" LOC = "C3" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IP<40>" LOC = "C15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

Figure 15-7: UCF Location Constraints for Accessory Headers

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Six-Pin Accessory Headers

Six-Pin Accessory Headers

The 6-pin accessory headers provide easy I/O interface expansion using the various
Digilent Peripheral Modules (see “Related Resources,” page 124). The location of the 6-pin
headers is provided in Figure 15-1, page 113.

Header J1
The J1 header, shown in Figure 15-8, is the top-most 6-pin connector along the right edge of
the board. It uses a female 6-pin 90° socket. Four FPGA pins connect to the J1 header,
FX2_IO<4:1>. These four signals are also shared with the Hirose FX2 connector. The board
supplies 3.3V to the accessory board mounted in the J1 socket on the bottom pin.

Spartan-3E FPGA J1
FX2_IO1
(B4)
FX2_IO2
(A4)
FX2_IO3
(D5)
FX2_IO4
(C5)

GND
3.3V
UG230_c12_07_022406

Figure 15-8: FPGA Connections to the J1 Accessory Header

Header J2
The J2 header, shown in Figure 15-9, is the bottom-most 6-pin connector along the right
edge of the board. It uses a female 6-pin 90° socket. Four FPGA pins connect to the J2
header, FX2_IO<8:5>. These four signals are also shared with the Hirose FX2 connector.
The board supplies 3.3V to the accessory board mounted in the J2 socket on the bottom pin.

Spartan-3E FPGA J2
FX2_IO5
(A6)
FX2_IO6
(B6)
FX2_IO7
(E7)
(F7) FX2_IO8

GND
3.3V
UG230_c12_08_022406

Figure 15-9: FPGA Connections to the J2 Accessory Header

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Chapter 15: Expansion Connectors

Header J4
The J4 header, shown in Figure 15-10, is located immediately to the left of the J1 header. It
uses a 6-pin header consisting of 0.1-inch centered stake pins. Four FPGA pins connect to
the J4 header, FX2_IO<12:9>. These four signals are also shared with the Hirose FX2
connector. The board supplies 3.3V to the accessory board mounted in the J4 socket on the
bottom pin.

Spartan-3E FPGA J4
FX2_IO9
(D7)
FX2_IO10
(C7)
(F8) FX2_IO11

(E8) FX2_IO12

GND
3.3V
UG230_c12_09_022406

Figure 15-10: FPGA Connections to the J4 Accessory Header

UCF Location Constraints

Figure 15-11 provides the User Constraint File (UCF) constraints for accessory headers,
including the I/O pin assignment and the I/O standard used. These header connections
are shared with the FX2 connector, as shown in Figure 15-7, page 120.

# ==== 6-pin header J1 ====

# These four connections are shared with the FX2 connector
#NET "J1<0>" LOC = "B4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J1<1>" LOC = "A4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J1<2>" LOC = "D5" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J1<3>" LOC = "C5" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;

# ==== 6-pin header J2 ====

# These four connections are shared with the FX2 connector
#NET "J2<0>" LOC = "A6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J2<1>" LOC = "B6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J2<2>" LOC = "E7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J2<3>" LOC = "F7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;

# ==== 6-pin header J4 ====

# These four connections are shared with the FX2 connector
#NET "J4<0>" LOC = "D7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J4<1>" LOC = "C7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J4<2>" LOC = "F8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J4<3>" LOC = "E8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;

Figure 15-11: UCF Location Constraints for Accessory Headers

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Connectorless Debugging Port Landing Pads (J6)

Connectorless Debugging Port Landing Pads (J6)

Landing pads for a connectorless debugging port are provided as header J6, shown in
Figure 15-1, page 113. There is no physical connector on the board. Instead a connectorless
probe, such as those available from Agilent, provides an interface to a logic analyzer. This
debugging port is intended primarily for the Xilinx ChipScope Pro software with the
Agilent’s FPGA Dynamic Probe. It can, however, be used with either the Agilent or
Tektronix probes, without the ChipScope software, using FPGA Editor’s probe command.
Refer to “Related Resources,” page 124 for more information on the ChipScope Pro tool,
probes, and connectors.
Table 15-3 provides the connector pinout. Only 18 FPGA pins attach to the connector; the
remaining connector pads are unconnected. All 18 FPGA pins are shared with the FX2
connector (J3) and the 6-pin accessory port connectors (J1, J2, and J4). See Table 15-1,
page 115 for more information on how these pins are shared.

Table 15-3: Connectorless Debugging Port Landing Pads (J6)

Connectorless
Signal Name FPGA Pin Landing Pads FPGA Pin Signal Name
FX2_IO1 B4 A1 B1 GND GND
FX2_IO2 A4 A2 B2 D5 FX2_IO3
GND GND A3 B3 C5 FX2_IO4
FX2_IO5 A6 A4 B4 GND GND
FX2_IO6 B6 A5 B5 E7 FX2_IO7
GND GND A6 B6 F7 FX2_IO8
FX2_IO9 D7 A7 B7 GND GND
FX2_IO10 C7 A8 B8 F8 FX2_IO11
GND GND A9 B9 E8 FX2_IO12
FX2_IO13 F9 A10 B10 GND GND
FX2_IO14 E9 A11 B11 D11 FX2_IO15
GND GND A12 B12 C11 FX2_IO16
FX2_IO17 F11 A13 B13 GND GND
FX2_IO18 E11 A14 B14
A15 B15
A16 B16
A17 B17
A18 B18
A19 B19
A20 B20
A21 B21
A22 B22
A23 B23
A24 B24
A25 B25
A26 B26
A27 B27

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Chapter 15: Expansion Connectors

Related Resources
• Hirose connectors
http://www.hirose-connectors.com/
• FX2 Series Connector Data Sheet
http://www.hirose.co.jp/cataloge_hp/e57220088.pdf
• Digilent, Inc. Peripheral Modules
http://www.digilentinc.com/Products/Catalog.cfm?Nav1=Products&Nav2=Peripheral&Cat=Peripheral
• Xilinx ChipScope Pro Tool
http://www.xilinx.com/ise/optional_prod/cspro.htm
• Agilent B4655A FPGA Dynamic Probe for Logic Analyzer
http://www.home.agilent.com/USeng/nav/-536898189.536883660/pd.html?cmpid=92641
• Agilent 5404A/6A Pro Series Soft Touch Connector
http://www.home.agilent.com/cgi-bin/pub/agilent/Product/cp_Product.jsp?NAV_ID=-536898227.0.00

• Tektronix P69xx Probe Module s with D-Max Technology

http://www.tek.com/products/accessories/logic_analyzers/p6800_p6900.html

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Chapter 16

XC2C64A CoolRunner-II CPLD

The Spartan-3E Starter Kit board includes a Xilinx XC2C64A CoolRunner-II CPLD. The
CPLD is user programmable and available for customer applications. Portions of the
CPLD are reserved to coordinate behavior between the various FPGA configuration
memories, namely the Xilinx Platform Flash PROM and the Intel StrataFlash PROM.
Consequently, the CPLD must provide the following functions in addition to the user
application.
• When the FPGA is in the Master Serial configuration mode (FPGA_M<2:0>=000),
generate an active-Low enable signal for the XCF04S Platform Flash PROM. The
Platform Flash PROM is disabled in all other configuration modes. The CPLD helps
reduce the number of jumpers on the board and simplifies the interaction of all the
possible FPGA configuration memory sources.
• When the FPGA is actively in the BPI-Up configuration mode (FPGA_M<2:0>=010,
DONE=0), set the upper five StrataFlash PROM address lines, A[24:20], to 00000
binary. When the FPGA is actively in the BPI-Down configuration mode
(FPGA_M<2:0>=011, DONE=0), set the upper five StrataFlash PROM address lines,
A[24:20], to 11111 binary. Set the upper five address lines to ZZZZZ for all non-BPI
configuration modes or whenever the FPGA’s DONE pin is High. This behavior is
identifical to the way the FPGA’s upper address lines function during BPI mode. So
why add a CPLD to mimic this behavior? A future reference design demonstrates
unique configuration capabilities. In a typical BPI-mode application, the CPLD is not
required.
Other than the required CPLD functionality, there are between 13 to 21 user-I/O pins and
58 remaining macrocells available to the user application.
Jumper JP10 (WDT_EN) defines the state on the CPLD’s XC_WDT_EN signal. By default,
this jumper is empty and the signal is pulled to a logic High.
The XC_PROG_B output from the CPLD, if used, must be configured as an open-drain out
(i.e., either actively drives Low or floats to Hi-Z, never drives High). This signal connects
directly to the FPGA’s PROG_B programming pin.
The most-siginficant StrataFlash PROM address bit, SF_A<24>, is the same as the FX2
connector signal called FX2_IO<32>. The 16 Mbyte StrataFlash PROM only physically uses
the lower 24 bits, SF_A<23:0>. The extra address bit, SF_A<24>, is provided for upward
density migration for the StrataFlash PROM.

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Chapter 16: XC2C64A CoolRunner-II CPLD

3.3V
JP10 XC2C64A VQ44
WDT_EN CoolRunner-II CPLD
XC_WDT_EN
(P16)

Spartan-3E FPGA
XC_CMD<1>
(N18) (P30)
XC_CMD<0>
(P18) (P29)
Required for Master Serial Mode
XC_D<2> Enable Platform Flash PROM when
(F17) (P36)
M[2:0]=000
XC_D<1>
(F18) (P34) XCF04S
XC_D<0> Platform Flash PROM
(G16) (P33)
FPGA_M2
(T10) (P8)
FPGA_M1 XC_PF_CE
(V11) (P6) (P2) CE
FPGA_M0
(M10) (P5)
XC_CPLD_EN
(D10) (P42)
XC_TRIG
(R17) (P41)
XC_DONE
DONE (P40)
XC_PROG_B
PROG_B (P39)
XC_GCK0
(H16) (P43)
GCLK10
(C9) (P1)
During Configuration:
SPI_SCK BPI Up: A[24:20]=00000
(U16) (FX2_IO<32>)
(P44)
BPI Down: A[24:20]=11111
SF_A<24> After Configuration or Other Modes:
(A11) (P23)
Upper Ad dress
Control During

A[24:20]=ZZZZ
Con figuration

SF_A<23>
(N11) (P22)
SF_A<22>
(V12) (P21)
Intel StrataFlash
SF_A<21>
(V13) (P20)
SF_A<20>
(T12) (P19)

A[23:20] A[24:20]
SF_A<19:0>
A[19:0] A[19:0]

A[23:20] Unconnected UG230_c16_01_030906

Figure 16-1: XC2C64A CoolRunner-II CPLD Controls Master Serial and BPI Configuration Modes

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UCF Location Constraints

UCF Location Constraints

There are two sets of constraints listed below–one for the Spartan-3E FPGA and one for the
XC2C64A CoolRunner-II CPLD.

FPGA Connections to CPLD

Figure 16-2 provides the UCF constraints for the FPGA connections to the CPLD ,
including the I/O pin assignment and the I/O standard used.

NET "XC_CMD<1>" LOC = "N18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET "XC_CMD<0>" LOC = "P18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "XC_D<2>" LOC = "F17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "XC_D<1>" LOC = "F18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "XC_D<0>" LOC = "G16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "FPGA_M2" LOC = "T10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "FPGA_M1" LOC = "V11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "FPGA_M0" LOC = "M10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "XC_CPLD_EN" LOC = "B10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "XC_TRIG" LOC = "R17" | IOSTANDARD = LVCMOS33 ;
NET "XC_GCK0" LOC = "H16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "GCLK10" LOC = "C9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SPI_SCK" LOC = "U16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
# SF_A<24> is the same as FX2_IO<32>
NET "SF_A<24>" LOC = "A11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<23>" LOC = "N11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<22>" LOC = "V12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<21>" LOC = "V13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<20>" LOC = "T12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

Figure 16-2: UCF Location Constraints for FPGA Connections to CPLD

CPLD
Figure 16-3 provides the UCF constraints for the CPLD , including the I/O pin assignment
and the I/O standard used.

NET "XC_WDT_EN" LOC = "P16" | IOSTANDARD = LVCMOS33 ;

NET "XC_CMD<1>" LOC = "P30" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
NET "XC_CMD<0>" LOC = "P29" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
NET "XC_D<2>" LOC = "P36" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
NET "XC_D<1>" LOC = "P34" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
NET "XC_D<0>" LOC = "P33" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
NET "FPGA_M2" LOC = "P8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
NET "FPGA_M1" LOC = "P6" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
NET "FPGA_M0" LOC = "P5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
NET "XC_CPLD_EN" LOC = "P42" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
NET "XC_TRIG" LOC = "P41" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
NET "XC_DONE" LOC = "P40" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
NET "XC_PROG_B" LOC = "P39" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
NET "XC_GCK0" LOC = "P43" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
NET "GCLK10" LOC = "P1" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
NET "SPI_SCK" LOC = "P44" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
# SF_A<24> is the same as FX2_IO<32>
NET "SF_A<24>" LOC = "P23" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
NET "SF_A<23>" LOC = "P22" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
NET "SF_A<22>" LOC = "P21" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
NET "SF_A<21>" LOC = "P20" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
NET "SF_A<20>" LOC = "P19" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;

Figure 16-3: UCF Location Constraints for the XC2C64A CPLD

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Chapter 16: XC2C64A CoolRunner-II CPLD

Related Resources
• CoolRunner-II CPLD Family Data Sheet
http://direct.xilinx.com/bvdocs/publications/ds090.pdf
• XC2C64A CoolRunner-II CPLD Data Sheet
http://direct.xilinx.com/bvdocs/publications/ds311.pdf
• Default XC2C64A CPLD Design for Spartan-3E Starter Kit Board
http://www.xilinx.com/s3estarter

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Chapter 17

DS2432 1-Wire SHA-1 EEPROM

The Spartan-3E Starter Kit board includes a Maxim DS2432 serial EEPROM with an
integrated SHA-1 engine. As shown in Figure 17-1, the DS2432 EEPROM uses the Maxim
1-Wire interface, which as the name implies, cleverly uses a single wire for power and
serial communication.
The DS2432 EEPROM offers one of many possible means to copy-protect the FPGA
configuration bitstream, making cloning difficult. Xilinx application note XAPP780, listed
under “Related Resources” provides one possible implementation method.

3.3V
Maxim DS2432
Spartan-3E FPGA SHA-1 EEPROM
(U4) DS_WIRE

GND

UG230_c17_01_030906

Figure 17-1: SHA-1 EEPROM

UCF Location Constraints

Figure 17-2 provides the UCF constraints for the FPGA connections to the DS2432 SHA-1
EEPROM, including the I/O pin assignment and the I/O standard used.

NET "DS_WIRE" LOC = "U4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;

Figure 17-2: UCF Location Constraints for DS2432 SHA-1 EEPROM

Related Resources
• Maxim DS2432 1-Wire EEPROM with SHA-1 Engine
http://www.maxim-ic.com/quick_view2.cfm/qv_pk/2914
• XAPP780: FPGA IFF Copy Protection Using Dallas Semiconductor/Maxim DS2432 Secure
EEPROMs
http://www.xilinx.com/bvdocs/appnotes/xapp780.pdf

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Chapter 17: DS2432 1-Wire SHA-1 EEPROM

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Appendix A

Schematics
This appendix provides the following circuit board schematics:
• “FX2 Expansion Header, 6-pin Headers, and Connectorless Probe Header”
• “RS-232 Ports, VGA Port, and PS/2 Port”
• “Ethernet PHY, Magnetics, and RJ-11 Connector”
• “Voltage Regulators”
• “FPGA Configurations Settings, Platform Flash PROM, SPI Serial Flash, JTAG
Connections”
• “FPGA I/O Banks 0 and 1, Oscillators”
• “FPGA I/O Banks 2 and 3”
• “Power Supply Decoupling”
• “XC2C64A CoolRunner-II CPLD”
• “Linear Technology ADC and DAC ”
• “Intel StrataFlash Parallel NOR Flash Memory and Micron DDR SDRAM ”
• “Buttons, Switches, Rotary Encoder, and Character LCD ”
• “DDR SDRAM Series Termination and FX2 Connector Differential Termination”

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Appendix A: Schematics

FX2 Expansion Header, 6-pin Headers, and Connectorless Probe

Header
Headers J1, J2, and J4 are six-pin connectors compatible with the Digilent Accessory board
format.
Headers J3A and J3B are the connections to the FX2 expansion connector located along the
right edge of the board.
Header J5 provides the four analog outputs from the Digital-to-Analog Converter (DAC).
Header J6 is the landing pad for an Agilent or Tektronix connectorless probe.
Header J7 provides the two analog inputs to the programmable pre-amplifier (AMP) and
two-channel Analog-to-Digital Converter (ADC).
The diagram in the lower left corner shows the JTAG chain.
See Chapter 15, “Expansion Connectors,” for additional information.

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FX2 Expansion Header, 6-pin Headers, and Connectorless Probe Header
UG230_Aa_01_021806
Figure A-1: Schematic Sheet 1
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Appendix A: Schematics

RS-232 Ports, VGA Port, and PS/2 Port

IC2 is the Maxim LVTTL to RS-232 level converter. One of the serial channels connects to a
female DB9 DCE connector (J9) and the other connects to a male DB9 DTE connector (J10).
See Chapter 7, “RS-232 Serial Ports,” for additional information.
Connector J14 is a PS/2-style mouse/keyboard connector, powered from 5 volts. See
Chapter 8, “PS/2 Mouse/Keyboard Port,” for additional information.
Connector J15 is a VGA connector, suitable for driving most VGA-compatible monitors
and flat-screen displays. See Chapter 6, “VGA Display Port,” for additional information.
Header J12 provides programming support for the SPI serial Flash. Jumper J11 controls
how the SPI serial Flash is enabled in the application. See Chapter 12, “SPI Serial Flash,”
for additional information.
The SMA connector allows an external clock source to drive one of the FPGA’s global clock
inputs. Alternatively, the FPGA can provide a high-performance clock to another board via
the SMA connector. See Chapter 3, “Clock Sources,” for additional information.

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RS-232 Ports, VGA Port, and PS/2 Port
UG230_Aa_02_021806
Figure A-2: Schematic Sheet 2
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Appendix A: Schematics

Ethernet PHY, Magnetics, and RJ-11 Connector

IC6 is an SMSC 10/100 Ethernet PHY, with its associated 25 MHz oscillator. The PHY
requires an Ethernet MAC implemented within the FPGA.
J19 is the RJ-11 Ethernet connector associated with the 10/100 Ethernet PHY.
See Chapter 14, “10/100 Ethernet Physical Layer Interface,” for additional information.

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Ethernet PHY, Magnetics, and RJ-11 Connector
UG230_Aa_03_021806
Figure A-3: Schematic Sheet 4
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Appendix A: Schematics

Voltage Regulators
IC7 is a Texas Instruments TPS75003 triple-output regulator. The regulator provides 1.2V
to the FPGA’s VCCINT supply input, 2.5V to the FPGA’s VCCAUX supply input, and 3.3V
to other components on the board and to the FPGA’s VCCO supply inputs on I/O Banks 0,
1, and 2.
Jumpers JP6 and JP7 provide a means to measure current across the FPGA’s VCCAUX and
VCCINT supplies respectively.
IC8 is a Linear Technology LT3412 regulator, providing 2.5V to the on-board DDR SDRAM.
Resistors R65 and R67 create a voltage divider to create the termination voltage required
for the DDR SDRAM interface.
IC9 is a 1.8V supply to the Embedded USB download/debug circuit and to the CPLD’s
VCCINT supply input.

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Voltage Regulators
UG230_Aa_04_021806
Figure A-4: Schematic Sheet 5
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Appendix A: Schematics

FPGA Configurations Settings, Platform Flash PROM, SPI Serial

Flash, JTAG Connections
IC10MISC represents the various FPGA configuration connections.
IC11 is a 4 Mbit XCF04S Platform Flash PROM. Landing pads for a second XCF04S PROM
is shown as IC13, although the second PROM is not mounted on the XC3S500E version of
the board. Resistor R100 jumpers over the JTAG chain, bypassing the second XCF04S
PROM.
Jumper header J30 selects the FPGA’s configuration mode. See Table 4-1, page 27 for
additional information.
Header J28 is an alternate JTAG header.
IC12 is a Maxim/Dallas Semiconductor DS2432 SHA-1 EEPROM. See Chapter 17, “DS2432
1-Wire SHA-1 EEPROM,” for more information.
IC14 and IC15 are alternate landing pads for the STMicro SPI serial Flash. IC14 accepts the
16-pin SOIC package option, while IC15 accepts either the 8-pin SOIC or MLP package
option. See Figure 12-19, page 101 for additional informaton.

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FPGA Configurations Settings, Platform Flash PROM, SPI Serial Flash, JTAG Connections
UG230_Aa_05_021806
Figure A-5: Schematic Sheet 6
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Appendix A: Schematics

FPGA I/O Banks 0 and 1, Oscillators

IC10B0 represents the connections to I/O Bank 0 on the FPGA. The VCCO input to Bank 0
is 3.3V by default, but can be set to 2.5V using jumper JP9.
IC10B1 represents the connections to I/O Bank 1 on the FPGA.
IC17 is the 50 MHz clock oscillator. Chapter 3, “Clock Sources,” for additional information.
IC16 is an 8-pin DIP socket to insert an alternate clock oscillator with a different frequency.

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FPGA I/O Banks 0 and 1, Oscillators
UG230_Aa_06_021806
Figure A-6: Schematic Sheet 7
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Appendix A: Schematics

FPGA I/O Banks 2 and 3

IC10B2 represents the connections to I/O Bank 2 on the FPGA. Some of the I/O Bank 2
connections are used for FPGA configuration and are listed as IC10MISC.
IC10B3 represents the connections to I/O Bank 3 on the FPGA. Bank 3 is dedicated to the
DDR SDRAM interface and is consequently powered by 2.5V. See Chapter 13, “DDR
SDRAM,” for additional information.

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FPGA I/O Banks 2 and 3
UG230_Aa_07_021806
Figure A-7: Schematic Sheet 8
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Appendix A: Schematics

Power Supply Decoupling

IC10PWR represents the various voltage supply inputs to the FPGA and shows the power
decoupling network.
Jumper JP9 defines the voltage applied to VCCO on I/O Bank 0. The default setting is 3.3V.
See “Voltage Control,” page 22 and “Voltage Supplies to the Connector,” page 114 for
additional details.

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Power Supply Decoupling
UG230_Aa_08_021806
Figure A-8: Schematic Sheet 9
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Appendix A: Schematics

XC2C64A CoolRunner-II CPLD

IC18 is a Xilinx XC2C64A CoolRunner-II CPLD. The CPLD primarily provides additional
flexibility when configuring the FPGA from parallel NOR Flash and during MultiBoot
configurations.
When the CPLD is loaded with the appropriate design, JP10 enables a watchdog timer in
the CPLD used during fail-safe MultiBoot configurations.
See Chapter 16, “XC2C64A CoolRunner-II CPLD,” for more information.

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XC2C64A CoolRunner-II CPLD
UG230_Aa_09_021806
Figure A-9: Schematic Sheet 10
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Appendix A: Schematics

Linear Technology ADC and DAC

IC19 is a Linear Technology LTC1407A-1 two-channel ADC. IC20 is a Linear Technology
LTC6912 programmable pre-amplifier (AMP) to condition the analog inputs to the ADC.
See Chapter 10, “Analog Capture Circuit,” for additional information.
IC21 is a Linear Technology LTC2624 four-channel DAC. See Chapter 9, “Digital to Analog
Converter (DAC),” for additional information.

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Linear Technology ADC and DAC
UG230_Aa_10_021806
Figure A-10: Schematic Sheet 11
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Appendix A: Schematics

Intel StrataFlash Parallel NOR Flash Memory and Micron DDR

SDRAM
IC22 is a 128 Mbit (16 Mbyte) Intel StrataFlash parallel NOR Flash PROM. See Chapter 11,
“Intel StrataFlash Parallel NOR Flash PROM,” for additional information.
IC23 is a 512 Mbit (64 Mbyte) Micron DDR SDRAM. See Chapter 13, “DDR SDRAM,” for
additional information.

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Intel StrataFlash Parallel NOR Flash Memory and Micron DDR SDRAM
UG230_Aa_11_021806
Figure A-11: Schematic Sheet 12
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Appendix A: Schematics

Buttons, Switches, Rotary Encoder, and Character LCD

SW0, SW1, SW2, and SW3 are slide switches.
Push-button switches W, E, S, and N are located around the ROT1 push-button
switch/rotary encoder.
LD0 through LD7 are discrete LEDs.
See Chapter 2, “Switches, Buttons, and Knob,” for additional information.
DISP1 is a 2x16 character LCD screen. See Chapter 5, “Character LCD Screen,” for
additional information.

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Buttons, Switches, Rotary Encoder, and Character LCD
UG230_Aa_12_021806
Figure A-12: Schematic Sheet 13
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Appendix A: Schematics

DDR SDRAM Series Termination and FX2 Connector Differential

Termination
Resistors R160 through R201 represent the series termination resistors for the DDR
SDRAM. See Chapter 13, “DDR SDRAM,” for additional information.
Resistors R202 through R210 are not loaded on the board. These landing pads provide
optional connections for 100Ω differential termination resistors. See “Using Differential
Inputs,” page 118 for additional information.

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DDR SDRAM Series Termination and FX2 Connector Differential Termination
UG230_Aa_13_021806
Figure A-13: Schematic Sheet 14
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Appendix A: Schematics

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Appendix B

Example User Constraints File (UCF)

#####################################################
### SPARTAN-3E STARTER KIT BOARD CONSTRAINTS FILE
#####################################################

# ==== Analog-to-Digital Converter (ADC) ====

# some connections shared with SPI Flash, DAC, ADC, and AMP
NET "AD_CONV" LOC = "P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;

# ==== Programmable Gain Amplifier (AMP) ====

# some connections shared with SPI Flash, DAC, ADC, and AMP
NET "AMP_CS" LOC = "N7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "AMP_DOUT" LOC = "E18" | IOSTANDARD = LVCMOS33 ;
NET "AMP_SHDN" LOC = "P7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;

# ==== Pushbuttons (BTN) ====

NET "BTN_EAST" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN ;
NET "BTN_NORTH" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN ;
NET "BTN_SOUTH" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ;
NET "BTN_WEST" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN ;

# ==== Clock inputs (CLK) ====

NET "CLK_50MHZ" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
# Define clock period for 50 MHz oscillator (40%/60% duty-cycle)
NET "CLK_50MHZ" PERIOD = 20.0ns HIGH 40%;
NET "CLK_AUX" LOC = "B8" | IOSTANDARD = LVCMOS33 ;
NET "CLK_SMA" LOC = "A10" | IOSTANDARD = LVCMOS33 ;

# ==== Digital-to-Analog Converter (DAC) ====

# some connections shared with SPI Flash, DAC, ADC, and AMP
NET "DAC_CLR" LOC = "P8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "DAC_CS" LOC = "N8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;

# ==== 1-Wire Secure EEPROM (DS)

NET "DS_WIRE" LOC = "U4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

# ==== Ethernet PHY (E) ====

NET "E_COL" LOC = "U6" | IOSTANDARD = LVCMOS33 ;
NET "E_CRS" LOC = "U13" | IOSTANDARD = LVCMOS33 ;
NET "E_MDC" LOC = "P9" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;

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Appendix B: Example User Constraints File (UCF)

NET "E_MDIO" LOC = "U5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;

NET "E_RX_CLK" LOC = "V3" | IOSTANDARD = LVCMOS33 ;
NET "E_RX_DV" LOC = "V2" | IOSTANDARD = LVCMOS33 ;
NET "E_RXD<0>" LOC = "V8" | IOSTANDARD = LVCMOS33 ;
NET "E_RXD<1>" LOC = "T11" | IOSTANDARD = LVCMOS33 ;
NET "E_RXD<2>" LOC = "U11" | IOSTANDARD = LVCMOS33 ;
NET "E_RXD<3>" LOC = "V14" | IOSTANDARD = LVCMOS33 ;
NET "E_RXD<4>" LOC = "U14" | IOSTANDARD = LVCMOS33 ;
NET "E_TX_CLK" LOC = "T7" | IOSTANDARD = LVCMOS33 ;
NET "E_TX_EN" LOC = "P15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "E_TXD<0>" LOC = "R11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "E_TXD<1>" LOC = "T15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "E_TXD<2>" LOC = "R5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "E_TXD<3>" LOC = "T5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "E_TXD<4>" LOC = "R6" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;

# ==== FPGA Configuration Mode, INIT_B Pins (FPGA) ====

NET "FPGA_M0" LOC = "M10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "FPGA_M1" LOC = "V11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "FPGA_M2" LOC = "T10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "FPGA_INIT_B" LOC = "T3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
NET "FPGA_RDWR_B" LOC = "U10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
NET "FPGA_HSWAP" LOC = "B3" | IOSTANDARD = LVCMOS33 ;

# ==== FX2 Connector (FX2) ====

NET "FX2_CLKIN" LOC = "E10" | IOSTANDARD = LVCMOS33 ;
NET "FX2_CLKIO" LOC = "D9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_CLKOUT" LOC = "D10" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
# These four connections are shared with the J1 6-pin accessory header
NET "FX2_IO<1>" LOC = "B4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<2>" LOC = "A4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<3>" LOC = "D5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<4>" LOC = "C5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
# These four connections are shared with the J2 6-pin accessory header
NET "FX2_IO<5>" LOC = "A6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<6>" LOC = "B6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<7>" LOC = "E7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<8>" LOC = "F7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
# These four connections are shared with the J4 6-pin accessory header
NET "FX2_IO<9>" LOC = "D7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<10>" LOC = "C7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<11>" LOC = "F8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<12>" LOC = "E8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
# The discrete LEDs are shared with the following 8 FX2 connections
#NET "FX2_IO<13>" LOC = "F9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<14>" LOC = "E9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<15>" LOC = "D11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<16>" LOC = "C11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<17>" LOC = "F11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<18>" LOC = "E11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<19>" LOC = "E12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<20>" LOC = "F12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<21>" LOC = "A13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<22>" LOC = "B13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<23>" LOC = "A14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<24>" LOC = "B14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<25>" LOC = "C14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<26>" LOC = "D14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

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NET "FX2_IO<27>" LOC = "A16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

NET "FX2_IO<28>" LOC = "B16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<29>" LOC = "E13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<30>" LOC = "C4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<31>" LOC = "B11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<32>" LOC = "A11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<33>" LOC = "A8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<34>" LOC = "G9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IP<35>" LOC = "D12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IP<36>" LOC = "C12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IP<37>" LOC = "A15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IP<38>" LOC = "B15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<39>" LOC = "C3" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IP<40>" LOC = "C15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

# ==== 6-pin header J1 ====

# These are shared connections with the FX2 connector
#NET "J1<0>" LOC = "B4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J1<1>" LOC = "A4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J1<2>" LOC = "D5" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J1<3>" LOC = "C5" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;

# ==== 6-pin header J2 ====

# These are shared connections with the FX2 connector
#NET "J2<0>" LOC = "A6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J2<1>" LOC = "B6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J2<2>" LOC = "E7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J2<3>" LOC = "F7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;

# ==== 6-pin header J4 ====

# These are shared connections with the FX2 connector
#NET "J4<0>" LOC = "D7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J4<1>" LOC = "C7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J4<2>" LOC = "F8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J4<3>" LOC = "E8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;

# ==== Character LCD (LCD) ====

NET "LCD_E" LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "LCD_RS" LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "LCD_RW" LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
# LCD data connections are shared with StrataFlash connections SF_D<11:8>
#NET "SF_D<8>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
#NET "SF_D<9>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
#NET "SF_D<10>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
#NET "SF_D<11>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

# ==== Discrete LEDs (LED) ====

# These are shared connections with the FX2 connector
NET "LED<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<4>" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<5>" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

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Appendix B: Example User Constraints File (UCF)

NET "LED<6>" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "LED<7>" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

# ==== PS/2 Mouse/Keyboard Port (PS2) ====

NET "PS2_CLK" LOC = "G14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "PS2_DATA" LOC = "G13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;

# ==== Rotary Pushbutton Switch (ROT) ====

NET "ROT_A" LOC = "K18" | IOSTANDARD = LVTTL | PULLUP ;
NET "ROT_B" LOC = "G18" | IOSTANDARD = LVTTL | PULLUP ;
NET "ROT_CENTER" LOC = "V16" | IOSTANDARD = LVTTL | PULLDOWN ;

# ==== RS-232 Serial Ports (RS232) ====

NET "RS232_DCE_RXD" LOC = "R7" | IOSTANDARD = LVTTL ;
NET "RS232_DCE_TXD" LOC = "M14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
NET "RS232_DTE_RXD" LOC = "U8" | IOSTANDARD = LVTTL ;
NET "RS232_DTE_TXD" LOC = "M13" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;

# ==== DDR SDRAM (SD) ==== (I/O Bank 3, VCCO=2.5V)

NET "SD_A<0>" LOC = "T1" | IOSTANDARD = SSTL2_I ;
NET "SD_A<1>" LOC = "R3" | IOSTANDARD = SSTL2_I ;
NET "SD_A<2>" LOC = "R2" | IOSTANDARD = SSTL2_I ;
NET "SD_A<3>" LOC = "P1" | IOSTANDARD = SSTL2_I ;
NET "SD_A<4>" LOC = "F4" | IOSTANDARD = SSTL2_I ;
NET "SD_A<5>" LOC = "H4" | IOSTANDARD = SSTL2_I ;
NET "SD_A<6>" LOC = "H3" | IOSTANDARD = SSTL2_I ;
NET "SD_A<7>" LOC = "H1" | IOSTANDARD = SSTL2_I ;
NET "SD_A<8>" LOC = "H2" | IOSTANDARD = SSTL2_I ;
NET "SD_A<9>" LOC = "N4" | IOSTANDARD = SSTL2_I ;
NET "SD_A<10>" LOC = "T2" | IOSTANDARD = SSTL2_I ;
NET "SD_A<11>" LOC = "N5" | IOSTANDARD = SSTL2_I ;
NET "SD_A<12>" LOC = "P2" | IOSTANDARD = SSTL2_I ;
NET "SD_BA<0>" LOC = "K5" | IOSTANDARD = SSTL2_I ;
NET "SD_BA<1>" LOC = "K6" | IOSTANDARD = SSTL2_I ;
NET "SD_CAS" LOC = "C2" | IOSTANDARD = SSTL2_I ;
NET "SD_CK_N" LOC = "J4" | IOSTANDARD = SSTL2_I ;
NET "SD_CK_P" LOC = "J5" | IOSTANDARD = SSTL2_I ;
NET "SD_CKE" LOC = "K3" | IOSTANDARD = SSTL2_I ;
NET "SD_CS" LOC = "K4" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<0>" LOC = "L2" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<1>" LOC = "L1" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<2>" LOC = "L3" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<3>" LOC = "L4" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<4>" LOC = "M3" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<5>" LOC = "M4" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<6>" LOC = "M5" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<7>" LOC = "M6" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<8>" LOC = "E2" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<9>" LOC = "E1" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<10>" LOC = "F1" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<11>" LOC = "F2" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<12>" LOC = "G6" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<13>" LOC = "G5" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<14>" LOC = "H6" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<15>" LOC = "H5" | IOSTANDARD = SSTL2_I ;

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 R

NET "SD_LDM" LOC = "J2" | IOSTANDARD = SSTL2_I ;

NET "SD_LDQS" LOC = "L6" | IOSTANDARD = SSTL2_I ;
NET "SD_RAS" LOC = "C1" | IOSTANDARD = SSTL2_I ;
NET "SD_UDM" LOC = "J1" | IOSTANDARD = SSTL2_I ;
NET "SD_UDQS" LOC = "G3" | IOSTANDARD = SSTL2_I ;
NET "SD_WE" LOC = "D1" | IOSTANDARD = SSTL2_I ;
# Path to allow connection to top DCM connection
NET "SD_CK_FB" LOC = "B9" | IOSTANDARD = LVCMOS33 ;
# Prohibit VREF pins
CONFIG PROHIBIT = D2;
CONFIG PROHIBIT = G4;
CONFIG PROHIBIT = J6;
CONFIG PROHIBIT = L5;
CONFIG PROHIBIT = R4;

# ==== Intel StrataFlash Parallel NOR Flash (SF) ====

NET "SF_A<0>" LOC = "H17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<1>" LOC = "J13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<2>" LOC = "J12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<3>" LOC = "J14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<4>" LOC = "J15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<5>" LOC = "J16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<6>" LOC = "J17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<7>" LOC = "K14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<8>" LOC = "K15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<9>" LOC = "K12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<10>" LOC = "K13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<11>" LOC = "L15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<12>" LOC = "L16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<13>" LOC = "T18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<14>" LOC = "R18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<15>" LOC = "T17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<16>" LOC = "U18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<17>" LOC = "T16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<18>" LOC = "U15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<19>" LOC = "V15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<20>" LOC = "T12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<21>" LOC = "V13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<22>" LOC = "V12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<23>" LOC = "N11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<24>" LOC = "A11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_BYTE" LOC = "C17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_CE0" LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<1>" LOC = "P10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<2>" LOC = "R10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<3>" LOC = "V9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<4>" LOC = "U9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<5>" LOC = "R9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<6>" LOC = "M9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<7>" LOC = "N9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<8>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<9>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<10>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<11>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<12>" LOC = "M16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<13>" LOC = "P6" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<14>" LOC = "R8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<15>" LOC = "T8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

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Appendix B: Example User Constraints File (UCF)

NET "SF_OE" LOC = "C18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET "SF_STS" LOC = "B18" | IOSTANDARD = LVCMOS33 ;
NET "SF_WE" LOC = "D17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

# ==== STMicro SPI serial Flash (SPI) ====

# some connections shared with SPI Flash, DAC, ADC, and AMP
NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 ;
NET "SPI_MOSI" LOC = "T4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "SPI_SCK" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "SPI_SS_B" LOC = "U3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "SPI_ALT_CS_JP11" LOC = "R12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;

# ==== Slide Switches (SW) ====

NET "SW<0>" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
NET "SW<1>" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;
NET "SW<2>" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ;
NET "SW<3>" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ;

# ==== VGA Port (VGA) ====

NET "VGA_BLUE" LOC = "G15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
NET "VGA_GREEN" LOC = "H15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
NET "VGA_HSYNC" LOC = "F15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
NET "VGA_RED" LOC = "H14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
NET "VGA_VSYNC" LOC = "F14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;

# ==== Xilinx CPLD (XC) ====

NET "XC_CMD<0>" LOC = "P18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
NET "XC_CMD<1>" LOC = "N18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
NET "XC_CPLD_EN" LOC = "B10" | IOSTANDARD = LVTTL ;
NET "XC_D<0>" LOC = "G16" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
NET "XC_D<1>" LOC = "F18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
NET "XC_D<2>" LOC = "F17" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
NET "XC_TRIG" LOC = "R17" | IOSTANDARD = LVCMOS33 ;
NET "XC_GCK0" LOC = "H16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "GCLK10" LOC = "C9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

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 LTC1407/LTC1407A
Serial 12-Bit/14-Bit, 3Msps
Simultaneous Sampling
ADCs with Shutdown
U
FEATURES DESCRIPTIO
■ 3Msps Sampling ADC with Two Simultaneous The LTC®1407/LTC1407A are 12-bit/14-bit, 3Msps ADCs
Differential Inputs with two 1.5Msps simultaneously sampled differential
■ 1.5Msps Throughput per Channel inputs. The devices draw only 4.7mA from a single 3V
■ Low Power Dissipation: 14mW (Typ) supply and come in a tiny 10-lead MS package. A Sleep
■ 3V Single Supply Operation shutdown feature lowers power consumption to 10µW.
■ 2.5V Internal Bandgap Reference with External The combination of speed, low power and tiny package
Overdrive makes the LTC1407/LTC1407A suitable for high speed,
■ 3-Wire Serial Interface portable applications.
■ Sleep (10µW) Shutdown Mode The LTC1407/LTC1407A contain two separate differential
■ Nap (3mW) Shutdown Mode inputs that are sampled simultaneously on the rising edge
■ 80dB Common Mode Rejection at 100kHz of the CONV signal. These two sampled inputs are then
■ 0V to 2.5V Unipolar Input Range converted at a rate of 1.5Msps per channel.
■ Tiny 10-Lead MS Package
U The 80dB common mode rejection allows users to elimi-
APPLICATIO S nate ground loops and common mode noise by measuring
signals differentially from the source.
■ Telecommunications
■ Data Acquisition Systems The devices convert 0V to 2.5V unipolar inputs differen-
■ Uninterrupted Power Supplies tially. The absolute voltage swing for CH0+, CH0–, CH1+
■ Multiphase Motor Control and CH1– extends from ground to the supply voltage.
■ I & Q Demodulation The serial interface sends out the two conversion results in
■ Industrial Control 32 clocks for compatibility with standard serial interfaces.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 6084440, 6522187.

W
BLOCK DIAGRA 10µF 3V

THD, 2nd and 3rd

7
VDD LTC1407A vs Input Frequency
CH0+ 1 + –44
14-BIT LATCH

S&H –50

CH0– –56 THD

2 – THREE- 2nd
STATE –62
3Msps
THD, 2nd, 3rd (dB)

MUX SERIAL 8 SDO

14-BIT ADC –68
14-BIT LATCH

OUTPUT
CH1+ 3rd
4 + PORT –74
S&H –80
CH1– 5 – –86
10 CONV
TIMING –92
VREF LOGIC
3 –98
9 SCK
10µF
GND 2.5V –104
6 REFERENCE 0.1 1 10 100
11 EXPOSED PAD FREQUENCY (MHz)
1407A BD 1407 G02

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LTC1407/LTC1407A
W W W U U W U
ABSOLUTE AXI U RATI GS PACKAGE/ORDER I FOR ATIO
(Notes 1, 2)
TOP VIEW
Supply Voltage (VDD) ................................................. 4V
CH0 + 1 10 CONV
Analog Input Voltage CH0 – 2 9 SCK
VREF 3 11 8 SDO
(Note 3) ................................... – 0.3V to (VDD + 0.3V) CH1+ 4 7 VDD
Digital Input Voltage .................... – 0.3V to (VDD + 0.3V) CH1– 5 6 GND

Digital Output Voltage .................. – 0.3V to (VDD + 0.3V) MSE PACKAGE

10-LEAD PLASTIC MSOP
Power Dissipation .............................................. 100mW TJMAX = 125°C, θJA = 150°C/ W
Operation Temperature Range EXPOSED PAD IS GND (PIN 11) MUST BE SOLDERED TO PCB

LTC1407C/LTC1407AC ............................ 0°C to 70°C ORDER PART NUMBER MSE PART MARKING
LTC1407I/LTC1407AI ......................... – 40°C to 85°C
LTC1407CMSE LTBDQ
Storage Temperature Range ................. – 65°C to 150°C
LTC1407IMSE LTBDR
Lead Temperature (Soldering, 10 sec).................. 300°C LTC1407ACMSE LTAFE
LTC1407AIMSE LTAFF
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.

U
CO VERTER CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. With internal reference, VDD = 3V.
LTC1407 LTC1407A
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
Resolution (No Missing Codes) ● 12 14 Bits
Integral Linearity Error (Notes 5, 17) ● –2 ±0.25 2 –4 ±0.5 4 LSB
Offset Error (Notes 4, 17) ● –10 ±1 10 –20 ±2 20 LSB
Offset Match from CH0 to CH1 (Note 17) –5 ±0.5 5 –10 ±1 10 LSB
Gain Error (Notes 4, 17) ● –30 ±5 30 –60 ±10 60 LSB
Gain Match from CH0 to CH1 (Note 17) –5 ±1 5 –10 ±2 10 LSB
Gain Tempco Internal Reference (Note 4) ±15 ±15 ppm/°C
External Reference ±1 ±1 ppm/°C
U U
A ALOG I PUT The ● denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. With internal reference, VDD = 3V.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Analog Differential Input Range (Notes 3, 9) 2.7V ≤ VDD ≤ 3.3V 0 to 2.5 V
VCM Analog Common Mode + Differential 0 to VDD V
Input Range (Note 10)
IIN Analog Input Leakage Current ● 1 µA
CIN Analog Input Capacitance 13 pF
tACQ Sample-and-Hold Acquisition Time (Note 6) ● 39 ns
tAP Sample-and-Hold Aperture Delay Time 1 ns
tJITTER Sample-and-Hold Aperture Delay Time Jitter 0.3 ps
tSK Sample-and-Hold Aperture Skew from CH0 to CH1 200 ps
CMRR Analog Input Common Mode Rejection Ratio fIN = 1MHz, VIN = 0V to 3V –60 dB
fIN = 100MHz, VIN = 0V to 3V –15 dB
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2
 LTC1407/LTC1407A
W U
DY A IC ACCURACY The ● denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. With internal reference, VDD = 3V.
LTC1407 LTC1407A
SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
SINAD Signal-to-Noise Plus 100kHz Input Signal 70.5 73.5 dB
Distortion Ratio 750kHz Input Signal ● 68 70.5 70 73.5 dB
100kHz Input Signal, External VREF = 3.3V, VDD ≥ 3.3V 72.0 76.3 dB
750kHz Input Signal, External VREF = 3.3V, VDD ≥ 3.3V 72.0 76.3 dB
THD Total Harmonic 100kHz First 5 Harmonics 87 –90 dB
Distortion 750kHz First 5 Harmonics ● 83 –77 –86 –80 dB
SFDR Spurious Free 100kHz Input Signal 87 90 dB
Dynamic Range 750kHz Input Signal 83 86 dB
IMD Intermodulation 1.25V to 2.5V 1.40MHz into CH0+ , 0V to 1.25V, –82 –82 dB
Distortion 1.56MHz into CH0– . Also Applicable to CH1+ and CH1–
Code-to-Code VREF = 2.5V (Note 17) 0.25 1 LSBRMS
Transition Noise
Full Power Bandwidth VIN = 2.5VP-P, SDO = 11585LSBP-P (–3dBFS) (Note 15) 50 50 MHz
Full Linear Bandwidth S/(N + D) ≥ 68dB 5 5 MHz

U U U
I TER AL REFERE CE CHARACTERISTICS TA = 25°C. VDD = 3V.

PARAMETER CONDITIONS MIN TYP MAX UNITS

VREF Output Voltage IOUT = 0 2.5 V
VREF Output Tempco 15 ppm/°C
VREF Line Regulation VDD = 2.7V to 3.6V, VREF = 2.5V 600 µV/V
VREF Output Resistance Load Current = 0.5mA 0.2 Ω
VREF Settling Time 2 ms

U U
DIGITAL I PUTS A D DIGITAL OUTPUTS The ● denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3V.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIH High Level Input Voltage VDD = 3.3V ● 2.4 V
VIL Low Level Input Voltage VDD = 2.7V ● 0.6 V
IIN Digital Input Current VIN = 0V to VDD ● ±10 µA
CIN Digital Input Capacitance 5 pF
VOH High Level Output Voltage VDD = 3V, IOUT = – 200µA ● 2.5 2.9 V
VOL Low Level Output Voltage VDD = 2.7V, IOUT = 160µA 0.05 V
VDD = 2.7V, IOUT = 1.6mA ● 0.10 0.4 V
IOZ Hi-Z Output Leakage DOUT VOUT = 0V to VDD ● ±10 µA
COZ Hi-Z Output Capacitance DOUT 1 pF
ISOURCE Output Short-Circuit Source Current VOUT = 0V, VDD = 3V 20 mA
ISINK Output Short-Circuit Sink Current VOUT = VDD = 3V 15 mA

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3
LTC1407/LTC1407A
U W
POWER REQUIRE E TS The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. With internal reference, VDD = 3V.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Supply Voltage 2.7 3.6 V
IDD Supply Current Active Mode, fSAMPLE = 1.5Msps ● 4.7 7.0 mA
Nap Mode ● 1.1 1.5 mA
Sleep Mode (LTC1407) 2.0 15 µA
Sleep Mode (LTC1407A) 2.0 10 µA
PD Power Dissipation Active Mode with SCK in Fixed State (Hi or Lo) 12 mW
WU
TI I G CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VDD = 3V.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSAMPLE(MAX) Maximum Sampling Frequency per Channel ● 1.5 MHz
(Conversion Rate)
tTHROUGHPUT Minimum Sampling Period (Conversion + Acquisiton Period) ● 667 ns
tSCK Clock Period (Note 16) ● 19.6 10000 ns
tCONV Conversion Time (Note 6) 32 34 SCLK cycles
t1 Minimum Positive or Negative SCLK Pulse Width (Note 6) 2 ns
t2 CONV to SCK Setup Time (Notes 6, 10) 3 10000 ns
t3 SCK Before CONV (Note 6) 0 ns
t4 Minimum Positive or Negative CONV Pulse Width (Note 6) 4 ns
t5 SCK to Sample Mode (Note 6) 4 ns
t6 CONV to Hold Mode (Notes 6, 11) 1.2 ns
t7 32nd SCK↑ to CONV↑ Interval (Affects Acquisition Period) (Notes 6, 7, 13) 45 ns
t8 Minimum Delay from SCK to Valid Bits 0 Through 11 (Notes 6, 12) 8 ns
t9 SCK to Hi-Z at SDO (Notes 6, 12) 6 ns
t10 Previous SDO Bit Remains Valid After SCK (Notes 6, 12) 2 ns
t12 VREF Settling Time After Sleep-to-Wake Transition (Notes 6, 14) 2 ms

Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 10: If less than 3ns is allowed, the output data will appear one clock
may cause permanent damage to the device. Exposure to any Absolute cycle later. It is best for CONV to rise half a clock before SCK, when
Maximum Rating condition for extended periods may affect device running the clock at rated speed.
reliability and lifetime. Note 11: Not the same as aperture delay. Aperture delay (1ns) is the
Note 2: All voltage values are with respect to ground GND. difference between the 2.2ns delay through the sample-and-hold and the
Note 3: When these pins are taken below GND or above VDD, they will be 1.2ns CONV to Hold mode delay.
clamped by internal diodes. This product can handle input currents greater Note 12: The rising edge of SCK is guaranteed to catch the data coming
than 100mA below GND or greater than VDD without latchup. out into a storage latch.
Note 4: Offset and range specifications apply for a single-ended CH0+ or Note 13: The time period for acquiring the input signal is started by the
CH1+ input with CH0 – or CH1– grounded and using the internal 2.5V 32nd rising clock and it is ended by the rising edge of CONV.
reference. Note 14: The internal reference settles in 2ms after it wakes up from Sleep
Note 5: Integral linearity is tested with an external 2.55V reference and is mode with one or more cycles at SCK and a 10µF capacitive load.
defined as the deviation of a code from the straight line passing through Note 15: The full power bandwidth is the frequency where the output code
the actual endpoints of a transfer curve. The deviation is measured from swing drops by 3dB with a 2.5VP-P input sine wave.
the center of quantization band. Note 16: Maximum clock period guarantees analog performance during
Note 6: Guaranteed by design, not subject to test. conversion. Output data can be read with an arbitrarily long clock period.
Note 7: Recommended operating conditions. Note 17: The LTC1407A is measured and specified with 14-bit Resolution
Note 8: The analog input range is defined for the voltage difference (1LSB = 152µV) and the LTC1407 is measured and specified with 12-bit
between CH0+ and CH0 – or CH1+ and CH1–. Resolution (1LSB = 610µV).
Note 9: The absolute voltage at CH0+, CH0 –, CH1+ and CH1– must be
within this range.
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TYPICAL PERFOR A CE CHARACTERISTICS VDD = 3V, TA = 25°C (LTC1407A)

ENOBs and SINAD THD, 2nd and 3rd

vs Input Sinewave Frequency vs Input Frequency SFDR vs Input Frequency
12.0 74 –44 104
–50 98
11.5 71
–56 THD 92
11.0 68 2nd
–62 86

THD, 2nd, 3rd (dB)

ENOBs (BITS)

10.5 65

SINAD (dB)
–68 80

SFDR (dB)
3rd
10.0 62 –74 74

9.5 59 –80 68
–86 62
9.0 56
–92 56
8.5 53 –98 50
8.0 50 –104 44
0.1 1 10 100 0.1 1 10 100 0.1 1 10 100
FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz)
1407 G01 1407 G02 1407 G19

98kHz Sine Wave 4096 Point 748kHz Sine Wave 4096 Point
SNR vs Input Frequency FFT Plot FFT Plot
74 0 0
1.5Msps 1.5Msps
–10 –10
71
–20 –20
68 –30 –30
MAGNITUDE (dB)

MAGNITUDE (dB)
–40 –40
65
–50
SNR (dB)

–50
62 –60 –60
–70 –70
59
–80 –80
56 –90 –90
–100 –100
53
–110 –110
50 –120 –120
0.1 1 10 100 0 100 200 300 400 500 600 700 0 100 200 300 400 500 600 700
FREQUENCY (MHz) FREQUENCY (kHz) FREQUENCY (kHz)
1407 G03
1407 G04 1407 G05

1403kHz Input Summed with

1563kHz Input IMD 4096 Point Differential Linearity for CH0 with Integral Linearity End Point Fit for
FFT Plot Internal 2.5V Reference CH0 with Internal 2.5V Reference
0 1.0 2.0
1.5Msps
–10 0.8 1.6
–20
DIFFERENTIAL LINEARITY (LSB)

0.6 1.2
INTEGRAL LINEARITY (LSB)

–30
0.4 0.8
MAGNITUDE (dB)

–40
–50 0.2 0.4
–60 0 0
–70 –0.2 –0.4
–80
–0.4 –0.8
–90
–0.6 –1.2
–100
–110 –0.8 –1.6
–120 –1.0 –2.0
0 100 200 300 400 500 600 700 0 4096 8192 12288 16384 0 4096 8192 12288 16384
FREQUENCY (kHz) OUTPUT CODE OUTPUT CODE
1407 G06 1407 G15 1407 G16

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LTC1407/LTC1407A
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TYPICAL PERFOR A CE CHARACTERISTICS VDD = 3V, TA = 25°C (LTC1407A)

Differential Linearity for CH1 with Integral Linearity End Point Fit for
Internal 2.5V Reference CH1 with Internal 2.5V Reference
1.0 2.0
0.8 1.6
DIFFERENTIAL LINEARITY (LSB)

0.6 1.2

INTEGRAL LINEARITY (LSB)

0.4 0.8
0.2 0.4
0 0
–0.2 –0.4
–0.4 –0.8
–0.6 –1.2
–0.8 –1.6
–1.0 –2.0
0 4096 8192 12288 16384 0 4096 8192 12288 16384
OUTPUT CODE OUTPUT CODE
1407 G17 1407 G18

VDD = 3V, TA = 25°C (LTC1407/LTC1407A)

Full-Scale Signal Frequency
Response CMRR vs Frequency Crosstalk vs Frequency
12 0 –20

6 –30
–20
0
–40
–40
AMPLITUDE (dB)

CROSSTALK (dB)
–6
CMRR (dB)

–50
–12 –60
CH0 CH1 –60
–18
–80 CH1 TO CH0
–70
–24 CH0 TO CH1
–100 –80
–30

–36 –120 –90

1M 10M 100M 1G 100 1k 10k 100k 1M 10M 100M 100 1k 10k 100k 1M 10M
FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (Hz)
1407 G07 1407 G08 1407 G09

Simultaneous Input Steps at CH0

and CH1 from 25Ω PSSR vs Frequency
3.0 –25

2.6 –30

2.2 –35
ANALOG INPUTS (V)

1.8 –40
PSRR (dB)

CH0
1.4 –45
CH1
1.0 –50

0.6 –55

0.2 –60

–0.2 –65

–0.6 –70
0 5 10 15 20 25 30 1 10 100 1k 10k 100k 1M
TIME (ns) FREQUENCY (Hz)
1407 G11
1407 G10

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TYPICAL PERFOR A CE CHARACTERISTICS VDD = 3V, TA = 25°C (LTC1407/LTC1407A)

Reference Voltage
Reference Voltage vs VDD vs Load Current
2.4902 2.4902

2.4900 2.4900

2.4898 2.4898

VREF (V)
VREF (V)

2.4896 2.4896

2.4894 2.4894

2.4892 2.4892

2.4890 2.4890
2.6 2.8 3.0 3.2 3.4 3.6 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VDD (V) LOAD CURRENT (mA)
1407 G12 1407 G13

U U U
PI FU CTIO S
CH0+ (Pin 1): Noninverting Channel 0. CH0+ operates fully VDD (Pin 7): 3V Positive Supply. This single power pin
differentially with respect to CH0– with a 0V to 2.5V supplies 3V to the entire chip. Bypass to GND pin and solid
differential swing and a 0 to VDD absolute input range. analog ground plane with a 10µF ceramic capacitor (or
10µF tantalum) in parallel with 0.1µF ceramic. Keep in
CH0– (Pin 2): Inverting Channel 0. CH0– operates fully
mind that internal analog currents and digital output signal
differentially with respect to CH0+ with a –2.5V to 0V
currents flow through this pin. Care should be taken to
differential swing and a 0 to VDD absolute input range.
place the 0.1µF bypass capacitor as close to Pins 6 and 7
VREF (Pin 3): 2.5V Internal Reference. Bypass to GND and as possible.
a solid analog ground plane with a 10µF ceramic capacitor
SDO (Pin 8): Three-state Serial Data Output. Each pair of
(or 10µF tantalum in parallel with 0.1µF ceramic). Can be
output data words represent the two analog input chan-
overdriven by an external reference voltage ≥ 2.55V and
nels at the start of the previous conversion.
≤VDD.
SCK (Pin 9): External Clock Input. Advances the conver-
CH1+ (Pin 4): Noninverting Channel 1. CH1+ operates fully
sion process and sequences the output data on the rising
differentially with respect to CH1– with a 0V to 2.5V
edge. One or more pulses wake from sleep.
differential swing and a 0 to VDD absolute input range.
CONV (Pin 10): Convert Start. Holds the two analog input
CH1– (Pin 5): Inverting Channel 1. CH1– operates fully
signals and starts the conversion on the rising edge. Two
differentially with respect to CH1+ with a –2.5V to 0V
pulses with SCK in fixed high or fixed low state starts Nap
differential swing and a 0 to VDD absolute input range.
mode. Four or more pulses with SCK in fixed high or fixed
GND (Pins 6, 11): Ground and Exposed Pad. This single low state starts Sleep mode.
ground pin and the Exposed Pad must be tied directly to
the solid ground plane under the part. Keep in mind that
analog signal currents and digital output signal currents
flow through these connections.

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LTC1407/LTC1407A
W
BLOCK DIAGRA
10µF 3V

7
VDD LTC1407A
CH0+ 1 +

14-BIT LATCH
S&H
CH0– 2 – THREE-
STATE
3Msps
MUX SERIAL 8 SDO
14-BIT ADC

14-BIT LATCH
OUTPUT
CH1+ 4 + PORT

S&H
CH1– 5 – 10 CONV
TIMING
VREF LOGIC
3
9 SCK
10µF
GND 2.5V
6 REFERENCE
11 EXPOSED PAD
1407A BD

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 UW

LTC1407 Timing Diagram

t2
t7
t3 t1
33 34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 1
SCK
W

t4 t5
TI I G DIAGRA S

CONV

t6 tACQ
INTERNAL
SAMPLE HOLD HOLD SAMPLE HOLD
S/H STATUS
t8 t10 t9 t8 t8 t9

SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH0 SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH1
Hi-Z Hi-Z Hi-Z
SDO D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X* X* D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X* X* 1407A TD01

12-BIT DATA WORD 12-BIT DATA WORD

tCONV
tTHROUGHPUT
*BITS MARKED “X” AFTER D0 SHOULD BE IGNORED

LTC1407A Timing Diagram

t2
t7
t3 t1
33 34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 1
SCK

t4 t5

CONV

t6 tACQ
INTERNAL
SAMPLE HOLD HOLD SAMPLE HOLD
S/H STATUS
t8 t10 t9 t8 t8 t9

SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH0 SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH1
Hi-Z Hi-Z Hi-Z
SDO D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1407A TD01

14-BIT DATA WORD 14-BIT DATA WORD

tCONV
tTHROUGHPUT

9
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LTC1407/LTC1407A
LTC1407/LTC1407A
UW W
TI I G DIAGRA S
Nap Mode Waveforms

SCK
t1

CONV

NAP

Sleeep Mode Waveforms

SCK

t1 t1

CONV

NAP

SLEEP

t12
VREF 1407 TD02

NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS

SCK to SDO Delay

SCK SCK
VIH VIH
t8
t10 t9
VOH 90%
SDO SDO
VOL 10%
1407 TD03

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 LTC1407/LTC1407A
U U W U
APPLICATIO S I FOR ATIO
DRIVING THE ANALOG INPUT increasing the time between conversions. The best choice
for an op amp to drive the LTC1407/LTC1407A depends
The differential analog inputs of the LTC1407/LTC1407A
on the application. Generally, applications fall into two
are easy to drive. The inputs may be driven differentially or
categories: AC applications where dynamic specifications
as a single-ended input (i.e., the CH0– input is grounded).
are most critical and time domain applications where DC
All four analog inputs of both differential analog input
accuracy and settling time are most critical. The following
pairs, CH0+ with CH0– and CH1+ with CH1–, are sampled
at the same instant. Any unwanted signal that is common list is a summary of the op amps that are suitable for
to both inputs of each input pair will be reduced by the driving the LTC1407/LTC1407A. (More detailed informa-
common mode rejection of the sample-and-hold circuit. tion is available in the Linear Technology Databooks and
The inputs draw only one small current spike while charg- on the LinearViewTM CD-ROM.)
ing the sample-and-hold capacitors at the end of conver- LTC1566-1: Low Noise 2.3MHz Continuous Time Low-
sion. During conversion, the analog inputs draw only a pass Filter.
small leakage current. If the source impedance of the
LT®1630: Dual 30MHz Rail-to-Rail Voltage FB Amplifier.
driving circuit is low, then the LTC1407/LTC1407A inputs
2.7V to ±15V supplies. Very high AVOL, 500µV offset and
can be driven directly. As source impedance increases, so
520ns settling to 0.5LSB for a 4V swing. THD and noise
will acquisition time. For minimum acquisition time with
are – 93dB to 40kHz and below 1LSB to 320kHz (AV = 1,
high source impedance, a buffer amplifier must be used.
2VP-P into 1kΩ, VS = 5V), making the part excellent for AC
The main requirement is that the amplifier driving the
applications (to 1/3 Nyquist) where rail-to-rail perfor-
analog input(s) must settle after the small current spike
mance is desired. Quad version is available as LT1631.
before the next conversion starts (settling time must be
39ns for full throughput rate). Also keep in mind, while LT1632: Dual 45MHz Rail-to-Rail Voltage FB Amplifier.
choosing an input amplifier, the amount of noise and 2.7V to ±15V supplies. Very high AVOL, 1.5mV offset and
harmonic distortion added by the amplifier. 400ns settling to 0.5LSB for a 4V swing. It is suitable for
applications with a single 5V supply. THD and noise are
CHOOSING AN INPUT AMPLIFIER – 93dB to 40kHz and below 1LSB to 800kHz (AV = 1,
2VP-P into 1kΩ, VS = 5V), making the part excellent for AC
Choosing an input amplifier is easy if a few requirements applications where rail-to-rail performance is desired.
are taken into consideration. First, to limit the magnitude Quad version is available as LT1633.
of the voltage spike seen by the amplifier from charging
the sampling capacitor, choose an amplifier that has a low LT1801: 80MHz GBWP, –75dBc at 500kHz, 2mA/ampli-
output impedance (< 100Ω) at the closed-loop bandwidth fier, 8.5nV/√Hz.
frequency. For example, if an amplifier is used in a gain of LT1806/LT1807: 325MHz GBWP, –80dBc distortion at
1 and has a unity-gain bandwidth of 50MHz, then the 5MHz, unity gain stable, rail-to-rail in and out,
output impedance at 50MHz must be less than 100Ω. The 10mA/amplifier, 3.5nV/√Hz.
second requirement is that the closed-loop bandwidth
LT1810: 180MHz GBWP, –90dBc distortion at 5MHz,
must be greater than 40MHz to ensure adequate small-
unity gain stable, rail-to-rail in and out, 15mA/amplifier,
signal settling for full throughput rate. If slower op amps
16nV/√Hz.
are used, more time for settling can be provided by LinearView is a trademark of Linear Technology Corporation.

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LTC1407/LTC1407A
U U W U
APPLICATIO S I FOR ATIO
LT1818/LT1819: 400MHz, 2500V/µs, 9mA, Single/Dual inputs to minimize noise. A simple 1-pole RC filter is suf-
Voltage Mode Operational Amplifier. ficient for many applications. For example, Figure 1 shows
LT6200: 165MHz GBWP, –85dBc distortion at 1MHz, a 47pF capacitor from CHO+ to ground and a 51Ω source
unity gain stable, rail-to-rail in and out, 15mA/amplifier, resistor to limit the net input bandwidth to 30MHz. The
0.95nV/√Hz. 47pF capacitor also acts as a charge reservoir for the input
sample-and-hold and isolates the ADC input from sam-
LT6203: 100MHz GBWP, –80dBc distortion at 1MHz, pling-glitch sensitive circuitry. High quality capacitors and
unity gain stable, rail-to-rail in and out, 3mA/amplifier, resistors should be used since these components can add
1.9nV/√Hz. distortion. NPO and silvermica type dielectric capacitors
LT6600: Amplifier/Filter Differential In/Out with 10MHz have excellent linearity. Carbon surface mount resistors
Cutoff. can generate distortion from self heating and from dam-
age that may occur during soldering. Metal film surface
mount resistors are much less susceptible to both prob-
INPUT FILTERING AND SOURCE IMPEDANCE
lems. When high amplitude unwanted signals are close in
The noise and the distortion of the input amplifier and frequency to the desired signal frequency a multiple pole
other circuitry must be considered since they will add to filter is required.
the LTC1407/LTC1407A noise and distortion. The small-
High external source resistance, combined with 13pF of
signal bandwidth of the sample-and-hold circuit is 50MHz.
input capacitance, will reduce the rated 50MHz input band-
Any noise or distortion products that are present at the
width and increase acquisition time beyond 39ns.
analog inputs will be summed over this entire bandwidth.
Noisy input circuitry should be filtered prior to the analog

51Ω* 1
ANALOG
CH0+
INPUT
47pF*
2
CH0–
LTC1407/
LTC1407A
3
VREF
10µF
11
GND

ANALOG 51Ω* 4
INPUT CH1+
47pF*
5
CH1–
1407 F01

*TIGHT TOLERANCE REQUIRED TO AVOID

APERTURE SKEW DEGRADATION

Figure 1. RC Input Filter

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 LTC1407/LTC1407A
U U W U
APPLICATIO S I FOR ATIO
INPUT RANGE overdriven with an external reference as shown in Figure 2.
The voltage of the external reference must be higher than
The analog inputs of the LTC1407/LTC1407A may be
the 2.5V of the open-drain P-channel output of the internal
driven fully differentially with a single supply. Either input
reference. The recommended range for an external refer-
may swing up to 3V, provided the differential swing is no
greater than 2.5V. In the valid input range, the noninvert- ence is 2.55V to VDD. An external reference at 2.55V will
see a DC quiescent load of 0.75mA and as much as 3mA
ing input of each channel should always be more positive
during conversion.
than the inverting input of each channel. The 0V to 2.5V
range is also ideally suited for single-ended input use with
single supply applications. The common mode range of INPUT SPAN VERSUS REFERENCE VOLTAGE
the inputs extend from ground to the supply voltage VDD. The differential input range has a unipolar voltage span
If the difference between the CH0+ and CH0– inputs or the that equals the difference between the voltage at the
CH1+ and CH1– inputs exceeds 2.5V, the output code will reference buffer output VREF (Pin 3) and the voltage at the
stay fixed at all ones, and if this difference goes below 0V, Exposed Pad ground. The differential input range of ADC
the ouput code will stay fixed at all zeros. is 0V to 2.5V when using the internal reference. The
internal ADC is referenced to these two nodes. This
INTERNAL REFERENCE relationship also holds true with an external reference.
The LTC1407/LTC1407A have an on-chip, temperature
compensated, bandgap reference that is factory trimmed DIFFERENTIAL INPUTS
near 2.5V to obtain a precise 2.5V input span. The refer- The ADC will always convert the unipolar difference of
ence amplifier output VREF, (Pin 3) must be bypassed with CH0+ minus CH0– or the unipolar difference of CH1+
a capacitor to ground. The reference amplifier is stable with minus CH1–, independent of the common mode voltage at
capacitors of 1µF or greater. For the best noise perfor- either set of inputs. The common mode rejection holds up
mance, a 10µF ceramic or a 10µF tantalum in parallel with at high frequencies (see Figure 3.) The only requirement is
a 0.1µF ceramic is recommended. The V REF pin can be that both inputs not go below ground or exceed VDD.

3 –20
3V REF VREF
LTC1407/
10µF –40
LTC1407A
11
CMRR (dB)

GND
–60
1407 F02
CH0 CH1
–80
Figure 2
–100

–120
100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
1407 G08

Figure 3. CMRR vs Frequency

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LTC1407/LTC1407A
U U W U
APPLICATIO S I FOR ATIO
Integral nonlinearity errors (INL) and differential nonlin- High quality tantalum and ceramic bypass capacitors should
earity errors (DNL) are largely independent of the common be used at the VDD and VREF pins as shown in the Block
mode voltage. However, the offset error will vary. CMRR Diagram on the first page of this data sheet. For optimum
is typically better than 60dB. performance, a 10µF surface mount tantalum capacitor
with a 0.1µF ceramic is recommended for the VDD and VREF
Figure 4 shows the ideal input/output characteristics for
pins. Alternatively, 10µF ceramic chip capacitors such as
the LTC1407/LTC1407A. The code transitions occur mid-
X5R or X7R may be used. The capacitors must be located
way between successive integer LSB values (i.e., 0.5LSB,
as close to the pins as possible. The traces connecting the
1.5LSB, 2.5LSB, FS – 1.5LSB). The output code is natural
pins and the bypass capacitors must be kept short and
binary with 1LSB = 2.5V/16384 = 153µV for the LTC1407A
should be made as wide as possible. The VDD bypass ca-
and 1LSB = 2.5V/4096 = 610µV for the LTC1407. The
pacitor returns to GND (Pin 6) and the VREF bypass capaci-
LTC1407A has 1LSB RMS of Gaussian white noise.
tor returns to the Exposed Pad ground (Pin 11). Care should
Board Layout and Bypassing be taken to place the 0.1µF VDD bypass capacitor as close
to Pins 6 and 7 as possible.
Wire wrap boards are not recommended for high resolu-
tion and/or high speed A/D converters. To obtain the best Figure 5 shows the recommended system ground connec-
performance from the LTC1407/LTC1407A, a printed cir- tions. All analog circuitry grounds should be terminated at
cuit board with ground plane is required. Layout for the the LTC1407/LTC1407A Exposed Pad. The ground return
printed circuit board should ensure that digital and analog from the LTC1407/LTC1407A Pin 6 to the power supply
signal lines are separated as much as possible. In particu- should be low impedance for noise-free operation. The
lar, care should be taken not to run any digital track Exposed Pad of the 10-lead MSE package is also tied to
alongside an analog signal track. If optimum phase match Pin 6 and the LTC1407/LTC1407A GND. The Exposed Pad
between the inputs is desired, the length of the four input should be soldered on the PC board to reduce ground
wires of the two input channels should be kept matched. connection inductance. Digital circuitry grounds must be
But each pair of input wires to the two input channels connected to the digital supply common.
should be kept separated by a ground trace to avoid high
frequency crosstalk between channels.

111...111
111...110
UNIPOLAR OUTPUT CODE

111...101

000...010
000...001
000...000
0 FS – 1LSB

INPUT VOLTAGE (V)

1407 F04

Figure 4. LTC1407/LTC1407A Transfer Characteristic

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 LTC1407/LTC1407A
U U W U
APPLICATIO S I FOR ATIO

1407 F05

Figure 5. Recommended Layout

POWER-DOWN MODES Four rising edges at CONV, without any intervening rising
edges at SCK, put the LTC1407/LTC1407A in Sleep mode
Upon power-up, the LTC1407/LTC1407A are initialized to
and the power drain drops from 14mW to 10µW. To bring
the active state and are ready for conversion. The Nap and
the part out of Sleep mode requires one or more rising SCK
Sleep mode waveforms show the power-down modes for
edges followed by a Nap request. Then one or more rising
the LTC1407/LTC1407A. The SCK and CONV inputs con-
edges at SCK wake up the LTC1407/LTC1407A for opera-
trol the power-down modes (see Timing Diagrams). Two
tion. When Nap mode is entered after Sleep mode, the
rising edges at CONV, without any intervening rising
reference that was shut down in Sleep mode is reactivated.
edges at SCK, put the LTC1407/LTC1407A in Nap mode
and the power drain drops from 14mW to 6mW. The The internal reference (VREF ) takes 2ms to slew and settle
internal reference remains powered in Nap mode. One or with a 10µF load. Using Sleep mode more frequently
more rising edges at SCK wake up the LTC1407/LTC1407A compromises the settled accuracy of the internal refer-
for service very quickly and CONV can start an accurate ence. Note that for slower conversion rates, the Nap and
conversion within a clock cycle. Sleep modes can be used for substantial reductions in
power consumption.

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LTC1407/LTC1407A
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APPLICATIO S I FOR ATIO
DIGITAL INTERFACE directly from the DSP crystal. Another problem with high
speed processor clocks is that they often use a low cost,
The LTC1407/LTC1407A have a 3-wire SPI (Serial Proto-
low speed crystal (i.e., 10MHz) to generate a fast, but
col Interface) interface. The SCK and CONV inputs and
jittery, phase-locked-loop system clock (i.e., 40MHz). The
SDO output implement this interface. The SCK and CONV
jitter in these PLL-generated high speed clocks can be
inputs accept swings from 3V logic and are TTL compat-
several nanoseconds. Note that if you choose to use the
ible, if the logic swing does not exceed VDD. A detailed
description of the three serial port signals follows: frame sync signal generated by the DSP port, this signal
will have the same jitter of the DSP’s master clock.
Conversion Start Input (CONV)
Serial Clock Input (SCK)
The rising edge of CONV starts a conversion, but subse-
quent rising edges at CONV are ignored by the LTC1407/ The rising edge of SCK advances the conversion process
LTC1407A until the following 32 SCK rising edges have and also udpates each bit in the SDO data stream. After
occurred. The duty cycle of CONV can be arbitrarily chosen CONV rises, the third rising edge of SCK sends out two
to be used as a frame sync signal for the processor serial sets of 12/14 data bits, with the MSB sent first. A simple
port. A simple approach to generate CONV is to create a approach is to generate SCK to drive the LTC1407/
pulse that is one SCK wide to drive the LTC1407/LTC1407A LTC1407A first and then buffer this signal with the appro-
and then buffer this signal to drive the frame sync input of priate number of inverters to drive the serial clock input of
the processor serial port. It is good practice to drive the the processor serial port. Use the falling edge of the clock
LTC1407/LTC1407A CONV input first to avoid digital noise to latch data from the Serial Data Output (SDO) into your
interference during the sample-to-hold transition trig- processor serial port. The 14-bit Serial Data will be re-
gered by CONV at the start of conversion. It is also good ceived right justified, in two 16-bit words with 32 or more
practice to keep the width of the low portion of the CONV clocks per frame sync. It is good practice to drive the
signal greater than 15ns to avoid introducing glitches in LTC1407/LTC1407A SCK input first to avoid digital noise
the front end of the ADC just before the sample-and-hold interference during the internal bit comparison decision
goes into Hold mode at the rising edge of CONV. by the internal high speed comparator. Unlike the CONV
input, the SCK input is not sensitive to jitter because the
Minimizing Jitter on the CONV Input input signal is already sampled and held constant.
In high speed applications where high amplitude sinewaves Serial Data Output (SDO)
above 100kHz are sampled, the CONV signal must have as
little jitter as possible (10ps or less). The square wave Upon power-up, the SDO output is automatically reset to
output of a common crystal clock module usually meets the high impedance state. The SDO output remains in high
this requirement easily. The challenge is to generate a impedance until a new conversion is started. SDO sends
CONV signal from this crystal clock without jitter corrup- out two sets of 12/14 bits in the output data stream after
tion from other digital circuits in the system. A clock the third rising edge of SCK after the start of conversion
divider and any gates in the signal path from the crystal with the rising edge of CONV. The two 12-/14-bit words are
clock to the CONV input should not share the same separated by two clock cycles in high impedance mode.
integrated circuit with other parts of the system. As shown Please note the delay specification from SCK to a valid
in the interface circuit examples, the SCK and CONV inputs SDO. SDO is always guaranteed to be valid by the next
should be driven first, with digital buffers used to drive the rising edge of SCK. The 32-bit output data stream is
serial port interface. Also note that the master clock in the compatible with the 16-bit or 32-bit serial port of most
DSP may already be corrupted with jitter, even if it comes processors.

1407fa

16
 LTC1407/LTC1407A
U U W U
APPLICATIO S I FOR ATIO
HARDWARE INTERFACE TO TMS320C54x and the serial clock at the BCLKR pin to accept an external
positive edge clock. Buffers near the LTC1407/LTC1407A
The LTC1407/LTC1407A are serial output ADCs whose
may be added to drive long tracks to the DSP to prevent
interface has been designed for high speed buffered serial
corruption of the signal to LTC1407/LTC1407A. This con-
ports in fast digital signal processors (DSPs). Figure 6
figuration is adequate to traverse a typical system board,
shows an example of this interface using a TMS320C54X.
but source resistors at the buffer outputs and termination
The buffered serial port in the TMS320C54x has direct resistors at the DSP, may be needed to match the charac-
access to a 2kB segment of memory. The ADC’s serial data teristic impedance of very long transmission lines. If you
can be collected in two alternating 1kB segments, in real need to terminate the SDO transmission line, buffer it first
time, at the full 3Msps conversion rate of the LTC1407/ with one or two 74ACxx gates. The TTL threshold inputs of
LTC1407A. The DSP assembly code sets frame sync mode the DSP port respond properly to the 3V swing used with
at the BFSR pin to accept an external positive going pulse the LTC1407/LTC1407A.

3V 5V
7
VDD VCC

10
CONV BFSR
LTC1407/
TMS320C54x
LTC1407A
9
SCK BCLKR
B13 B12
8
SDO BDR
6
GND
CONV 3-WIRE SERIAL
CLK INTERFACELINK 1407 F06

0V TO 3V LOGIC SWING

Figure 6. DSP Serial Interface to TMS320C54x

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17
LTC1407/LTC1407A
U U W U
APPLICATIO S I FOR ATIO
; 08-21-03 ******************************************************************
; Files: 1407ASIAB.ASM -> 1407A Sine wave collection with Serial Port interface
; both channels collected in sequence in the same 2k record
; bvectors.asm buffered mode.
; s2k14ini.asm 2k buffer size.
; unipolar mode
; Works 16 or 64 clock frames.
; negative edge BCLKR
; negative BFSR pulse
; -0 data shifted
; 1' cable from counter to CONV at DUT
; 2' cable from counter to CLK at DUT
; ***************************************************************************

.width 160
.length 110
.title “sineb0 BSP in auto buffer mode”
.mmregs
.setsect “.text”, 0x500,0 ;Set address of executable
.setsect “vectors”, 0x180,0 ;Set address of incoming 1407A data
.setsect “buffer”, 0x800,0 ;Set address of BSP buffer for clearing
.setsect “result”, 0x1800,0 ;Set address of result for clearing
.text ;.text marks start of code

start:
;this label seems necessary
;Make sure /PWRDWN is low at J1-9
;to turn off AC01 adc
tim=#0fh
prd=#0fh
tcr = #10h ; stop timer
tspc = #0h ; stop TDM serial port to AC01
pmst = #01a0h ; set up iptr. Processor Mode STatus register
sp = #0700h ; init stack pointer.
dp = #0 ; data page
ar2 = #1800h ; pointer to computed receive buffer.
ar3 = #0800h ; pointer to Buffered Serial Port receive buffer
ar4 = #0h ; reset record counter
call sineinit ; Double clutch the initialization to insure a proper
sinepeek:
call sineinit ; reset. The external frame sync must occur 2.5 clocks
; or more after the port comes out of reset.
wait goto wait

; ————————Buffered Receive Interrupt Routine -————————-

breceive:
ifr = #10h ; clear interrupt flags
TC = bitf(@BSPCE,#4000h) ; check which half (bspce(bit14)) of buffer
if (NTC) goto bufull ; if this still the first half get next half
bspce = #(2023h + 08000h); turn on halt for second half (bspce(bit15))
return_enable
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18
 LTC1407/LTC1407A
U U W U
APPLICATIO S I FOR ATIO
; ———————mask and shift input data ——————————————

bufull:
b = *ar3+ << -0 ; load acc b with BSP buffer and shift right -0
b = #07FFFh & b ; mask out the TRISTATE bits with #03FFFh
;
*ar2+ = data(#0bh) ; store B to out buffer and advance AR2 pointer
TC = (@ar2 == #02000h) ; output buffer is 2k starting at 1800h
if (TC) goto start ; restart if out buffer is at 1fffh
goto bufull

; —————————dummy bsend return————————————

bsend return_enable ;this is also a dummy return to define bsend
;in vector table file BVECTORS.ASM
; ——————————— end ISR ——————————————

.copy “c:\dskplus\1407A\s2k14ini.asm” ;initialize buffered serial port

.space 16*32 ;clear a chunk at the end to mark the end

;======================================================================
;
; VECTORS
;
;======================================================================
.sect “vectors” ;The vectors start here
.copy “c:\dskplus\1407A\bvectors.asm” ;get BSP vectors

.sect “buffer” ;Set address of BSP buffer for clearing

.space 16*0x800
.sect “result” ;Set address of result for clearing
.space 16*0x800

.end

; ***************************************************************************
; File: BVECTORS.ASM -> Vector Table for the ‘C54x DSKplus 10.Jul.96
; BSP vectors and Debugger vectors
; TDM vectors just return
; ***************************************************************************
; The vectors in this table can be configured for processing external and
; internal software interrupts. The DSKplus debugger uses four interrupt
; vectors. These are RESET, TRAP2, INT2, and HPIINT.
; * DO NOT MODIFY THESE FOUR VECTORS IF YOU PLAN TO USE THE DEBUGGER *
;
; All other vector locations are free to use. When programming always be sure
; the HPIINT bit is unmasked (IMR=200h) to allow the communications kernel and
; host PC interact. INT2 should normally be masked (IMR(bit 2) = 0) so that the
; DSP will not interrupt itself during a HINT. HINT is tied to INT2 externally.
;
;
;
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19
LTC1407/LTC1407A
U U W U
APPLICATIO S I FOR ATIO
.title “Vector Table”
.mmregs

reset goto #80h ;00; RESET * DO NOT MODIFY IF USING DEBUGGER *

nop
nop
nmi return_enable ;04; non-maskable external interrupt
nop
nop
nop
trap2 goto #88h ;08; trap2 * DO NOT MODIFY IF USING DEBUGGER *
nop
nop
.space 52*16 ;0C-3F: vectors for software interrupts 18-30
int0 return_enable ;40; external interrupt int0
nop
nop
nop
int1 return_enable ;44; external interrupt int1
nop
nop
nop
int2 return_enable ;48; external interrupt int2
nop
nop
nop
tint return_enable ;4C; internal timer interrupt
nop
nop
nop
brint goto breceive ;50; BSP receive interrupt
nop
nop
nop
bxint goto bsend ;54; BSP transmit interrupt
nop
nop
nop
trint return_enable ;58; TDM receive interrupt
nop
nop
nop
txint return_enable ;5C; TDM transmit interrupt
nop
nop
int3 return_enable ;60; external interrupt int3
nop
nop
nop
hpiint dgoto #0e4h ;64; HPIint * DO NOT MODIFY IF USING DEBUGGER *
nop
nop
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20
 LTC1407/LTC1407A
U U W U
APPLICATIO S I FOR ATIO
.space 24*16 ;68-7F; reserved area

**********************************************************************
* (C) COPYRIGHT TEXAS INSTRUMENTS, INC. 1996 *
**********************************************************************
* *
* File: BSPI1407A.ASM BSP initialization code for the ‘C54x DSKplus *
* for use with 1407A in standard mode *
* BSPC and SPC seem interchangeable in the ‘C542 *
* BSPCE and SPCE seem interchangeable in the ‘C542 *
**********************************************************************
.title “Buffered Serial Port Initialization Routine”
ON .set 1
OFF .set !ON
YES .set 1
NO .set !YES
BIT_8 .set 2
BIT_10 .set 1
BIT_12 .set 3
BIT_16 .set 0
GO .set 0x80

**********************************************************************
* This is an example of how to initialize the Buffered Serial Port (BSP).
* The BSP is initialized to require an external CLK and FSX for
* operation. The data format is 16-bits, burst mode, with autobuffering
* enabled. Set the variables listed below to configure the BSP for
* your application.
*
*****************************************************************************************************
*LTC1407A timing with 40MHz crystal.
*
*10MHz, divided from 40MHz, forced to CLKIN by 1407A board.
*
*Horizontal scale is 6.25ns/chr or 25ns period at BCLKR
*
*BFSR Pin J1-20 ~~\____/~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\____/
~~~~~~~~~~~*
*BCLKR Pin J1-14 _/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/
~\_/~\_/~*
*BDR Pin J1-26 _—_—_—<B13-B12-B11-B10-B09-B08-B07-B06-B05-B04-B03-B02-B01-B00>—_—<B13-
B12*
*CLKIN Pin J5-09 ~~~~~\_______/~~~~~~~\_______/~~~~~~~\_______/~~~~~~~\_______/
~~~~~~~\_______/~~~~~*
*C542 read 0 B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00 0 0
B13 B12*
*
*
* negative edge BCLKR
* negative BFSR pulse
* no data shifted
* 1' cable from counter to CONV at DUT
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21
LTC1407/LTC1407A
U U W U
APPLICATIO S I FOR ATIO
* 2' cable from counter to CLK at DUT
*No right shift is needed to right justify the input data in the main program
*
*the two msbs should also be masked
*
****************************************************************************************************
*
Loopback .set NO ;(digital looback mode?) DLB bit
Format .set BIT_16 ;(Data format? 16,12,10,8) FO bit
IntSync .set NO ;(internal Frame syncs generated?) TXM bit
IntCLK .set NO ;(internal clks generated?) MCM bit
BurstMode .set YES ;(if BurstMode=NO, then Continuous) FSM bit
CLKDIV .set 3 ;(3=default value, 1/4 CLOCKOUT)
PCM_Mode .set NO ;(Turn on PCM mode?)
FS_polarity .set YES ;(change polarity)YES=~~~\_/~~~, NO=___/~\___
CLK_polarity .set NO ;(change polarity)for BCLKR YES=_/~, NO=~\_
Frame_ignore .set !YES ;(inverted !YES -ignores frame)
XMTautobuf .set NO ;(transmit autobuffering)
RCVautobuf .set NO ;(receive autobuffering)
XMThalt .set NO ;(transmit buff halt if XMT buff is full)
RCVhalt .set NO ;(receive buff halt if RCV buff is full)
XMTbufAddr .set 0x600 ;(address of transmit buffer)
RCVbufAddr .set 0x800 ;(address of receive buffer)
XMTbufSize .set 0x200 ;(length of transmit buffer)
RCVbufSize .set 0x040 ;(length of receive buffer)
*
* See notes in the ‘C54x CPU and Peripherals Reference Guide on setting up
* valid buffer start and length values.
*
*
**********************************************************************
.eval ((Loopback >> 1)|((Format & 2)<<1)|(BurstMode <<3)|(IntCLK <<4)|(IntSync
<<5)) ,SPCval
.eval ((CLKDIV)|(FS_polarity <<5)|(CLK_polarity<<6)|((Format &
1)<<7)|(Frame_ignore<<8)|(PCM_Mode<<9)), SPCEval
.eval (SPCEval|(XMTautobuf<<10)|(XMThalt<<12)|(RCVautobuf<<13)|(RCVhalt<<15)),
SPCEval

bspi1407A:
bspc = #SPCval ; places buffered serial port in reset
bspce = #SPCEval ; programs BSPCE and ABU
axr = #XMTbufAddr ; initializes transmit buffer start address
bkx = #XMTbufSize ; initializes transmit buffer size
arr = #RCVbufAddr ; initializes receive buffer start address
bkr = #RCVbufSize ; initializes receive buffer size
bspc = #(SPCval | GO) ; bring buffered serial port out of reset
return ; for transmit and receive because GO=0xC0

1407fa

22
 LTC1407/LTC1407A
U
PACKAGE DESCRIPTIO
MSE Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1664)

BOTTOM VIEW OF
EXPOSED PAD OPTION
2.06 ± 0.102
2.794 ± 0.102 0.889 ± 0.127
(.110 ± .004) 1 (.081 ± .004)
(.035 ± .005)
1.83 ± 0.102
(.072 ± .004)

5.23
2.083 ± 0.102 3.20 – 3.45
(.206)
(.082 ± .004) (.126 – .136)
MIN

10

0.305 ± 0.038 0.50 3.00 ± 0.102

(.0120 ± .0015) (.0197) (.118 ± .004) 0.497 ± 0.076
TYP BSC (NOTE 3) (.0196 ± .003)
RECOMMENDED SOLDER PAD LAYOUT 10 9 8 7 6
REF

4.90 ± 0.152 3.00 ± 0.102

(.193 ± .006) (.118 ± .004)
(NOTE 4)
DETAIL “A”
0.254
(.010)
0° – 6° TYP
GAUGE PLANE 1 2 3 4 5

0.53 ± 0.152 1.10 0.86

(.021 ± .006) (.043) (.034)
MAX REF
DETAIL “A”
0.18
(.007)
SEATING
PLANE 0.17 – 0.27 0.127 ± 0.076
(.007 – .011) (.005 ± .003)
0.50
TYP MSOP (MSE) 0603
NOTE: (.0197)
1. DIMENSIONS IN MILLIMETER/(INCH) BSC
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

1407fa

23
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC1407/LTC1407A
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
ADCs
LTC1608 16-Bit, 500ksps Parallel ADC ±5V Supply, ±2.5V Span, 90dB SINAD
LTC1609 16-Bit, 250ksps Serial ADC 5V Configurable Bipolar/Unipolar Inputs
LTC1403/LTC1403A 12-/14-Bit, 2.8Msps Serial ADC 3V, 15mW, MSOP Package
LTC1411 14-Bit, 2.5Msps Parallel ADC 5V, Selectable Spans, 80dB SINAD
LTC1420 12-Bit, 10Msps Parallel ADC 5V, Selectable Spans, 72dB SINAD
LTC1405 12-Bit, 5Msps Parallel ADC 5V, Selectable Spans, 115mW
LTC1412 12-Bit, 3Msps Parallel ADC ±5V Supply, ±2.5V Span, 72dB SINAD
LTC1402 12-Bit, 2.2Msps Serial ADC 5V or ±5V Supply, 4.096V or ±2.5V Span
LTC1864/LTC1865 16-Bit, 250ksps 1-/2-Channel Serial ADCs 5V or 3V (L-Version), Micropower, MSOP Package
LTC1864L/LTC1865L
DACs
LTC1666/LTC1667 12-/14-/16-Bit, 50Msps DAC 87dB SFDR, 20ns Settling Time
LTC1668
LTC1592 16-Bit, Serial SoftSpanTM IOUT DAC ±1LSB INL/DNL, Software Selectable Spans
References
LT1790-2.5 Micropower Series Reference in SOT-23 0.05% Initial Accuracy, 10ppm Drift
LT1461-2.5 Precision Voltage Reference 0.04% Initial Accuracy, 3ppm Drift
LT1460-2.5 Micropower Series Voltage Reference 0.10% Initial Accuracy, 10ppm Drift
SoftSpan is a trademark of Linear Technology Corporation.

1407fa

LT 0506 REV A • PRINTED IN USA

24 Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ●
www.linear.com © LINEAR TECHNOLOGY CORPORATION 2003
 LTC6912
Dual Programmable
Gain Amplifiers with
Serial Digital Interface
U
FEATURES DESCRIPTIO
■ 2 Channels with Independent Gain Control The LTC®6912 is a family of dual channel, low noise,
LTC6912-1: (0, 1, 2, 5, 10, 20, 50, and 100V/V) digitally programmable gain amplifiers (PGA) that are
LTC6912-2: (0, 1, 2, 4, 8, 16, 32, and 64V/V) easy to use and occupy very little PC board space. The
■ Offset Voltage = 2mV Max (–40°C to 85°C) gains for both channels are independently programmable
■ Channel-to-Channel Gain Matching of 0.1dB Max using a 3-wire SPI interface to select voltage gains of 0, 1,
■ 3-Wire SPITM Interface 2, 5, 10, 20, 50, and 100V/V (LTC6912-1 ); and 0, 1, 2, 4,
■ Extended Gain-Bandwidth at High Gains 8, 16, 32, and 64V/V (LTC6912-2). All gains are inverting.
■ Wired-OR Outputs Possible (2:1 Analog MUX
Function) The LTC6912 family consists of 2 matched amplifiers with
■ Low Power Hardware Shutdown (GN-16 Only, rail-to-rail outputs. When operated with unity gain, they
2µA Max at 2.7V) will also process rail-to-rail input signals. A half-supply
■ Rail-to-Rail Input Range reference generated internally at the AGND pin supports
■ Rail-to-Rail Output Swing single power supply applications. Operating from single
■ Single or Dual Supply: 2.7V to 10.5V Total or split supplies from 2.7V to 10.5V total, the LTC6912-X
■ Input Noise: 12.6nV/√Hz family is offered in tiny SSOP and DFN-12 Packages.
■ Total System Dynamic Range to 115dB
■ 16-Pin GN (SSOP) or 12-Pin DFN Package Options
U , LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
APPLICATIO S
■ Data Acquisition Systems
■ Dynamic Gain Changing
■ Automatic Ranging Circuits
■ Automatic Gain Control

U
TYPICAL APPLICATIO
A Dual, Matched Low Noise PGA (16-Lead SSOP Package)
3V
0.1µF
LTC6912-2
12 14
V+ V–
Frequency Response
40
GAIN OF 64 VS = ±2.5V
2 INA OUT A 15 VIN = 10mVRMS
VINA VOUTA = GAINA • VINA GAIN OF 32
30
1µF GAIN OF 16
3
AGND LTC6912-X 20 GAIN OF 8
GAIN (dB)

GAIN OF 4
4 INB OUT B 13 10
VINB VOUTB = GAINB • VINB
GAIN OF 2

GAIN OF 1
0

CHB CHA –10

5 0.1 1 10 100 1000 10000
SHDN SHDN 10
6 DGND FREQUENCY (kHz)
CS/LD CS/LD
3-WIRE 7 6912 TA01b
SPI DATA DIN 9
INTERFACE 8 DOUT
CLK
6912 TA01a

6912fa

1
LTC6912
W W W U
ABSOLUTE AXI U RATI GS
(Note 1)
Specified Temperature Range (Note 3)
Total Supply Voltage (V + to V –) ............................... 11V LTC6912C-1, LTC6912C-2 ..................–40°C to 85°C
Input Current ...................................................... ±10mA LTC6912I-1, LTC6912I-2 .....................–40°C to 85°C
Operating Temperature Range (Note 2) LTC6912H-1, LTC6912H-2
LTC6912C-1, LTC6912C-2 ..................–40°C to 85°C (GN-16 Only) .....................................–40°C to 125°C
LTC6912I-1, LTC6912I-2 .....................–40°C to 85°C Storage Temperature Range ..................–65°C to 150°C
LTC6912H-1, LTC6912H-2 UE Package ....................................... –65°C to 125°C
(GN-16 Only) .....................................–40°C to 125°C Lead Temperature (Soldering, 10sec)................... 300°C

W U U
PACKAGE/ORDER I FOR ATIO
TOP VIEW TOP VIEW

INA 1 12 OUTA NC 1 16 NC

AGND 2 11 V – INA 2 15 OUT A

AGND 3 14 V –
INB 3 10 OUTB
13 INB 4 13 OUT B
CS/LD 4 9 V+
SHDN 5 12 V +
DIN 5 8 DGND
CS/LD 6 11 NC
CLK 6 7 DOUT
DIN 7 10 DGND
UE12 PACKAGE CLK 8 9 DOUT
12-LEAD (4mm × 3mm) PLASTIC DFN
EXPOSED PAD IS CONNECTED TO V – (PIN 13), GN PACKAGE
MUST BE SOLDERED TO PCB 16-LEAD NARROW PLASTIC SSOP
TJMAX = 125°C, θJA = 160°C/W TJMAX = 150°C, θJA = 120°C/W

ORDER PART DFN PART* ORDER PART GN PART

NUMBER MARKING NUMBER MARKING

LTC6912CGN-1 69121
LTC6912CDE-1 69121 LTC6912IGN-1 6912I1
LTC6912IDE-1 69121 LTC6912HGN-1 6912H1
LTC6912CDE-2 69122 LTC6912CGN-2 69122
LTC6912IDE-2 69122 LTC6912IGN-2 6912I2
LTC6912HGN-2 6912H2
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

6912fa

2
 LTC6912
U U U
GAI SETTI GS A D PROPERTIES
Table 1. LTC6912-1 GAIN SETTINGS AND PROPERTIES
UPPER/LOWER NOMINAL
NIBBLE VOLTAGE GAIN MAXIMUM LINEAR INPUT RANGE (VP-P)
Q7 Q6 Q5 Q4 Dual 5V Single 5V Single 3V NOMINAL INPUT NOMINAL OUTPUT
Q3 Q2 Q1 Q0 Volts/Volt dB Supply Supply Supply IMPEDANCE (kΩ) IMPEDANCE (Ω)
0 0 0 0 0 –120 10 5 3 (Open) 0.4
0 0 0 1 –1 0 10 5 3 10 0.7
0 0 1 0 –2 6 5 2.5 1.5 5 3.4
0 0 1 1 –5 14 2 1 0.6 2 3.4
0 1 0 0 –10 20 1 0.5 0.3 1 3.4
0 1 0 1 –20 26 0.5 0.25 0.15 1 6.4
0 1 1 0 –50 34 0.2 0.1 0.06 1 15
0 1 1 1 –100 40 0.1 0.05 0.03 1 30
1 0 X X 0 –120 10 5 3 (Open) (Open)
1 1 X X Not Used (Note 11) Not Used

Table 2. LTC6912-2 GAIN SETTINGS AND PROPERTIES

UPPER/LOWER NOMINAL
NIBBLE VOLTAGE GAIN MAXIMUM LINEAR INPUT RANGE (VP-P)
Q7 Q6 Q5 Q4 Dual 5V Single 5V Single 3V NOMINAL INPUT NOMINAL OUTPUT
Q3 Q2 Q1 Q0 Volts/Volt dB Supply Supply Supply IMPEDANCE (kΩ) IMPEDANCE (Ω)
0 0 0 0 0 –120 10 5 3 (Open) 0.4
0 0 0 1 –1 0 10 5 3 10 0.7
0 0 1 0 –2 6 5 2.5 1.5 5 3.4
0 0 1 1 –4 12 2.5 1.25 0.75 2.5 3.4
0 1 0 0 –8 18.1 1.25 0.625 0.375 1.25 3.4
0 1 0 1 –16 24.1 0.625 0.3125 0.188 1.25 6.4
0 1 1 0 –32 30.1 0.3125 0.156 0.094 1.25 15
0 1 1 1 –64 36.1 0.156 0.078 0.047 1.25 30
1 0 X X 0 –120 10 5 3 (Open) (Open)
1 1 X X Not Used (Note 11) Not Used

6912fa

3
LTC6912
ELECTRICAL CHARACTERISTICS The ● denotes the specifications that apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VS = 5V, AGND = 2.5V, Gain = 1, RL = 10k to midsupply point, unless
otherwise noted.
C, I GRADES H GRADE
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
Specifications for Both the LTC6912-1 and the LTC6912-2
Total Supply Voltage (VS) ● 2.7 10.5 2.7 10.5 V
Supply Current per Channel Both Amplifiers Active (Gain = 1)
VS = 2.7V, VINA = VINB = VAGND ● 1.75 2.75 1.75 3.0 mA
VS = 5V, VINA = VINB = VAGND ● 2.0 3.0 2.0 3.25 mA
VS = ±5V, VINA = VINB = 0V ● 2.25 3.5 2.25 3.75 mA
Supply Current per Channel Both Amplifiers Inactive (State 1000)
(Software Shutdown) VS = 2.7V, VINA = VINB = VAGND ● 150 255 150 280 µA
VS = 5V, VINA = VINB = VAGND ● 200 325 200 350 µA
VS = ±5V, VINA = VINB = 0V ● 265 750 265 750 µA
Total-Supply Current VS = 2.7V, VSHDN = 2.43V ● 0.3 2 0.3 5 µA
(Hardware Shutdown, VS = 5V, VSHDN = 4.5V ● 3.6 10 3.6 10 µA
GN-16 Package Only) VS = ±5V, VSHDN = 4.5V ● 20 50 20 50 µA
Output Voltage Swing LOW VS = 2.7V, RL = 10k Tied to Midsupply Point ● 12 30 12 35 mV
(Note 4) VS = 2.7V, RL = 500Ω Tied to Midsupply Point ● 60 110 50 125 mV
VS = 5V, RL = 10k Tied to Midsupply Point ● 20 40 20 45 mV
VS = 5V, RL = 500Ω Tied to Midsupply Point ● 100 170 90 190 mV
VS = ±5V, RL = 10k Tied to 0V ● 30 50 30 60 mV
VS = ±5V, RL = 500Ω Tied to 0V ● 190 260 80 290 mV
Output Voltage Swing HIGH VS = 2.7V, RL = 10k Tied to Midsupply Point ● 10 20 10 25 mV
(Note 4) VS = 2.7V, RL = 500Ω Tied to Midsupply Point ● 50 80 50 90 mV
VS = 5V, RL = 10k Tied to Midsupply Point ● 15 30 15 35 mV
VS = 5V, RL = 500Ω Tied to Midsupply Point ● 90 160 80 175 mV
VS = ±5V, RL = 10k Tied to 0V ● 20 40 20 45 mV
VS = ±5V, RL = 500Ω Tied to 0V ● 180 250 180 270 mV
Output Short-Circuit Current VS = 2.7V ● ±27 ±27 mA
(Note 5) VS = ±5V ● ±35 ±35 mA
AGND Open-Circuit Voltage VS = Single 5V Supply, VSHDN = 0.5V ● 2.45 2.5 2.55 2.45 2.5 2.55 V
(GN-16 Package Only) VS = Single 5V Supply, VSHDN = 4.5V 2.65 2.65 V
AGND (Common Mode) VS = Single 2.7V Supply ● 0.55 1.6 0.55 1.6 V
Input Voltage Range VS = Single 5V Supply ● 0.75 3.65 0.75 3.65 V
VS = ±5V ● –4.3 3.2 –4.3 3.2 V
AGND Rejection (i.e., Common VS = 2.7V, VAGND = 1.1V to 1.6V ● 55 80 50 80 dB
Mode Rejection or CMRR) VS = ±5V, VAGND = –2.5V to 2.5V ● 55 75 50 75 dB
Power Supply Rejection Ratio (PSRR) VS =2.7V to ±5V ● 60 80 57 80 dB
Slew Rate Gain = 1
VS = 5V, VOUTA = VOUTB = 1.1V to 3.9V 12 12 V/µs
VS = ±5V, VOUTA = VOUTB = ±1.4V 16 16 V/µs
Gain = 10 (–1), Gain = 8 (–2)
VS = 5V, VOUTA = VOUTB = 1.1V to 3.9V 20 20 V/µs
VS = ±5V, VOUTA = VOUTB = ±1.4V 26 26 V/µs
Signal Attenuation at Gain = 0 Setting Gain = 0 (Digital Inputs 0000), ● –120 –120 dB
f = 200kHz
Signal Attenuation in Software (State = 1000) ● –120 –120 dB
Shutdown

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 LTC6912
ELECTRICAL CHARACTERISTICS The ● denotes the specifications that apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VS = 5V, AGND = 2.5V, Gain = 1, RL = 10k to midsupply point, unless
otherwise noted.
C, I GRADES H GRADE
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
Specifications for Both the LTC6912-1 and the LTC6912-2
SHDN Input High Voltage VS = Single 2.7V ● 2.43 2.43 V
(GN-16 Package Only) VS = Single 5V ● 4.5 4.5 V
VS = ±5V ● 4.5 4.5 V
SHDN Input Low Voltage VS = Single 2.7V ● 0.27 0.27 V
(GN-16 Package Only) VS = Single 5V ● 0.5 0.5 V
VS = ±5V ● 0.5 0.5 V
SHDN Pin 5, Input High Current VS = Single 2.7V 0.2 0.2 µA
(GN-16 Package Only) VS = Single 5V 1 1 µA
VS = ±5V 1 1 µA
SHDN Pin 5, Input Low Current VS = Single 2.7V 0.2 0.2 µA
(GN-16 Package Only) VS = Single 5V 1 1 µA
VS = ±5V 1 1 µA
Specifications for the LTC6912-1 ONLY
Voltage Gain (Note 6) VS = 2.7V, Gain = 1, RL = 10k ● –0.07 0 0.07 –0.08 0 0.07 dB
VS = 2.7V, Gain = 1, RL = 500Ω ● –0.11 –0.02 0.07 –0.13 –0.02 0.07 dB
VS = 2.7V, Gain = 2, RL = 10k ● 5.94 6.01 6.08 5.93 6.01 6.08 dB
VS = 2.7V, Gain = 5, RL = 10k ● 13.85 13.95 14.05 13.8 13.95 14.05 dB
VS = 2.7V, Gain = 10, RL =10k ● 19.7 19.93 20.1 19.65 19.93 20.1 dB
VS = 2.7V, Gain = 10, RL = 500Ω ● 19.55 19.85 20.05 19.35 19.85 20.05 dB
VS = 2.7V, Gain = 20, RL = 10k ● 25.75 25.94 26.1 25.65 25.94 26.1 dB
VS = 2.7V, Gain = 50, RL = 10k ● 33.5 33.8 34.05 33.40 33.8 34.05 dB
VS = 2.7V, Gain = 100, RL = 10k ● 39.2 39.6 40.0 39.0 39.6 40.0 dB
VS = 2.7V, Gain = 100, RL = 500Ω ● 37.3 38.9 39.7 36.20 38.9 39.7 dB
VS = 5V, Gain = 1, RL = 10k ● –0.08 0.01 0.08 –0.09 0.01 0.08 dB
VS = 5V, Gain = 1, RL = 500Ω ● –0.11 –0.01 0.07 –0.13 –0.01 0.07 dB
VS = 5V, Gain = 2, RL = 10k ● 5.95 6.02 6.09 5.94 6.02 6.09 dB
VS = 5V, Gain = 5, RL = 10k ● 13.8 13.96 14.1 13.78 13.96 14.1 dB
VS = 5V, Gain = 10, RL = 10k ● 19.8 19.94 20.1 19.75 19.94 20.1 dB
VS = 5V, Gain = 10, RL = 500Ω ● 19.6 19.87 20.1 19.45 19.87 20.1 dB
VS = 5V, Gain = 20, RL = 10k ● 25.78 25.94 26.08 25.75 25.94 26.08 dB
VS = 5V, Gain = 50, RL = 10k ● 33.5 33.84 34.1 33.4 33.84 34.1 dB
VS = 5V, Gain = 100, RL = 10k ● 39.3 39.7 40.1 39.1 39.7 40.1 dB
VS = 5V, Gain = 100, RL = 500Ω ● 37.75 39.2 39.85 36.6 39.2 39.85 dB
VS = ±5V, Gain = 1, RL = 10k ● –0.06 0.01 0.08 –0.07 0.01 0.08 dB
VS = ±5V, Gain = 1, RL = 500Ω ● –0.10 0 0.08 –0.11 0 0.08 dB
VS = ±5V, Gain = 2, RL = 10k ● 5.95 6.02 6.09 5.94 6.02 6.09 dB
VS = ±5V, Gain = 5, RL = 10k ● 13.8 13.96 14.1 13.79 13.96 14.1 dB
VS = ±5V, Gain = 10, RL = 10k ● 19.78 19.94 20.08 19.75 19.94 20.08 dB
VS = ±5V, Gain = 10, RL = 500Ω ● 19.68 19.91 20.05 19.58 19.91 20.05 dB
VS = ±5V, Gain = 20, RL = 10k ● 25.78 25.95 26.08 25.73 25.95 26.08 dB
VS = ±5V, Gain = 50, RL = 10k ● 33.65 33.87 34.05 33.60 33.87 34.05 dB
VS = ±5V, Gain = 100, RL = 10k ● 39.4 39.8 40.2 39.25 39.8 40.2 dB
VS = ±5V, Gain = 100, RL = 500Ω ● 38.6 39.5 39.9 37.6 39.5 39.9 dB

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LTC6912
ELECTRICAL CHARACTERISTICS The ● denotes the specifications that apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VS = 5V, AGND = 2.5V, Gain = 1, RL = 10k to midsupply point, unless
otherwise noted.
C, I GRADES H GRADE
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
Specifications for the LTC6912-1 ONLY
Channel-to-Channel VS = 2.7V, Gain = 1, RL = 10k ● –0.1 ±0.02 0.1 –0.1 ±0.02 0.1 dB
Voltage Gain Match VS = 2.7V, Gain = 1, RL = 500Ω ● –0.1 ±0.02 0.1 –0.1 ±0.02 0.1 dB
(Note 6) VS = 2.7V, Gain = 2, RL = 10k ● –0.1 ±0.02 0.1 –0.1 ±0.02 0.1 dB
VS = 2.7V, Gain = 5, RL = 10k ● –0.15 ±0.02 0.15 –0.15 ±0.02 0.15 dB
VS = 2.7V, Gain = 10, RL = 10k ● –0.15 ±0.02 0.15 –0.15 ±0.02 0.15 dB
VS = 2.7V, Gain = 10, RL = 500Ω ● –0.15 ±0.02 0.15 –0.2 ±0.02 0.2 dB
VS = 2.7V, Gain = 20, RL = 10k ● –0.15 ±0.02 0.15 –0.15 ±0.02 0.15 dB
VS = 2.7V, Gain = 50, RL = 10k ● –0.15 ±0.02 0.15 –0.15 ±0.02 0.15 dB
VS = 2.7V, Gain = 100, RL = 10k ● –0.2 ±0.02 0.2 –0.2 ±0.02 0.2 dB
VS = 2.7V, Gain = 100, RL = 500Ω ● –1.0 ±0.02 1.0 –1.5 ±0.02 1.5 dB
VS = 5V, Gain = 1, RL = 10k ● –0.1 ±0.02 0.1 –0.1 ±0.02 0.1 dB
VS = 5V, Gain = 1, RL = 500Ω ● –0.1 ±0.02 0.1 –0.1 ±0.02 0.1 dB
VS = 5V, Gain = 2, RL = 10k ● –0.1 ±0.02 0.1 –0.1 ±0.02 0.1 dB
VS = 5V, Gain = 5, RL = 10k ● –0.15 ±0.02 0.15 –0.15 ±0.02 0.15 dB
VS = 5V, Gain = 10, RL = 10k ● –0.15 ±0.02 0.15 –0.15 ±0.02 0.15 dB
VS = 5V, Gain = 10, RL = 500Ω ● –0.15 ±0.02 0.15 –0.15 ±0.02 0.15 dB
VS = 5V, Gain = 20, RL = 10k ● –0.15 ±0.02 0.15 –0.15 ±0.02 0.15 dB
VS = 5V, Gain = 50, RL = 10k ● –0.15 ±0.02 0.15 –0.15 ±0.02 0.15 dB
VS = 5V, Gain = 100, RL = 10k ● –0.2 ±0.02 0.2 –0.2 ±0.02 0.2 dB
VS = 5V, Gain = 100, RL = 500Ω ● –0.8 ±0.02 0.8 –1.2 ±0.02 1.2 dB
VS = ±5V, Gain = 1, RL = 10k ● –0.1 ±0.02 0.1 –0.1 ±0.02 0.1 dB
VS = ±5V, Gain = 1, RL = 500Ω ● –0.1 ±0.02 0.1 –0.1 ±0.02 0.1 dB
VS = ±5V, Gain = 2, RL = 10k ● –0.1 ±0.02 0.1 –0.1 ±0.02 0.1 dB
VS = ±5V, Gain = 5, RL = 10k ● –0.15 ±0.02 0.15 –0.15 ±0.02 0.15 dB
VS = ±5V, Gain = 10, RL = 10k ● –0.15 ±0.02 0.15 –0.15 ±0.02 0.15 dB
VS = ±5V, Gain = 10, RL = 500Ω ● –0.15 ±0.02 0.15 –0.15 ±0.02 0.15 dB
VS = ±5V, Gain = 20, RL = 10k ● –0.15 ±0.02 0.15 –0.15 ±0.02 0.15 dB
VS = ±5V, Gain = 50, RL = 10k ● –0.15 ±0.02 0.15 –0.15 ±0.02 0.15 dB
VS = ±5V, Gain = 100, RL = 10k ● –0.2 ±0.02 0.2 –0.2 ±0.02 0.2 dB
VS = ±5V, Gain = 100, RL = 500Ω ● –0.6 ±0.02 0.6 –0.9 ±0.02 0.9 dB
Gain Temperature Coefficient VS = 5V, Gain = 1, RL = OPEN 2 2 ppm/°C
(Note 6) VS = 5V, Gain = 2, RL = OPEN –1.5 –1.5 ppm/°C
VS = 5V, Gain = 5, RL = OPEN –11 –11 ppm/°C
VS = 5V, Gain = 10, RL = OPEN –30 –30 ppm/°C
VS = 5V, Gain = 20, RL = OPEN –40 –40 ppm/°C
VS = 5V, Gain = 50, RL = OPEN –70 –70 ppm/°C
VS = 5V, Gain = 100, RL = OPEN –140 –140 ppm/°C
Channel-to-Channel Gain VS = 5V, Gain = 1, RL = OPEN 1 1 ppm/°C
Temperature Coefficient Match VS = 5V, Gain = 2, RL = OPEN 1 1 ppm/°C
(Gain Specified in dB’s) VS = 5V, Gain = 5, RL = OPEN 0.2 0.2 ppm/°C
(Note 6) VS = 5V, Gain = 10, RL = OPEN –1 –1 ppm/°C
VS = 5V, Gain = 20, RL = OPEN –1 –1 ppm/°C
VS = 5V, Gain = 50, RL = OPEN –3 –3 ppm/°C
VS = 5V, Gain = 100, RL = OPEN –3 –3 ppm/°C
Channel-to-Channel Isolation f = 200kHz,
(Note 7) VS = 5V, Gain = 1, RL = 10k 113 113 dB
VS = 5V, Gain = 10, RL = 10k 108 108 dB
VS = 5V, Gain = 100, RL = 10k 89 89 dB

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 LTC6912
ELECTRICAL CHARACTERISTICS The ● denotes the specifications that apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VS = 5V, AGND = 2.5V, Gain = 1, RL = 10k to midsupply point, unless
otherwise noted.
C, I SUFFIXES H SUFFIX
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
Specifications for the LTC6912-1 ONLY
Offset Voltage Magnitude Gain = 1 ● 0.125 2 0.125 3.5 mV
(Internal Op-Amp, Note 8)
Offset Voltage Magnitude Gain = 1 ● 0.25 3.5 0.25 6.5 mV
Referred to INA or INB Pins Gain = 10 ● 0.14 2 0.14 4 mV
(Note 8)
Input Offset Voltage Drift, 6 10 µV/°C
Internal Op Amp
DC Input Resistance at DC VINA or VINB = 0V
INA or INB Pins (Note 9) Gain = 0 ● >10 >10 MΩ
State = 8, Software Shutdown ● >10 >10 MΩ
Gain = 1 ● 10 10 kΩ
Gain = 2 ● 5 5 kΩ
Gain = 5 ● 2 2 kΩ
Gain > 5 ● 1 1 kΩ
DC Input Resistance Drift at Gain = 1 85 95 ppm/°C
INA or INB Pins (Note 9) Gain = 2 90 100 ppm/°C
Gain = 5 100 110 ppm/°C
Gain = 10 120 130 ppm/°C
Gain = 20 130 140 ppm/°C
Gain = 50 150 160 ppm/°C
Gain = 100 190 200 ppm/°C
DC Input Resistance Match Gain = 1 ● 10 10 Ω
RINA-RINB Gain = 2 ● 5 5 Ω
Gain = 5 ● 5 5 Ω
Gain > 5 ● 5 5 Ω
DC Small Signal Output Resistance DC VINA or VINB = 0V
at OUT A or OUT B Pins Gain = 0 0.4 0.4 Ω
Gain = 1 0.7 0.7 Ω
Gain = 2 1.0 1.0 Ω
Gain = 5 1.9 1.9 Ω
Gain = 10 3.4 3.4 Ω
Gain = 20 6.4 6.4 Ω
Gain = 50 15 15 Ω
Gain = 100 30 30 Ω
State = 8, Software Shutdown ● >1 >1 MΩ
Gain Bandwidth Product Gain = 100 ● 18 33 50 16 33 50 MHz
Wideband Noise f = 1kHz to 200kHz
(Referred to Input) Gain = 0 (Output Noise only) 8.9 8.9 µVRMS
Gain = 1 15.6 15.6 µVRMS
Gain = 2 11.1 11.1 µVRMS
Gain = 5 8.3 8.3 µVRMS
Gain = 10 7.4 7.4 µVRMS
Gain = 20 7.0 7.0 µVRMS
Gain = 50 6.7 6.7 µVRMS
Gain = 100 6.3 6.3 µVRMS

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LTC6912
ELECTRICAL CHARACTERISTICS The ● denotes the specifications that apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VS = 5V, AGND = 2.5V, Gain = 1, RL = 10k to midsupply point, unless
otherwise noted.
C, I GRADES H GRADE
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
Specifications for the LTC6912-1 ONLY
Voltage Noise Density f = 50kHz
(Referred to Input) Gain = 1 35.6 35.6 nV/√Hz
Gain = 2 24.8 24.8 nV/√Hz
Gain = 5 19.1 19.1 nV/√Hz
Gain = 10 16.7 16.7 nV/√Hz
Gain = 20 16 16 nV/√Hz
Gain = 50 15.4 15.4 nV/√Hz
Gain = 100 15.1 15.1 nV/√Hz
Total Harmonic Distortion Gain = 10, fIN = 10kHz, VOUT = 1VRMS –90 –90 dB
0.003 0.003 %
Gain = 10, fIN = 100kHz, –82 –82 dB
VOUT = 1VRMS 0.008 0.008 %
Specifications for the LTC6912-2 ONLY
Voltage Gain (Note 6) VS = 2.7V, Gain = 1, RL = 10k ● –0.07 0 0.07 –0.08 0 0.07 dB
VS = 2.7V, Gain = 1, RL = 500Ω ● –0.11 –0.02 0.07 –0.13 –0.02 0.07 dB
VS = 2.7V, Gain = 2, RL = 10k ● 5.94 6.01 6.08 5.93 6.01 6.08 dB
VS = 2.7V, Gain = 4, RL = 10k ● 11.9 12.02 12.12 11.88 12.02 12.12 dB
VS = 2.7V, Gain = 8, RL = 10k ● 17.8 18.0 18.15 17.75 18.0 18.15 dB
VS = 2.7V, Gain = 8, RL = 500Ω ● 17.65 17.94 18.15 17.50 17.94 18.15 dB
VS = 2.7V, Gain = 16, RL =10k ● 23.8 24.01 24.25 23.75 24.01 24.25 dB
VS = 2.7V, Gain = 32, RL = 10k ● 29.7 30.0 30.2 29.65 30.0 30.2 dB
VS = 2.7V, Gain = 64, RL = 10k ● 35.4 35.8 36.2 35.15 35.8 36.2 dB
VS = 2.7V, Gain = 64, RL = 500Ω ● 34.15 35.3 36.0 33.40 35.3 36.0 dB
VS = 5V, Gain = 1, RL = 10k ● –0.08 0 0.08 –0.09 0 0.08 dB
VS = 5V, Gain = 1, RL = 500Ω ● –0.1 –0.01 0.08 –0.12 –0.01 0.08 dB
VS = 5V, Gain = 2, RL = 10k ● 5.95 6.02 6.09 5.94 6.02 6.09 dB
VS = 5V, Gain = 4, RL = 10k ● 11.85 12.02 12.15 11.83 12.02 12.15 dB
VS = 5V, Gain = 8, RL = 10k ● 17.85 18.01 18.15 17.83 18.01 18.15 dB
VS = 5V, Gain = 8, RL = 500Ω ● 17.65 17.96 18.15 17.50 17.96 18.15 dB
VS = 5V, Gain = 16, RL = 10k ● 23.85 24.02 24.15 23.80 24.02 24.15 dB
VS = 5V, Gain = 32, RL = 10k ● 29.70 30.02 30.2 29.65 30.02 30.2 dB
VS = 5V, Gain = 64, RL = 10k ● 35.5 35.9 36.25 35.40 35.9 36.25 dB
VS = 5V, Gain = 64, RL = 500Ω ● 34.6 35.6 36.0 33.8 35.6 36.0 dB
VS = ±5V, Gain = 1, RL = 10k ● –0.06 0.01 0.08 –0.07 0.01 0.08 dB
VS = ±5V, Gain = 1, RL = 500Ω ● –0.1 0 0.08 –0.11 0 0.08 dB
VS = ±5V, Gain = 2, RL = 10k ● 5.95 6.02 6.09 5.94 6.02 6.09 dB
VS = ±5V, Gain = 4, RL = 10k ● 11.9 12.03 12.15 11.88 12.03 12.15 dB
VS = ±5V, Gain = 8, RL = 10k ● 17.85 18.02 18.15 17.83 18.02 18.15 dB
VS = ±5V, Gain = 8, RL = 500Ω ● 17.80 17.99 18.15 17.73 17.99 18.15 dB
VS = ±5V, Gain = 16, RL = 10k ● 23.85 24.03 24.15 23.82 24.03 24.15 dB
VS = ±5V, Gain = 32, RL = 10k ● 29.85 30.0 30.2 29.8 30.0 30.20 dB
VS = ±5V, Gain = 64, RL = 10k ● 35.65 36.0 36.20 35.55 36.0 36.20 dB
VS = ±5V, Gain = 64, RL = 500Ω ● 35.15 35.8 36.10 34.45 35.8 36.10 dB

6912fa

8
 LTC6912
ELECTRICAL CHARACTERISTICS The ● denotes the specifications that apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VS = 5V, AGND = 2.5V, Gain = 1, RL = 10k to midsupply point, unless
otherwise noted.
C, I GRADES H GRADE
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
Specifications for the LTC6912-2 ONLY
Channel-to-Channel VS = 2.7V, Gain = 1, RL = 10k ● –0.1 ±0.02 0.1 –0.1 ±0.02 0.1 dB
Voltage Gain Match VS = 2.7V, Gain = 1, RL = 500Ω ● –0.1 ±0.02 0.1 –0.1 ±0.02 0.1 dB
(Note 6) VS = 2.7V, Gain = 2, RL = 10k ● –0.1 ±0.02 0.1 –0.1 ±0.02 0.1 dB
VS = 2.7V, Gain = 4, RL = 10k ● –0.15 ±0.02 0.15 –0.15 ±0.02 0.15 dB
VS = 2.7V, Gain = 8, RL = 10k ● –0.15 ±0.02 0.15 –0.15 ±0.02 0.15 dB
VS = 2.7V, Gain = 8, RL = 500Ω ● –0.15 ±0.02 0.15 –0.2 ±0.02 0.2 dB
VS = 2.7V, Gain = 16, RL = 10k ● –0.15 ±0.02 0.15 –0.15 ±0.02 0.15 dB
VS = 2.7V, Gain = 32, RL = 10k ● –0.15 ±0.02 0.15 –0.15 ±0.02 0.15 dB
VS = 2.7V, Gain = 64, RL = 10k ● –0.2 ±0.02 0.2 –0.2 ±0.02 0.2 dB
VS = 2.7V, Gain = 64, RL = 500Ω ● –0.7 ±0.02 0.7 –1.0 ±0.02 1.0 dB
VS = 5V, Gain = 1, RL = 10k ● –0.1 ±0.02 0.1 –0.1 ±0.02 0.1 dB
VS = 5V, Gain = 1, RL = 500Ω ● –0.1 ±0.02 0.1 –0.1 ±0.02 0.1 dB
VS = 5V, Gain = 2, RL = 10k ● –0.1 ±0.02 0.1 –0.1 ±0.02 0.1 dB
VS = 5V, Gain = 4, RL = 10k ● –0.15 ±0.02 0.15 –0.15 ±0.02 0.15 dB
VS = 5V, Gain = 8, RL = 10k ● –0.15 ±0.02 0.15 –0.15 ±0.02 0.15 dB
VS = 5V, Gain = 8, RL = 500Ω ● –0.15 ±0.02 0.15 –0.15 ±0.02 0.15 dB
VS = 5V, Gain = 16, RL = 10k ● –0.15 ±0.02 0.15 –0.15 ±0.02 0.15 dB
VS = 5V, Gain = 32, RL = 10k ● –0.15 ±0.02 0.15 –0.15 ±0.02 0.15 dB
VS = 5V, Gain = 64, RL = 10k ● –0.15 ±0.02 0.15 –0.15 ±0.02 0.15 dB
VS = 5V, Gain = 64, RL = 500Ω ● –0.6 ±0.02 0.6 –0.8 ±0.02 0.8 dB
VS = ±5V, Gain = 1, RL = 10k ● –0.1 ±0.02 0.1 –0.1 ±0.02 0.1 dB
VS = ±5V, Gain = 1, RL = 500Ω ● –0.1 ±0.02 0.1 –0.1 ±0.02 0.1 dB
VS = ±5V, Gain = 2, RL = 10k ● –0.1 ±0.02 0.1 –0.1 ±0.02 0.1 dB
VS = ±5V, Gain = 4, RL = 10k ● –0.15 ±0.02 0.15 –0.15 ±0.02 0.15 dB
VS = ±5V, Gain = 8, RL = 10k ● –0.15 ±0.02 0.15 –0.15 ±0.02 0.15 dB
VS = ±5V, Gain = 8, RL = 500Ω ● –0.15 ±0.02 0.15 –0.15 ±0.02 0.15 dB
VS = ±5V, Gain = 16, RL = 10k ● –0.15 ±0.02 0.15 –0.15 ±0.02 0.15 dB
VS = ±5V, Gain = 32, RL = 10k ● –0.15 ±0.02 0.15 –0.15 ±0.02 0.15 dB
VS = ±5V, Gain = 64, RL = 10k ● –0.15 ±0.02 0.15 –0.15 ±0.02 0.15 dB
VS = ±5V, Gain = 64, RL = 500Ω ● –0.4 ±0.02 0.4 –0.6 ±0.02 0.6 dB
Gain Temperature Coefficient VS = 5V, Gain = 1, RL = OPEN 2 2 ppm/°C
(Note 6) VS = 5V, Gain = 2, RL = OPEN –4 –4 ppm/°C
VS = 5V, Gain = 4, RL = OPEN –10 –10 ppm/°C
VS = 5V, Gain = 8, RL = OPEN –24 –24 ppm/°C
VS = 5V, Gain = 16, RL = OPEN –30 –30 ppm/°C
VS = 5V, Gain = 32, RL = OPEN –40 –40 ppm/°C
VS = 5V, Gain = 64, RL = OPEN –120 –120 ppm/°C
Channel-to-Channel Gain VS = 5V, Gain = 1, RL = OPEN 0 0 ppm/°C
Temperature Coefficient Match VS = 5V, Gain = 2, RL = OPEN –0.5 –0.5 ppm/°C
(Note 6) VS = 5V, Gain = 4, RL = OPEN 0 0 ppm/°C
VS = 5V, Gain = 8, RL = OPEN 0 0 ppm/°C
VS = 5V, Gain = 16, RL = OPEN –1 –1 ppm/°C
VS = 5V, Gain = 32, RL = OPEN –4 –4 ppm/°C
VS = 5V, Gain = 64, RL = OPEN –4 –4 ppm/°C
Channel-to-Channel Isolation f = 200kHz,
(Note 7) VS = 5V, Gain = 1, RL = 10k 117 117 dB
VS = 5V, Gain = 8, RL = 10k 110 110 dB
VS = 5V, Gain = 64, RL = 10k 92 92 dB
Offset Voltage Magnitude Gain = 1 ● 0.125 2 0.125 3.5 mV
(Internal Op-Amp, Note 8)

6912fa

9
LTC6912
ELECTRICAL CHARACTERISTICS The ● denotes the specifications that apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VS = 5V, AGND = 2.5V, Gain = 1, RL = 10k to midsupply point, unless
otherwise noted.
C, I GRADES H GRADE
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
Specifications for the LTC6912-2 ONLY
Offset Voltage Magnitude Gain = 1 ● 0.25 3.5 0.25 6.5 mV
Referred to INA or INB Pins Gain = 8 ● 0.14 2 0.14 4 mV
(Note 8)
Input Offset Voltage Drift, 6 10 µV/°C
Internal Op Amp
DC Input Resistance at DC VINA or VINB = 0V
INA or INB Pins (Note 9) Gain = 0 ● >10 >10 MΩ
State = 8, Software Shutdown ● >10 >10 MΩ
Gain = 1 ● 10 10 kΩ
Gain = 2 ● 5 5 kΩ
Gain = 4 ● 2.5 2.5 kΩ
Gain > 4 ● 1.25 1.25 kΩ
DC Input Resistance Drift at Gain = 1 85 95 ppm/°C
INA or INB Pins (Note 9) Gain = 2 90 100 ppm/°C
Gain = 4 95 105 ppm/°C
Gain = 8 120 130 ppm/°C
Gain = 16 130 140 ppm/°C
Gain = 32 140 150 ppm/°C
Gain = 64 170 180 ppm/°C
DC Input Resistance Match Gain = 1 ● 10 10 Ω
RINA-RINB Gain = 2 ● 5 5 Ω
Gain = 4 ● 5 5 Ω
Gain > 4 ● 5 5 Ω
DC Small Signal Output Resistance DC VINA or VINB = 0V
at OUT A or OUT B Pins Gain = 0 0.4 0.4 Ω
Gain = 1 0.7 0.7 Ω
Gain = 2 1.0 1.0 Ω
Gain = 4 1.9 1.9 Ω
Gain = 8 3.4 3.4 Ω
Gain = 16 6.4 6.4 Ω
Gain = 32 15 15 Ω
Gain = 64 30 30 Ω
State = 8, Software Shutdown ● >1 >1 MΩ
Gain Bandwidth Product Gain = 64 ● 17 30 50 15 30 50 MHz
Wideband Noise f = 1kHz to 200kHz
(Referred to Input) Gain = 0 (Output Noise Only) 8.1 8.1 µVRMS
Gain = 1 13.8 13.8 µVRMS
Gain = 2 9.6 9.6 µVRMS
Gain = 4 7.5 7.5 µVRMS
Gain = 8 6.4 6.4 µVRMS
Gain = 16 6.0 6.0 µVRMS
Gain = 32 5.8 5.8 µVRMS
Gain = 64 5.6 5.6 µVRMS

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 LTC6912
ELECTRICAL CHARACTERISTICS The ● denotes the specifications that apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VS = 5V, AGND = 2.5V, Gain = 1, RL = 10k to midsupply point, unless
otherwise noted.
C, I GRADES H GRADE
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
Specifications for the LTC6912-2 ONLY
Voltage Noise Density f = 50kHz
(Referred to Input) Gain = 1 31.1 31.1 nV/√Hz
Gain = 2 22.8 22.8 nV/√Hz
Gain = 4 17 17 nV/√Hz
Gain = 8 14.6 14.6 nV/√Hz
Gain = 16 13.2 13.2 nV/√Hz
Gain = 32 12.9 12.9 nV/√Hz
Gain = 64 12.6 12.6 nV/√Hz
Total Harmonic Distortion Gain = 8, fIN = 10kHz, VOUT = 1VRMS –84 –84 dB
0.006 0.006 %
Gain = 8, fIN = 100kHz, VOUT = 1VRMS –82 –82 dB
0.008 0.008 %

U U
SERIAL I TERFACE SPECIFICATIO S
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Digital I/O Logic Levels, All Digital I/O Voltage Referenced to DGND
VIH Digital Input High Voltage ● 2 V
VIL Digital Input Low Voltage ● 0.8 V
VOH Digital Output High Voltage Sourcing 500µA ● V+ – 0.3 V
VOL Digital Output Low Voltage Sinking 500µA ● 0.3 V
Serial Interface Timing, V + = 2.7V ~ 4.5V, V – = 0V (Note 10)
t1 DIN Valid to CLK Setup ● 60 ns
t2 DIN Valid to CLK Hold ● 0 ns
t3 CLK Low ● 100 ns
t4 CLK High ● 100 ns
t5 CS/LD Pulse Width ● 60 ns
t6 LSB CLK to CS/LD ● 60 ns
t7 CS/LD Low to CLK ● 30 ns
t8 DOUT Output Delay CL = 15pF ● 125 ns
t9 CLK Low to CS/LD Low ● 0 ns
Serial Interface Timing, V + = 4.5V ~ 5.5V, V – = 0V (Note 10)
t1 DIN Valid to CLK Setup ● 30 ns
t2 DIN Valid to CLK Hold ● 0 ns
t3 CLK Low ● 50 ns
t4 CLK High ● 50 ns
t5 CS/LD Pulse Width ● 40 ns
t6 LSB CLK to CS/LD ● 40 ns
t7 CS/LD Low to CLK ● 20 ns
t8 DOUT Output Delay CL = 15pF ● 85 ns
t9 CLK Low to CS/LD Low ● 0 ns
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LTC6912
U U
SERIAL I TERFACE SPECIFICATIO S
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Serial Interface Timing, Dual ±4.5V ~ ±5.5V Supplies (Note 10)
t1 DIN Valid to CLK Setup ● 30 ns
t2 DIN Valid to CLK Hold ● 0 ns
t3 CLK High ● 50 ns
t4 CLK Low ● 50 ns
t5 CS/LD Pulse Width ● 40 ns
t6 LSB CLK to CS/LD ● 40 ns
t7 CS/LD Low to CLK ● 20 ns
t8 DOUT Output Delay CL = 15pF ● 85 ns
t9 CLK Low to CS/LD Low ● 0 ns

t1 t2 t4 t3 t6 t7

CLK
t9

DIN D3 D2 D31 D0 D7 • • • D4 D3
t5

CS/LD
t8

DOUT D4 D3 D2 D31 D0 D7 • • • D4 D3

PREVIOUS BYTE CURRENT BYTE 6912 TD

Note 1: Absolute Maximum Ratings are those values beyond which the life Note 7: Channel-to-channel isolation is measured by applying a 200kHz
of the device may be impaired. input signal to one channel so that its output varies 1VRMS, and measuring
Note 2: The LTC6912-1C and LTC6912-1I are guaranteed functional over the output voltage RMS of the other channel relative to AGND with its
the operating temperature range of –40°C to 85°C. The LTC6912-1H is input tied to AGND. Isolation is calculated:
guaranteed functional over the operating temperature range of –40°C to IsolationB = 20 • log10(VOUTA/VOUTB) or
125°C. IsolationA = 20 • log10(VOUTB/VOUTA)
Note 3: The LTC6912-1C is guaranteed to meet specified performance High channel-to-channel isolation is strongly dependent on proper circuit
from 0°C to 70°C. The LTC6912-1C is designed, characterized and layout. See Applications Information.
expected to meet specified performance from – 40°C to 85°C but is not Note 8: Offset voltage referred to the INA or INB input is (1 + 1/|GAIN|)
tested or QA sampled at these temperatures. The LTC6912-1I is times the offset voltage of the internal op amp, where GAIN is the nominal
guaranteed to meet specified performance from –40°C to 85°C. The gain magnitude. The typical offset voltage values are for 25°C only. See
LTC6912-1H is guaranteed to meet specified performance from –40°C to Applications Information.
125°C. Note 9: Input resistance can vary by approximately ±30% part-to-part at a
Note 4: Output voltage swings are measured as differences between the given gain setting.
output and the respective supply rail. Note 10: Guaranteed by design, not subject to test.
Note 5: Extended operation with output shorted may cause junction Note 11: States 13, 14 and 15 (binary 11xx) are not used. Programming a
temperature to exceed the 150°C limit for GN package and 125°C for a channel to states 8 or higher will configure that particular channel into a
DFN package is not recommended. low power shutdown state. In addition, programming a channel into
Note 6: Gain is measured with a large signal DC test using an output state 15 (binary 1111) will cause that particular channel to draw up to
excursion between approximately 30% and 70% of supply voltage. 20mA of supply current and is not recommended.

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 LTC6912
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC6912-1 Channel Gain LTC6912-1 –3dB Bandwidth vs
LTC6912-1 Frequency Response Matching vs Frequency Gain Setting
50 0.10 6
VS = ±5V VS = ±5V VIN = 10mVRMS

CHANNEL-TO-CHANNEL GAIN MATCH (dB)

VIN = 10mVRMS VIN = 10mVRMS
GAIN OF 100
40 0.05
GAIN OF 50 GAIN OF 100

–3dB FREQUENCY (MHz)

GAIN OF 1
30 0 VS = ±5V
GAIN OF 20 GAIN OF 10
GAIN (dB)

1
GAIN OF 10
20 –0.05 VS = 2.7V
GAIN OF 5
10 –0.10
GAIN OF 2
GAIN OF 1
0 –0.15

–10 –0.20 0.1

1 10 100 1000 10000 1 10 100 1000 10000 1 10 100
FREQUENCY (kHz) FREQUENCY (Hz) GAIN (V/V)
6912 G01 6912 G02 6912 G03

LTC6912-1 Channel Isolation vs LTC6912-1 Power Supply LTC6912-1 Noise Density vs

Frequency Rejection vs Frequency Frequency
125 90 100
VS = ±5V VS = 5V
CHANNEL-TO-CHANNEL ISOLATION (dB)

120 VOUT = 1VRMS 80 GAIN = 1

VOLTAGE NOISE DENSITY (nV/√HZ)

GAIN OF 1
115 GAIN OF 1 70
GAIN OF 10
110 60
REJECTION (dB)

+SUPPLY
GAIN OF 10 GAIN OF 100
105 50
–SUPPLY 10
100 40

95 30
GAIN OF 100
90 20
VS = ±2.5V
85 10 TA = 25°C
INPUT REFERRED
80 0 1
100 1000 1 10 100 1000 10000 1 10 100
FREQUENCY (kHz) FREQUENCY (kHz) FREQUENCY (kHz)
6912 G04 6912 G05 6912 G06

LTC6912-1 Distortion vs LTC6912-1 Distortion vs LTC6912-1 THD Plus Noise vs

Frequency with Light Loading Frequency with Heavy Loading Input Voltage
–50 –30 –30
THD-AMPLITUDE BELOW FUNDAMENTAL (dB)

THD-AMPLITUDE BELOW FUNDAMENTAL (dB)

RL = 10k
V = ±2.5V GAIN OF 100 GAIN OF 100
–55 S –40
VOUT = 1VRMS (2.83)VP-P –40
–60
THD PLUS NOISE (dB)

–50
–50
–65 GAIN OF 10
GAIN OF 100 –60
GAIN
–70 –60 OF 10
–70
–75
GAIN OF 10 –70 GAIN OF 1
–80
–80 VS = ±5V
GAIN OF 1 RL = 500Ω
–85
–80
VS = ±2.5V –90 RL = 10k
fIN = 1kHz GAIN OF 1
VOUT = 1VRMS (2.83)VP-P BW = 22kHz
–90 –90 –100
0 50 100 150 200 0 50 100 150 200 0.001 0.01 0.1 1 10
FREQUENCY (kHz) FREQUENCY (kHz) INPUT VOLTAGE (VP-P)
6912 G07 6912 G08 6912 G09

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 LTC6912
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TYPICAL PERFOR A CE CHARACTERISTICS
LTC6912-1 Hardware Shutdown LTC6912-1 Software Shutdown LTC6912-1 Total Supply Current
Total Supply Current vs Total Supply Current vs vs Temperature (Both Amplifiers
Temperature Temperature Active)
700 5.00
HARDWARE SHUTDOWN (GN-16 ONLY) BOTH AMPLIFIERS IN BOTH AMPLIFIERS
SOFTWARE SHUTDOWN 4.75 PROGRAMMED TO GAIN = 1 VS = ±5V
VS = ±5V
600 RL = 10k RL = 10k

TOTAL SUPPLY CURRENT (mA)

TOTAL SUPPLY CURRENT (µA)
TOTAL SUPPLY CURRENT (µA)

VS = ±5V
10 4.50
500
VS = 5V 4.25
VS = 5V
400 VS = 5V 4.00

1 VS = 2.7V 3.75
VS = 3V 300 VS = 2.7V
3.50
VS = 2.7V
200
3.25

0.1 100 3.00

–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
6912 G10 6912 G11 6912 G12

LTC6912-1 Gain Shift vs LTC6912-1 Gain Shift vs LTC6912-2

Temperature (Light Load) Temperature (Heavy Load) Frequency Response
0.10 0.5 40
VS = 5V VS = 5V GAIN OF 64 VS = ±5V
RL = 10k RL = 500Ω VIN = 10mVRMS
0.05 GAIN OF 32
GAIN OF 1 30
GAIN OF 1 0
0 GAIN OF 16
GAIN CHANGE (dB)
GAIN CHANGE (dB)

GAIN OF 10
GAIN (dB) 20 GAIN OF 8
–0.05 GAIN OF 10
–0.5
GAIN OF 4
–0.10
10
GAIN OF 100 GAIN OF 100 GAIN OF 2
–0.15
–1.0 GAIN OF 1
0
–0.20

–0.25 –1.5 –10

–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 1 10 100 1000 10000
TEMPERATURE (°C) TEMPERATURE (°C) FREQUENCY (kHz)
6912 G13 6912 G14 6912 G14a

LTC6912-2 Channel Gain LTC6912-2 –3dB Bandwidth vs LTC6912-2 Channel Isolation vs

Matching vs Frequency Gain Setting Frequency
0.100 8.0 125
VS = ±5V VS = ±5V VIN = 10mVRMS GAIN = 1 VS = 5V
CHANNEL-TO-CHANNEL GAIN MATCH (dB)

CHANNEL-TO-CHANNEL ISOLATION (dB)

VIN = 10mVRMS 6.0 120 VOUT = 1VRMS

0.075
RL = 10kΩ VS = 2.7V
4.0 115
0.050
–3dB FREQUENCY (MHz)

110
0.025 GAIN OF 1 GAIN = 8
2.0 105
0 GAIN OF 8
100
–0.025 GAIN OF 64 GAIN = 64
95
1.0
–0.050 0.8 90
–0.075 0.6 85

–0.100 0.4 80
1 10 100 1000 10000 1 10 100 100 1000
FREQUENCY (kHz) GAIN (V/V) FREQUENCY (kHz)
6912 G16 6912 G17
6912 G15

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 LTC6912
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TYPICAL PERFOR A CE CHARACTERISTICS
LTC6912-2 Distortion vs
LTC6912-2 Power Supply LTC6912-2 Noise Density vs Frequency with Light Loading
Rejection vs Frequency Frequency (RL = 10k)
90 100 –50

THD (AMPLITUDE BELOW FUNDAMENTAL) (dB)

VS = 5V VS = ±2.5V VS = ±2.5V
80 GAIN = 1 TA = 25°C VOUT = 1VRMS (2.83VP-P)
–55

VOLTAGE NOISE DENSITY (nV/Hz)

INPUT REFERRED
GAIN = 1
70
–60
60
REJECTION (dB)

GAIN = 8 –65 GAIN = 64

+SUPPLY
50
–SUPPLY 10 GAIN = 64 –70
40
–75 GAIN = 8
30
–80 GAIN = 1
20

10 –85

0 1 –90
1 10 100 1000 10000 1 10 100 0 50 100 150 200
FREQUENCY (kHz) FREQUENCY (kHz) FREQUENCY (kHz)
6912 G19 6912 G20
6912 G18

LTC6912-2 Distortion vs LTC6912-2 Hardware Shutdown

Frequency with Heavy Loading LTC6912-2 THD + Noise vs Total Supply Current vs
(RL = 500Ω) Input Voltage Temperature
–30 –30
THD (AMPLITUDE BELOW FUNDAMENTAL) (dB)

VS = ±2.5V HARDWARE SHUTDOWN (GN-16 ONLY)

VOUT = 1VRMS (2.83VP-P) VS = ±5V
–40 –40

TOTAL SUPPLY CURRENT (µA)

GAIN = 64 10
–50
THD + NOISE (dB)

–50 GAIN = 64
VS = 5V
GAIN = 8 –60
–60 GAIN = 8
–70
GAIN = 1 1
–70 GAIN = 1 VS = 3V
–80
VS = 2.7V
–80 VS = 5V
–90
RL = 10k
fIN = 1kHz
–90 –100 0.1
0 50 100 150 200 0.001 0.01 0.1 1 10 –50 –25 0 25 50 75 100 125
FREQUENCY (kHz) INPUT VOLTAGE (VP-P) TEMPERATURE (°C)
6912 G21 6912 G22
6912 G22A

LTC6912-2 Software Shutdown LTC6912-2 Total Supply Current

Total Supply Current vs vs Temperature (Both Amplifiers LTC6912-2 Gain Shift vs
Temperature Active) Temperature (Light Load)
800 6.0 0.100
BOTH AMPLIFIERS BOTH AMPLIFIERS VS = 5V
PROGRAMMED TO STATE = 8 ACTIVE : GAIN = 1 0.075
700 R = 10k RL = 10k
L 5.5 RL = 10k 0.050
TOTAL SUPPLY CURRENT (mA)
TOTAL SUPPLY CURRENT (A)

VS = 5V VS = ±5V
0.025
600 GAIN = 1
GAIN CHANGE (dB)

5.0 0
500 VS = 5V –0.025
VS = 5V 4.5 –0.050 GAIN = 8
400 –0.075
VS = 2.7V VS = 2.7V
4.0 –0.100
300
–0.125
GAIN = 64
200 3.5 –0.150
–0.175
100 3.0 –0.200
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
6912 G23 6912 G24 6912 G25

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LTC6912
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC6912-2 Gain Shift vs
Temperature (Heavy Load)
0.25
VS = 5V
RL = 500
GAIN = 1
0

GAIN = 8

GAIN CHANGE (dB)

–0.25

GAIN = 64
–0.50

–0.75

–1.00
–50 –25 0 25 50 75 100 125
TEMPERATURE (°C)
6912 G26

U U U
PI FU CTIO S
INA, INB: Analog Inputs. The input signal to the A channel In single supply voltage applications, the LTC6912-X’s DC
amplifier of the LTC6912-X is the voltage difference be- ground reference for both input and output is AGND, not
tween the INA pin and AGND pin. Likewise, the input signal V –. With increasing gains, the LTC6912-X’s input voltage
to the B channel amplifier of the LTC6912-X is the voltage range for an unclipped output is no longer rail-to-rail but
difference between the INB pin and AGND pin. The INA (or diminishes inversely to gain, centered about the AGND
INB) pin connects internally to a digitally controlled resis- potential.
tance whose other end is a current summing point at the
same potential as the AGND pin (Figure 1). At unity gain, NC 1 16 NC

the value of this input resistance is approximately 10kΩ INA 2

and the INA (or INB) pin voltage range is rail-to-rail (V+ to INPUT R ARRAY
V–). At gain settings above unity, the input resistance falls.
FEEDBACK R ARRAY
V+

The linear input range at INA and INB also falls inversely 100k MOS INPUT
–
15 OUT A
+
proportional to the programmed gain. Tables 1 and 2 AGND 3
OP AMP
14 V –
MOS INPUT
summarize this behavior. The higher gains are designed to 100k OP AMP
+
13 OUT B
–
boost lower level signals with good noise performance. In V–
the “zero” gain state (state = 0), or in software shutdown
(state = 8) analog switches disconnect the INA or INB pin INB 4 12 V+

internally and this pin presents a very high input resis- INPUT R ARRAY FEEDBACK R ARRAY
tance. In the “zero” gain state (state = 0), the input may CHANNEL A CHANNEL B 11 NC

vary from rail to rail but the output is insensitive to it and LOWER UPPER
8-BIT
is forced to the AGND potential. Circuitry driving the INA NIBBLE
LATCH
NIBBLE 10 DGND
V+
and INB pins must consider the LTC6912-X’s input resis-
DOUT
tance, its process variance, and the variation of this 9

resistance from gain setting to gain setting. Signal sources SHDN 5

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

with significant output resistance may introduce a gain CS/LD 6 8-BIT

SHIFT-REGISTER
error as the source’s output resistance and the LTC6912- DATA 7
CLK 8
X’s input resistance forms a voltage divider. This is espe-
cially true at higher gain settings where the input resis- 6912 BD

tance is the lowest. Figure 1. GN-16 Block Diagram

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 LTC6912
U U U
PI FU CTIO S
AGND: Analog Ground. The AGND pin is at the midpoint of asymmetrical supply, however, it is often desirable to refer
an internal resistive voltage divider, developing a potential the LTC6912-X’s analog input and output to a voltage
halfway between the V + and V – pins. In normal operation, equidistant from the two supply rails V + and V –. The AGND
the AGND pin has an equivalent input resistance of nomi- pin will provide such a potential when open-circuited and
nally 50k (Figure 1). In order to reduce the quiescent bypassed with a capacitor (Figure 4). In noise sensitive
supply current in hardware shutdown (SHDN pin pulled to applications where AGND does not tie directly to a ground
V +, GN-16 only), the equivalent series resistance of this plane, as in Figures 2 and 4, it is important to AC-bypass
pin significantly increases (to a value on the order of the AGND pin. Otherwise channel to channel isolation is
800kΩ with 5V supplies, but is highly supply voltage, degraded, and wideband noise will enter the signal path
temperature, and process dependent). AGND is the from the thermal noise of the internal voltage divider
noninverting input to both the internal channel A and resistors which present a Thévenin equivalent resistance
channel B amplifiers. This makes AGND the ground refer- of approximately 50kΩ. This noise can reduce SNR by at
ence voltage for the INA, INB, OUTA, and OUTB pins. least 15dB at high gain settings. An external capacitor
Recommended analog ground plane connection depends from AGND to the ground plane, whose impedance is well
on how power is applied to the LTC6912-X (See Figures 2, below 50kΩ at frequencies of interest, will filter and
3, and 4). Single power supply applications typically use suppress this noise. A 0.1µF high quality capacitor is
V – for the system signal ground. The analog ground plane effective for frequencies down to 1kHz. Larger capacitors
in single-supply applications should therefore tie to V –, will extend this suppression to lower frequencies. This
and the AGND pin should be bypassed to this ground plane issue does not arise in dual supply applications because
by a high quality capacitor of at least 0.1µF (Figure 2). The the AGND pin ties directly to ground. In applications
AGND pin provides an internal analog reference voltage at requiring an analog ground reference other than half the
half the V+ supply voltage. Dual supply applications with total supply voltage, the user can override the built-in
symmetrical supplies (such as ±5V) have a natural system analog ground reference by tying the AGND pin to a
ground plane potential of zero volts, in which the AGND pin reference voltage with the AGND voltage range specified in
can be directly tied to, making the zero volt ground plane the Electrical Characteristics Table. The AGND pin will load
the input and output reference voltage for the LTC6912-X the external reference with approximately 50kΩ returned
(Figure 3). Finally, if dual asymmetrical power supplies are to the half-supply potential. AGND should still be capaci-
used, the supply ground is still the natural ground plane tively bypassed to a ground plane as noted above. Do not
voltage. To maximize signal swing capability with an connect the AGND pin to the V – pin.

ANALOG GROUND PLANE ANALOG GROUND PLANE

V+
REFERENCE 1 16 1 16
2
2 15 2 15
≥0.1µF LTC6912-X LTC6912-X 0.1µF
3 14 3 14 V –
SINGLE-POINT 4 13
4 13 0.1µF
0.1µF SYSTEM GND SINGLE-POINT
5 12 5 12 V +
V+ SYSTEM GND
6 11 6 11
SERIAL 7 10 SERIAL 7 10
INTERFACE INTERFACE
8 9 8 9

DIGITAL GROUND PLANE DIGITAL GROUND PLANE

6912 F02 6912 F03

Figure 2. Single Supply Ground Plane Connection Figure 3. Symmetrical Dual Supply Ground Plane Connection

6912fa

17
LTC6912
U U U
PI FU CTIO S
ANALOG GROUND PLANE
V+ + V–
DIN: TTL/CMOS Compatible Logic Serial Data Input. The
REFERENCE 1 16
2 serial interface is synchronously loaded MSB first via DIN
≥0.1µF 2 15
3
LTC6912-X
14 V –
0.1µF on the rising edge of CLK with CS/LD asserted low.
4 13 0.1µF
SINGLE-POINT
CLK: TTL/CMOS Compatible Logic Input. With CS/LD
5 12 V +
SYSTEM GND asserted low, the clock synchronizes the loading of the
6 11
SERIAL 7 10
serial shift register on its rising and falling edges. Data is
INTERFACE
8 9 shifted in at DIN on the rising edge of CLK and is shifted out
on DOUT on the falling edge of CLK.
DIGITAL GROUND PLANE
6912 F04 DOUT: TTL/CMOS Compatible Logic Output. The MSB of
Figure 4. Asymmetrical Dual Supply Ground Plane Connection the shift register contents is shifted out at DOUT on the
falling edge of CLK. The output at DOUT swings between V+
SHDN (GN-16 ONLY): CMOS Compatible Logic Hardware and DGND, and is rated to drive approximately 15pF.
Shutdown Input. The LTC6912-X has two shutdown modes. DGND: Digital Ground: The DGND pin defines the potential
One is a software shutdown state which can be software from which LOGIC levels VIH and VIL for the 3-wire serial
programmed into either Channel A, Channel B, or both. digital interface are referenced. The recommended con-
The software shutdown, when programmed to a particular nection of DGND depends on how power is applied to the
channel (state = 8), will disable that channel’s amplifier LTC6912 (See Figures 2, 3, and 4). (CAVEAT: Under no
and tri-state open its analog input and analog output. The conditions is DGND to exceed either supply pins V + and
serial interface, however is still active. A hardware shut- V –, which could result in damage to the IC if not current
down occurs when the SHDN pin is pulled to the positive limited.)
rail. In this condition, both amplifiers and serial interface
Single power supply applications typically use V – for the
are disabled. The SHDN pin is allowed to swing from V – to
system signal ground. The preferred connection for DGND
10.5V above V –, regardless of V+ so long as the logic levels
is therefore V – (See Figure 2).
meet the minimum requirements specified in the Electrical
Characteristics table. The SHDN pin is a high impedance Dual supply applications with symmetrical supplies (such
CMOS logic input, but has a small pull-down current as ±5V) have a natural system ground potential of zero
source (<10µA) which will force SHDN low if the logic volts, in which the DGND pin can be tied to, making the
input is externally floated. On initial power up (with SHDN zero volt ground plane the logic reference (Figure 3).
open), or coming out of the hardware shutdown mode Finally, if dual asymmetrical power supplies are used, the
(pulling SHDN to V –), both amplifiers are reset into the system ground is still the natural ground plane voltage.
power-on reset state (software shutdown mode, state = 8)
for both channels. V–, V+: Power Supply Pins. The V + and V – pins should be
bypassed with 0.1µF capacitors to an adequate analog
CS/LD: TTL/CMOS Compatible Logic Input. When this pin ground plane using the shortest possible wiring. Electri-
is asserted low, the CLK pin is enabled, and the 8-bit shift cally clean supplies and a low impedance ground are
register serially shifts the shift register contents and important for the high dynamic range available from the
whatever data is present on the DIN pin into the shift LTC6912 (see further details under the AGND pin descrip-
register on the rising edge of CLK. On the rising edge of tion). Low noise linear power supplies are recommended.
CS/LD, the contents of the shift register data are loaded Switching power supplies require special care to prevent
into the eight bit latch which configures the gain state of switching noise coupling into the signal path, reducing
both channel A and channel B amplifiers. A logic high on dynamic range.
CS/LD inhibits the CLK signal internally to the IC.

6912fa

18
 LTC6912
U U U
PI FU CTIO S
OUT A, OUT B: Analog Output. These pins are the output Output current above 10mA is possible but current-limit-
of the A and B channel amplifiers respectively. Each ing circuitry will begin to affect amplifier performance at
operational amplifier can swing rail-to-rail (V + to V –) as approximately 20mA. Long-term operation above 20mA
specified in the Electrical Characteristics table. For best output is not recommended. Do not exceed maximum
performance, loading the output as lightly as possible will junction temperature of 150°C for a GN and 125°C for a
minimize signal distortion and gain error. The Electrical DFN package. The output will drive capacitive loads up to
Characteristics table shows performance at output cur- 50pF. Capacitances higher than 50pF should be isolated
rents up to 10mA, and the current limits which occur when by a series resistor (10Ω or higher).
the output is shorted midsupply at 2.7V and ±5V supplies.

U U W U
APPLICATIO S I FOR ATIO
Functional Description Description of the 3-Wire SPI Interface
The LTC6912-X is a small outline, wideband, inverting Gain control of each amplifier is independently program-
two-channel amplifier with voltage gains that are indepen- mable using the 3-wire SPI interface (see Figure 5). Logic
dently programmable. Each delivers a choice of eight levels for the LTC6912 3-wire serial interface are TTL/
voltage gains, configurable through a 3-wire serial digital CMOS compatible. When CS/LD is low, the serial data on
interface, which accepts TTL or CMOS logic levels (See DIN is shifted into an 8-bit shift-register on the rising edge
Figure 5). Tables 1 and 2 list the nominal gains for the of the clock, with the MSB transferred first. Serial data on
LTC6912-1 and LTC6912-2 respectively. Gain control DOUT is shifted out on the clock’s falling edge. A rising edge
within the amplifier occurs by switching resistors from a on CS/LD will latch the shift-register’s contents into an 8-
matched array in or out of a closed-loop op amp circuit bit D-latch and disable the clock internally on the IC. The
using MOS analog switches (Figure 1). The bandwidths of upper nibble of the D-latch (4 most significant bits),
the individual amplifiers depend on gain setting. The configure the gain for the B-channel amplifier. The lower
Typical Performance Characteristics section shows mea- nibble of the D-latch (4 least significant bits), configures
sured frequency responses. the gain for the A-channel amplifier. Tables 1 and 2 detail
the nominal gains and respective gain codes. Care must be
CHANNEL A CHANNEL B taken to ensure CLK is taken low before CS/LD is pulled
low to avoid an extra internal clock pulse to the input of the
RESET
8-BIT LATCH
8-bit shift-register (See Figure 5).
LE
LOWER NIBBLE UPPER NIBBLE
DOUT is active in all states, therefore DOUT cannot be
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
“wire-OR’d” to other SPI outputs.
DIN LSB MSB
An LTC6912 may be daisy-chained with other LTC6912s
CLK
8-BIT
SHIFT-REGISTER DOUT
or other devices having serial interfaces by connecting the
CS/LD
SHDN
DOUT to the DIN of the next chip while CLK and CS/LD
RESET 6912 F05 remain common to all chips in the daisy chain. The serial
data is clocked to all the chips then the CS/LD signal is
Figure 5. Serial Digital Interface Block Diagram pulled high to update all of them simultaneously. Figure 6
shows an example of two LTC6912s in a daisy chained SPI

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19
LTC6912
U U W U
APPLICATIO S I FOR ATIO
configuration. It is recommended the serial interface sig- Timing Constraints
nals should remain idle in between data transfers in order Settling time in the CMOS gain-control logic is typically
to minimize digital noise coupling into the analog path. several nanoseconds and is faster than the analog signal
path. When the amplifier gain changes, the limiting timing
Power On Reset
is analog. As with any programmable-gain amplifier, each
On the initial application of power, the power on reset gain change causes an output transient as the amplifier’s
state of both amplifiers is low power software shutdown output moves, with finite speed, toward a differently
(state = 8) (see Tables 1 and 2). In this state, both analog scaled version of the input signal. The LTC6912-X analog
amplifiers are disabled and have their inputs and outputs path settles with a characteristic time constant or time
opened. This will facilitate the application of using the scale, τ, that is roughly the standard value for a first order
device as a 2:1 analog MUX, in that the amplifier’s outputs band limited response:
may be wired-OR together and the LTC6912 can alter-
τ = 0.35/f–3dB
nately select between A and B channels. Care must be
taken if the outputs are wired-OR’d to ensure the software See the –3dB BW vs Gain Setting graph in the Typical
shutdown state (state = 8) is always programmed in one Performance Characteristics section.
of the two channels.

ANALOG GROUND PLANE

1 16 1 16
SINGLE-POINT 2 15 2 15
SYSTEM GND LTC6912-X 0.1µF LTC6912-X 0.1µF
3 14 V – 3 14 V –
4 13 4 13
0.1µF 0.1µF
5 12 V + 5 12 V +
SHDN SHDN
CS/LD 6 11 6 11
CS/LD CS/LD
DATA 7 10 7 10
µP DIN DGND DIN DGND
CLK 8 9 8 9
DOUT DOUT

DIGITAL GROUND PLANE

CLK

DIN D15 D11 D10 D9 D8 D7 D3 D2 D1 D0

CS/LD
6912 F06

Figure 6. Two LTC6912s (Four PGAs) in Daisy Chain Configuration

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20
 LTC6912
U U W U
APPLICATIO S I FOR ATIO
Offset Voltage vs Gain Setting Note that operating the LTC6912 family in “zero” gain
The electrical tables list DC offset (error), VOS(OA), at the mode (digital state 0000) open circuits both the INA and
inputs of the internal op amp (See Figure 1). The electrical INB pins and this demands some care if employed with a
tables also show the resulting, gain dependent offset series AC coupling input capacitor. When the chip enters
voltage referred to the INA, or INB pins, VOS(IN). The two the zero gain mode, the opened INA or INB pin tends to
measures are related through the feedback/input resistor sample and freeze the voltage across the capacitor to the
ratio, which equals the nominal gain-magnitude setting, value it held just before the zero gain state. This can place
|GAIN|: the INA or INB pin at or near the DC potential of a supply
rail. (The INA or INB pin may also drift to a supply potential
VOS(IN) = (1 + 1/|GAIN|) VOS(OA) in this state due to small leakage currents.) To prevent
Offset voltages at any gain setting can be inferred from this driving the INA or INB pin outside the supply limit and
relationship. For example, an internal amplifier offset potentially damaging the chip, avoid AC input signals in
VOS(OA) of 1mV will appear referred to the INA, INB pins as the zero gain state with an AC coupling capacitor. Also,
2mV at a gain setting of 1, or 1.5mV at a gain setting of 2. switching later to a non-zero gain value will cause a
At high gains, VOS(IN) approaches VOS(OA). (Offset voltage transient pulse at the output of the LTC6912-1 (with a time
is random and can have either polarity centered on 0V). constant set by the capacitor value and the new LTC6912-1
The MOS input circuitry of the internal op amp in Figure 1 input resistance value). This occurs because the INA and
draws negligible input currents (less than 10µA), so only INB pins return to the AGND potential forcing transient
VOS(OA) and the GAIN affect the overall amplifier’s offset. current sourced by the amplifier output to charge the AC
coupling capacitor to its proper DC blocking value.
AC-Coupled Operation
SNR and Dynamic Range
Adding capacitors in series with the INA and INB pins
converts the LTC6912-X into a dual AC-coupled inverting The term “dynamic range” is much used (and abused)
amplifier, suppressing the input signal’s DC level (and also with signal paths. Signal-to-noise (SNR) is an unambigu-
adding the additional benefit of reducing the offset voltage ous comparison of signal and noise levels, measured in
from the LTC6912-X’s amplifier itself). No further compo- the same way and under the same operating conditions. In
nents are required because the input of the LTC6912-X a variable gain amplifier, however, further characterization
biases itself correctly when a series capacitor is added. is useful because both noise and maximum signal level in
The INA and INB analog input pins connect internally to a the amplifier will vary with the gain setting, in general. In
resistor whose nominal value varies between 10kΩ and the LTC6912-X, maximum output signal is independent of
1kΩ depending on the version of LTC6912 used (see the gain (and is near the full power supply voltage, as detailed
rightmost column of Tables 1 and 2). Therefore, the low in the swing sections of the Electrical Characteristics
frequency cutoff will vary with capacitor and gain setting. table). The maximum input level falls with increasing gain,
If, for example, a low frequency corner of 1kHz (or lower) and the input-referred noise falls as well (listed also in the
on the LTC6912-1 is desired, use a series capacitor of table). To summarize the useful signal range in such an
0.16µF or larger. 0.16µF has a reactance of 1kΩ at 1kHz, amplifier, we define dynamic range (DR) as the ratio of
giving a 1kHz lower –3dB frequency for gain settings of maximum input (at unity gain) to minimum input-referred
10V/V through 100V/V. If the LTC6912-1 is operated at noise (at maximum gain). This DR has a physical interpre-
lower gain settings with a 0.16µF capacitor, the higher tation as the range of signal levels that will experience an
input resistance will reduce the lower corner frequency SNR above unity V/V or 0dB. At a 10V total power supply,
down to 100Hz at a gain setting of 1V/V. These frequencies DR in the LTC6912-X (gains 0V/V to 100V/V), the DR is
scale inversely with the value of input capacitor used. typically 115dB (the ratio of 9.9 VP-P, or 3.5VRMS, maxi-
mum input to the 6.3µVRMS high gain input noise). The

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21
LTC6912
U U W U
APPLICATIO S I FOR ATIO
SNR from an amplifier is the ratio of input level to input- decoupling from a clean, low inductance power source.
referred noise, and can be 108dB with the LTC6912 family But several centimeters of wire (i.e., a few µH of induc-
at unity gain. tance) from the power supplies, unless decoupled by
substantial capacitance (>10µF) near the chip, can create
Construction and Instrumentation Cautions a parasitic high-Q LC resonant circuit in the hundreds of
kHz range in the chip’s supplies or ground reference. This
Electrically clean construction is important in applications
may impair circuit performance at those frequencies. A
seeking the full dynamic range of the LTC6912 family of
compact, carefully laid out printed circuit board with a
dual amplifiers. It is absolutely critical to have AGND either good ground plane makes a significant difference in mini-
AC bypassed or wired directly using the shortest possible mizing distortion. Finally, equipment to measure perfor-
wiring, to a low impedance ground return for best channel- mance can itself introduce distortion or noise floors.
to-channel isolation. Short, direct wiring minimizes para- Checking for these limits with wired shorts from INA to
sitic capacitance and inductance. High quality supply OUTA and INB to OUTB in place of the chip is a prudent
bypass capacitors of 0.1µF near the chip provide good routine procedure.

U
TYPICAL APPLICATIO
Low Noise AC Amplifier with Programmable Gain and an integrating lowpass loop with capacitor C2 to set the
Bandwidth programmable upper corner frequency. The LT1884 also
supports rail-to-rail output swings over the total supply
Analog data acquisition can exploit band limiting as well as
voltage range of 2.7V to 10.5V. AC coupling through
gain to suppress unwanted signals or noise. Tailoring an
capacitor C1 establishes a fixed low frequency corner of
analog front end to both the level and bandwidth of each
1Hz, which can be adjusted by changing C1. Alternatively,
source maximizes the resulting SNR. Figure 7 shows a
shorting C1 makes the amplifier DC coupled. If DC gain is
block diagram for a low noise amplifier with gain and
not needed, the AC coupling cap C1 serves to suppress
bandwidth independently programmable over a 100:1
several error sources: any shift in DC levels, low frequency
range. Channels A and B of the LTC6912-1 are used to
noise, and DC offset voltages (not including the LT1884’s
independently control the gain and bandwidth respec-
low internal offset).
tively over a 100:1 range. The LT1884 dual op amp forms
R2
15.8k

C2
1µF R
GAIN
CONTROL 1M
PGA C1 BANDWIDTH
10µF R1 CONTROL
15.8k PGA
VIN GAINA – R
INA OUTA
1/2 LT1884 GAINB –
INB OUTB
LTC6912-1 + 1/2 LT1884 VOUT
CHANNEL A
LTC6912-1 +
CHANNEL B
1/2 LT1884
R2 1 1 6912 F07
VOUT = GAINA V –3dB BANDWIDTH RANGE IS FROM TO ≤
R1 IN 2πR1C1 R2
2π ( )C2
GAINB

Figure 7. Block Diagram of an AC Amplifier with Programmable Gain and Bandwidth

6912fa

22
 LTC6912
U
PACKAGE DESCRIPTIO
DE/UE Package
12-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1695)

4.00 ±0.10 R = 0.115 0.38 ± 0.10

(2 SIDES) TYP
7 12
0.65 ±0.05 R = 0.20
TYP

3.50 ±0.05 1.70 ±0.05 3.00 ±0.10 1.70 ± 0.10

2.20 ±0.05 (2 SIDES) (2 SIDES) (2 SIDES)
PIN 1
TOP MARK PIN 1
PACKAGE OUTLINE (NOTE 6) NOTCH
(UE12/DE12) DFN 0603

6 1
0.25 ± 0.05 0.200 REF 0.75 ±0.05 0.25 ± 0.05
0.50 0.50
BSC BSC
3.30 ±0.05 3.30 ±0.10
(2 SIDES) 0.00 – 0.05 (2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS BOTTOM VIEW—EXPOSED PAD

NOTE:
1. DRAWING PROPOSED TO BE A VARIATION OF VERSION 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
(WGED) IN JEDEC PACKAGE OUTLINE M0-229 MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
2. DRAWING NOT TO SCALE 5. EXPOSED PAD SHALL BE SOLDER PLATED
3. ALL DIMENSIONS ARE IN MILLIMETERS 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE

GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)

.045 ±.005 .189 – .196*

(4.801 – 4.978)
.009
(0.229)
16 15 14 13 12 11 10 9 REF

.254 MIN .150 – .165

.229 – .244 .150 – .157**

(5.817 – 6.198) (3.810 – 3.988)

.0165 ± .0015 .0250 BSC

RECOMMENDED SOLDER PAD LAYOUT
1 2 3 4 5 6 7 8

.015 ± .004
× 45° .0532 – .0688 .004 – .0098
(0.38 ± 0.10)
(1.35 – 1.75) (0.102 – 0.249)
.007 – .0098
0° – 8° TYP
(0.178 – 0.249)

.016 – .050 .008 – .012 .0250 GN16 (SSOP) 0204

(0.406 – 1.270) (0.203 – 0.305) (0.635)
NOTE: TYP BSC
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

6912fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 23
LTC6912
U
TYPICAL APPLICATIO
A 2:1 PGA MUX
V+
0.1µF

12 14
V+ V–

CHANNEL A 2 INA OUT A 15 VOUT

INPUT (TO ADC)
1µF
3
AGND LTC6912-X

CHANNEL B 4 INB OUT B 13

INPUT

5 CHB CHA
SHDN SHDN 10
6 DGND
CS/LD CS/LD
3-WIRE 7
SPI DATA DIN 9
INTERFACE 8 DOUT
CLK
6912 TA02

MUX OPERATION: IF THE LOWER NIBBLE (Q3, Q2, Q1, Q0) IS (1, 0, 0, 0) THEN OUTA IS IN
TRI-STATE AND THE UPPER NIBBLE (Q7, Q6, Q5, Q4) CONTROLS THE ACTIVE CHANNEL B.
IF THE UPPER NIBBLE IS (1, 0, 0, 0) THEN OUTB IS IN TRI-STATE
AND THE LOWER NIBBLE CONTROLS ACTIVE CHANNEL A.

RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LT1228 100MHZ Gain Controlled Transconductance Amplifier Differential Input, Continuous Analog Gain Control
LT1251/LT1256 40Mhz Video Fader and Gain Controlled Amplifier Two Input, One Output, Continuous Analog Gain Control
LTC1564 10kHz to 150kHz Digitally Controlled Filter and PGA Continuous Time, Low Noise 8th Order Filter and 4-Bit PGA
LTC6910-1/-2/-3 Digitally Controlled Programmable Gain Amplifier Single Programmable Gain Amplifier, 3-Bit Parallel Digital Interface
in SOT-23
LTC6911-1/-2 Dual Digitally Controlled Programmable Gain Amplifier Dual Programmable Gain Amplifiers, 3-Bit Parallel Digital Interface
in MSOP-10
LTC6915 Zero Drift Instrumentation Amp Gains 0 - 4096V/V, 116dB CMRR
with Digitally Programmable Gain

6912fa

Linear Technology Corporation LT/LT 1005 REV A • PRINTED IN USA

24 1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ●
FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2004
 LTC2604/LTC2614/LTC2624
Quad 16-Bit Rail-to-Rail DACs
in 16-Lead SSOP

U
FEATURES DESCRIPTIO
■ Smallest Pin Compatible Quad 16-Bit DAC: The LTC®2604/LTC2614/LTC2624 are quad 16-,14- and
LTC2604: 16-Bits 12-bit 2.5V to 5.5V rail-to-rail voltage output DACs in
LTC2614: 14-Bits 16-lead narrow SSOP packages. These parts have sepa-
LTC2624: 12-Bits rate reference inputs for each DAC. They have built-in
■ Guaranteed 16-Bit Monotonic Over Temperature high performance output buffers and are guaranteed
■ Separate Reference Inputs for each DAC monotonic.
■ Wide 2.5V to 5.5V Supply Range
■
These parts establish advanced performance standards
Low Power Operation: 250µA per DAC at 3V
for output drive, crosstalk and load regulation in single-
■ Individual DAC Power-Down to 1µA, Max
■
supply, voltage output multiples.
Ultralow Crosstalk Between DACs (<5µV)
■ High Rail-to-Rail Output Drive (±15mA) The parts use a simple SPI/MICROWIRETM compatible
■ Double Buffered Digital Inputs 3-wire serial interface which can be operated at clock
■ 16-Lead Narrow SSOP Package rates up to 50MHz. Daisy-chain capability and a hardware
CLR function are included.
U
APPLICATIO S The LTC2604/LTC2614/LTC2624 incorporate a power-
■ Mobile Communications on reset circuit. During power-up, the voltage outputs
■ Process Control and Industrial Automation rise less than 10mV above zero scale; and after power-
■ Instrumentation up, they stay at zero scale until a valid write and update
■ Automatic Test Equipment take place.
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.

W
BLOCK DIAGRA
GND VCC
1 16
REF LO REF D
2 15
Differential Nonlinearity (LTC2604)
REF A VOUT D
REGISTER

REGISTER
INPUT

3 1.0
DAC

DAC D 14 VCC = 5V
VOUTA 0.8 VREF = 4.096V
REGISTER

REGISTER
INPUT
DAC

4 DAC A 0.6
REGISTER

VOUT C
REGISTER

0.4
INPUT

DAC

DAC C
ERROR (LSB)

13 0.2
REGISTER

REGISTER

VOUTB
INPUT

REF C 0
DAC

5 DAC B
12
–0.2
REF B
CLR –0.4
6
11 –0.6
CS/LD CONTROL DECODE SDO –0.8
LOGIC
7 10 –1.0
0 16384 32768 49152 65535
SCK SDI CODE
8 32-BIT SHIFT REGISTER 9 2604 TA01

2604 BD

2604fa

1
LTC2604/LTC2614/LTC2624
W W W U U W U
ABSOLUTE AXI U RATI GS PACKAGE/ORDER I FOR ATIO
(Note 1)
TOP VIEW
Any Pin to GND ........................................... – 0.3V to 6V 1
GND 16 VCC
Any Pin to VCC ............................................ – 6V to 0.3V REF LO 2 15 REF D

Maximum Junction Temperature ......................... 125°C REF A 3 14 VOUT D

4 13 VOUT C
Operating Temperature Range VOUT A
5 12 REF C
VOUT B
LTC2604/LTC2614/LTC2624C ............... 0°C to 70°C REF B 6 11 CLR

LTC2604/LTC2614/LTC2624I ............ – 40°C to 85°C CS/LD 7 10 SDO

8 9 SDI
Storage Temperature Range ................ – 65°C to 150°C SCK

GN PACKAGE
Lead Temperature (Soldering, 10 sec)................ 300°C 16-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 150°C/W

ORDER PART NUMBER GN PART MARKING

LTC2604CGN LTC2614IGN 2604 2614I
LTC2604IGN LTC2624CGN 2604I 2624
LTC2614CGN LTC2624IGN 2614 2624I
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications
are at TA = 25°C. REF A = REF B = REF C = REF D = 4.096V (VCC = 5V), REF A = REF B = REF C = REF D = 2.048V (VCC = 2.5V),
REF LO = 0V, VOUT unloaded, unless otherwise noted.
LTC2624 LTC2614 LTC2604
SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
DC Performance
Resolution ● 12 14 16 Bits
Monotonicity (Note 2) ● 12 14 16 Bits
DNL Differential Nonlinearity (Note 2) ● ±0.5 ±1 ±1 LSB
INL Integral Nonlinearity (Note 2) ● ±0.9 ±4 ±4 ±16 ±14 ±64 LSB
Load Regulation VREF = VCC = 5V, Midscale
IOUT = 0mA to 15mA Sourcing ● 0.025 0.125 0.1 0.5 0.3 2 LSB/mA
IOUT = 0mA to 15mA Sinking ● 0.025 0.125 0.1 0.5 0.3 2 LSB/mA
VREF = VCC = 2.5V, Midscale
IOUT = 0mA to 7.5mA Sourcing ● 0.05 0.25 0.2 1 0.7 4 LSB/mA
IOUT = 0mA to 7.5mA Sinking ● 0.05 0.25 0.2 1 0.7 4 LSB/mA
ZSE Zero-Scale Error ● 1.5 9 1.5 9 1.5 9 mV
VOS Offset Error (Note 7) ● ±1.5 ±9 ±1.5 ±9 ±1.5 ±9 mV
VOS Temperature ±5 ±5 ±5 µV/°C
Coefficient
GE Gain Error ● ±0.1 ±0.7 ±0.1 ±0.7 ±0.1 ±0.7 %FSR
Gain Temperature ±5 ±5 ±5 ppm/°C
Coefficient

LTC2604/LTC2614/LTC2624
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
PSR Power Supply Rejection VCC = 5V ±10% –80 dB
VCC = 3V ±10% –80 dB
ROUT DC Output Impedance VREF = VCC = 5V, Midscale; –15mA ≤ IOUT ≤ 15mA ● 0.025 0.15 Ω
VREF = VCC = 2.5V, Midscale; –7.5mA ≤ IOUT ≤ 7.5mA ● 0.030 0.15 Ω
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 LTC2604/LTC2614/LTC2624
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications
are at TA = 25°C. REF A = REF B = REF C = REF D = 4.096V (VCC = 5V), REF A = REF B = REF C = REF D = 2.048V (VCC = 2.5V),
REF LO = 0V, VOUT unloaded, unless otherwise noted.
LTC2604/LTC2614/LTC2624
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
DC Crosstalk (Note 4) Due to Full Scale Output Change (Note 5) ±5 µV
Due to Load Current Change ±1 µV/mA
Due to Powering Down (per Channel) ±3.5 µV
ISC Short-Circuit Output Current VCC = 5.5V, VREF = 5.5V
Code: Zero Scale; Forcing Output to VCC ● 15 34 60 mA
Code: Full Scale; Forcing Output to GND ● 15 36 60 mA
VCC = 2.5V, VREF = 2.5V
Code: Zero Scale; Forcing Output to VCC ● 7.5 18 50 mA
Code: Full Scale; Forcing Output to GND ● 7.5 24 50 mA
Reference Input
Input Voltage Range ● 0 VCC V
Resistance Normal Mode ● 88 128 160 kΩ
Capacitance 14 pF
IREF Reference Current, Power Down Mode All DACs Powered Down ● 0.001 1 µA
Power Supply
VCC Positive Supply Voltage For Specified Performance ● 2.5 5.5 V
ICC Supply Current VCC = 5V (Note 3) ● 1.3 2 mA
VCC = 3V (Note 3) ● 1 1.6 mA
All DACs Powered Down (Note 3) VCC = 5V ● 0.35 1 µA
All DACs Powered Down (Note 3) VCC = 3V ● 0.10 1 µA
Digital I/O
VIH Digital Input High Voltage VCC = 2.5V to 5.5V ● 2.4 V
VCC = 2.5V to 3.6V ● 2.0 V
VIL Digital Input Low Voltage VCC = 4.5V to 5.5V ● 0.8 V
VCC = 2.5V to 5.5V ● 0.6 V
VOH Digital Output High Voltage Load Current = –100µA ● VCC – 0.4 V
VOL Digital Output Low Voltage Load Current = +100µA ● 0.4 V
ILK Digital Input Leakage VIN = GND to VCC ● ±1 µA
CIN Digital Input Capacitance (Note 6) ● 8 pF

LTC2624 LTC2614 LTC2604

SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
AC Performance
ts Settling Time (Note 8) ±0.024% (±1LSB at 12 Bits) 7 7 7 µs
±0.006% (±1LSB at 14 Bits) 9 9 µs
±0.0015% (±1LSB at 16 Bits) 10 µs
Settling Time for ±0.024% (±1LSB at 12 Bits) 2.7 2.7 2.7 µs
1LSB Step (Note 9) ±0.006% (±1LSB at 14 Bits) 4.8 4.8 µs
±0.0015% (±1LSB at 16 Bits) 5.2 µs
Voltage Output Slew Rate 0.80 0.80 0.80 V/µs
Capacitive Load Driving 1000 1000 1000 pF
Glitch Impulse At Midscale Transition 12 12 12 nV • s
Multiplying Bandwidth 180 180 180 kHz
en Output Voltage Noise At f = 1kHz 120 120 120 nV/√Hz
Density At f = 10kHz 100 100 100 nV/√Hz
Output Voltage Noise 0.1Hz to 10Hz 15 15 15 µVP-P

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LTC2604/LTC2614/LTC2624
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TI I G CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications
are at TA = 25°C. REF A = REF B = REF C = REF D = 4.096V (VCC = 5V), REF A = REF B = REF C = REF D = 2.048V (VCC = 2.5V),
REF LO = 0V, VOUT unloaded, unless otherwise noted.
LTC2604/LTC2614/LTC2624
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC = 2.5V to 5.5V
t1 SDI Valid to SCK Setup ● 4 ns
t2 SDI Valid to SCK Hold ● 4 ns
t3 SCK High Time ● 9 ns
t4 SCK Low Time ● 9 ns
t5 CS/LD Pulse Width ● 10 ns
t6 LSB SCK High to CS/LD High ● 7 ns
t7 CS/LD Low to SCK High ● 7 ns
t8 SDO Propagation Delay from SCK Falling Edge CLOAD = 10pF
VCC = 4.5V to 5.5V ● 20 ns
VCC = 2.5V to 5.5V ● 45 ns
t9 CLR Pulse Width ● 20 ns
t10 CS/LD High to SCK Positive Edge ● 7 ns
SCK Frequency 50% Duty Cycle ● 50 MHz
Note 1: Absolute maximum ratings are those values beyond which the life Note 5: RL = 2kΩ to GND or VCC.
of a device may be impaired. Note 6: Guaranteed by design and not production tested.
Note 2: Linearity and monotonicity are defined from code kL to code Note 7: Inferred from measurement at code 256 (LTC2604), code 64
2N – 1, where N is the resolution and kL is given by kL = 0.016(2N/VREF), (LTC2614) or code 16 (LTC2624), and at full scale.
rounded to the nearest whole code. For VREF = 4.096V and N = 16, Note 8: VCC = 5V, VREF = 4.096V. DAC is stepped 1/4 scale to 3/4 scale
kL = 256, linearity is defined from code 256 to code 65,535. and 3/4 scale to 1/4 scale. Load is 2k in parallel with 200pF to GND.
Note 3: Digital inputs at 0V or VCC. Note 9: VCC = 5V, VREF = 4.096V. DAC is stepped 1LSB between half scale
Note 4: DC crosstalk is measured with VCC = 5V and VREF = 4.096V, with and half scale –1. Load is 2k in parallel with 200pF to GND.
the measured DAC at midscale, unless otherwise noted.

U W
TYPICAL PERFOR A CE CHARACTERISTICS (LTC2604/LTC2614/LTC2624)

Current Limiting Load Regulation Offset Error vs Temperature

0.10 1.0 3
CODE = MIDSCALE CODE = MIDSCALE
0.08 0.8
VREF = VCC = 5V
0.06 2
0.6
VREF = VCC = 3V
0.04
OFFSET ERROR (mV)

0.4
1
∆VOUT (mV)

0.02 0.2
∆VOUT (V)

0 0 0
VREF = VCC = 5V
–0.02 –0.2
VREF = VCC = 3V
–0.04 –0.4 –1
VREF = VCC = 5V VREF = VCC = 3V
–0.06 –0.6
–2
–0.08 –0.8
–0.10 –1.0 –3
–40 –30 –20 –10 0 10 20 30 40 –35 –25 –15 –5 5 15 25 35 –50 –30 –10 10 30 50 70 90
IOUT (mA) IOUT (mA) TEMPERATURE (°C)
2604 G01 2604 G02 2604 G03

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TYPICAL PERFOR A CE CHARACTERISTICS (LTC2604/LTC2614/LTC2624)

Zero-Scale Error vs Temperature Gain Error vs Temperature Offset Error vs VCC

3 0.4 3

0.3
2.5 2
ZERO-SCALE ERROR (mV)

0.2

GAIN ERROR (%FSR)

OFFSET ERROR (mV)

2.0 1
0.1

1.5 0 0

–0.1
1.0 –1
–0.2
0.5 –2
–0.3

0 –0.4 –3
–50 –30 –10 10 30 50 70 90 –50 –30 –10 10 30 50 70 90 2.5 3 3.5 4 4.5 5 5.5
TEMPERATURE (°C) TEMPERATURE (°C) VCC (V)
2604 G04 2604 G05 2604 G06

Gain Error vs VCC ICC Shutdown vs VCC Large-Signal Settling

0.4 450
0.3 400

0.2 350
GAIN ERROR (%FSR)

0.1 300
VOUT
0.5V/DIV
ICC (nA)

250
0
200
–0.1
150 VREF = VCC = 5V
–0.2 1/4-SCALE TO 3/4-SCALE
100
–0.3 2.5µs/DIV 2604 G09
50
–0.4 0
2.5 3 3.5 4 4.5 5 5.5 2.5 3 3.5 4 4.5 5 5.5
VCC (V) VCC (V)
2604 G07 2604 G08

Headroom at Rails
Midscale Glitch Impulse Power-On Reset Glitch vs Output Current
5.0
4.5 5V SOURCING

4.0
VOUT 3.5
10mV/DIV VCC
1V/DIV 3V SOURCING
12nV-s TYP 3.0
VOUT (V)

2.5
4mV
4mVPEAK
PEAK
CS/LD 2.0
5V/DIV VOUT 1.5
10mV/DIV 5V SINKING
1.0
2604 G11
2.5µs/DIV
2604 G10
250µs/DIV 3V SINKING
0.5
0
0 1 2 3 4 5 6 7 8 9 10
IOUT (mA)
2604 G12

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TYPICAL PERFOR A CE CHARACTERISTICS (LTC2604/LTC2614/LTC2624)

Supply Current vs Logic Voltage Exiting Power-Down to Midscale Hardware CLR

2.0
VCC = 5V VCC = 5V
SWEEP SCK, SDI VREF = 2V
1.8 AND CS/LD
0V TO VCC
VOUT
VOUT
1.6 0.5V/DIV
1V/DIV
ICC (mA)

DACs A-C IN
1.4 POWER-DOWN MODE
CS/LD
1.2 5V/DIV CLR
5V/DIV

1.0
2.5µs/DIV 2604 G14
1µs/DIV
2604 G15

0.8
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
LOGIC VOLTAGE (V)
2604 G13

Output Voltage Noise, Short-Circuit Output Current vs

Multiplying Frequency Response 0.1Hz to 10Hz VOUT (Sinking)
0 50
–3 V CC = 5.5V
V REF = 5.6V
–6 CODE = 0
40
–9 V OUT SWEPT 0V TO V CC
–12
VOUT
30
10mA/DIV
–15 10µV/DIV
dB

–18
–21 20
–24
VCC = 5V
–27 VREF (DC) = 2V
–30 VREF (AC) = 0.2VP-P 10
0 1 2 3 4 5 6 7 8 9 10
–33 CODE = FULL SCALE
SECONDS
–36 2604 G17 0
1k 10k 100k 1M 0 1 2 3 4 5 6
FREQUENCY (Hz) 1V/DIV
2604 G16
2604 G18

Short-Circuit Output Current vs

VOUT (Sourcing)
0
V CC = 5.5V
V REF = 5.6V
–10 CODE = FULL SCALE
V OUT SWEPT V CC TO 0V

–20
10mA/DIV

–30

–40

–50
0 1 2 3 4 5 6
1V/DIV
2604 G19

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TYPICAL PERFOR A CE CHARACTERISTICS (LTC2604)

Integral Nonlinearity (INL) Differential Nonlinearity (DNL) INL vs Temperature

32 1.0 32
VCC = 5V VCC = 5V
VREF = 4.096V 0.8 VREF = 4.096V VCC = 5V
24 24
VREF = 4.096V
0.6
16 16
0.4
8 8 INL (POS)
0.2

DNL (LSB)

INL (LSB)
INL (LSB)

0 0 0

–8 –0.2 –8
INL (NEG)
–0.4
–16 –16
–0.6
–24 –24
–0.8
–32 –1.0 –32
0 16384 32768 49152 65535 0 16384 32768 49152 65535 –50 –30 –10 10 30 50 70 90
CODE CODE TEMPERATURE (°C)
2604 G20 2604 G21 2604 G22

DNL vs Temperature INL vs VREF DNL vs VREF

1.0 32 1.5
0.8 VCC = 5V VCC = 5.5V VCC = 5.5V
24
VREF = 4.096V 1.0
0.6
16
0.4
DNL (POS) INL (POS) 0.5
8
0.2 DNL (POS)
DNL (LSB)

DNL (LSB)
INL (LSB)

0 0 0
–0.2 –8 DNL (NEG)
DNL (NEG) INL (NEG)
–0.5
–0.4
–16
–0.6
–1.0
–24
–0.8
–1.0 –32 –1.5
–50 –30 –10 10 30 50 70 90 0 1 2 3 4 5 0 1 2 3 4 5
TEMPERATURE (°C) VREF (V) VREF (V)
2604 G23 2604 G24 2604 G25

Settling to ±1LSB Settling of Full-Scale Step

VOUT VOUT
100µV/DIV 100µV/DIV
12.3µs
9.7µs

CS/LD CS/LD
2V/DIV 2V/DIV

2604 G27
2µs/DIV 2604 G26 5µs/DIV
VCC = 5V, VREF = 4.096V VCC = 5V, VREF = 4.096V
1/4-SCALE TO 3/4-SCALE STEP CODE 512 TO 65535 STEP
RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS
AVERAGE OF 2048 EVENTS SETTLING TO ±1LSB

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LTC2604/LTC2614/LTC2624
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TYPICAL PERFOR A CE CHARACTERISTICS
(LTC2614)
Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Settling to ±1LSB
8 1.0
VCC = 5V VCC = 5V
6 VREF = 4.096V 0.8 VREF = 4.096V
0.6
4
0.4
VOUT
2
0.2 100µV/DIV

DNL (LSB)
INL (LSB)

0 0
–0.2 CS/LD
–2 2V/DIV 8.9µs
–0.4
–4
–0.6 2604 G30
2µs/DIV
–6
–0.8 VCC = 5V, VREF = 4.096V
–8 1/4-SCALE TO 3/4-SCALE STEP
–1.0
0 4096 8192 12288 16383 0 4096 8192 12288 16383 RL = 2k, CL = 200pF
CODE CODE AVERAGE OF 2048 EVENTS

2604 G28 2604 G29

(LTC2624)
Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Settling to ±1LSB
2.0 1.0
VCC = 5V VCC = 5V
1.5 VREF = 4.096V 0.8 VREF = 4.096V
0.6
1.0
0.4 6.8µs
VOUT
0.5 0.2
DNL (LSB)

1mV/DIV
INL (LSB)

0 0
–0.2 CS/LD
–0.5
2V/DIV
–0.4
–1.0
–0.6 2604 G33
2µs/DIV
–1.5 –0.8 VCC = 5V, VREF = 4.096V
–2.0 –1.0 1/4-SCALE TO 3/4-SCALE STEP
0 1024 2048 3072 4095 0 1024 2048 3072 4095 RL = 2k, CL = 200pF
CODE CODE AVERAGE OF 2048 EVENTS

2604 G31 2604 G32

U U U
PIN FUNCTIONS
GND (Pin 1): Analog Ground. CS/LD (Pin 7): Serial Interface Chip Select/Load Input.
When CS/LD is low, SCK is enabled for shifting data on SDI
REF LO (Pin 2): Reference Low. The voltage at this pin sets
into the register. When CS/LD is taken high, SCK is
the zero scale (ZS) voltage of all DACs. This pin can be
disabled and the specified command (see Table 1) is
raised up to 1V above ground at VCC = 5V or 100mV above
executed.
ground at VCC = 3V.
SCK (Pin 8): Serial Interface Clock Input. CMOS and TTL
REF A, REF B, REF C, REF D (Pins 3, 6, 12, 15): Reference
compatible.
Voltage Inputs for each DAC. REF x sets the full scale
voltage of the DACs. 0V ≤ REF x ≤ VCC. SDI (Pin 9): Serial Interface Data Input. Data is applied to
SDI for transfer to the device at the rising edge of SCK. The
VOUT A to VOUT D (Pins 4, 5, 13, 14): DAC Analog Voltage
LTC2604/LTC2614/LTC2624 accepts input word lengths
Outputs. The output range is from REF LO to REF x.
of either 24 or 32 bits.
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 LTC2604/LTC2614/LTC2624
U U U
PIN FUNCTIONS
SDO (Pin 10): Serial Interface Data Output. The serial CLR (Pin 11): Asynchronous Clear Input. A logic low at this
output of the shift register appears at the SDO pin. The data level-triggered input clears all registers and causes the
transferred to the device via the SDI pin is delayed 32 SCK DAC voltage outputs to drop to 0V. CMOS and TTL-
rising edges before being output at the next falling edge. compatible.
This pin is used for daisy-chain operation.
VCC (Pin 16): Supply Voltage Input. 2.5V ≤ VCC ≤ 5.5V.

W
BLOCK DIAGRA
GND VCC
1 16
REF LO REF D
2 15
REF A VOUT D

REGISTER

REGISTER
INPUT
3

DAC
DAC D 14
VOUTA
REGISTER

REGISTER
INPUT
DAC

4 DAC A
REGISTER VOUT C

REGISTER
INPUT

DAC
DAC C 13
REGISTER

REGISTER

VOUTB
INPUT

REF C
DAC

5 DAC B
12
REF B
CLR
6
11

CS/LD CONTROL DECODE SDO

LOGIC
7 10

SCK SDI
8 32-BIT SHIFT REGISTER 9
2604 BD

WU W
TI I G DIAGRA
t1
t2 t3 t4 t6

SCK 1 2 3 23 24

t10

SDI

t5 t7

CS/LD

t8

SDO
2604 F01

Figure 1
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9
LTC2604/LTC2614/LTC2624
U
OPERATIO
Power-On Reset Table 1.
COMMAND*
The LTC2604/LTC2614/LTC2624 clear the outputs to zero C3 C2 C1 C0
scale when power is first applied, making system initializa- 0 0 0 0 Write to Input Register n
tion consistent and repeatable. 0 0 0 1 Update (Power Up) DAC Register n
For some applications, downstream circuits are active 0 0 1 0 Write to Input Register n, Update (Power Up) All n
during DAC power-up, and may be sensitive to nonzero 0 0 1 1 Write to and Update (Power Up) n
outputs from the DAC during this time. The LTC2604/ 0 1 0 0 Power Down n
1 1 1 1 No Operation
LTC2614/LTC2624 contain circuitry to reduce the power-
ADDRESS (n)*
on glitch; furthermore, the glitch amplitude can be made
A3 A2 A1 A0
arbitrarily small by reducing the ramp rate of the power
0 0 0 0 DAC A
supply. For example, if the power supply is ramped to 5V
0 0 0 1 DAC B
in 1ms, the analog outputs rise less than 10mV above
0 0 1 0 DAC C
ground (typ) during power-on. See Power-On Reset Glitch
0 0 1 1 DAC D
in the Typical Performance Characteristics section. 1 1 1 1 All DACs
*Command and address codes not shown are reserved and should not be used.
Power Supply Sequencing
The voltage at REF (Pins 3, 6, 12 and 15) should be kept only be transferred to the device when the CS/LD signal is
within the range – 0.3V ≤ REF x ≤ VCC + 0.3V (see Absolute low. The rising edge of CS/LD ends the data transfer and
Maximum Ratings). Particular care should be taken to causes the device to carry out the action specified in the
observe these limits during power supply turn-on and 24-bit input word. The complete sequence is shown in
turn-off sequences, when the voltage at VCC (Pin 16) is in Figure 2a.
transition. The command (C3-C0) and address (A3-A0) assignments
are shown in Table 1. The first four commands in the table
Transfer Function consist of write and update operations. A write operation
The digital-to-analog transfer function is loads a 16-bit data word from the 32-bit shift register into
the input register of the selected DAC, n. An update
⎛ k⎞
VOUT(IDEAL) = ⎜ N ⎟ [REF x – REFLO] + REFLO operation copies the data word from the input register to
⎝2 ⎠ the DAC register. Once copied into the DAC register, the
where k is the decimal equivalent of the binary DAC input data word becomes the active 16-, 14- or 12-bit input
code, N is the resolution and REF x is the voltage at REF A, code, and is converted to an analog voltage at the DAC
REF B, REF C and REF D (Pins 3, 6, 12 and 15). output. The update operation also powers up the selected
DAC if it had been in power-down mode. The data path and
Serial Interface registers are shown in the block diagram.
The CS/LD input is level triggered. When this input is taken While the minimum input word is 24 bits, it may optionally
low, it acts as a chip-select signal, powering-on the SDI be extended to 32 bits. To use the 32-bit word width, 8
and SCK buffers and enabling the input shift register. Data don’t-care bits are transferred to the device first, followed
(SDI input) is transferred at the next 24 rising SCK edges. by the 24-bit word as just described. Figure 2b shows the
The 4-bit command, C3-C0, is loaded first; then the 4-bit 32-bit sequence. The 32-bit word is required for daisy-
DAC address, A3-A0; and finally the 16-bit data word. The chain operation, and is also available to accommodate
data word comprises the 16-, 14- or 12-bit input code, microprocessors which have a minimum word width of 16
ordered MSB-to-LSB, followed by 0, 2 or 4 don’t-care bits bits (2 bytes).
(LTC2604, LTC2614 and LTC2624 respectively). Data can

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 LTC2604/LTC2614/LTC2624
U
OPERATIO
INPUT WORD (LTC2604)

COMMAND ADDRESS DATA (16 BITS)

C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

MSB LSB
2604 TBL01

INPUT WORD (LTC2614)

COMMAND ADDRESS DATA (14 BITS + 2 DON’T-CARE BITS)

C3 C2 C1 C0 A3 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X

MSB LSB
2604 TBL02

INPUT WORD (LTC2624)

COMMAND ADDRESS DATA (12 BITS + 4 DON’T-CARE BITS)

C3 C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X
MSB LSB
2604 TBL03

Daisy-Chain Operation Power-Down Mode

The serial output of the shift register appears at the SDO For power-constrained applications, power-down mode
pin. Data transferred to the device from the SDI input is can be used to reduce the supply current whenever less
delayed 32 SCK rising edges before being output at the than four outputs are needed. When in power-down, the
next SCK falling edge. buffer amplifiers, bias circuits and reference inputs are
disabled, and draw essentially zero current. The DAC
The SDO output can be used to facilitate control of multiple
serial devices from a single 3-wire serial port (i.e., SCK, outputs are put into a high-impedance state, and the
SDI and CS/LD). Such a “daisy-chain” series is configured output pins are passively pulled to ground through indi-
by connecting SDO of each upstream device to SDI of the vidual 90k resistors. Input- and DAC-register contents are
not disturbed during power-down.
next device in the chain. The shift registers of the devices
are thus connected in series, effectively forming a single Any channel or combination of channels can be put into
input shift register which extends through the entire chain. power-down mode by using command 0100b in combina-
Because of this, the devices can be addressed and con- tion with the appropriate DAC address, (n). The 16-bit data
trolled individually by simply concatenating their input word is ignored. The supply current is reduced by approxi-
words; the first instruction addresses the last device in the mately 1/4 for each DAC powered down. The effective
chain and so forth. The SCK and CS/LD signals are resistance at REF x (pins 3, 6, 12 and 15) are at high-
common to all devices in the series. impedance input (typically > 1GΩ) when the correspond-
In use, CS/LD is first taken low. Then the concatenated ing DACs are powered down.
input data is transferred to the chain, using SDI of the first Normal operation can be resumed by executing any com-
device as the data input. When the data transfer is com- mand which includes a DAC update, as shown in Table 1.
plete, CS/LD is taken high, completing the instruction The selected DAC is powered up as its voltage output is
sequence for all devices simultaneously. A single device updated. When a DAC which is in a powered-down state is
can be controlled by using the no-operation command powered up and updated, normal settling is delayed. If less
(1111) for the other devices in the chain. than four DACs are in a powered-down state prior to the
update command, the power-up delay time is 5µs. If on the
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11
LTC2604/LTC2614/LTC2624
U
OPERATIO
other hand, all four DACs are powered down, then the main The PC board should have separate areas for the analog
bias generation circuit block has been automatically shut and digital sections of the circuit. This keeps digital signals
down in addition to the individual DAC amplifiers and away from sensitive analog signals and facilitates the use
reference inputs. In this case, the power up delay time is of separate digital and analog ground planes which have
12µs (for VCC = 5V) or 30µs (for VCC = 3V). minimal capacitive and resistive interaction with each
other.
Voltage Outputs
Digital and analog ground planes should be joined at only
Each of the four rail-to-rail amplifiers contained in these one point, establishing a system star ground as close to
parts has guaranteed load regulation when sourcing or the device’s ground pin as possible. Ideally, the analog
sinking up to 15mA at 5V (7.5mA at 3V). ground plane should be located on the component side of
Load regulation is a measure of the amplifier’s ability to the board, and should be allowed to run under the part to
maintain the rated voltage accuracy over a wide range of shield it from noise. Analog ground should be a continu-
load conditions. The measured change in output voltage ous and uninterrupted plane, except for necessary lead
per milliampere of forced load current change is ex- pads and vias, with signal traces on another layer.
pressed in LSB/mA. The GND pin functions as a return path for power supply
DC output impedance is equivalent to load regulation, and currents in the device and should be connected to analog
may be derived from it by simply calculating a change in ground. Resistance from the GND pin to system star
units from LSB/mA to Ohms. The amplifiers’ DC output ground should be as low as possible. When a zero scale
impedance is 0.025Ω when driving a load well away from DAC output voltage of zero is desired, the REFLO pin
the rails. (pin 2) should be connected to system star ground.
When drawing a load current from either rail, the output Rail-to-Rail Output Considerations
voltage headroom with respect to that rail is limited by the
30Ω typical channel resistance of the output devices; e.g., In any rail-to-rail voltage output device, the output is
when sinking 1mA, the minimum output voltage = 30Ω • limited to voltages within the supply range.
1mA = 25mV. See the graph Headroom at Rails vs Output Since the analog outputs of the device cannot go below
Current in the Typical Performance Characteristics ground, they may limit for the lowest codes as shown in
section. Figure 3b. Similarly, limiting can occur near full scale
The amplifiers are stable driving capacitive loads of up to when the REF pins are tied to VCC. If REF x = VCC and the
1000pF. DAC full-scale error (FSE) is positive, the output for the
highest codes limits at VCC as shown in Figure 3c. No full-
Board Layout scale limiting can occur if REF x is less than VCC – FSE.
The excellent load regulation and DC crosstalk perfor- Offset and linearity are defined and tested over the region
mance of these devices is achieved in part by keeping of the DAC transfer function where no output limiting can
“signal” and “power” grounds separate. occur.

2604fa

12
 OPERATIO
CS/LD
U

SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

SDI C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

2604 F02a

COMMAND WORD ADDRESS WORD DATA WORD

24-BIT INPUT WORD

Figure 2a. LTC2604 24-Bit Load Sequence (Minimum Input Word)

LTC2614 SDI Data Word: 14-Bit Input Code + 2 Don’t Care Bits
LTC2624 SDI Data Word: 12-Bit Input Code + 4 Don’t Care Bits

CS/LD

SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

SDI X X X X X X X X C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

DON’T CARE COMMAND WORD ADDRESS WORD DATA WORD

SDO X X X X X X X X C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

PREVIOUS 32-BIT INPUT WORD CURRENT

t1 32-BIT
t2 INPUT WORD
2604 F02b
SCK 17 18
t3 t4
SDI D15 D14
t8
SDO PREVIOUS D15 PREVIOUS D14

Figure 2b. LTC2604 32-Bit Load Sequence

LTC2614 SDI/SDO Data Word: 14-Bit Input Code + 2 Don’t Care Bits
LTC2624 SDI/SDO Data Word: 12-Bit Input Code + 4 Don’t Care Bits

13
2604fa
LTC2604/LTC2614/LTC2624
LTC2604/LTC2614/LTC2624
U
OPERATIO

POSITIVE
VREF = VCC FSE

VREF = VCC
OUTPUT
VOLTAGE

OUTPUT
VOLTAGE
INPUT CODE

OUTPUT
VOLTAGE (c)
0 32,768 65,535
INPUT CODE
0V
NEGATIVE INPUT CODE (a)
OFFSET 2600 F03

(b)

Figure 3. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect
of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Codes Near Full Scale

2604fa

14
 LTC2604/LTC2614/LTC2624
U
PACKAGE DESCRIPTIO

GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)

.045 ±.005 .189 – .196*

(4.801 – 4.978)
.009
(0.229)
16 15 14 13 12 11 10 9 REF

.254 MIN .150 – .165

.229 – .244 .150 – .157**

(5.817 – 6.198) (3.810 – 3.988)

.0165 ± .0015 .0250 BSC

RECOMMENDED SOLDER PAD LAYOUT
1 2 3 4 5 6 7 8

.015 ± .004
× 45° .0532 – .0688 .004 – .0098
(0.38 ± 0.10)
(1.35 – 1.75) (0.102 – 0.249)
.007 – .0098
0° – 8° TYP
(0.178 – 0.249)

.016 – .050 .008 – .012 .0250 GN16 (SSOP) 0204

(0.406 – 1.270) (0.203 – 0.305) (0.635)
NOTE: TYP BSC
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

2604fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15
LTC2604/LTC2614/LTC2624
U
TYPICAL APPLICATIO
5V 5V

1k 1k
10k 10k

0.1µF 0.1µF
10k 10k

0.01µF 0.01µF
20Ω 49.9Ω
70MHz IN OUT
47pF 10pF
ZC830
49.9Ω

20pF
49.9Ω ZC830

DAC A DAC B

OPTIONAL OPTIONAL
DAC C DAC D
20k CS/LD 20k
SCK
0.1µF SDI 0.1µF
LTC2604
5V 5V
LO
2.74k 2.74k
100k 100k
1% 1%

2.74k 2.74k
90°
1% 1%

Q INPUT I+Q I INPUT

MODULATOR

5V 5V

2.74k 0° 2.74k
1% 1%

2.74k 2.74k
1% 1%
RF
2604 F04
*ZETEX (516) 543-7100

Figure 4. Using DAC A and DAC B for Nearly Continuous Attenuation Control and DAC C and
DAC D to Trim for Minimum LO Feedthrough in a Mixer.

RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS

LTC1458/LTC1458L Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.096V
LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1654 Dual 14-Bit Rail-to-Rail VOUT DAC Programmable Speed/Power
LTC1655/LTC1655L Single 16-Bit VOUT DAC with Serial Interface in SO-8 VCC = 5V(3V), Low Power, Deglitched
LTC1657/LTC1657L Parallel 5V/3V 16-Bit VOUT DAC Low Power, Deglitched, Rail-to-Rail VOUT
LTC1660/LTC1665 Octal 8/10-Bit VOUT DAC in 16-Pin Narrow SSOP VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output
LTC1821 Parallel 16-Bit Voltage Output DAC Precision 16-Bit Settling in 2µs for 10V Step
LTC2600/LTC2610/LTC2620 Octal 16-/14-/12-Bit Rail-to-Rail DACs in 16-Lead SSOP 250µA per DAC, 2.5V to 5.5V Supply Range
LTC2602/LTC2612/LTC2622 Dual 16-/14-/12-Bit Rail-to-Rail DACs in 8-Lead MSOP 300µA per DAC, 2.5V to 5.5V Supply Range
2604fa

RD/LT 0106 REV A • PRINTED IN THE USA

16 Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ●
www.linear.com © LINEAR TECHNOLOGY CORPORATION 2004
 512Mb: x4, x8, x16 DDR SDRAM
Features

Double Data Rate (DDR) SDRAM

MT46V128M4 – 32 Meg x 4 x 4 banks
MT46V64M8 – 16 Meg x 8 x 4 banks
MT46V32M16 – 8 Meg x 16 x 4 banks

Features Options Marking

• Configuration
• VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V 128 Meg x 4 (32 Meg x 4 x 4 banks) 128M4
• VDD = +2.6V ±0.1V, VDDQ = +2.6V ±0.1V (DDR400) 64 Meg x 8 (16 Meg x 8 x 4 banks) 64M8
• Bidirectional data strobe (DQS) transmitted/ 32 Meg x 16 (8 Meg x 16 x 4 banks) 32M16
received with data, i.e., source-synchronous data • Plastic Package
capture (x16 has two – one per byte) 66-pin TSOP TG
• Internal, pipelined double-data-rate (DDR) 66-pin TSOP Lead-free P
architecture; two data accesses per clock cycle 60-Ball FBGA (10 x 12.5mm) FN
• Differential clock inputs (CK and CK#) 60-Ball FBGA (10 x 12.5mm) lead-free BN
• Commands entered on each positive CK edge • Timing – cycle time
• DQS edge-aligned with data for READs; center- 5ns @ CL = 3 (DDR400B) -5B
6ns @ CL = 2.5 (DDR333) (FBGA only) -6
aligned with data for WRITEs
6ns @ CL = 2.5 (DDR333) (TSOP only) -6T
• DLL to align DQ and DQS transitions with CK
7.5ns @ CL = 2 (DDR266) -75E
• Four internal banks for concurrent operation 7.5ns @ CL = 2 (DDR266A) -75Z
• Data mask (DM) for masking write data (x16 has two 7.5ns @ CL = 2.5 (DDR266B) -75
– one per byte) • Self refresh
• Programmable burst lengths: 2, 4, or 8 Standard None
• Auto refresh and self refresh modes Low-Power self refresh L
• Longer lead TSOP for improved reliability (OCPL) • Temperature rating
• 2.5V I/O (SSTL_2 compatible) Standard (0°C to +70°C) None
• Concurrent auto precharge option is supported Industrial (–40°C to +85°C) IT
• tRAS lockout supported (tRAP = tRCD) • Revision
x4, x8 :D
x4, x8, x16 :F

Table 1: Addressing Configuration

128 Meg x 4 64 Meg x 8 32 Meg x 16
Configuration 32 Meg x 4 x 4 banks 16 Meg x 8 x 4 banks 8 Meg x 16 x 4 banks
Refresh count 8K 8K 8K
Row addressing 8K (A0–A12) 8K (A0–A12) 8K (A0–A12)
Bank addressing 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1)
Column addressing 4K (A0–A9, A11, A12) 2K (A0–A9, A11) 1K (A0–A9)

Table 2: Key Timing Parameters

CL = CAS (Read) latency; data-out window is MIN clock rate with 50% duty cycle @ CL = 2, CL = 2.5, or CL = 3
Clock Rate
Speed Access DQS–DQ
Grade CL = 2 CL = 2.5 CL = 3 Data-Out Window Window Skew
-5B 133 MHz 167 MHz 200 MHz 1.6ns ±0.70ns +0.40ns
-6 133 MHz 167 MHz n/a 2.1ns ±0.70ns +0.40ns
6T 133 MHz 167 MHz n/a 2.0ns ±0.70ns +0.45ns
-75E/-75Z 133 MHz 133 MHz n/a 2.5ns ±0.75ns +0.50ns
-75 100 MHz 133 MHz n/a 2.5ns ±0.75ns +0.50ns

PDF: 09005aef80a1d9d4/Source: 09005aef80a1d9e7 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_1.fm - Rev. K 6/06 EN 1 ©2000 Micron Technology, Inc. All rights reserved.

Products and specifications discussed herein are subject to change by Micron without notice.
 512Mb: x4, x8, x16 DDR SDRAM
FBGA Part Number System

Table 3: Speed Grade Backward Compatibility

PC3200 PC2700 PC2100 PC2100 PC2100 PC1600

Marking (3-3-3) (2.5-3-3) (2-2-2) (2-3-3) (2.5-3-3) (2-2-2)
-5B Yes Yes Yes Yes Yes Yes

-6 – Yes Yes Yes Yes Yes

-6T – Yes Yes Yes Yes Yes

-75E – – Yes Yes Yes Yes

-75Z – – – Yes Yes Yes

-75 – – – – Yes Yes

-5B -6/-6T -75E -75Z -75 -75

Figure 1: 512Mb DDR SDRAM Part Numbers

Example Part Number: MT46V32M16TG-75Z

- :
Sp.
MT46V Configuration Package Speed Op. Temp. Revision

Revision
:D x4, x8
:F x4, x8, x16
Configuration
128 Meg x4 128M4
64 Meg x8 64M8 Operating Temp
32 Meg x16 32M16 Standard
IT Industrial Temp
Package
TG Special Options
400 mil TSOP
P Standard
400 mil TSOP Lead-Free
L Low Power
10 x 12.5mm FBGA FN
10 x 12.5mm FBGA Lead-Free BN Speed Grade
-5B tCK = 5ns, CL = 3

-6 tCK = 6ns, CL = 2.5

-6T tCK = 6ns, CL = 2.5

-75E tCK = 7.5ns, CL = 2

-75Z tCK = 7.5ns, CL = 2

-75 tCK = 7.5ns, CL = 2.5

FBGA Part Number System

Due to space limitations, FBGA-packaged components have an abbreviated part mark-
ing that is different from the part number. For a quick conversion of an FBGA code, see
the FBGA Part Marking Decoder on the Micron Web site: www.micron.com/decoder.

PDF: 09005aef80a1d9d4/Source: 09005aef80a1d9e7 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_1.fm - Rev. K 6/06 EN 2 ©2000 Micron Technology, Inc. All rights reserved.
 512Mb: x4, x8, x16 DDR SDRAM
Table of Contents

Table of Contents
FBGA Part Number System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
General Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Ball/Pin Assignments and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
CAS (READ) Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Output Drive Strength. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
DLL Enable/Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
DESELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
LOAD MODE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
BURST TERMINATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Bank/Row Activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
WRITEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Power-Down (CKE Not Active) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

PDF: 09005aef80a1d9d4/Source: 09005aef80a1d9e7 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDRx4x8x16TOC.fm - Rev. K 6/06 EN 3 ©2000–2005 Micron Technology, Inc. All rights reserved.
 512Mb: x4, x8, x16 DDR SDRAM
List of Figures

List of Figures
Figure 1: 512Mb DDR SDRAM Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Figure 2: 128 Meg x 4 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 3: 64 Meg x 8 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 4: 32 Meg x 16 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 5: 66-Pin TSOP Pin Assignment (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 6: 60-Ball FBGA Ball Assignment (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 7: Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 8: CAS Latency (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 9: Extended Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 10: Activating a Specific Row in a Specific Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 11: Example: Meeting tRCD (tRRD) MIN When 2 < tRCD (tRRD) MIN/tCK≤3 . . . . . . . . . . . . . . . . . . . . . . .26
Figure 12: READ Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Figure 13: READ Burst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Figure 14: Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Figure 15: Nonconsecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Figure 16: Random READ Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Figure 17: Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Figure 18: READ-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Figure 19: READ-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Figure 20: WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Figure 21: WRITE Burst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Figure 23: Nonconsecutive WRITE-to-WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Figure 24: Random WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Figure 26: WRITE-to-READ – Interrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Figure 27: WRITE-to-READ – Odd Number of Data, Interrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Figure 28: WRITE-to-PRECHARGE – Uninterrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Figure 29: WRITE-to-PRECHARGE – Interrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Figure 30: WRITE-to-Precharge – Odd Number of Data, Interrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Figure 31: PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Figure 32: Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Figure 33: Input Voltage Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Figure 34: SSTL_2 Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Figure 35: Derating Data Valid Window (tQH – tDQSQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Figure 36: Full Drive Pull-Down Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Figure 37: Full Drive Pull-Up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Figure 38: Reduced Drive Pull-Down Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Figure 39: Reduced Drive Pull-Up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Figure 40: x4, x8 Data Output Timing – tDQSQ, tQH, and Data Valid Window . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Figure 41: x16 Data Output Timing – tDQSQ, tQH, and Data Valid Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Figure 42: Data Output Timing – tAC and tDQSCK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Figure 43: Data Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Figure 44: Initialization Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Figure 45: Initialize and Load Mode Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Figure 46: Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Figure 47: Auto Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Figure 48: Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Figure 49: Bank Read – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Figure 50: Bank Read – With Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Figure 51: Bank Write – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Figure 52: Bank Write – With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Figure 53: Write – DM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

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 512Mb: x4, x8, x16 DDR SDRAM
List of Figures

Figure 54: 66-Pin Plastic TSOP (400 mil). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

Figure 55: 60-Ball FBGA (10 x 12.5mm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

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 512Mb: x4, x8, x16 DDR SDRAM
List of Tables

List of Tables
Table 1: Addressing Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Table 2: Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Table 3: Speed Grade Backward Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Table 4: Ball/Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Table 5: Reserved NC Balls and Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Table 6: Burst Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 7: CAS Latency (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 8: Truth Table – Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 9: Truth Table – DM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 10: Truth Table – CKE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Table 11: Truth Table – Current State Bank n – Command to Bank n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Table 12: Truth Table – Current State Bank n – Command to Bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Table 13: Command Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Table 14: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Table 15: DC Electrical Characteristics and Operating Conditions (-6, -6T, -75E, -75Z, -75) . . . . . . . . . . . . . . .54
Table 16: DC Electrical Characteristics and Operating Conditions (-5B DDR400) . . . . . . . . . . . . . . . . . . . . . . . .55
Table 17: AC Input Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Table 18: Clock Input Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Table 19: Capacitance (x4, x8 TSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Table 20: Capacitance (x4, x8 FBGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Table 21: Capacitance (x16 TSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Table 22: Capacitance (x16 FBGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Table 23: IDD Specifications and Conditions (x4, x8; -5B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Table 24: IDD Specifications and Conditions (x4, x8; -6/-6T/-75E/-75Z/-75) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Table 25: IDD Specifications and Conditions (x16; -5B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Table 26: IDD Specifications and Conditions (x16; -6/-6T/-75E/-75Z/-75) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Table 27: IDD Test Cycle Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Table 28: Electrical Characteristics & Recommended AC Operating Conditions (-5B) . . . . . . . . . . . . . . . . . . . .64
Table 29: Electrical Characteristics and Recommended AC Operating Conditions (-6/-6T/-75E) . . . . . . . . . .66
Table 30: Electrical Characteristics and Recommended AC Operating Conditions (-75Z/-75) . . . . . . . . . . . . .68
Table 31: Input Slew Rate Derating Values for Addresses and Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Table 32: Input Slew Rate Derating Values for DQ, DQS, and DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Table 33: Normal Output Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Table 34: Reduced Output Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

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 512Mb: x4, x8, x16 DDR SDRAM
General Description

General Description
The 512Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory con-
taining 536,870,912 bits. It is internally configured as a quad-bank DRAM.
The 512Mb DDR SDRAM uses a double data rate architecture to achieve high-speed
operation. The double data rate architecture is essentially a 2n-prefetch architecture
with an interface designed to transfer two data words per clock cycle at the I/O pins. A
single read or write access for the 512Mb DDR SDRAM effectively consists of a single 2n-
bit wide, one-clock-cycle data transfer at the internal DRAM core and two correspond-
ing n-bit wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in
data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during
READs and by the memory controller during WRITEs. DQS is edge-aligned with data for
READs and center-aligned with data for WRITEs. The x16 offering has two data strobes,
one for the lower byte and one for the upper byte.
The 512Mb DDR SDRAM operates from a differential clock (CK and CK#); the crossing of
CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Com-
mands (address and control signals) are registered at every positive edge of CK. Input
data is registered on both edges of DQS, and output data is referenced to both edges of
DQS, as well as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a
selected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which may then
be followed by a READ or WRITE command. The address bits registered coincident with
the ACTIVE command are used to select the bank and row to be accessed. The address
bits registered coincident with the READ or WRITE command are used to select the bank
and the starting column location for the burst access.
The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4, or 8
locations. An auto precharge function may be enabled to provide a self-timed row pre-
charge that is initiated at the end of the burst access.
As with standard SDR SDRAMs, the pipelined, multibank architecture of DDR SDRAMs
allows for concurrent operation, thereby providing high effective bandwidth by hiding
row precharge and activation time.
An auto refresh mode is provided, along with a power-saving power-down mode. All
inputs are compatible with the JEDEC Standard for SSTL_2. All full drive option outputs
are SSTL_2, Class II compatible.

General Notes
• The functionality and the timing specifications discussed in this data sheet are for the
DLL-enabled mode of operation.
• Throughout the data sheet, the various figures and text refer to DQs as “DQ.” The DQ
term is to be interpreted as any and all DQ collectively, unless specifically stated oth-
erwise. Additionally, the x16 is divided into two bytes, the lower byte and upper byte.
For the lower byte (DQ0–DQ7) DM refers to LDM and DQS refers to LDQS. For the
upper byte (DQ8–DQ15) DM refers to UDM and DQS refers to UDQS.
• Complete functionality is described throughout the document and any page or dia-
gram may have been simplified to convey a topic and may not be inclusive of all
requirements.
• Any specific requirement takes precedence over a general statement.

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 512Mb: x4, x8, x16 DDR SDRAM
General Description

Figure 2: 128 Meg x 4 Functional Block Diagram

CKE
CK#
CK

CS# CONTROL
COMMAND

LOGIC
DECODE

WE#
BANK3
CAS# BANK2
RAS# BANK1

REFRESH 13
MODE REGISTERS COUNTER
ROW- 13 BANK0
ADDRESS ROW- CK
BANK0
MUX ADDRESS MEMORY
15 8192
LATCH ARRAY
13 & (8,192 x 2,048 x 8) DATA DLL
DECODER 4

8 4
READ MUX
SENSE AMPLIFIERS LATCH 4 DRVRS

DQS 1
16384
GENERATOR
DQ0–
COL0 DQ3
DQS
2 I/O GATING INPUT
DM MASK LOGIC 8 REGISTERS
DQS
BANK
A0-A12, 1 1
ADDRESS CONTROL
BA0, BA1 15 MASK
1
REGISTER LOGIC
2 WRITE 1 1
2048 8 FIFO 2
(x8) & RCVRS
4 4 DM
DRIVERS
8 4
4 4
COLUMN clk clk
DECODER out in DATA

COLUMN-
ADDRESS 11 CK
12 1
COUNTER/
LATCH
COL0

Figure 3: 64 Meg x 8 Functional Block Diagram

CKE
CK#
CK

CS# CONTROL
COMMAND

LOGIC
DECODE

WE#
BANK3
CAS# BANK2
RAS# BANK1

REFRESH 13
MODE REGISTERS COUNTER
ROW- 13 BANK0
ADDRESS ROW- CK
BANK0
MUX ADDRESS MEMORY
15 8192
LATCH ARRAY
13 & (8,192 x 1,024 x 16) DATA DLL
DECODER 8

16 8
READ MUX
SENSE AMPLIFIERS LATCH 8 DRVRS

DQS 1
16384
GENERATOR
DQ0–
COL0 DQ7
DQS
2 I/O GATING INPUT
DM MASK LOGIC 16 REGISTERS
DQS
BANK
A0-A12, 1 1
ADDRESS CONTROL
BA0, BA1 15 MASK
1
REGISTER LOGIC
2 WRITE 1 1
1024 16 FIFO 2
(x16) & RCVRS
8 8 DM
DRIVERS
16 8
8 8
COLUMN clk clk
DECODER out in DATA

COLUMN-
ADDRESS 10 CK
11 COUNTER/ 1
LATCH COL0

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 512Mb: x4, x8, x16 DDR SDRAM
General Description

Figure 4: 32 Meg x 16 Functional Block Diagram

CKE
CK#
CK

CS# CONTROL
COMMAND

LOGIC
DECODE

WE#
BANK3
CAS# BANK2
RAS# REFRESH BANK1
COUNTER
13

MODE REGISTERS
ROW- 13 BANK0
ADDRESS ROW- C?K
BANK0
MUX ADDRESS MEMORY
15 8192
LATCH ARRAY
13 & DATA DLL
(8,192 x 512 x 32)
DECODER 16

32 16
READ MUX
SENSE AMPLIFIERS LATCH 16 DRVRS

DQS 2
16384
GENERATOR
DQ0 -
COL0 DQ15
DQS
2 I/O GATING INPUT
DM MASK LOGIC 32 REGISTERS LDQS
BANK UDQS
A0-A12, 2 2
ADDRESS CONTROL
BA0, BA1 15 MASK
2
REGISTER LOGIC
2 WRITE 2 2
512 32 FIFO 4
(x32) & RCVRS
16 16 LDM,
DRIVERS 32 UDM
16
16 16
COLUMN clk clk
DECODER out in DATA

COLUMN-
ADDRESS 9 CK
10 2
COUNTER/
LATCH
COL0

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 512Mb: x4, x8, x16 DDR SDRAM
Ball/Pin Assignments and Descriptions

Ball/Pin Assignments and Descriptions

Table 4: Ball/Pin Descriptions

FBGA TSOP
Numbers Numbers Symbol Type Description
G2, G3 45, 46 CK, CK# Input Clock: CK and CK# are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of CK and
negative edge of CK#. Output data (DQ and DQS) is referenced to the
crossings of CK and CK#.
H3 44 CKE Input Clock enable: CKE HIGH activates and CKE LOW deactivates the internal
clock, input buffers and output drivers. Taking CKE LOW provides
PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle),
or ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE is synchronous
for POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE is
asynchronous for SELF REFRESH exit and for disabling the outputs. CKE
must be maintained HIGH throughout read and write accesses. Input
buffers (excluding CK, CK#, and CKE) are disabled during POWER-DOWN.
Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an
SSTL_2 input but will detect an LVCMOS LOW level after VDD is applied
and until CKE is first brought HIGH, after which it becomes a SSTL_2
input only.
H8 24 CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH)
the command decoder. All commands are masked when CS# is registered
HIGH. CS# provides for external bank selection on systems with multiple
banks. CS# is considered part of the command code.
H7, G8, 23, 22, RAS#, CAS#, Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the
G7 21 WE# command being entered.
3F 47 DM Input Input data mask: DM is an input mask signal for write data. Input data is
F7, 3F 20, 47 LDM, UDM masked when DM is sampled HIGH along with that input data during a
WRITE access. DM is sampled on both edges of DQS. Although DM pins
are input-only, the DM loading is designed to match that of DQ and DQS
pins. For the x16, LDM is DM for DQ0–DQ7 and UDM is DM for DQ8–
DQ15. Pin 20 is a NC on x4 and x8.
J8, J7 26, 27 BA0, BA1 Input Bank address inputs: BA0 and BA1 define to which bank an ACTIVE, READ,
WRITE, or PRECHARGE command is being applied.
K7, L8, L7, 29, 30, 31, A0, A1, A2, Input Address inputs: Provide the row address for ACTIVE commands, and the
M8, M2, L3, 32, 35, 36, A3, A4, A5, column address and auto precharge bit (A10) for READ/WRITE commands,
L2, K3, K2, 37, 38, 39, A6, A7, A8, to select one location out of the memory array in the respective bank. A10
J3, K8, 40, 28 A9, A10, sampled during a PRECHARGE command determines whether the
J2, H2 41, 42 A11, A12 PRECHARGE applies to one bank (A10 LOW, bank selected by BA0, BA1) or
all banks (A10 HIGH). The address inputs also provide the op-code during
a MODE REGISTER SET command. BA0 and BA1 define which mode
register (mode register or extended mode register) is loaded during the
LOAD MODE REGISTER (LMR) command.

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 512Mb: x4, x8, x16 DDR SDRAM
Ball/Pin Assignments and Descriptions

Table 4: Ball/Pin Descriptions (Continued)

FBGA TSOP
Numbers Numbers Symbol Type Description
A8, B9, B7, 2, 4, 5, DQ0–DQ2 I/O Data input/output: Data bus for x16
C9, C7, D9, 7, 8, 10, DQ3–DQ5
D7, E9, E1, 11, 13, 54, DQ6–DQ8
D3, D1, C3, 56, 57, 59, DQ9–DQ11
C1, B3, B1, 60, 62, 63, DQ12–DQ14
A2 65 DQ15
– 14, 17, 25, NC – No connect for x16
43, 53 These pins should be left unconnected.
A8, B7, C7, 2, 5, 8, DQ0–DQ2 I/O Data input/output: Data bus for x8
D7, D3, C3, 11, 56, 59, DQ3–DQ5
B3, A2 62, 65 DQ6, DQ7
B1, B9, C1, 4, 7, 10, 13, NC – No connect for x8
C9, D1, D9, 14, 16, 17, These pins should be left unconnected.
E1, E7, E9, 20, 25, 43,
F7 53, 54, 57,
60, 63,
B7, D7, D3, 5, 11, 56, DQ0–DQ2 I/O Data input/output: Data bus for x4
B3 62 DQ3
B1, B9, C1, 4, 7, 10, 13, NC – No connect for x4
C9, D1, D9, 14, 16, 17, These pins should be left unconnected.
E1, E7, E9, 20, 25, 43,
F7 53, 54, 57,
60, 63
A2, A8, C3, 2, 8, 59, 65 NF – No function for x4
C7 These pins should be left unconnected.
E3 51 DQS I/O Data strobe: Output with read data, input with write data. DQS is edge-
E7 16 LDQS aligned with read data, centered in write data. It is used to capture data.
E3 51 UDQS For the x16, LDQS is DQS for DQ0–DQ7 and UDQS is DQS for DQ8–DQ15.
Pin 16 (E7) is NC on x4 and x8.
F9 19, 50 DNU – Do not use: Must float to minimize noise on VREF.
B2, D2, C8, 3, 9, 15, 55, VDDQ Supply DQ power supply: +2.5V ±0.2V (+2.6V ±0.1V for DDR400). Isolated on the
E8, A9 61 die for improved noise immunity.
A1, C2, E2, 6, 12, 52, 58, VSSQ Supply DQ ground. Isolated on the die for improved noise immunity.
B8, D8 64
F8, M7, A7 1, 18, 33 VDD Supply Power supply: +2.5V ±0.2V. (+2.6V ±0.1V for DDR400)
A3, F2, M3 34, 48, 66 VSS Supply Ground.
F1 49 VREF Supply SSTL_2 reference voltage.

Table 5: Reserved NC Balls and Pins

This table defines specific NC pins; NC pins not listed may also be reserved for other uses now or in the future.

FBGA TSOP
Numbers Numbers Symbol Type Description
F9 17 A13 I Address input A13 for 1Gb devices.

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 512Mb: x4, x8, x16 DDR SDRAM
Ball/Pin Assignments and Descriptions

Figure 5: 66-Pin TSOP Pin Assignment (Top View)

x4 x8 x16 x16 x8 x4
VDD VDD VDD 1 66 VSS VSS VSS
NF DQ0 DQ0 2 65 DQ15 DQ7 NF
VDDQ VDDQ VDDQ 3 64 VSSQ VSSQ VSSQ
NC NC DQ1 4 63 DQ14 NC NC
DQ0 DQ1 DQ2 5 62 DQ13 DQ6 DQ3
VSSQ VSSQ VssQ 6 61 VDDQ VDDQ VDDQ
NC NC DQ3 7 60 DQ12 NC NC
NF DQ2 DQ4 8 59 DQ11 DQ5 NF
VDDQ VDDQ VDDQ 9 58 VSSQ VSSQ VSSQ
NC NC DQ5 10 57 DQ10 NC NC
DQ1 DQ3 DQ6 11 56 DQ9 DQ4 DQ2
VSSQ VSSQ VssQ 12 55 VDDQ VDDQ VDDQ
NC NC DQ7 13 54 DQ8 NC NC
NC NC NC 14 53 NC NC NC
VDDQ VDDQ VDDQ 15 52 VSSQ VSSQ VSSQ
NC NC LDQS 16 51 UDQS DQS DQS
NC NC NC 17 50 DNU DNU DNU
VDD VDD VDD 18 49 VREF VREF VREF
DNU DNU DNU 19 48 VSS VSS VSS
NC NC LDM 20 47 UDM DM DM
WE# WE# WE# 21 46 CK# CK# CK#
CAS# CAS# CAS# 22 45 CK CK CK
RAS# RAS# RAS# 23 44 CKE CKE CKE
CS# CS# CS# 24 43 NC NC NC
NC NC NC 25 42 A12 A12 A12
BA0 BA0 BA0 26 41 A11 A11 A11
BA1 BA1 BA1 27 40 A9 A9 A9
A10/AP A10/AP A10/AP 28 39 A8 A8 A8
A0 A0 A0 29 38 A7 A7 A7
A1 A1 A1 30 37 A6 A6 A6
A2 A2 A2 31 36 A5 A5 A5
A3 A3 A3 32 35 A4 A4 A4
VDD VDD VDD 33 34 VSS VSS VSS

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 512Mb: x4, x8, x16 DDR SDRAM
Ball/Pin Assignments and Descriptions

Figure 6: 60-Ball FBGA Ball Assignment (Top View)

x4 (Top View)
1 2 3 4 5 6 7 8 9

VSSQ NF VSS A VDD NF VDDQ

NC VDDQ DQ3 B DQ0 VSSQ NC
NC VSSQ NF C NF VDDQ NC
NC VDDQ DQ2 D DQ1 VSSQ NC
NC VSSQ DQS E NC VDDQ NC
VREF VSS DM F NC VDD NC
CK CK# G WE# CAS#
A12 CKE H RAS# CS#
A11 A9 J BA1 BA0
A8 A7 K A0 A10
A6 A5 L A2 A1
A4 VSS M VDD A3

x8 (Top View)
1 2 3 4 5 6 7 8 9

VSSQ DQ7 VSS A VDD DQ0 VDDQ

NC VDDQ DQ6 B DQ1 VSSQ NC
NC VSSQ DQ5 C DQ2 VDDQ NC
NC VDDQ DQ4 D DQ3 VSSQ NC
NC VSSQ DQS E NC VDDQ NC
VREF VSS DM F NC VDD NC
CK CK# G WE# CAS#
A12 CKE H RAS# CS#
A11 A9 J BA1 BA0
A8 A7 K A0 A10
A6 A5 L A2 A1
A4 VSS M VDD A3

x16 (Top View)

1 2 3 4 5 6 7 8 9

VSSQ DQ15 VSS A VDD DQ0 VDDQ

DQ14 VDDQ DQ13 B DQ2 VSSQ DQ1
DQ12 VSSQ DQ11 C DQ4 VDDQ DQ3
DQ10 VDDQ DQ9 D DQ6 VSSQ DQ5
DQ8 VSSQ UDQS E LDQS VDDQ DQ7
VREF VSS UDM F LDM VDD NC
CK CK# G WE# CAS#
A12 CKE H RAS# CS#
A11 A9 J BA1 BA0
A8 A7 K A0 A10
A6 A5 L A2 A1
A4 VSS M VDD A3

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 512Mb: x4, x8, x16 DDR SDRAM
Functional Description

Functional Description
The 512Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory con-
taining 536,870,912 bits. The 512Mb DDR SDRAM is internally configured as a quad-
bank DRAM.
The 512Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed
operation. The double-data-rate architecture is essentially a 2n-prefetch architecture,
with an interface designed to transfer two data words per clock cycle at the I/O pins. A
single read or write access for the 512Mb DDR SDRAM consists of a single 2n-bit wide,
one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit
wide, one-half-clock-cycle data transfers at the I/O pins.
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a
selected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select
the bank; A0–A12 select the row). The address bits registered coincident with the READ
or WRITE command are used to select the starting column location for the burst access.
Prior to normal operation, the DDR SDRAM must be initialized. The following sections
provide detailed information covering device initialization, register definition, com-
mand descriptions, and device operation.

Initialization
DDR SDRAMs must be powered up and initialized in a predefined manner. Operational
procedures other than those specified may result in undefined operation. Power must
first be applied to VDD and VDDQ simultaneously, and then to VREF (and to the system
VTT). VTT must be applied after VDDQ to avoid device latch-up, which may cause perma-
nent damage to the device. VREF can be applied any time after VDDQ but is expected to
be nominally coincident with VTT. Except for CKE, inputs are not recognized as valid
until after VREF is applied. CKE is an SSTL_2 input but will detect an LVCMOS LOW level
after VDD is applied. After CKE passes through VIH, it will transition to a SSTL 2 signal
and remain as such until power is cycled. Maintaining an LVCMOS LOW level on CKE
during power-up is required to ensure that the DQ and DQS outputs will be in the High-
Z state, where they will remain until driven in normal operation (by a read access). After
all power supply and reference voltages are stable, and the clock is stable, the DDR
SDRAM requires a 200µs delay prior to applying an executable command.
Once the 200µs delay has been satisfied, a DESELECT or NOP command should be
applied, and CKE should be brought HIGH. Following the NOP command, a PRE-
CHARGE ALL command should be applied. Next a LOAD MODE REGISTER command
should be issued for the extended mode register (BA1 LOW and BA0 HIGH) to enable the
DLL, followed by another LOAD MODE REGISTER command to the mode register (BA0/
BA1 both LOW) to reset the DLL and to program the operating parameters. Two-hun-
dred clock cycles are required between the DLL reset and any READ command. A PRE-
CHARGE ALL command should then be applied, placing the device in the all banks idle
state.
Once in the idle state, two AUTO REFRESH cycles must be performed (tRFC must be sat-
isfied.) Additionally, a LOAD MODE REGISTER command for the mode register with the
reset DLL bit deactivated (i.e., to program operating parameters without resetting the
DLL) is required. Following these requirements, the DDR SDRAM is ready for normal
operation.

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 512Mb: x4, x8, x16 DDR SDRAM
Register Definition

Register Definition
Mode Register
The mode register is used to define the specific mode of operation of the DDR SDRAM.
This definition includes the selection of a burst length, a burst type, a CAS latency and
an operating mode, as shown in Figure 7 on page 16. The mode register is programmed
via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the
stored information until it is programmed again or the device loses power (except for bit
A8, which is self-clearing).
Reprogramming the mode register will not alter the contents of the memory, provided it
is performed correctly. The mode register must be loaded (reloaded) when all banks are
idle and no bursts are in progress, and the controller must wait the specified time before
initiating the subsequent operation. Violating either of these requirements will result in
unspecified operation.
Mode register bits A0–A2 specify the burst length, A3 specifies the type of burst (sequen-
tial or interleaved), A4–A6 specify the CAS latency, and A7–A12 specify the operating
mode.

Burst Length
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length
being programmable, as shown in Figure 7 on page 16. The burst length determines the
maximum number of column locations that can be accessed for a given READ or WRITE
command. BL = 2, BL = 4, or BL = 8 locations are available for both the sequential and the
interleaved burst types.
Reserved states should not be used, as unknown operation or incompatibility with
future versions may result.
When a READ or WRITE command is issued, a block of columns equal to the burst
length is effectively selected. All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a boundary is reached. The block is
uniquely selected by A1-Ai when BL = 2, by A2–Ai when BL = 4 and by A3–Ai when BL = 8
(where Ai is the most significant column address bit for a given configuration). The
remaining (least significant) address bit(s) is (are) used to select the starting location
within the block. The programmed burst length applies to both READ and WRITE
bursts.

Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved;
this is referred to as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the burst length, the burst type
and the starting column address, as shown in Table 6 on page 17.

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 512Mb: x4, x8, x16 DDR SDRAM
Register Definition

Figure 7: Mode Register Definition

BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus

14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register
0 0 Operating Mode CAS Latency BT Burst Length (Mx)

M2 M1 M0 Burst Length
M14 M13 Mode Register Definition
0 0 0 Reserved
0 0 Base Mode Register
0 0 1 2
0 1 Extended Mode Register M3 Burst Type
0 1 0 4
1 0 Reserved 0 Sequential
0 1 1 8
1 1 Reserved 1 Interleaved
1 0 0 Reserved
1 0 1 Reserved
M12 M11 M10 M9 M8 M7 M6-M0 Operating Mode 1 1 0 Reserved
0 0 0 0 0 0 Valid Normal operation 1 1 1 Reserved
0 0 0 0 1 0 Valid Normal operation/Reset DLL
- - - - - - - All other states reserved
M6 M5 M4 CAS Latency
0 0 0 Reserved
0 0 1 Reserved
0 1 0 2
0 1 1 3 (DDR400 Only)
1 0 0 Reserved
1 0 1 Reserved
1 1 0 2.5
1 1 1 Reserved

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 512Mb: x4, x8, x16 DDR SDRAM
Register Definition

Table 6: Burst Definition

Order of Accesses Within a Burst

Burst Starting Column
Length Address Type= Sequential Type= Interleaved
2 – – A0 – –
– – 0 0-1 0-1
– – 1 1-0 1-0
4 – A1 A0 – –
– 0 0 0-1-2-3 0-1-2-3
– 0 1 1-2-3-0 1-0-3-2
– 1 0 2-3-0-1 2-3-0-1
– 1 1 3-0-1-2 3-2-1-0
8 A2 A1 A0 – –
0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
Notes: 1. Whenever a boundary of the block is reached within a given sequence above, the follow-
ing access wraps within the block.
2. For BL = 2, A1–Ai select the two-data-element block; A0 selects the first access within the
block.
3. For BL = 4, A2–Ai select the four-data-element block; A0–A1 select the first access within
the block.
4. For BL = 8, A3–Ai select the eight-data-element block; A0–A2 select the first access within
the block.

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 512Mb: x4, x8, x16 DDR SDRAM
Register Definition

CAS (READ) Latency

The READ latency is the delay, in clock cycles, between the registration of a READ com-
mand and the availability of the first bit of output data. The latency can be set to 2, 2.5, or
3 (DDR400 only) clocks, as shown in Figure 8.
If a READ command is registered at clock edge n, and the latency is m clocks, the data
will be available nominally coincident with clock edge n + m. Table 7 on page 19 indi-
cates the operating frequencies at which each CAS latency (CL) setting can be used.
Reserved states should not be used, as unknown operation or incompatibility with
future versions may result.

Figure 8: CAS Latency (CL)

T0 T1 T2 T2n T3 T3n
CK#
CK

COMMAND READ NOP NOP NOP

CL = 2

DQS

DQ

T0 T1 T2 T2n T3 T3n
CK#
CK

COMMAND READ NOP NOP NOP

CL = 2.5

DQS

DQ

T0 T1 T2 T3 T3n
CK#
CK

COMMAND READ NOP NOP NOP

CL = 3

DQS

DQ

TRANSITIONING DATA DON’T CARE

Note: Burst Length = 4 in the cases shown; shown with nominal tAC, tDQSCK, and tDQSQ.

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 512Mb: x4, x8, x16 DDR SDRAM
Extended Mode Register

Table 7: CAS Latency (CL)

Allowable Operating Clock Frequency (MHz)

Speed CL = 2 CL = 2.5 CL = 3
-5B 75 ≤ f ≤ 133 75 ≤ f ≤ 167 133 ≤ f ≤ 200
-6/-6T 75 ≤ f ≤ 133 75 ≤ f ≤ 167 –
-75E 75 ≤ f ≤ 133 75 ≤ f ≤ 133 –
-75Z 75 ≤ f ≤ 133 75 ≤ f ≤ 133 –
-75 75 ≤ f ≤ 100 75 ≤ f ≤ 133 –

Operating Mode
The normal operating mode is selected by issuing a MODE REGISTER SET command
with bits A7–A12 each set to zero, and bits A0–A6 set to the desired values. A DLL reset is
initiated by issuing a MODE REGISTER SET command with bits A7 and A9–A12 each set
to zero, bit A8 set to one, and bits A0–A6 set to the desired values. Although not required
by the Micron device, JEDEC specifications recommend that a LOAD MODE REGISTER
command resetting the DLL should always be followed by a LOAD MODE REGISTER
command selecting normal operating mode.
All other combinations of values for A7–A12 are reserved for future use and/or test
modes. Test modes and reserved states should not be used, as unknown operation or
incompatibility with future versions may result.

Extended Mode Register

The extended mode register controls functions beyond those controlled by the mode
register; these additional functions are DLL enable/disable, and output drive strength.
These functions are controlled via the bits shown in Figure 9 on page 20. The extended
mode register is programmed via the LOAD MODE REGISTER command to the mode
register (with BA0 = 1 and BA1 = 0) and will retain the stored information until it is pro-
grammed again or the device loses power. The enabling of the DLL should always be fol-
lowed by a LOAD MODE REGISTER command to the mode register (BA0/BA1 both
LOW) to reset the DLL.
The extended mode register must be loaded when all banks are idle and no bursts are in
progress, and the controller must wait the specified time before initiating any subse-
quent operation. Violating either requirement could result in unspecified operation.

Output Drive Strength

The normal drive strength for all outputs are specified to be SSTL2, Class II. The x16 sup-
ports a programmable option for reduced drive. This option is intended for the support
of the lighter load and/or point-to-point environments. The selection of the reduced
drive strength will alter the DQ pins and DQS pins from SSTL2, Class II drive strength to
a reduced drive strength, which is approximately 54 percent of the SSTL2, Class II drive
strength.

DLL Enable/Disable
When the part is running without the DLL enabled, device functionality may be altered.
The DLL must be enabled for normal operation. DLL enable is required during power-
up initialization and upon returning to normal operation after having disabled the DLL
for the purpose of debug or evaluation. (When the device exits self refresh mode, the
DLL is enabled automatically.) Anytime the DLL is enabled, 200 clock cycles with CKE
HIGH must occur before a READ command can be issued.

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 512Mb: x4, x8, x16 DDR SDRAM
Extended Mode Register

Figure 9: Extended Mode Register Definition

BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus

14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Extended Mode
0 1 Operating Mode DS DLL Register (Ex)

E0 DLL
0 Enable
M14 M13 Mode Register Definition
1 Disable
0 0 Base Mode Register
0 1 Extended Mode Register E11 Drive Strength
1 0 Reserved 0 Normal
1 1 Reserved 1 Reduced

2
E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1, E0 Operating Mode
0 0 0 0 0 0 0 0 0 0 0 Valid Reserved
– – – – – – – – – – – – Reserved

Notes: 1. The reduced drive strength option is available on the x16 version. The reduced drive
strength option is not supported on the x4 and x8 versions; contact Micron for future sup-
port of this feature.
2. The QFC# option is not supported.

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 512Mb: x4, x8, x16 DDR SDRAM
Commands

Commands
Table 8 and Table 9 provide a quick reference of available commands. This is followed by
a text description of each command. Two additional Truth Tables—Table 11 on page 50,
and Table 12 on page 52— appear following “Operations” on page 25 and provide cur-
rent state/next state information.

Table 8: Truth Table – Commands

CKE is HIGH for all commands shown except SELF REFRESH.

Name (Function) CS# RAS# CAS# WE# Address Notes

DESELECT (NOP) H X X X X 1
NO OPERATION (NOP) L H H H X 1
ACTIVE (Select bank and activate row) L L H H Bank/Row 2
READ (Select bank and column, and start READ burst) L H L H Bank/Col 3
WRITE (Select bank and column, and start WRITE burst) L H L L Bank/Col 3
BURST TERMINATE L H H L X 4
PRECHARGE (Deactivate row in bank or banks) L L H L Code 5
AUTO REFRESH or SELF REFRESH L L L H X 6, 7
(Enter self refresh mode)
LOAD MODE REGISTER L L L L Op-Code 8

Notes: 1. DESELECT and NOP are functionally interchangeable.

2. BA0–BA1 provide bank address and A0–A12 provide row address.
3. BA0–BA1 provide bank address; A0–Ai provide column address, (where i = 9 for x16, i = 9,
11 for x8, and i = 9, 11, 12 for x4) A10 HIGH enables the auto precharge feature (non per-
sistent), and A10 LOW disables the auto precharge feature.
4. Applies only to read bursts with auto precharge disabled; this command is undefined (and
should not be used) for read bursts with auto precharge enabled and for write bursts.
5. A10 LOW: BA0–BA1 determine which bank is precharged.
A10 HIGH: all banks are precharged and BA0–BA1 are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing while in self refresh mode, all inputs and
I/Os are “Don’t Care” except for CKE.
8. BA0–BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0
select the mode register; BA0 = 1, BA1 = 0 select extended mode register; other combina-
tions of BA0–BA1 are reserved). A0–A12 provide the op-code to be written to the selected
mode register.

Table 9: Truth Table – DM Operation

Used to mask write data; provided coincident with the corresponding data.

Name (Function) DM DQ
Write Enable L Valid
Write Inhibit H X

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 512Mb: x4, x8, x16 DDR SDRAM
Commands

DESELECT
The DESELECT function (CS# HIGH) prevents new commands from being executed by
the DDR SDRAM. The DDR SDRAM is effectively deselected. Operations already in
progress are not affected.

NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to instruct the selected DDR SDRAM to
perform a NOP (CS# is LOW with RAS#, CAS#, and WE# are HIGH). This prevents
unwanted commands from being registered during idle or wait states. Operations
already in progress are not affected.

LOAD MODE REGISTER

The mode registers are loaded via inputs A0–A12. See mode register descriptions in
“Register Definition” on page 15. The LOAD MODE REGISTER command can only be
issued when all banks are idle, and a subsequent executable command cannot be issued
until tMRD is met.

ACTIVE
The ACTIVE command is used to open (or activate) a row in a particular bank for a sub-
sequent access. The value on the BA0, BA1 inputs selects the bank, and the address pro-
vided on inputs A0–A12 selects the row. This row remains active (or open) for accesses
until a precharge command is issued to that bank. A PRECHARGE command must be
issued before opening a different row in the same bank.

READ
The READ command is used to initiate a burst read access to an active row. The value on
the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–Ai (where i
= 9 for x16; 9, 11 for x8; or 9, 11, 12 for x4) selects the starting column location. The value
on input A10 determines whether or not auto precharge is used. If auto precharge is
selected, the row being accessed will be precharged at the end of the READ burst; if auto
precharge is not selected, the row will remain open for subsequent accesses.

WRITE
The WRITE command is used to initiate a burst write access to an active row. The value
on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–Ai
(where i = 9 for x16; 9, 11 for x8; or 9, 11, 12 for x4) selects the starting column location.
The value on input A10 determines whether or not auto precharge is used. If auto pre-
charge is selected, the row being accessed will be precharged at the end of the WRITE
burst; if auto precharge is not selected, the row will remain open for subsequent
accesses. Input data appearing on the DQ is written to the memory array subject to the
DM input logic level appearing coincident with the data. If a given DM signal is regis-
tered LOW, the corresponding data will be written to memory; if the DM signal is regis-
tered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be
executed to that byte/column location.

PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or
the open row in all banks. The bank(s) will be available for a subsequent row access a
specified time (tRP) after the precharge command is issued, except in the case of concur-
rent auto precharge. With concurrent auto precharge, a READ or WRITE command to a
different bank is allowed as long as it does not interrupt the data transfer in the current
bank and does not violate any other timing parameters. Input A10 determines whether

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 512Mb: x4, x8, x16 DDR SDRAM
Commands

one or all banks are to be precharged, and in the case where only one bank is to be pre-
charged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t
Care.” Once a bank has been precharged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued to that bank. A PRECHARGE com-
mand will be treated as a NOP if there is no open row in that bank (idle state), or if the
previously open row is already in the process of precharging.

Auto Precharge
Auto precharge is a feature which performs the same individual-bank precharge func-
tion described above, but without requiring an explicit command. This is accomplished
by using A10 to enable auto precharge in conjunction with a specific READ or WRITE
command. A precharge of the bank/row that is addressed with the READ or WRITE com-
mand is automatically performed upon completion of the READ or WRITE burst. Auto
precharge is either enabled or disabled for each individual READ or WRITE command.
This device supports concurrent auto precharge if the command to the other bank does
not interrupt the data transfer to the current bank.
Auto precharge ensures that the precharge is initiated at the earliest valid stage within a
burst. This “earliest valid stage” is determined as if an explicit PRECHARGE command
was issued at the earliest possible time, without violating tRAS (MIN), as described for
each burst type in “Operations” on page 25. The user must not issue another command
to the same bank until the precharge time (tRP) is completed.

BURST TERMINATE
The BURST TERMINATE command is used to truncate read bursts (with auto precharge
disabled). The most recently registered READ command prior to the BURST TERMI-
NATE command will be truncated, as shown in “Operations” on page 25. The open page
from which the READ burst was terminated remains open.

AUTO REFRESH
AUTO REFRESH is used during normal operation of the DDR SDRAM and is analogous
to CAS#-BEFORE-RAS# (CBR) refresh in FPM/EDO DRAMs. This command is nonper-
sistent, so it must be issued each time a refresh is required. All banks must be idle before
an AUTO REFRESH command is issued.
The addressing is generated by the internal refresh controller. This makes the address
bits a “Don’t Care” during an AUTO REFRESH command. The 512Mb DDR SDRAM
requires AUTO REFRESH cycles at an average interval of 7.8125µs (MAX).
To allow for improved efficiency in scheduling and switching between tasks, some flexi-
bility in the absolute refresh interval is provided. A maximum of eight AUTO REFRESH
commands can be posted to any given DDR SDRAM, meaning that the maximum abso-
lute interval between any AUTO REFRESH command and the next AUTO REFRESH
command is 9 x 7.8125µs (70.3µs). JEDEC specifications only allows 8 x 7.8125µs; Micron
specification exceeds the JEDEC requirement by one clock. This maximum absolute
interval is to allow future support for DLL updates internal to the DDR SDRAM to be
restricted to AUTO REFRESH cycles, without allowing excessive drift in tAC between
updates.
Although not a JEDEC requirement, to provide for future functionality features, CKE
must be active (HIGH) during the AUTO REFRESH period. The AUTO REFRESH period
begins when the AUTO REFRESH command is registered and ends tRFC later.

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 512Mb: x4, x8, x16 DDR SDRAM
Commands

SELF REFRESH
The SELF REFRESH command can be used to retain data in the DDR SDRAM, even if the
rest of the system is powered down. When in the self refresh mode, the DDR SDRAM
retains data without external clocking. The SELF REFRESH command is initiated like an
AUTO REFRESH command except CKE is disabled (LOW). The DLL is automatically dis-
abled upon entering SELF REFRESH and is automatically enabled upon exiting SELF
REFRESH (A DLL reset and 200 clock cycles must then occur before a READ command
can be issued). Input signals except CKE are “Don’t Care” during SELF REFRESH. VREF
voltage is also required for the full duration of SELF REFRESH.
The procedure for exiting SELF REFRESH requires a sequence of commands. First, CK
and CK# must be stable prior to CKE going back HIGH. Once CKE is HIGH, the DDR
SDRAM must have NOP commands issued for tXSNR because time is required for the
completion of any internal refresh in progress. A simple algorithm for meeting both
refresh and DLL requirements is to apply NOPs for tXSRD time, then a DLL RESET (via
the extended mode register) and NOPs for 200 additional clock cycles before applying a
READ. Any command besides a READ can be performed tXSNR MIN after the DLL reset.
NOP or DESELECT commands must be issued during the tXSNR MIN time.

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 512Mb: x4, x8, x16 DDR SDRAM
Operations

Operations
Bank/Row Activation
Before any READ or WRITE commands can be issued to a bank within the DDR SDRAM,
a row in that bank must be “opened.” This is accomplished via the ACTIVE command,
which selects both the bank and the row to be activated, as shown in Figure 10.
After a row is opened with an ACTIVE command, a READ or WRITE command may be
issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by
the clock period and rounded up to the next whole number to determine the earliest
clock edge after the ACTIVE command on which a READ or WRITE command can be
entered. For example, a tRCD specification of 20ns with a 133 MHz clock (7.5ns period)
results in 2.7 clocks rounded to 3. This is reflected in Figure 11 on page 26, which covers
any case where 2 < tRCD (MIN)/tCK ≤ 3. (Figure 11 also shows the same case for tRCD;
the same procedure is used to convert other specification limits from time units to clock
cycles.)
A subsequent ACTIVE command to a different row in the same bank can only be issued
after the previous active row has been “closed” (precharged). The minimum time inter-
val between successive ACTIVE commands to the same bank is defined by tRC.
A subsequent ACTIVE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The minimum
time interval between successive ACTIVE commands to different banks is defined by
t
RRD.

Figure 10: Activating a Specific Row in a Specific Bank

CK#
CK

CKE HIGH

CS#

RAS#

CAS#

WE#

A0-A12 RA

BA0, BA1 BA

DON’T CARE
RA = Row address
BA = Bank address

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 512Mb: x4, x8, x16 DDR SDRAM
Operations

Figure 11: Example: Meeting tRCD (tRRD) MIN When 2 < tRCD (tRRD) MIN/tCK≤3

T0 T1 T2 T3 T4 T5 T6 T7
CK#
CK

COMMAND ACT NOP NOP ACT NOP NOP RD/WR NOP

A0-A12 Row Row Col

BA0, BA1 Bank x Bank y Bank y

t RRD t RCD

DON’T CARE

READs
READ bursts are initiated with a READ command, as shown in Figure 12 on page 27.
The starting column and bank addresses are provided with the READ command and
auto precharge is either enabled or disabled for that burst access. If auto precharge is
enabled, the row being accessed is precharged at the completion of the burst.
Note: For the READ commands used in the following illustrations, auto precharge is dis-
abled.
During READ bursts, the valid data-out element from the starting column address will
be available following the CAS latency after the READ command. Each subsequent data-
out element will be valid nominally at the next positive or negative clock edge (i.e., at the
next crossing of CK and CK#). Figure 13 on page 28 shows general timing for each possi-
ble CAS latency setting. DQS is driven by the DDR SDRAM along with output data. The
initial LOW state on DQS is known as the read preamble; the LOW state coincident with
the last data-out element is known as the read postamble.
Upon completion of a burst, assuming no other commands have been initiated, the DQs
will go High-Z. A detailed explanation of tDQSQ (valid data-out skew), tQH (data-out
window hold), the valid data window are depicted in Figure 40 on page 80 and Figure 41
on page 81. A detailed explanation of tDQSCK (DQS transition skew to CK) and tAC
(data-out transition skew to CK) is depicted in Figure 42 on page 82.
Data from any READ burst may be concatenated with or truncated with data from a sub-
sequent READ command. In either case, a continuous flow of data can be maintained.
The first data element from the new burst follows either the last element of a completed
burst or the last desired data element of a longer burst which is being truncated. The
new READ command should be issued x cycles after the first READ command, where x
equals the number of desired data element pairs (pairs are required by the 2n-prefetch
architecture). This is shown in Figure 14 on page 29. A READ command can be initiated
on any clock cycle following a previous READ command. Nonconsecutive read data is
shown for illustration in Figure 15 on page 30. Full-speed random read accesses within a
page (or pages) can be performed, as shown in Figure 16 on page 31.

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Operations

Data from any READ burst may be truncated with a BURST TERMINATE command, as
shown in Figure 17 on page 32. The BURST TERMINATE latency is equal to the read
(CAS) latency, i.e., the BURST TERMINATE command should be issued x cycles after the
READ command, where x equals the number of desired data element pairs (pairs are
required by the 2n-prefetch architecture).
Data from any READ burst must be completed or truncated before a subsequent WRITE
command can be issued. If truncation is necessary, the BURST TERMINATE command
must be used, as shown in Figure 18 on page 33. The tDQSS (NOM) case is shown; the
t
DQSS (MAX) case has a longer bus idle time. (tDQSS [MIN] and tDQSS [MAX] are
defined in the section on WRITEs.)
A READ burst may be followed by, or truncated with, a PRECHARGE command to the
same bank provided that auto precharge was not activated.
The PRECHARGE command should be issued x cycles after the READ command, where
x equals the number of desired data element pairs (pairs are required by the 2n-prefetch
architecture). This is shown in Figure 19 on page 34. Following the PRECHARGE com-
mand, a subsequent command to the same bank cannot be issued until both tRAS and
tRP has been met. Part of the row precharge time is hidden during the access of the last

data elements.

Figure 12: READ Command

CK#
CK

CKE HIGH

CS#

RAS#

CAS#

WE#

x4: A0–A9, A11, A12

x8: A0–A9, A11 CA
x16: A0–A9

x8: A12
x16: A11, A12
EN AP
A10
DIS AP

BA0,1 BA

DON’T CARE

Note: CA = Column address; BA = Bank address; EN AP = Enable auto precharge; and DIS AP =
Disable auto precharge.

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 512Mb: x4, x8, x16 DDR SDRAM
Operations

Figure 13: READ Burst

T0 T1 T2 T2n T3 T3n T4 T5
CK#
CK
COMMAND READ NOP NOP NOP NOP NOP

ADDRESS Bank a,
Col n
CL = 2

DQS

DO
DQ n

T0 T1 T2 T2n T3 T3n T4 T5
CK#
CK
COMMAND READ NOP NOP NOP NOP NOP

ADDRESS Bank a,
Col n
CL = 2.5

DQS

DQ DO
n

T0 T1 T2 T3 T3n T4 T4n T5
CK#
CK
COMMAND READ NOP NOP NOP NOP NOP

ADDRESS Bank a,
Col n
CL = 3

DQS

DQ DO
n

DON’T CARE TRANSITIONING DATA

Notes: 1. DO n = data-out from column n.

2. BL = 4.
3. Three subsequent elements of data-out appear in the programmed order following DO n.
4. Shown with nominal tAC, tDQSCK, and tDQSQ.

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 512Mb: x4, x8, x16 DDR SDRAM
Operations

Figure 14: Consecutive READ Bursts

T0 T1 T2 T2n T3 T3n T4 T4n T5 T5n

CK#
CK
COMMAND READ NOP READ NOP NOP NOP

ADDRESS Bank, Bank,

Col n Col b
CL = 2

DQS

DO DO
DQ n b

T0 T1 T2 T2n T3 T3n T4 T4n T5 T5n

CK#
CK
COMMAND READ NOP READ NOP NOP NOP

ADDRESS Bank, Bank,

Col n Col b
CL = 2.5

DQS

DO DO
DQ n b

T0 T1 T2 T3 T3n T4 T4n T5 T5n

CK#
CK
COMMAND READ NOP READ NOP NOP NOP

ADDRESS Bank, Bank,

Col n Col b
CL = 3

DQS

DO DO
DQ n b

DON’T CARE TRANSITIONING DATA

Notes: 1. DO n (or b) = data-out from column n (or column b).

2. BL = 4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first).
3. Three subsequent elements of data-out appear in the programmed order following DO n.
4. Three (or seven) subsequent elements of data-out appear in the programmed order fol-
lowing DO b.
5. Shown with nominal tAC, tDQSCK, and tDQSQ.
6. Example applies only when READ commands are issued to same device.

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 512Mb: x4, x8, x16 DDR SDRAM
Operations

Figure 15: Nonconsecutive READ Bursts

T0 T1 T2 T2n T3 T3n T4 T5 T5n T6

CK#
CK
COMMAND READ NOP NOP READ NOP NOP NOP

ADDRESS Bank, Bank,

Col n Col b
CL = 2

DQS

DO DO
DQ n b

T0 T1 T2 T2n T3 T3n T4 T5 T5n T6

CK#
CK
COMMAND READ NOP NOP READ NOP NOP NOP

ADDRESS Bank, Bank,

Col n Col b
CL = 2.5

DQS

DO DO
DQ n b

T0 T1 T2 T3 T3n T4 T4n T5 T6
CK#
CK
COMMAND READ NOP NOP READ NOP NOP NOP

ADDRESS Bank, Bank,

Col n Col b
CL = 3

DQS

DO DO
DQ n b

DON’T CARE TRANSITIONING DATA

Notes: 1. DO n (or b) = data-out from column n (or column b).

2. BL = 4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first).
3. Three subsequent elements of data-out appear in the programmed order following DO n.
4. Three (or seven) subsequent elements of data-out appear in the programmed order fol-
lowing DO b.
5. Shown with nominal tAC, tDQSCK, and tDQSQ.

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 512Mb: x4, x8, x16 DDR SDRAM
Operations

Figure 16: Random READ Accesses

T0 T1 T2 T2n T3 T3n T4 T4n T5 T5n

CK#
CK
COMMAND READ READ READ READ NOP NOP

ADDRESS Bank, Bank, Bank, Bank,

Col n Col x Col b Col g
CL = 2

DQS

DO DO DO DO DO DO DO
DQ n n' x x' b b' g

T0 T1 T2 T2n T3 T3n T4 T4n T5 T5n

CK#
CK
COMMAND READ READ READ READ NOP NOP

ADDRESS Bank, Bank, Bank, Bank,

Col n Col x Col b Col g
CL = 2.5

DQS

DO DO DO DO DO DO
DQ n n' x x' b b'

T0 T1 T2 T3 T3n T4 T4n T5 T5n

CK#
CK
COMMAND READ READ READ READ NOP NOP

ADDRESS Bank, Bank, Bank, Bank,

Col n Col x Col b Col g
CL = 3

DQS

DO DO DO DO DO DO
DQ n n' x x' b b'

DON’T CARE TRANSITIONING DATA

Notes: 1. DO n (or x or b or g) = data-out from column n (or column x or column b or column g).
2. BL = 2, 4, or 8 (if 4 or 8, the following burst interrupts the previous).
3. n' or x' or b' or g' indicates the next data-out following DO n or DO x or DO b or DO g,
respectively.
4. READs are to an active row in any bank.
5. Shown with nominal tAC, tDQSCK, and tDQSQ.

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 512Mb: x4, x8, x16 DDR SDRAM
Operations

Figure 17: Terminating a READ Burst

T0 T1 T2 T2n T3 T4 T5
CK#
CK
COMMAND READ BST5 NOP NOP NOP NOP

ADDRESS Bank a,
Col n
CL = 2

DQS

DO
DQ n

T0 T1 T2 T2n T3 T4 T5
CK#
CK
COMMAND READ BST5 NOP NOP NOP NOP

ADDRESS Bank a,
Col n
CL = 2.5

DQS

DQ DO
n

T0 T1 T2 T3 T3n T4 T5
CK#
CK
COMMAND READ BST5 NOP NOP NOP NOP

ADDRESS Bank a,
Col n
CL = 3

DQS

DQ DO
n

DON’T CARE TRANSITIONING DATA

Notes: 1. DO n = data-out from column n.

2. BL = 4.
3. Subsequent element of data-out appears in the programmed order following DO n.
4. Shown with nominal tAC, tDQSCK, and tDQSQ.
5. BST = BURST TERMINATE command, page remains open.

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 512Mb: x4, x8, x16 DDR SDRAM
Operations

Figure 18: READ-to-WRITE

T0 T1 T2 T2n T3 T4 T4n T5 T5n

CK#
CK
COMMAND READ BST7 NOP WRITE NOP NOP

ADDRESS Bank, Bank,

Col n Col b
tDQSS
CL = 2 (NOM)

DQS

DO DI
DQ n b

DM

T0 T1 T2 T2n T3 T3n T4 T5 T5n

CK#
CK
COMMAND READ BST7 NOP NOP WRITE NOP

ADDRESS Bank, Bank,

Col n Col b
tDQSS
CL = 2.5 (NOM)

DQS

DO DI
DQ n b

DM

T0 T1 T2 T3 T3n T4 T5 T5n
CK#
CK
COMMAND READ BST7 NOP NOP WRITE NOP

ADDRESS Bank a,
Col n
tDQSS
CL = 3 (NOM)

DQS

DO DI
DQ n b

DM

DON’T CARE TRANSITIONING DATA

Notes: 1. DO n = data-out from column n.

2. DI b = data-in from column b.
3. BL = 4 in the cases shown (applies for bursts of 8 as well; if BL = 2, the BST command shown
can be NOP).
4. One subsequent element of data-out appears in the programmed order following DO n.
5. Data-in elements are applied following DI b in the programmed order.
6. Shown with nominal tAC, tDQSCK, and tDQSQ.
7. BST = BURST TERMINATE command, page remains open.

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 512Mb: x4, x8, x16 DDR SDRAM
Operations

Figure 19: READ-to-PRECHARGE

T0 T1 T2 T2n T3 T3n T4 T5
CK#
CK

COMMAND6 READ NOP PRE NOP NOP ACT

ADDRESS Bank a, Bank a, Bank a,

Col n (a or all) Row
CL = 2 tRP
DQS

DQ DO
n

T0 T1 T2 T2n T3 T3n T4 T5
CK#
CK

COMMAND6 READ NOP PRE NOP NOP ACT

ADDRESS Bank a, Bank a, Bank a,

Col n (a or all) Row
tRP
CL = 2.5

DQS

DQ DO
n

T0 T1 T2 T3 T3n T4 T4n T5
CK#
CK

COMMAND6 READ NOP PRE NOP NOP ACT

ADDRESS Bank a, Bank a, Bank a,

Col n (a or all) Row
tRP
CL = 3

DQS

DQ DO
n

DON’T CARE TRANSITIONING DATA

Notes: 1. DO n = data-out from column n.

2. BL = 4, or an interrupted burst of 8.
3. Three subsequent elements of data-out appear in the programmed order following DO n.
4. Shown with nominal tAC, tDQSCK, and tDQSQ.
5. READ to PRECHARGE equals two clocks, which allows two data pairs of data-out.
6. A READ command with AUTO PRECHARGE enabled, provided tRAS(MIN) is met, would
cause a precharge to be performed at x number of clock cycles after the READ command,
where x = BL/2.
7. PRE = PRECHARGE command; ACT = ACTIVE command.

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 512Mb: x4, x8, x16 DDR SDRAM
Operations

WRITEs
WRITE bursts are initiated with a WRITE command, as shown in Figure 20 on page 36.
The starting column and bank addresses are provided with the WRITE command, and
auto precharge is either enabled or disabled for that access. If auto precharge is enabled,
the row being accessed is precharged at the completion of the burst and after the tWR
time.
Note: For the WRITE commands used in the following illustrations, auto precharge is dis-
abled.
During WRITE bursts, the first valid data-in element will be registered on the first rising
edge of DQS following the WRITE command, and subsequent data elements will be reg-
istered on successive edges of DQS. The LOW state on DQS between the WRITE com-
mand and the first rising edge is known as the write preamble; the LOW state on DQS
following the last data-in element is known as the write postamble.
The time between the WRITE command and the first corresponding rising edge of
DQS (tDQSS) is specified with a relatively wide range (from 75 percent to 125 per-
cent of one clock cycle). All of the WRITE diagrams show the nominal case, and
where the two extreme cases (i.e., tDQSS [MIN] and tDQSS [MAX]) might not be intui-
tive, they have also been included. Figure 21 on page 37 shows the nominal case and
the extremes of tDQSS for BL = 4. Upon completion of a burst, assuming no other
commands have been initiated, the DQ will remain High-Z and any additional input
data will be ignored.
Data for any WRITE burst may be concatenated with or truncated with a subsequent
WRITE command. In either case, a continuous flow of input data can be maintained.
The new WRITE command can be issued on any positive edge of clock following the pre-
vious WRITE command. The first data element from the new burst is applied after either
the last element of a completed burst or the last desired data element of a longer burst
which is being truncated. The new WRITE command should be issued x cycles after the
first WRITE command, where x equals the number of desired data element pairs (pairs
are required by the 2n-prefetch architecture).
Figure 22 on page 38 shows concatenated bursts of 4. An example of nonconsecutive
WRITEs is shown in Figure 23 on page 39. Full-speed random write accesses within a
page or pages can be performed as shown in Figure 24 on page 40.

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 512Mb: x4, x8, x16 DDR SDRAM
Operations

Figure 20: WRITE Command

CK#
CK

CKE HIGH

CS#

RAS#

CAS#

WE#

x4: A0–A9, A11, A12

x8: A0–A9, A11 CA
x16: A0–A9

x8: A12
x16: A11, A12

EN AP
A10
DIS AP

BA0,1 BA

DON’T CARE

Note: CA = Column address; BA = Bank address; EN AP = Enable auto precharge; and DIS AP =
Disable auto precharge.

Data for any WRITE burst may be followed by a subsequent READ command. To follow a
WRITE without truncating the WRITE burst, tWTR should be met, as shown in Figure 25
on page 41.
Data for any WRITE burst may be truncated by a subsequent READ command, as shown
in Figure 26 on page 42.
Note that only the data-in pairs that are registered prior to the tWTR period are written
to the internal array, and any subsequent data-in should be masked with DM, as shown
in Figure 27 on page 43.
Data for any WRITE burst may be followed by a subsequent PRECHARGE command. To
follow a WRITE without truncating the WRITE burst, tWR should be met, as shown in
Figure 28 on page 44.
Data for any WRITE burst may be truncated by a subsequent PRECHARGE command, as
shown in Figure 29 on page 45 and Figure 30 on page 46. Only the data-in pairs regis-
tered prior to the tWR period are written to the internal array; any subsequent data-in
should be masked with DM, as shown in Figures 29 and 30. After the PRECHARGE com-
mand, a subsequent command to the same bank cannot be issued until tRP is met.

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Operations

Figure 21: WRITE Burst

T0 T1 T2 T2n T3
CK#
CK

COMMAND WRITE NOP NOP NOP

ADDRESS Bank a,
Col b

tDQSS (NOM)
tDQSS
DQS

DI
DQ b

DM

tDQSS (MIN)
tDQSS
DQS

DI
DQ b

DM

tDQSS (MAX)
tDQSS
DQS

DI
DQ b

DM

DON’T CARE TRANSITIONING DATA

Notes: 1. DI b = data-in for column b.

2. Three subsequent elements of data-in are applied in the programmed order following
DI b.
3. An uninterrupted BL = 4 is shown.
4. A10 is LOW with the WRITE command (auto precharge is disabled).

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Operations

Figure 22: Consecutive WRITE-to-WRITE

T0 T1 T1n T2 T2n T3 T3n T4 T4n T5

CK#
CK

COMMAND WRITE NOP WRITE NOP NOP NOP

ADDRESS Bank, Bank,

Col b Col n

tDQSS (NOM) tDQSS

DQS

DI DI
DQ b n

DM

DON’T CARE TRANSITIONING DATA

Notes: 1. DI b, etc. = data-in for column b, etc.

2. Three subsequent elements of data-in are applied in the programmed order following
DI b.
3. Three subsequent elements of data-in are applied in the programmed order following
DI n.
4. An uninterrupted burst of 4 is shown.
5. Each WRITE command may be to any bank.

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Operations

Figure 23: Nonconsecutive WRITE-to-WRITE

T0 T1 T1n T2 T2n T3 T4 T4n T5 T5n

CK#
CK

COMMAND WRITE NOP NOP WRITE NOP NOP

ADDRESS Bank, Bank,

Col b Col n

tDQSS (NOM) tDQSS

DQS

DI DI
DQ b n

DM

DON’T CARE TRANSITIONING DATA

Notes: 1. DI b, etc. = data-in for column b, etc.

2. Three subsequent elements of data-in are applied in the programmed order following
DI b.
3. Three subsequent elements of data-in are applied in the programmed order following
DI n.
4. An uninterrupted burst of 4 is shown.
5. Each WRITE command may be to any bank.

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Operations

Figure 24: Random WRITE Cycles

T0 T1 T1n T2 T2n T3 T3n T4 T4n T5 T5n

CK#
CK

COMMAND WRITE WRITE WRITE WRITE WRITE NOP

ADDRESS Bank, Bank, Bank, Bank, Bank,

Col b Col x Col n Col a Col g

tDQSS (NOM)

DQS

DI DI DI DI DI DI DI DI DI DI
DQ b b' x x' n n' a a' g g'

DM

DON’T CARE TRANSITIONING DATA

Notes: 1. DI b, etc. = data-in for column b, etc.

2. Symbol b', etc. = the next data-in following DI b, etc., according to the programmed burst
order.
3. Programmed BL = 2, 4, or 8 in cases shown.
4. Each WRITE command may be to any bank.

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 512Mb: x4, x8, x16 DDR SDRAM
Operations

Figure 25: WRITE-to-READ – Uninterrupting

T0 T1 T1n T2 T2n T3 T4 T5 T6 T6n

CK#
CK
COMMAND WRITE NOP NOP NOP READ NOP NOP
tWTR

ADDRESS Bank a, Bank a,

Col b Col n

tDQSS (NOM) tDQSS CL = 2

DQS

DI DO
DQ b n

DM

tDQSS (MIN) tDQSS CL = 2

DQS

DI DO
DQ b n

DM

tDQSS (MAX) tDQSS CL = 2

DQS

DI DO
DQ b n

DM

DON’T CARE TRANSITIONING DATA

Notes: 1. DI b = data-in for column b, DO n = data-out for column n.

2. Three subsequent elements of data-in are applied in the programmed order following
DI b.
3. An uninterrupted burst of 4 is shown.
4. tWTR is referenced from the first positive CK edge after the last data-in pair.
5. The READ and WRITE commands are to same device. However, the READ and WRITE com-
mands may be to different devices, in which case tWTR is not required and the READ com-
mand could be applied earlier.
6. A10 is LOW with the WRITE command (auto precharge is disabled).

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 512Mb: x4, x8, x16 DDR SDRAM
Operations

Figure 26: WRITE-to-READ – Interrupting

T0 T1 T1n T2 T2n T3 T3n T4 T5 T5n T6 T6n

CK#
CK
COMMAND WRITE NOP NOP READ NOP NOP NOP
tWTR

ADDRESS Bank a, Bank a,

Col b Col n

tDQSS (NOM) tDQSS CL = 2

DQS

DI DO
DQ b n

DM

tDQSS (MIN) tDQSS CL = 2

DQS

DI DO
DQ b n

DM

tDQSS (MAX) tDQSS CL = 2

DQS

DI DO
DQ b n

DM

DON’T CARE TRANSITIONING DATA

Notes: 1. DI b = data-in for column b, DO n = data-out for column n.

2. An interrupted burst of 4 is shown; two data elements are written.
3. One subsequent element of data-in is applied in the programmed order following DI b.
tWTR is referenced from the first positive CK edge after the last data-in pair.
4.
5. A10 is LOW with the WRITE command (auto precharge is disabled).
6. DQS is required at T2 and T2n (nominal case) to register DM.
7. If the burst of 8 was used, DM and DQS would be required at T3 and T3n because the
READ command would not mask these two data elements.

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Operations

Figure 27: WRITE-to-READ – Odd Number of Data, Interrupting

T0 T1 T1n T2 T2n T3 T3n T4 T5 T5n T6 T6n

CK#
CK
COMMAND WRITE NOP NOP READ NOP NOP NOP
tWTR

ADDRESS Bank a, Bank a,

Col b Col n

tDQSS (NOM) tDQSS CL = 2

DQS

DI DO
DQ b n

DM

tDQSS (MIN) tDQSS CL = 2

DQS

DI DO
DQ b n

DM

tDQSS (MAX) tDQSS CL = 2

DQS

DI DO
DQ b n

DM

DON’T CARE TRANSITIONING DATA

Notes: 1. DI b = data-in for column b, DO n = data-out for column n.

2. An interrupted burst of 4 is shown; one data element is written.
t
3. WTR is referenced from the first positive CK edge after the last desired data-in pair (not
the last two data elements).
4. A10 is LOW with the WRITE command (auto precharge is disabled).
5. DQS is required at T1n, T2, and T2n (nominal case) to register DM.
6. If the burst of 8 was used, DM and DQS would be required at T3–T3n because the READ
command would not mask these data elements.

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Operations

Figure 28: WRITE-to-PRECHARGE – Uninterrupting

T0 T1 T1n T2 T2n T3 T4 T5 T6
CK#
CK
COMMAND WRITE NOP NOP NOP NOP PRE7 NOP
tWR tRP

ADDRESS Bank a, Bank,

Col b (a or all)

tDQSS (NOM) tDQSS

DQS

DI
DQ b

DM

tDQSS (MIN) tDQSS

DQS

DI
DQ b

DM

tDQSS (MAX) tDQSS

DQS

DI
DQ b

DM

DON’T CARE TRANSITIONING DATA

Notes: 1. DI b = data-in for column b.

2. Three subsequent elements of data-in are applied in the programmed order following DI
b.
3. An uninterrupted burst of 4 is shown.
4. tWR is referenced from the first positive CK edge after the last data-in pair.
5. The PRECHARGE and WRITE commands are to the same device. However, the PRECHARGE
and WRITE commands may be to different devices, in which case tWR is not required and
the PRECHARGE command could be applied earlier.
6. A10 is LOW with the WRITE command (auto precharge is disabled).
7. PRE = PRECHARGE command.

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Operations

Figure 29: WRITE-to-PRECHARGE – Interrupting

T0 T1 T1n T2 T2n T3 T3n T4 T4n T5 T6

CK#
CK
COMMAND WRITE NOP NOP NOP PRE8 NOP NOP
tWR tRP

ADDRESS Bank a, Bank,

Col b (a or all)

tDQSS (NOM) tDQSS

DQS

DI
DQ b

DM

tDQSS (MIN) tDQSS

DQS

DI
DQ b

DM

tDQSS (MAX) tDQSS

DQS

DI
DQ b

DM

DON’T CARE TRANSITIONING DATA

Notes: 1. DI b = data-in for column b.

2. Subsequent element of data-in is applied in the programmed order following DI b.
3. An interrupted burst of 8 is shown; two data elements are written.
tWR is referenced from the first positive CK edge after the last data-in pair.
4.
5. A10 is LOW with the WRITE command (auto precharge is disabled).
6. DQS is required at T4 and T4n (nominal case) to register DM.
7. If the burst of 4 was used, DQS and DM would not be required at T3, T3n, T4, and T4n.
8. PRE = PRECHARGE command.

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Operations

Figure 30: WRITE-to-Precharge – Odd Number of Data, Interrupting

T0 T1 T1n T2 T2n T3 T3n T4 T4n T5 T6

CK#
CK
COMMAND WRITE NOP NOP NOP PRE7 NOP NOP
tWR tRP

ADDRESS Bank a, Bank,

Col b (a or all)

tDQSS (NOM) tDQSS

DQS

DI
DQ b

DM

tDQSS (MIN) tDQSS

DQS

DI
DQ b

DM

tDQSS (MAX) tDQSS

DQS

DI
DQ b

DM

DON’T CARE TRANSITIONING DATA

Notes: 1. DI b = data-in for column b.

2. An interrupted burst of 8 is shown; one data element is written.
tWR is referenced from the first positive CK edge after the last data-in pair.
3.
4. A10 is LOW with the WRITE command (auto precharge is disabled).
5. DQS is required at T4 and T4n (nominal case) to register DM.
6. If the burst of 4 was used, DQS and DM would not be required at T3, T3n, T4, and T4n.
7. PRE = PRECHARGE command.

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 512Mb: x4, x8, x16 DDR SDRAM
Operations

PRECHARGE
The PRECHARGE command (Figure 31) is used to deactivate the open row in a particu-
lar bank or the open row in all banks. The bank(s) will be available for a subsequent row
access some specified time (tRP) after the PRECHARGE command is issued. Input A10
determines whether one or all banks are to be precharged, and in the case where only
one bank is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be
precharged, inputs BA0, BA1 are treated as “Don’t Care.” Once a bank has been pre-
charged, it is in the idle state and must be activated prior to any READ or WRITE com-
mands being issued to that bank.

Figure 31: PRECHARGE Command

CK#
CK

CKE HIGH

CS#

RAS#

CAS#

WE#

A0–A9, A11, A12

ALL BANKS
A10
ONE BANK

BA0,1 BA

DON’T CARE

Note: BA = Bank Address (if A10 is LOW; otherwise “Don’t Care”).

Power-Down (CKE Not Active)

Unlike SDR SDRAMs, DDR SDRAMs require CKE to be active at all times an access is in
progress, from the issuing of a READ or WRITE command until completion of the access.
Thus a clock suspend is not supported. For READs, an access completion is defined
when the read postamble is satisfied; for WRITEs, an access completion is defined when
the write recovery time (tWR) is satisfied.
Power-down, as shown in Figure 32 on page 48, is entered when CKE is registered LOW
and all Table 10 (page 49) criteria are met. If power-down occurs when all banks are idle,
this mode is referred to as precharge power-down; if power-down occurs when there is a
row active in any bank, this mode is referred to as active power-down. Entering power-
down deactivates the input and output buffers, excluding CK, CK#, and CKE. For maxi-
mum power savings, the DLL is frozen during precharge power-down mode. Exiting

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Operations

power-down requires the device to be at the same voltage and frequency as when it
entered power-down. However, power-down duration is limited by the refresh require-
ments of the device (tREFC).
While in power-down, CKE LOW and a stable clock signal must be maintained at the
inputs of the DDR SDRAM, while all other input signals are “Don’t Care.” The power-
down state is synchronously exited when CKE is registered HIGH (in conjunction with a
NOP or DESELECT command). A valid executable command may be applied one clock
cycle later.

Figure 32: Power-Down

T0 T1 T2 ( ( Ta0 Ta1 Ta2 Ta3

CK# ))
((
CK ))
tIS tIS

CKE ((
))

((
))
COMMAND VALID NOP NOP VALID VALID
((
))

No READ/WRITE
Enter power-down mode Exit power-down mode
access in progress

DON’T CARE

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 512Mb: x4, x8, x16 DDR SDRAM
Operations

Table 10: Truth Table – CKE

CKEn-1 CKEn Current State Commandn Actionn Notes

L L Power-Down X Maintain power-down
Self refresh X Maintain self refresh
L H Power-Down DESELECT or NOP Exit power-down
Self refresh DESELECT or NOP Exit self refresh 7
H L All banks idle DESELECT or NOP Precharge power-down entry
Bank(s) active DESELECT or NOP Active power-down entry
All banks idle AUTO REFRESH Self refresh entry
H H See Table 11 on page 50
Notes: 1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous
clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COM-
MANDn.
4. All states and sequences not shown are illegal or reserved.
5. CKE must not drop LOW during a column access. For a READ, this means CKE must stay
HIGH until after the read postamble time; for a WRITE, CKE must stay HIGH until the
WRITE recovery time (tWR) has been met.
6. Once initialized, including during self refresh mode, VREF must be powered within the
specified range.
7. Upon exit of the self refresh mode the DLL is automatically enabled. A minimum of 200
clock cycles is needed before applying a READ command for the DLL to lock. DESELECT or
NOP commands should be issued on any clock edges occurring during the tXSNR period.

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 512Mb: x4, x8, x16 DDR SDRAM
Operations

Table 11: Truth Table – Current State Bank n – Command to Bank n

Notes: 1–6; notes appear below and on next page.

Current
State CS# RAS# CAS# WE# Command/Action Notes
Any H X X X DESELECT (NOP/continue previous operation)
L H H H NO OPERATION (NOP/continue previous operation)
Idle L L H H ACTIVE (select and activate row)
L L L H AUTO REFRESH 7
L L L L LOAD MODE REGISTER 7
Row L H L H READ (select column and start READ burst) 10
active L H L L WRITE (select column and start WRITE burst) 10
L L H L PRECHARGE (deactivate row in bank or banks) 8
Read L H L H READ (select column and start new READ burst) 10
(Auto- L H L L WRITE (select column and start WRITE burst) 10, 12
precharge L L H L PRECHARGE (truncate READ burst, start PRECHARGE) 8
disabled)
L H H L BURST TERMINATE 9
Write L H L H READ (select column and start READ burst) 10, 11
(Auto- L H L L WRITE (select column and start new WRITE burst) 10
precharge L L H L PRECHARGE (truncate WRITE burst, start PRECHARGE) 8, 11
disabled)
Notes: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Table 10 on page 49) and
after tXSNR has been met (if the previous state was self refresh).
2. This table is bank-specific, except where noted (i.e., the current state is for a specific bank
and the commands shown are those allowed to be issued to that bank when in that state).
Exceptions are covered in the notes below.
3. Current state definitions:
• Idle: The bank has been precharged, and tRP has been met.
• Row active: A row in the bank has been activated, and tRCD has been met. No data
bursts/accesses and no register accesses are in progress.
• Read: A READ burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
• Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
4. The following states must not be interrupted by a command issued to the same bank.
COMMAND INHIBIT or NOP commands, or allowable commands to the other bank should
be issued on any clock edge occurring during these states. Allowable commands to the
other bank are determined by its current state and Table 11 and according to Table 12 on
page 52.
• Precharging: Starts with registration of a PRECHARGE command and ends when tRP is
met. Once tRP is met, the bank will be in the idle state.
• Row activating: Starts with registration of an ACTIVE command and ends when tRCD is
met. Once tRCD is met, the bank will be in the “row active” state.
• Read w/auto-precharge Enabled: Starts with registration of a READ command with auto
precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be
in the idle state.
• Write w/auto-precharge Enabled: Starts with registration of a WRITE command with
auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank
will be in the idle state.
5. The following states must not be interrupted by any executable command; COMMAND
INHIBIT or NOP commands must be applied on each positive clock edge during these
states.

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Operations

• Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRFC
is met. Once tRFC is met, the DDR SDRAM will be in the all banks idle state.
• Accessing mode register: Starts with registration of a LOAD MODE REGISTER command
and ends when tMRD has been met. Once tMRD is met, the DDR SDRAM will be in the
all banks idle state.
• Precharging all: Starts with registration of a PRECHARGE ALL command and ends when
t
RP is met. Once tRP is met, all banks will be in the idle state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle, and bursts are not in progress.
8. May or may not be bank-specific; if multiple banks are to be precharged, each must be in a
valid state for precharging.
9. Not bank-specific; BURST TERMINATE affects the most recent READ burst, regardless of
bank.
10. READs or WRITEs listed in the Command/Action column include READs or WRITEs with
auto precharge enabled and READs or WRITEs with auto precharge disabled.
11. Requires appropriate DM masking.
12. A WRITE command may be applied after the completion of the READ burst; otherwise, a
BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE com-
mand.

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 512Mb: x4, x8, x16 DDR SDRAM
Operations

Table 12: Truth Table – Current State Bank n – Command to Bank m

Notes: 1–6; notes appear below and on next page.

Current State CS# RAS# CAS# WE# Command/Action Notes

Any H X X X DESELECT (NOP/continue previous operation)
L H H H NO OPERATION (NOP/continue previous operation)
Idle X X X X Any Command Otherwise Allowed to Bank m
Row L L H H ACTIVE (select and activate row)
activating, L H L H READ (select column and start READ burst) 7
active, or L H L L WRITE (select column and start WRITE burst) 7
precharging
L L H L PRECHARGE
Read L L H H ACTIVE (select and activate row)
(Auto- L H L H READ (select column and start new READ burst) 7
Precharge L H L L WRITE (select column and start WRITE burst) 7, 9
Disabled)
L L H L PRECHARGE
Write L L H H ACTIVE (select and activate row)
(auto- L H L H READ (select column and start READ burst) 7, 8
precharge L H L L WRITE (select column and start new WRITE burst) 7
disabled)
L L H L PRECHARGE
Read L L H H ACTIVE (select and activate row)
(with auto- L H L H READ (select column and start new READ burst) 7, 3
precharge) L H L L WRITE (select column and start WRITE burst) 7, 9, 3
L L H L PRECHARGE
Write L L H H ACTIVE (select and activate row)
(with auto- L H L H READ (select column and start READ burst) 7, 3
precharge) L H L L WRITE (select column and start new WRITE burst) 7, 3
L L H L PRECHARGE
Notes: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after
tXSNR has been met (if the previous state was self refresh).

2. This table describes alternate bank operation, except where noted (i.e., the current state is
for bank n and the commands shown are those allowed to be issued to bank m, assuming
that bank m is in such a state that the given command is allowable). Exceptions are cov-
ered in the notes below.
3. Current state definitions:
• Idle: The bank has been precharged, and tRP has been met.
• Row active: A row in the bank has been activated, and tRCD has been met. No data
bursts/accesses and no register accesses are in progress.
• Read: A READ burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
• Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated
• Read with auto precharge enabled: See following text – 3a
• Write with auto precharge enabled: See following text – 3a
a. The read with auto precharge enabled or write with auto precharge enabled states
can each be broken into two parts: the access period and the precharge period. For
read with auto precharge, the precharge period is defined as if the same burst was
executed with auto precharge disabled and then followed with the earliest possible
PRECHARGE command that still accesses all of the data in the burst. For write with
auto precharge, the precharge period begins when tWR ends, with tWR measured as
if auto precharge was disabled. The access period starts with registration of the com-
mand and ends where the precharge period (or tRP) begins.

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 512Mb: x4, x8, x16 DDR SDRAM
Operations

This device supports concurrent auto precharge such that when a read with auto
precharge is enabled or a write with auto precharge is enabled any command to
other banks is allowed, as long as that command does not interrupt the read or write
data transfer already in process. In either case, all other related limitations apply
(e.g., contention between read data and write data must be avoided).
b. The minimum delay from a read or write command with auto precharge enabled, to
a command to a different bank is summarized below:.

Table 13: Command Delays

CLRU = CAS latency (CL) rounded up to the next integer; BL = Burst length

Minimum Delay
From Command To Command (with Concurrent Auto Precharge)
WRITE w/AP READ or READ w/AP [1 + (BL/2)] × tCK + tWTR
WRITE or WRITE w/AP (BL/2) × tCK
PRECHARGE 1 tCK
ACTIVE 1 tCK
READ w/AP READ or READ w/AP (BL/2) × tCK
WRITE or WRITE w/AP [CLRU + (BL/2)] × tCK
PRECHARGE 1 tCK
ACTIVE 1 tCK

4. AUTO REFRESH and LOAD MODE REGISTER commands may only be issued when all banks
are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank
represented by the current state only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with
auto precharge enabled and READs or WRITEs with auto precharge disabled.
8. Requires appropriate DM masking.
9. A WRITE command may be applied after the completion of the READ burst; otherwise, a
BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE com-
mand.

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 512Mb: x4, x8, x16 DDR SDRAM
Electrical Specifications

Electrical Specifications
Absolute Maximum Ratings
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reli-
ability.

Table 14: Absolute Maximum Ratings

Parameter Absolute Maximum Value

VDD supply voltage relative to VSS –1V to +3.6V
VDDQ supply voltage relative to VSS –1V to +3.6V
VREF and inputs voltage relative to VSS –1V to +3.6V
I/O pins voltage relative to VSS –0.5V to VDDQ +0.5V
Operating temperature, TA (ambient, Commercial) 0°C to +70°C
Operating temperature, TA (ambient, Industrial) –40°C to +85°C
Storage temperature (plastic) –55°C to +150°C

Table 15: DC Electrical Characteristics and Operating Conditions (-6, -6T, -75E, -75Z, -75)
Notes: 1–5, 16, notes appear on pages 71–77; 0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V

Parameter/Condition Symbol Min Max Units Notes

Supply voltage VDD 2.3 2.7 V 36, 41
I/O supply voltage VDDQ 2.3 2.7 V 36, 41 44
I/O reference voltage VREF 0.49 x VDDQ 0.51 x VDDQ V 6, 44
I/O termination voltage (system) VTT VREF - 0.04 VREF + 0.04 V 7, 44
Input high (logic 1) voltage VIH(DC) VREF + 0.15 VDD + 0.3 V 28
Input low (logic 0) voltage VIL(DC) –0.3 VREF - 0.15 V 28
Input Leakage Current II –2 2 µA
Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 1.35V
(All other pins not under test = 0V)
Output Leakage Current IOZ –5 5 µA
(DQs are disabled; 0V ≤ VOUT ≤ VDDQ)
Output Levels: Full drive option - x4, x8, x16 IOH –16.8 – mA 37, 39
High current (VOUT = VDDQ - 0.373V, minimum VREF,
minimum VTT)
Low Current (VOUT = 0.373V, maximum VREF, IOL 16.8 – mA
maximum VTT)
Output Levels: Reduced drive option - x16 only IOHR –9 – mA 38, 39
High current (VOUT = VDDQ - 0.763V, minimum VREF,
minimum VTT)
Low current (VOUT = 0.763V, maximum VREF, IOLR 9 – mA
maximum VTT)

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 512Mb: x4, x8, x16 DDR SDRAM
Electrical Specifications

Table 16: DC Electrical Characteristics and Operating Conditions (-5B DDR400)

Notes: 1–5, and 16; notes appear on pages 71–77; 0°C ≤ TA ≤ +70°C; VDDQ = +2.6V ±0.1V, VDD = +2.6V ±0.1V

Parameter/Condition Symbol Min Max Units Notes

Supply voltage VDD 2.5 2.7 V 36, 41
I/O supply voltage VDDQ 2.5 2.7 V 36, 41, 44
I/O reference voltage VREF 0.49 × VDDQ 0.51 × VDDQ V 6, 44
I/O termination voltage (system) VTT VREF - 0.04 VREF + 0.04 V 7, 44
Input high (logic 1) voltage VIH(DC) VREF + 0.15 VDD + 0.3 V 28
Input low (logic 0) voltage VIL(DC) –0.3 VREF - 0.15 V 28
Input Leakage Current II –2 2 µA
Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 1.35V
(All other pins not under test = 0V)
Output Leakage Current IOZ –5 5 µA
(DQs are disabled; 0V ≤ VOUT ≤ VDDQ)
Output Levels: Full drive option - x4, x8, x16 IOH –16.8 – mA 37, 39
High current (VOUT = VDDQ - 0.373V, minimum VREF,
minimum VTT)
Low current (VOUT = 0.373V, maximum VREF, IOL 16.8 – mA
maximum VTT)
Output Levels: Full drive option - x4, x8, x16 IOHR –9 – mA 38, 39
High current (VOUT = VDDQ - 0.373V, minimum VREF,
minimum VTT)
Low current (VOUT = 0.763V, maximum VREF, IOLR 9 – mA
maximum VTT)

Table 17: AC Input Operating Conditions

0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V (VDDQ = +2.6V ±0.1V, VDD = +2.6V ±0.1V for DDR400)
Notes: 1–5, 14, 16; notes appear on pages 71–77.

Parameter/Condition Symbol Min Max Units Notes

Input high (logic 1) voltage VIH(AC) VREF + 0.310 – V 14, 28, 40
Input low (logic 0) voltage VIL(AC) – VREF - 0.310 V 14, 28, 40
I/O reference voltage VREF(AC) 0.49 × VDDQ 0.51 × VDDQ V 6

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 512Mb: x4, x8, x16 DDR SDRAM
Electrical Specifications

Figure 33: Input Voltage Waveform

VDDQ (2.3V minimum)

1
VOH(MIN) (1.670V for SSTL2 termination)
System Noise Margin (Power/Ground,
Crosstalk, Signal Integrity Attenuation)

1.560V VIH (AC)

1.400V VIH(DC)

1.300V
VREF + AC Noise
1.275V
VREF + DC Error
1.250V
VREF - DC Error
1.225V
VREF - AC Noise
1.200V

1.100V VIL(DC)

0.940V VIL(AC)
VINAC - Provides margin
between VOL (MAX) and VILAC Receiver

VOL (MAX) (0.83V2 for

SSTL2 termination)

VSSQ
Transmitter

Notes: 1. VOH (MIN) with test load is 1.927V.

2. VOL (MAX) with test load is 0.373V.
3. For Non-DDR400 devices, numbers in diagram reflect nominal values utilizing circuit
below.

VTT
25Ω

25Ω Reference
Point

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Electrical Specifications

Table 18: Clock Input Operating Conditions

0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V (VDDQ = +2.6V ±0.1V, VDD = +2.6V ±0.1V for DDR400)
Notes: 1–5, 15, 16, 30; notes appear on pages 71–77.

Parameter/Condition Symbol Min Max Units Notes

Clock input mid-point voltage; CK and CK# VMP(DC) 1.15 1.35 V 6, 9
Clock input voltage level; CK and CK# VIN(DC) –0.3 VDDQ + 0.3 V 6
Clock input differential voltage; CK and CK# VID(DC) 0.36 VDDQ + 0.6 V 6, 8
Clock input differential voltage; CK and CK# VID(AC) 0.7 VDDQ + 0.6 V 8
Clock input crossing point voltage; CK and CK# VIX(AC) 0.5 × VDDQ - 0.2 0.5 × VDDQ + 0.2 V 9

Figure 34: SSTL_2 Clock Input

2.80V Maximum clock level5

CK#

1.45V X
1 2 3
1.25V VMP(DC) VIX(AC) VID(DC)
4
VID(AC)
1.05V X

CK

5
- 0.30V Minimum clock level

Notes: 1. This provides a minimum of 1.15V to a maximum of 1.35V, and is always half of VDDQ.
2. CK and CK# must cross in this region.
3. CK and CK# must meet at least VID(DC) MIN when static and is centered around VMP(DC).
4. CK and CK# must have a minimum 700mv peak to peak swing.
5. CK or CK# may not be more positive than VDDQ + 0.3V or more negative than VSS - 0.3V.
6. For AC operation, all DC clock requirements must also be satisfied.
7. Numbers in diagram reflect nominal values non-DDR400 devices.

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Electrical Specifications

Table 19: Capacitance (x4, x8 TSOP)

Note: 13; notes appear on pages 71–77.

Parameter Symbol Min Max Units Notes

Delta input/output capacitance: DQ0–DQ3 (x4), DQ0–DQ7 (x8) DCIO – 0.50 pF 24
Delta input capacitance: Command and address DCI1 – 0.50 pF 29
Delta input capacitance: CK, CK# DCI2 – 0.25 pF 29
Input/Output capacitance: DQs, DQS, DM CIO 4.0 5.0 pF
Input capacitance: Command and address CI1 2.0 3.0 pF
Input capacitance: CK, CK# CI2 2.0 3.0 pF
Input capacitance: CKE CI3 2.0 3.0 pF

Table 20: Capacitance (x4, x8 FBGA)

Note: 13; notes appear on pages 71–77.

Parameter Symbol Min Max Units Notes

Delta input/output capacitance: DQs, DQS, DM DCIO – 0.50 pF 24
Delta input capacitance: Command and address DCI1 – 0.50 pF 29
Delta Input capacitance: CK, CK# DCI2 – 0.25 pF 29
Input/Output capacitance: DQs, DQS, DM CIO 3.5 4.5 pF
Input capacitance: Command and address CI1 1.5 2.5 pF
Input capacitance: CK, CK# CI2 1.5 2.5 pF
Input capacitance: CKE CI3 1.5 2.5 pF

Table 21: Capacitance (x16 TSOP)

Note: 13; notes appear on pages 71–77.

Parameter Symbol Min Max Units Notes

Delta input/output capacitance: DQ0–DQ7, LDQS, LDM DCIOL – 0.50 pF 24
Delta input/output capacitance: DQ8–DQ15, UDQS, UDM DCIOU – 0.50 pF 24
Delta input capacitance: Command and address DCI1 – 0.50 pF 29
Delta input capacitance: CK, CK# DCI2 – 0.25 pF 29
Input/Output capacitance: DQ, LDQS, UDQS, LDM, UDM CIO 4.0 5.0 pF
Input capacitance: Command and address CI1 2.0 3.0 pF
Input capacitance: CK, CK# CI2 2.0 3.0 pF
Input capacitance: CKE CI3 2.0 3.0 pF

Table 22: Capacitance (x16 FBGA)

Note: 13; notes appear on pages 71–77.

Parameter Symbol Min Max Units Notes

Delta input/output capacitance: DQ0–DQ7, LDQS, LDM DCIOL – 0.50 pF 24
Delta input/output capacitance: DQ8–DQ15, UDQS, UDM DCIOU – 0.50 pF 24
Delta input capacitance: Command and address DCI1 – 0.50 pF 29
Delta input capacitance: CK, CK# DCI2 – 0.25 pF 29
Input/Output capacitance: DQ, LDQS, UDQS, LDM, UDM CIO 3.5 4.5 pF
Input capacitance: Command and address CI1 1.5 2.5 pF
Input capacitance: CK, CK# CI2 1.5 2.5 pF
Input capacitance: CKE CI3 1.5 2.5 pF

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Electrical Specifications

Table 23: IDD Specifications and Conditions (x4, x8; -5B)

0°C ≤ TA ≤ +70°C; VDDQ = +2.6V ±0.1V, VDD = +2.6V ±0.1V
Notes: 1–5, 10, 12, 14, 46; notes appear on pages 71–77; see also Table 27 on page 63.

Max
Parameter/Condition Symbol -5B Units Notes
Operating Current: One bank; Active precharge; IDD0 155 mA 22, 47
tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing
once per clock cycle; Address and control inputs changing once every
two clock cycles
Operating Current: One bank; Active-read precharge; IDD1 185 mA 22, 47
Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and
control inputs changing once per clock cycle
Precharge Power-down Standby Current: All banks idle; Power- IDD2P 5 mA 23, 32, 49
down mode; tCK = tCK (MIN); CKE = (LOW)
Idle Standby Current: CS# = HIGH; All banks are idle; IDD2F 55 mA 50
t
CK = tCK (MIN); CKE = HIGH; Address and other control inputs
changing once per clock cycle; VIN = VREF for DQ, DQS, and DM
Active Power-down Standby Current: One bank active; IDD3P 45 mA 23, 32, 49
Power-down mode; tCK = tCK (MIN); CKE = LOW
Active Standby Current: CS# = HIGH; CKE = HIGH; IDD3N 60 mA 22
One bank active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS
inputs changing twice per clock cycle; Address and other control inputs
changing once per clock cycle
Operating Current: Burst = 2; Reads; Continuous burst; IDD4R 190 mA 22, 47
One bank active; Address and control inputs changing once per clock
cycle; tCK = tCK (MIN); IOUT = 0mA
Operating Current: Burst = 2; Writes; Continuous burst; IDD4W 195 mA 22
One bank active; Address and control inputs changing once per clock
cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per
clock cycle
Auto Refresh Burst Current: tREFC = tRFC (MIN) IDD5 345 mA 49
tREFC = 7.8µs IDD5A 11 mA 27, 49
Self Refresh Current: CKE ≤ 0.2V Standard IDD6 5 mA 11
Low Power (L) IDD6A 3 mA 11
Operating Current: Four bank interleaving READs IDD7 450 mA 22, 48
(Burst = 4) with auto precharge, tRC = minimum tRC allowed;
t
CK = tCK (MIN); Address and control inputs change only during active
READ or WRITE commands

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Electrical Specifications

Table 24: IDD Specifications and Conditions (x4, x8; -6/-6T/-75E/-75Z/-75)

0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V
Notes: 1–5, 10, 12, 14, 46; notes appear on pages 71–77; see also Table 27 on page 63.

Max
Parameter/Condition Symbol -6/6T -75E -75Z/-75 Units Notes
Operating Current: One bank; Active precharge; IDD0 130 130 115 mA 22, 47
tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs
changing once per clock cycle; Address and control inputs
changing once every two clock cycles
Operating Current: One bank; Active-read precharge; IDD1 160 160 145 mA 22, 47
Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA;
Address and control inputs changing once per clock cycle
Precharge Power-down Standby Current: All banks idle; IDD2P 5 5 5 mA 23, 32, 49
Power-down mode; tCK = tCK (MIN); CKE = (LOW)
Idle Standby Current: CS# = HIGH; All banks are idle; IDD2F 45 45 40 mA 50
t
CK = tCK (MIN); CKE = HIGH; Address and other control inputs
changing once per clock cycle; VIN = VREF for DQ, DQS, and DM
Active Power-down Standby Current: One bank active; IDD3P 35 35 30 mA 23, 32, 49
Power-down mode; tCK = tCK (MIN); CKE = LOW
Active Standby Current: CS# = HIGH; CKE = HIGH; IDD3N 50 50 45 mA 22
One bank active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM,
and DQS inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle
Operating Current: Burst = 2; Reads; Continuous burst; IDD4R 165 165 145 mA 22, 47
One bank active; Address and control inputs changing once per
clock cycle; tCK = tCK (MIN); IOUT = 0mA
Operating Current: Burst = 2; Writes; Continuous burst; IDD4W 175 155 135 mA 22
One bank active; Address and control inputs changing once per
clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing
twice per clock cycle
Auto Refresh Burst Current: tREFC = tRFC (MIN) IDD5 290 290 280 mA 49
tREFC = 7.8µs IDD5A 10 10 10 mA 27, 49
Self Refresh Current: CKE ≤ 0.2V Standard IDD6 5 5 5 mA 11
Low Power (L) IDD6A 3 3 3 mA 11
Operating Current: Four bank interleaving READs IDD7 405 400 350 mA 22, 48
(Burst = 4) with auto precharge, tRC = minimum tRC allowed;
t
CK = tCK (MIN); Address and control inputs change only during
active READ or WRITE commands

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Electrical Specifications

Table 25: IDD Specifications and Conditions (x16; -5B)

0°C ≤ TA ≤ +70°C; VDDQ = +2.6V ±0.1V, VDD = +2.6V ±0.1V
Notes: 1–5, 10, 12, 14, 46; notes appear on pages 71–77; see also Table 27 on page 63.

Max
Parameter/Condition Symbol -5B Units Notes
Operating Current: One bank; Active precharge; IDD0 155 mA 22, 47
tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing once
per clock cycle; Address and control inputs changing once every two clock
cycles
Operating Current: One bank; Active-read precharge; IDD1 195 mA 22, 47
Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and
control inputs changing once per clock cycle
Precharge Power-down Standby Current: All banks idle; Power- IDD2P 5 mA 23, 32,
down mode; tCK = tCK (MIN); CKE = (LOW) 49
Idle Standby Current: CS# = HIGH; All banks are idle; IDD2F 55 mA 50
t
CK = tCK (MIN); CKE = HIGH; Address and other control inputs changing
once per clock cycle; VIN = VREF for DQ, DQS, and DM
Active Power-down Standby Current: One bank active; IDD3P 45 mA 23, 32,
Power-down mode; tCK = tCK (MIN); CKE = LOW 49
Active Standby Current: CS# = HIGH; CKE = HIGH; IDD3N 60 mA 22
One bank active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs
changing twice per clock cycle; Address and other control inputs changing
once per clock cycle
Operating Current: Burst = 2; Reads; Continuous burst; IDD4R 210 mA 22, 47
One bank active; Address and control inputs changing once per clock cycle;
tCK = tCK (MIN); IOUT = 0mA

Operating Current: Burst = 2; Writes; Continuous burst; IDD4W 215 mA 22

One bank active; Address and control inputs changing once per clock cycle;
tCK
= tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle
tREFC = tRFC(MIN) IDD5 345 mA 49
Auto Refresh Burst Current:
tREFC = 7.8µs IDD5A 11 mA 27, 49
Self Refresh Current: CKE ≤ 0.2V Standard IDD6 6 mA 11
Low Power (L) IDD6A 4 mA 11
Operating Current: Four bank interleaving READs IDD7 480 mA 22, 48
(Burst = 4) with auto precharge, tRC = minimum tRC allowed;
tCK = tCK (MIN); Address and control inputs change only during active READ

or WRITE commands

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Electrical Specifications

Table 26: IDD Specifications and Conditions (x16; -6/-6T/-75E/-75Z/-75)

0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V
Notes: 1–5, 10, 12, 14, 46; notes appear on pages 71–77; see also Table 27 on page 63.

Max
Parameter/Condition Symbol -6/6T -75E -75Z/-75 Units Notes
Operating Current: One bank; Active precharge; IDD0 130 130 115 mA 22, 47
tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs
changing once per clock cycle; Address and control inputs
changing once every two clock cycles
Operating Current: One bank; Active-read precharge; IDD1 160 160 145 mA 22, 47
Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA;
Address and control inputs changing once per clock cycle
Precharge Power-down Standby Current: All banks IDD2P 5 5 5 mA 23, 32, 49
idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW)
Idle Standby Current: CS# = HIGH; All banks are idle; IDD2F 45 45 40 mA 50
t
CK = tCK (MIN); CKE = HIGH; Address and other control
inputs changing once per clock cycle; VIN = VREF for DQ, DQS,
and DM
Active Power-down Standby Current: One bank active; IDD3P 35 35 30 mA 23, 32, 49
Power-down mode; tCK = tCK (MIN); CKE = LOW
Active Standby Current: CS# = HIGH; CKE = HIGH; IDD3N 50 50 45 mA 22
One bank active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM,
and DQS inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle
Operating Current: Burst = 2; Reads; Continuous burst; IDD4R 165 165 145 mA 22, 47
One bank active; Address and control inputs changing once
per clock cycle; tCK = tCK (MIN); IOUT = 0mA
Operating Current: Burst = 2; Writes; Continuous burst; IDD4W 195 160 135 mA 22
One bank active; Address and control inputs changing once
per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs
changing twice per clock cycle
Auto Refresh Burst Current: tREFC = tRFC (MIN) IDD5 290 290 280 mA 49
tREFC = 7.8µs IDD5A 10 10 10 mA 27, 49
Self Refresh Current: CKE ≤ 0.2V Standard IDD6 5 5 5 mA 11
Low Power (L) IDD6A 3 3 3 mA 11
Operating Current: Four bank interleaving READs IDD7 405 400 350 mA 22, 48
(Burst = 4) with auto precharge, tRC = minimum tRC allowed;
tCK = tCK (MIN); Address and control inputs change only

during active READ or WRITE commands

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Electrical Specifications

Table 27: IDD Test Cycle Times

Values reflect number of clock cycles for each test

Speed Clock Cycle

t t t t t t t
IDD Test Grade Time RRD RCD RAS RP RC RFC REFI CL
IDD0 -75/75Z 7.5ns n/a n/a 6 3 9 n/a n/a n/a
-75E 7.5ns n/a n/a 6 2 8 n/a n/a n/a
-6/-6T 6ns n/a n/a 7 3 10 n/a n/a n/a
-5B 5ns n/a n/a 8 3 11 n/a n/a n/a
IDD1 -75 7.5ns n/a n/a 6 3 9 n/a n/a 2.5
-75Z 7.5ns n/a n/a 6 3 9 n/a n/a 2
-75E 7.5ns n/a n/a 6 2 8 n/a n/a 2
-6/-6T 6ns n/a n/a 7 3 10 n/a n/a 2.5
-5B 5ns n/a n/a n/a n/a n/a n/a n/a 3
IDD4R -75 7.5ns n/a n/a n/a n/a n/a n/a n/a 2.5
-75Z 7.5ns n/a n/a n/a n/a n/a n/a n/a 2
-75E 7.5ns n/a n/a n/a n/a n/a n/a n/a 2
-6/-6T 6ns n/a n/a n/a n/a n/a n/a n/a 2.5
-5B 5ns n/a n/a n/a n/a n/a n/a n/a 3
IDD4W -75 7.5ns n/a n/a n/a n/a n/a n/a n/a n/a
-75Z 7.5ns n/a n/a n/a n/a n/a n/a n/a n/a
-75E 7.5ns n/a n/a n/a n/a n/a n/a n/a n/a
-6/-6T 6ns n/a n/a n/a n/a n/a n/a n/a n/a
-5B 5ns n/a n/a n/a n/a n/a n/a n/a n/a
IDD5 -75/75Z 7.5ns n/a n/a n/a n/a n/a 10 10 n/a
-75E 7.5ns n/a n/a n/a n/a n/a 9 9 n/a
-6/-6T 6ns n/a n/a n/a n/a n/a 12 12 n/a
-5B 5ns n/a n/a n/a n/a n/a 14 14 n/a
IDD5A -75/75Z 7.5ns n/a n/a n/a n/a n/a 10 1,029 n/a
-75E 7.5ns n/a n/a n/a n/a n/a 10 1,029 n/a
-6/-6T 6ns n/a n/a n/a n/a n/a 12 1,288 n/a
-5B 5ns n/a n/a n/a n/a n/a 14 1,546 n/a
IDD7 -75 7.5ns 2/4 3 n/a 3 10 n/a n/a 2.5
-75Z 7.5ns 2/4 3 n/a 3 10 n/a n/a 2
-75E 7.5ns 2 3 n/a 2 8 n/a n/a 2
-6/-6T 6ns 2/4 3 n/a 3 10 n/a n/a 2.5
-5B 5ns 2/4 3 n/a 3 11 n/a n/a 3

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Electrical Specifications

Table 28: Electrical Characteristics & Recommended AC Operating Conditions (-5B)

Notes: 1–5, 14–17, 33; notes appear on pages 71–77; 0°C ≤ TA ≤ +70°C; VDDQ = +2.6V ±0.1V, VDD = +2.6V ±0.1V

AC Characteristics -5B
Parameter Symbol Min Max Units Notes
t
Access window of DQ from CK/CK# AC –0.70 +0.70 ns
t t
CK high-level width CH 0.45 0.55 CK 30
t t
CK low-level width CL 0.45 0.55 CK 30
tCK (3) 5 7.5 ns 51
Clock cycle time CL = 3
tCK (2.5) 6 13 ns 45, 51
CL = 2.5
tCK (2) 7.5 13 ns 45, 51
CL = 2
tDH 0.40 – ns 26, 31
DQ and DM input hold time relative to DQS
tDS 0.40 – ns 26, 31
DQ and DM input setup time relative to DQS
tDIPW
DQ and DM input pulse width (for each input) 1.75 – ns 31
tDQSCK –0.60 +0.60 ns
Access window of DQS from CK/CK#
tDQSH tCK
DQS input high pulse width 0.35 –
tDQSL tCK
DQS input low pulse width 0.35 –
tDQSQ
DQS–DQ skew, DQS to last DQ valid, per group, per access – 0.40 ns 25, 26
tDQSS 0.72 1.28 tCK
WRITE command to first DQS latching transition
tDSS 0.2 – tCK
DQS falling edge to CK rising – setup time
tDSH tCK
DQS falling edge from CK rising – hold time 0.2 –
tHP tCH,tCL
Half-clock period – ns 34
tHZ
Data-out High-Z window from CK/CK# – +0.70 ns 18, 42
tLZ –0.70 – ns 18, 42
Data-out Low-Z window from CK/CK#
tIH
Address and control input hold time (slew rate ≤ 0.5 V/ns) F 0.60 – ns 14
tIS
Address and control input setup time (slew rate ≤ 0.5 V/ns) F 0.60 – ns 14
tIPW
Address and control input pulse width (for each input) 2.2 – ns
tMRD
LOAD MODE REGISTER command cycle time 10 – ns
tQH tHP – ns 25, 26
DQ–DQS hold, DQS to first DQ to go non-valid, per access
-tQHS
t
Data hold skew factor QHS – 0.50 ns
tRAS 40 70,000 ns 35
ACTIVE-to-PRECHARGE command
tRAP 15 – ns
ACTIVE-to-READ with auto precharge command
tRC 55 – ns
ACTIVE-to-ACTIVE/AUTO REFRESH command period
tRFC 70 – ns 49
AUTO REFRESH command period
t
ACTIVE-to-READ or WRITE delay RCD 15 – ns
t
PRECHARGE command period RP 15 – ns
tRPRE 0.9 1.1 tCK 43
DQS read preamble
tRPST 0.4 0.6 tCK 43
DQS read postamble
tRRD
ACTIVE bank a to ACTIVE bank b command 10 – ns
t t
DQS write preamble WPRE 0.25 – CK
t
DQS write preamble setup time WPRES 0 – ns 20, 21
tWPST tCK
DQS write postamble 0.4 0.6 19
tWR
Write recovery time 15 – ns
tWTR 2 – tCK
Internal WRITE-to-READ command delay
t
Data valid output window (DVW) n/a QH - tDQSQ ns 25
tREFC
REFRESH-to-REFRESH command interval – 70.3 µs 23
tREFI
Average periodic refresh interval – 7.8 µs 23

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Electrical Specifications

Table 28: Electrical Characteristics & Recommended AC Operating Conditions (-5B)

Notes: 1–5, 14–17, 33; notes appear on pages 71–77; 0°C ≤ TA ≤ +70°C; VDDQ = +2.6V ±0.1V, VDD = +2.6V ±0.1V

AC Characteristics -5B
Parameter Symbol Min Max Units Notes
t
Terminating voltage delay to VDD VTD 0 – ns
t
Exit SELF REFRESH-to-non-READ command XSNR 70 – ns
t t
Exit SELF REFRESH-to-READ command XSRD 200 – CK

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Table 29: Electrical Characteristics and Recommended AC Operating Conditions (-6/-6T/-75E)

Notes: 1–5, 14–17, 33; notes appear on pages 71–77; 0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V

AC Characteristics -6 (FBGA) -6T (TSOP) -75E

Parameter Symbol Min Max Min Max Min Max Units Notes
t
Access window of DQ from CK/CK# AC –0.70 +0.70 –0.70 +0.70 –0.75 +0.75 ns
t t
CK high-level width CH 0.45 0.55 0.45 0.55 0.45 0.55 CK 30
t t
CK low-level width CL 0.45 0.55 0.45 0.55 0.45 0.55 CK 30
tCK (2.5) 6 13 6 13 7.5 13 ns 45, 51
Clock cycle time CL = 2.5
tCK (2) 7.5 13 7.5 13 7.5 13 ns 45, 51
CL = 2
t
DQ and DM input hold time relative to DQS DH 0.45 – 0.45 – 0.5 – ns 26, 31
t
DQ and DM input setup time relative to DQS DS 0.45 – 0.45 – 0.5 – ns 26, 31
t
DQ and DM input pulse width (for each input) DIPW 1.75 – 1.75 – 1.75 – ns 31
tDQSCK –0.6 +0.6 –0.6 +0.6 –0.75 +0.75 ns
Access window of DQS from CK/CK#
tDQSH tCK
DQS input high pulse width 0.35 – 0.35 – 0.35 –
tDQSL 0.35 – 0.35 – 0.35 – tCK
DQS input low pulse width
tDQSQ – 0.4 – 0.45 – 0.5 ns 25, 26
DQS–DQ skew, DQS to last DQ valid, per group, per
access
tDQSS tCK
WRITE command-to-first DQS latching transition 0.75 1.25 0.75 1.25 0.75 1.25
tDSS tCK
DQS falling edge to CK rising - setup time 0.2 – 0.2 – 0.2 –
tDSH tCK
DQS falling edge from CK rising - hold time 0.2 – 0.2 – 0.2 –
tHP tCH, – tCH, – tCH, – ns 34
Half-clock period
tCL tCL tCL
t
Data-out High-Z window from CK/CK# HZ – +0.7 – +0.7 – +0.75 ns 18, 42
tLZ –0.7 – –0.7 – -0.75 – ns 18, 42
Data-out Low-Z window from CK/CK#
tIH
Address and control input hold time (fast slew rate) F 0.75 – 0.75 – 0.90 – ns
tIS
Address and control input setup time (fast slew rate) F 0.75 – 0.75 – 0.90 – ns
tIH
Address and control input hold time (slow slew rate) S 0.8 – 0.8 – 1 – ns 14
tIS 0.8 – 0.8 – 1 – ns 14
Address and control input setup time (slow slew S
rate)
tIPW 2.2 – 2.2 – 2.2 – ns
Address and Control input pulse width (for each
input)
tMRD 12 – 12 – 15 – ns
LOAD MODE REGISTER command cycle time
tQH tHP – tHP – tHP – ns 25, 26
DQ-DQS hold, DQS to first DQ to go non-valid, per
access -tQHS -tQHS -tQHS
tQHS
Data Hold Skew Factor – 0.50 – 0.55 – 0.75 ns
tRAS
ACTIVE-to-PRECHARGE command 42 70,00 42 70,00 40 120,00 ns 35, 53
0 0 0
tRAP 15 – 15 – 15 – ns
ACTIVE-to-READ with auto precharge command
tRC 60 – 60 – 60 – ns
ACTIVE-to-ACTIVE/AUTO REFRESH command period
t
AUTO REFRESH command period RFC 72 – 72 – 75 – ns 49
t
ACTIVE-to-READ or WRITE delay RCD 15 – 15 – 15 – ns
tRP
PRECHARGE command period 15 – 15 – 15 – ns
tRPRE tCK
DQS read preamble 0.9 1.1 0.9 1.1 0.9 1.1 43
tRPST tCK
DQS read postamble 0.4 0.6 0.4 0.6 0.4 0.6 43
t
ACTIVE bank a to ACTIVE bank b command RRD 12 – 12 – 15 – ns
tWPRE 0.25 – 0.25 – 0.25 – tCK
DQS write preamble
tWPRES
DQS write preamble setup time 0 – 0 – 0 – ns 20, 21
tWPST tCK
DQS write postamble 0.4 0.6 0.4 0.6 0.4 0.6 19

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Electrical Specifications

Table 29: Electrical Characteristics and Recommended AC Operating Conditions (-6/-6T/-75E)

Notes: 1–5, 14–17, 33; notes appear on pages 71–77; 0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V

AC Characteristics -6 (FBGA) -6T (TSOP) -75E

Parameter Symbol Min Max Min Max Min Max Units Notes
t
Write recovery time WR 15 – 15 – 15 – ns
t t
Internal WRITE-to-READ command delay WTR 1 – 1 – 1 – CK
t
Data valid output window (DVW) n/a QH - tDQSQ t
QH - tDQSQ t
QH - tDQSQ ns 25
tREFC – 70.3 – 70.3 – 70.3 µs 23
REFRESH-to-REFRESH command interval
tREFI – 7.8 – 7.8 – 7.8 µs 23
Average periodic refresh interval
t
Terminating voltage delay to VDD VTD 0 – 0 – 0 – ns
t
Exit SELF REFRESH-to-non-READ command XSNR 75 – 75 – 75 – ns
t t
Exit SELF REFRESH-to-READ command XSRD 200 – 200 – 200 – CK

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Electrical Specifications

Table 30: Electrical Characteristics and Recommended AC Operating Conditions (-75Z/-75)

Notes: 1–5, 14–17, 33; notes appear on pages 71–77; 0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V

AC Characteristics -75Z -75

Parameter Symbol Min Max Min Max Units Notes
t
Access window of DQ from CK/CK# AC –0.75 +0.75 –0.75 +0.75 ns
t t
CK high-level width CH 0.45 0.55 0.45 0.55 CK 30
t t
CK low-level width CL 0.45 0.55 0.45 0.55 CK 30
tCK (2.5) 7.5 13 7.5 13 ns 45,
Clock cycle time CL = 2.5
tCK (2) 7.5 13 10 13 ns 45,
CL = 2
t
DQ and DM input hold time relative to DQS DH 0.5 – 0.5 – ns 26, 31
t
DQ and DM input setup time relative to DQS DS 0.5 – 0.5 – ns 26, 31
t
DQ and DM input pulse width (for each input) DIPW 1.75 – 1.75 – ns 31
tDQSCK –0.75 +0.75 –0.75 +0.75 ns
Access window of DQS from CK/CK#
tDQSH tCK
DQS input high pulse width 0.35 – 0.35 –
tDQSL 0.35 – 0.35 – tCK
DQS input low pulse width
tDQSQ – 0.5 – 0.5 ns 25, 26
DQS–DQ skew, DQS to last DQ valid, per group, per access
tDQSS tCK
WRITE command-to-first DQS latching transition 0.75 1.25 0.75 1.25
tDSS tCK
DQS falling edge to CK rising – setup time 0.2 – 0.2 –
tDSH tCK
DQS falling edge from CK rising – hold time 0.2 – 0.2 –
tHP tCH,tCL – tCH,tCL – ns 34
Half-clock period
tHZ – +0.75 – +0.75 ns 18, 42
Data-out High-Z window from CK/CK#
tLZ
Data-out Low-Z window from CK/CK# –0.75 – –0.75 – ns 18, 42
tIH
Address and control input hold time (fast slew rate) F 0.90 – 0.90 – ns
tIS
Address and control input setup time (fast slew rate) F 0.90 – 0.90 – ns
tIH 1 – 1 – ns 14
Address and control input hold time (slow slew rate) S
tIS 1 – 1 – ns 14
Address and control input setup time (slow slew rate) S
tIPW
Address and Control input pulse width (for each input) 2.2 – 2.2 – ns
tMRD
LOAD MODE REGISTER command cycle time 15 – 15 – ns
tQH tHP – tHP – ns 25, 26
DQ–DQS hold, DQS to first DQ to go non-valid, per access
-tQHS -tQHS
tQHS
Data Hold Skew Factor – 0.75 – 0.75 ns
t
ACTIVE-to-PRECHARGE command RAS 40 120,000 40 120,000 ns 35
t
ACTIVE-to-READ with auto precharge command RAP 20 – 20 – ns
tRC
ACTIVE-to-ACTIVE/AUTO REFRESH command period 65 – 65 – ns
tRFC 75 – 75 – ns 49
AUTO REFRESH command period
tRCD 20 – 20 – ns
ACTIVE-to-READ or WRITE delay
t
PRECHARGE command period RP 20 – 20 – ns
t t
DQS read preamble RPRE 0.9 1.1 0.9 1.1 CK 43
tRPST 0.4 0.6 0.4 0.6 tCK 43
DQS read postamble
tRRD 15 – 15 – ns
ACTIVE bank a to ACTIVE bank b command
tWPRE tCK
DQS write preamble 0.25 – 0.25 –
t
DQS write preamble setup time WPRES 0 – 0 – ns 20, 21
tWPST tCK
DQS write postamble 0.4 0.6 0.4 0.6 19
tWR
Write recovery time 15 – 15 – ns
tWTR tCK
Internal WRITE-to-READ command delay 1 – 1 –
n/a tQH - tDQSQ tQH - tDQSQ ns 25
Data valid output window (DVW)
t
REFRESH-to-REFRESH command interval REFC – 70.3 – 70.3 µs 23

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Table 30: Electrical Characteristics and Recommended AC Operating Conditions (-75Z/-75)

Notes: 1–5, 14–17, 33; notes appear on pages 71–77; 0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V

AC Characteristics -75Z -75

Parameter Symbol Min Max Min Max Units Notes
t
Average periodic refresh interval REFI – 7.8 – 7.8 µs 23
t
Terminating voltage delay to VDD VTD 0 – 0 – ns
t
Exit SELF REFRESH-to-non-READ command XSNR 75 – 75 – ns
tXSRD 200 – 200 – tCK
Exit SELF REFRESH-to-READ command

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Table 31: Input Slew Rate Derating Values for Addresses and Commands
Notes: 14; notes appear on pages 71–77; 0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V

t t
Speed Slew Rate IS IH Units
-75/-75Z/-75E 0.500 V/ns 1.00 1 ns
-75/-75Z/-75E 0.400 V/ns 1.05 1 ns
-75/-75Z/-75E 0.300 V/ns 1.15 1 ns

Table 32: Input Slew Rate Derating Values for DQ, DQS, and DM
Notes: 31; notes appear on pages 71–77; 0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V

Speed Slew Rate tDS tDH Units

-75/-75Z/-75E 0.500 V/ns 0.50 0.50 ns
-75/-75Z/-75E 0.400 V/ns 0.55 0.55 ns
-75/-75Z/-75E 0.300 V/ns 0.60 0.60 ns

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Notes

Notes
1. All voltages referenced to VSS.
2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted
at nominal reference/supply voltage levels, but the related specifications and device
operation are guaranteed for the full voltage range specified.
3. Outputs (except for IDD measurements) measured with equivalent load:

VTT
50Ω
Output Reference
Point
(VOUT)
30pF

4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environ-
ment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#),
and parameter specifications are guaranteed for the specified AC input levels under
normal use conditions. The minimum slew rate for the input signals used to test the
device is 1V/ns in the range between VIL(AC) and VIH(AC).
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e.,
the receiver will effectively switch as a result of the signal crossing the AC input level,
and will remain in that state as long as the signal does not ring back above [below] the
DC input LOW [HIGH] level).
6. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in
the DC level of the same. Peak-to-peak noise (non-common mode) on VREF may not
exceed ±2 percent of the DC value. Thus, from VDDQ/2, VREF is allowed ±25mV for DC
error and an additional ±25mV for AC noise. This measurement is to be taken at the
nearest VREF bypass capacitor.
7. VTT is not applied directly to the device. VTT is a system supply for signal termination
resistors, is expected to be set equal to VREF and must track variations in the DC level
of VREF.
8. VID is the magnitude of the difference between the input level on CK and the input
level on CK#.
9. The value of VIX and VMP are expected to equal VDDQ/2 of the transmitting device and
must track variations in the DC level of the same.
10. IDD is dependent on output loading and cycle rates. Specified values are obtained
with minimum cycle times at CL = 3 for -5B, CL = 2.5 for -6/-6T/-75, and CL = 2 for -
75E/-75Z speeds with the outputs open.
11. Enables on-chip refresh and address counters.
12. IDD specifications are tested after the device is properly initialized, and is averaged at
the defined cycle rate.
13. This parameter is sampled. VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V, VREF = VSS, f = 100
MHz, TA = 25°C, VOUT(DC) = VDDQ/2, VOUT (peak-to-peak) = 0.2V. DM input is
grouped with I/O pins, reflecting the fact that they are matched in loading.
14. For slew rates less than 1 V/ns and greater than or equal to 0.5 V/ns. If the slew rate is
less than 0.5 V/ns, timing must be derated: tIS has an additional 50ps per each
100 mV/ns reduction in slew rate from the 500 mV/ns. tIH has 0ps added, that is, it
remains constant. If the slew rate exceeds 4.5 V/ns, functionality is uncertain. For -5B,
-6, and -6T, slew rates must be greater than or equal to 0.5 V/ns.

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 512Mb: x4, x8, x16 DDR SDRAM
Notes

15. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at
which CK and CK# cross; the input reference level for signals other than CK/CK# is
VREF.
16. Inputs are not recognized as valid until VREF stabilizes. Once initialized, including self
refresh mode, VREF must be powered within specified range. Exception: during the
period before VREF stabilizes, CKE < 0.3 × VDDQ is recognized as LOW.
17. The output timing reference level, as measured at the timing reference point (indi-
cated in Note 3) is VTT.
18. tHZ and tLZ transitions occur in the same access time windows as data valid transi-
tions. These parameters are not referenced to a specific voltage level, but specify
when the device output is no longer driving (HZ) or begins driving (LZ).
19. The intent of the “Don’t Care” state after completion of the postamble is the DQS-
driven signal should either be HIGH, LOW, or High-Z, and that any signal transition
within the input switching region must follow valid input requirements. That is, if
DQS transitions HIGH (above VIHDC (MIN) then it must not transition LOW (below
VIH(DC) prior to tDQSH (MIN).
20. This is not a device limit. The device will operate with a negative value, but system
performance could be degraded due to bus turnaround.
21. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE com-
mand. The case shown (DQS going from High-Z to logic LOW) applies when no
WRITEs were previously in progress on the bus. If a previous WRITE was in progress,
DQS could be HIGH during this time, depending on tDQSS.
22. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the
minimum absolute value for the respective parameter. tRAS (MAX) for IDD measure-
ments is the largest multiple of tCK that meets the maximum absolute value for tRAS.
23. The refresh period is 64ms. This equates to an average refresh rate of 7.8125µs. How-
ever, an AUTO REFRESH command must be asserted at least once every 70.3µs; burst
refreshing or posting by the DRAM controller greater than 8 REFRESH cycles is not
allowed.
24. The I/O capacitance per DQS and DQ byte/group will not differ by more than this
maximum amount for any given device.
25. The data valid window is derived by achieving other specifications - tHP (tCK/2),
t
DQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates in direct propor-
tion to the clock duty cycle and a practical data valid window can be derived. The
clock is allowed a maximum duty cycle variation of 45/55, because functionality is
uncertain when operating beyond a 45/55 ratio. The data valid window derating
curves are provided in Figure 35 on page 73 for duty cycles ranging between 50/50
and 45/55.
26. Referenced to each output group: x4 = DQS with DQ0–DQ3; x8 = DQS with DQ0–DQ7;
x16 = LDQS with DQ0–DQ7; and UDQS with DQ8–DQ15.
27. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH
during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during
standby).
28. To maintain a valid level, the transitioning edge of the input must:
A. Sustain a constant slew rate from the current AC level through to the target AC
level, VIL(AC) or VIH(AC).
B. Reach at least the target AC level.
C. After the AC target level is reached, continue to maintain at least the target DC
level, VIL(DC) or VIH(DC).

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 512Mb: x4, x8, x16 DDR SDRAM
Notes

29. The Input capacitance per pin group will not differ by more than this maximum
amount for any given device.
30. CK and CK# input slew rate must be ≥ 1 V/ns (≥ 2 V/ns if measured differentially).

Figure 35: Derating Data Valid Window (tQH – tDQSQ)

-6T @ tCK = 7.5ns

-75E / -75 @ tCK = 7.5ns
3.0ns
-6 @ tCK = 6ns
2.75
2.71
2.68
-6T @ tCK = 6ns
2.64
2.60
2.56 -5B @ tCK = 5ns
2.53
2.50 2.49
2.5ns 2.46
2.43
2.45
2.41
2.39 2.38
2.35
Data Valid Window

2.31
2.28
2.24
2.20
2.16
2.13
2.10 2.07
2.04
2.01
2.0ns 1.98
1.95
1.92
2.00 1.89 1.86
1.97 1.83
1.94 1.80
1.91
1.88
1.85
1.82
1.79 1.76
1.73
1.70
1.5ns 1.60 1.58
1.55
1.53 1.50 1.48 1.45
1.43 1.40 1.38
1.35

1.0ns
50/50 49/51 48/53 47/53 46/54 45/55

Clock Duty Cycle

31. DQ and DM input slew rates must not deviate from DQS by more than 10 percent. If
the DQ/DM/DQS slew rate is less than 0.5 V/ns, timing must be derated: 50ps must be
added to tDS and tDH for each 100 mV/ns reduction in slew rate. For -5B, -6, and -6T
speed grades, slew rate must be ≥ 0.5 V/ns. If slew rate exceeds 4 V/ns, functionality is
uncertain.
32. VDD must not vary more than 4 percent if CKE is not active while any bank is active.
33. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary by
the same amount.
34. tHP (MIN) is the lesser of tCL minimum and tCH minimum actually applied to the
device CK and CK# inputs, collectively, during bank active.
35. READs and WRITEs with auto precharge are not allowed to be issued until tRAS (MIN)
can be satisfied prior to the internal precharge command being issued.
36. Any positive glitch must be less than 1/3 of the clock cycle and not more than +400mV
or 2.9V (+300mV or 2.9V maximum for -5B), whichever is less. Any negative glitch
must be less than 1/3 of the clock cycle and not exceed either –300mV or 2.2V (2.4V for
-5B), whichever is more positive. The average cannot be below the +2.5V (2.6V for -5B)
minimum.
37. Normal output drive curves:
A. The full driver pull-down current variation from MIN to MAX process, tempera-
ture and voltage will lie within the outer bounding lines of the V-I curve of
Figure 36 on page 74.
B. The driver pull-down current variation, within nominal voltage and temperature
limits, is expected, but not guaranteed, to lie within the inner bounding lines of
the V-I curve of Figure 36 on page 74.

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Notes

C. The full driver pull-up current variation from MIN to MAX process, temperature
and voltage will lie within the outer bounding lines of the V-I curve of Figure 37 on
page 74.
D. The driver pull-up current variation within nominal limits of voltage and temper-
ature is expected, but not guaranteed, to lie within the inner bounding lines of the
V-I curve of Figure 37 on page 74.
E. The full ratio variation of MAX to MIN pull-up and pull-down current should be
between 0.71 and 1.4 for drain-to-source voltages from 0.1V to 1.0V at the same
voltage and temperature.
F. The full ratio variation of the nominal pull-up to pull-down current should be
unity ±10 percent for device drain-to-source voltages from 0.1V to 1.0V.

Figure 36: Full Drive Pull-Down Characteristics

160

140

120

100
I OUT (mA)

80

60

40

20

0
0.0 0.5 1.0 1.5 2.0 2.5
VOUT (V)

Figure 37: Full Drive Pull-Up Characteristics

-20

-40

-60

-80
IOUT (mA)

-100

-120

-140

-160

-180

-200
0.0 0.5 1.0 1.5 2.0 2.5
VDDQ - VOUT (V)

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 512Mb: x4, x8, x16 DDR SDRAM
Notes

38. Reduced output drive curves:

A. The full driver pull-down current variation from MIN to MAX process, tempera-
ture, and voltage will lie within the outer bounding lines of the V-I curve of
Figure 38 on page 75.
B. The driver pull-down current variation, within nominal voltage and temperature
limits, is expected, but not guaranteed, to lie within the inner bounding lines of
the V-I curve of Figure 38 on page 75.
C. The full driver pull-up current variation from MIN to MAX process, temperature
and voltage will lie within the outer bounding lines of the V-I curve of Figure 39.
D. The driver pull-up current variation, within nominal voltage and temperature
limits, is expected, but not guaranteed, to lie within the inner bounding lines of
the V-I curve of Figure 39 on page 76.
E. The full ratio variation of the MAX to MIN pull-up and pull-down current should
be between 0.71 and 1.4 for device drain-to-source voltages from 0.1V to 1.0V at
the same voltage and temperature.
F. The full ratio variation of the nominal pull-up to pull-down current should be
unity ±10 percent, for device drain-to-source voltages from 0.1V to 1.0V.

Figure 38: Reduced Drive Pull-Down Characteristics

160

140

120

100
I OUT (mA)

80

60

40

20

0
0.0 0.5 1.0 1.5 2.0 2.5
VOUT (V)

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 512Mb: x4, x8, x16 DDR SDRAM
Notes

Figure 39: Reduced Drive Pull-Up Characteristics

-20

-40

-60

-80
IOUT (mA)

-100

-120

-140

-160

-180

-200
0.0 0.5 1.0 1.5 2.0 2.5
VDDQ - VOUT (V)

39. The voltage levels used are derived from a minimum VDD level and the referenced test
load. In practice, the voltage levels obtained from a properly terminated bus will pro-
vide significantly different voltage values.
40. VIH overshoot: VIH (MAX) = VDDQ + 1.5V for a pulse width ≤ 3ns and the pulse width
can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL (MIN) = –1.5V for a
pulse width ≤ 3ns and the pulse width can not be greater than 1/3 of the cycle rate.
41. VDD and VDDQ must track each other.
42. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will
prevail over tDQSCK (MIN) + tRPRE (MAX) condition.
43. RPST end point and tRPRE begin point are not referenced to a specific voltage level
t
but specify when the device output is no longer driving (tRPST), or begins driving
(tRPRE).
44. During initialization, VDDQ, VTT, and VREF must be equal to or less than VDD + 0.3V.
Alternatively, VTT may be 1.35V maximum during power up, even if VDD/VDDQ are 0V,
provided a minimum of 42Ω of series resistance is used between the VTT supply and
the input pin.
45. The current Micron part operates below 83 MHz (slowest specified JEDEC operating
frequency). As such, future die may not reflect this option.
46. When an input signal is HIGH or LOW, it is defined as a steady state logic HIGH or
LOW.
47. Random addressing changing 50 percent of data changing at every transfer.
48. Random addressing changing 100 percent of data changing at every transfer.
49. CKE must be active (HIGH) during the entire time a refresh command is executed.
That is, from the time the AUTO REFRESH command is registered, CKE must be
active at each rising clock edge, until tRFC has been satisfied.
50. IDD2N specifies the DQ, DQS, and DM to be driven to a valid HIGH or LOW logic level.
IDD2Q is similar to IDD2F except IDD2Q specifies the address and control inputs to
remain stable. Although IDD2F, IDD2N, and IDD2Q are similar, IDD2F is “worst case.”
51. Whenever the operating frequency is altered, not including jitter, the DLL is required
to be reset followed by 200 clock cycles before any READ command.

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Notes

52. This is the DC voltage supplied at the DRAM and is inclusive of all noise up to 20 MHz.
Any noise above 20 MHz at the DRAM generated from any source other than that of
the DRAM itself may not exceed the DC voltage range of 2.6V ±100mV.
53. The -6/-6T speed grades will operate with tRAS (MIN) = 40ns and tRAS (MAX) =
120,000ns at any slower frequency.

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 512Mb: x4, x8, x16 DDR SDRAM
Notes

Table 33: Normal Output Drive Characteristics

Pull-Down Current (mA) Pull-Up Current (mA)

Voltage Nominal Nominal Nominal Nominal
(V) LOW HIGH Min Max LOW HIGH Min Max
0.1 6.0 6.8 4.6 9.6 –6.1 –7.6 –4.6 –10.0
0.2 12.2 13.5 9.2 18.2 –12.2 –14.5 –9.2 –20.0
0.3 18.1 20.1 13.8 26.0 –18.1 –21.2 –13.8 –29.8
0.4 24.1 26.6 18.4 33.9 –24.0 –27.7 –18.4 –38.8
0.5 29.8 33.0 23.0 41.8 –29.8 –34.1 –23.0 –46.8
0.6 34.6 39.1 27.7 49.4 –34.3 –40.5 –27.7 –54.4
0.7 39.4 44.2 32.2 56.8 –38.1 –46.9 –32.2 –61.8
0.8 43.7 49.8 36.8 63.2 –41.1 –53.1 –36.0 –69.5
0.9 47.5 55.2 39.6 69.9 –43.8 –59.4 –38.2 –77.3
1.0 51.3 60.3 42.6 76.3 –46.0 –65.5 –38.7 –85.2
1.1 54.1 65.2 44.8 82.5 –47.8 –71.6 –39.0 –93.0
1.2 56.2 69.9 46.2 88.3 –49.2 –77.6 –39.2 –100.6
1.3 57.9 74.2 47.1 93.8 –50.0 –83.6 –39.4 –108.1
1.4 59.3 78.4 47.4 99.1 –50.5 –89.7 –39.6 –115.5
1.5 60.1 82.3 47.7 103.8 –50.7 –95.5 –39.9 –123.0
1.6 60.5 85.9 48.0 108.4 –51.0 –101.3 –40.1 –130.4
1.7 61.0 89.1 48.4 112.1 –51.1 –107.1 –40.2 –136.7
1.8 61.5 92.2 48.9 115.9 –51.3 –112.4 –40.3 –144.2
1.9 62.0 95.3 49.1 119.6 –51.5 –118.7 –40.4 –150.5
2.0 62.5 97.2 49.4 123.3 –51.6 –124.0 –40.5 –156.9
2.1 62.8 99.1 49.6 126.5 –51.8 –129.3 –40.6 –163.2
2.2 63.3 100.9 49.8 129.5 –52.0 –134.6 –40.7 –169.6
2.3 63.8 101.9 49.9 132.4 –52.2 –139.9 –40.8 –176.0
2.4 64.1 102.8 50.0 135.0 –52.3 –145.2 –40.9 –181.3
2.5 64.6 103.8 50.2 137.3 –52.5 –150.5 –41.0 –187.6
2.6 64.8 104.6 50.4 139.2 –52.7 –155.3 –41.1 –192.9
2.7 65.0 105.4 50.5 140.8 –52.8 –160.1 –41.2 –198.2
Note: The above characteristics are specified under best, worst, and nominal process variation/
conditions.

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 512Mb: x4, x8, x16 DDR SDRAM
Notes

Table 34: Reduced Output Drive Characteristics

Pull-Down Current (mA) Pull-Up Current (mA)

Voltage Nominal Nominal Nominal Nominal
(V) LOW HIGH Min Max LOW HIGH Min Max
0.1 3.4 3.8 2.6 5.0 –3.5 –4.3 –2.6 –5.0
0.2 6.9 7.6 5.2 9.9 –6.9 –7.8 –5.2 –9.9
0.3 10.3 11.4 7.8 14.6 –10.3 –12.0 –7.8 –14.6
0.4 13.6 15.1 10.4 19.2 –13.6 –15.7 –10.4 –19.2
0.5 16.9 18.7 13.0 23.6 –16.9 –19.3 –13.0 –23.6
0.6 19.9 22.1 15.7 28.0 –19.4 –22.9 –15.7 –28.0
0.7 22.3 25.0 18.2 32.2 –21.5 –26.5 –18.2 –32.2
0.8 24.7 28.2 20.8 35.8 –23.3 –30.1 –20.4 –35.8
0.9 26.9 31.3 22.4 39.5 –24.8 –33.6 –21.6 –39.5
1.0 29.0 34.1 24.1 43.2 –26.0 –37.1 –21.9 –43.2
1.1 30.6 36.9 25.4 46.7 –27.1 –40.3 –22.1 –46.7
1.2 31.8 39.5 26.2 50.0 –27.8 –43.1 –22.2 –50.0
1.3 32.8 42.0 26.6 53.1 –28.3 –45.8 –22.3 –53.1
1.4 33.5 44.4 26.8 56.1 –28.6 –48.4 –22.4 –56.1
1.5 34.0 46.6 27.0 58.7 –28.7 –50.7 –22.6 –58.7
1.6 34.3 48.6 27.2 61.4 –28.9 –52.9 –22.7 –61.4
1.7 34.5 50.5 27.4 63.5 –28.9 –55.0 –22.7 –63.5
1.8 34.8 52.2 27.7 65.6 –29.0 –56.8 –22.8 –65.6
1.9 35.1 53.9 27.8 67.7 –29.2 –58.7 –22.9 –67.7
2.0 35.4 55.0 28.0 69.8 –29.2 –60.0 –22.9 –69.8
2.1 35.6 56.1 28.1 71.6 –29.3 –61.2 –23.0 –71.6
2.2 35.8 57.1 28.2 73.3 –29.5 –62.4 –23.0 –73.3
2.3 36.1 57.7 28.3 74.9 –29.5 –63.1 –23.1 –74.9
2.4 36.3 58.2 28.3 76.4 –29.6 –63.8 –23.2 –76.4
2.5 36.5 58.7 28.4 77.7 –29.7 –64.4 –23.2 –77.7
2.6 36.7 59.2 28.5 78.8 –29.8 –65.1 –23.3 –78.8
2.7 36.8 59.6 28.6 79.7 –29.9 –65.8 –23.3 –79.7
Note: The above characteristics are specified under best, worst, and nominal process variation/
conditions.

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 512Mb: x4, x8, x16 DDR SDRAM
Notes

Figure 40: x4, x8 Data Output Timing – tDQSQ, tQH, and Data Valid Window

T1 T2 T2n T3 T3n T4
CK#
CK
tHP5 tHP5 tHP5 tHP5 tHP5 tHP5

tDQSQ3 tDQSQ3 tDQSQ3 tDQSQ3

DQS1

DQ (Last data valid)

DQ2
DQ2
DQ2
DQ2
DQ2
DQ2
DQ (First data no longer valid)

tQH4 tQH4 tQH4 tQH4

DQ (Last data valid) T2 T2n T3 T3n

DQ (First data no longer valid) T2 T2n T3 T3n

All DQ and DQS, collectively6 T2 T2n T3 T3n

Earliest signal transition
Latest signal transition
Data Data Data Data
Valid Valid Valid Valid
Window Window Window Window

Notes: 1. DQ transitioning after DQS transition define tDQSQ window. DQS transitions at T2 and at
T2n are an “early DQS,” at T3 is a “nominal DQS,” and at T3n is a “late DQS.”
2. For a x4, only two DQ apply.
3. tDQSQ is derived at each DQS clock edge and is not cumulative over time and begins with
DQS transition and ends with the last valid DQ transition.
4. tQH is derived from tHP: tQH = tHP - tQHS.
5. tHP is the lesser of tCL or tCH clock transition collectively when a bank is active.
6. The data valid window is derived for each DQS transitions and is defined as tQH minus
t
DQSQ.

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Notes

Figure 41: x16 Data Output Timing – tDQSQ, tQH, and Data Valid Window

T1 T2 T2n T3 T3n T4
CK#
CK
tHP5 tHP5 tHP5 tHP5 tHP5 tHP5

tDQSQ3 tDQSQ3 tDQSQ3 tDQSQ3

LDQS1

DQ (Last data valid)2

DQ2
DQ2
DQ2
DQ2

Lower Byte
DQ2
DQ2
DQ (First data no longer valid)2

tQH4 tQH4 tQH4 tQH4

DQ (Last data valid)2 T2 T2n T3 T3n

DQ (First data no longer valid)2 T2 T2n T3 T3n

DQ0 - DQ7 and LDQS, collectively6 T2 T2n T3 T3n

Data Valid Data Valid Data Valid Data Valid

window window window window
tDQSQ3 tDQSQ3 tDQSQ3 tDQSQ3

UDQS1

DQ (Last data valid)7

DQ7
DQ7
DQ7
DQ7

Upper Byte
DQ7
DQ7
DQ (First data no longer valid)7

tQH4
tQH4 tQH4 tQH4

DQ (Last data valid)7 T2 T2n T3 T3n

DQ (First data no longer valid)7 T2 T2n T3 T3n

DQ8–DQ15 and UDQS, collectively6 T2 T2n T3 T3n

Data Valid Data Valid Data Valid Data Valid

Window Window Window Window
Notes: 1. DQ transitioning after DQS transition define tDQSQ window. LDQS defines the lower byte
and UDQS defines the upper byte.
2. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.
3. tDQSQ is derived at each DQS clock edge and is not cumulative over time and begins with
DQS transition and ends with the last valid DQ transition.
4. tQH is derived from tHP: tQH = tHP - tQHS.
5. tHP is the lesser of tCL or tCH clock transition collectively when a bank is active.
6. The data valid window is derived for each DQS transition and is tQH minus tDQSQ.
7. DQ8, DQ9, DQ10, D11, DQ12, DQ13, DQ14, or DQ15.

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Notes

Figure 42: Data Output Timing – tAC and tDQSCK

T07 T1 T2 T2n T3 T3n T4 T4n T5 T5n T6

CK#
CK
tDQSCK1 (MAX) tDQSCK1 (MAX) tHZ(MAX)
tLZ (MIN) tDQSCK1 (MIN) tDQSCK1 (MIN)

tRPRE tRPST
DQS, or LDQS/UDQS2

DQ (Last data valid) T2 T2n T3 T3n T4 T4n T5 T5n

DQ (First data valid) T2 T2n T3 T3n T4 T4n T5 T5n

All DQ values, collectively3 T2 T2n T3 T3n T4 T4n T5 T5n

tLZ (MIN) tAC4 (MIN) tAC4 (MAX)

tHZ (MAX)

Notes: 1. tDQSCK is the DQS output window relative to CK and is the “long term” component of
DQS skew.
2. DQ transitioning after DQS transition define tDQSQ window.
3. All DQ must transition by tDQSQ after DQS transitions, regardless of tAC.
4. tAC is the DQ output window relative to CK, and is the “long term” component of
DQ skew.
5. tLZ (MIN) and tAC (MIN) are the first valid signal transition.
6. tHZ (MAX) and tAC (MAX) are the latest valid signal transition.
7. READ command with CL = 2 issued at T0.

Figure 43: Data Input Timing

T03 T1 T1n T2 T2n T3

CK#
CK
tDQSS tDSH1 tDSS2 tDSH1 tDSS2

DQS
tDQSL tDQSH tWPST
tWPRES tWPRE
DQ DI
b

DM

tDS tDH
TRANSITIONING DATA

DON’T CARE

t
Notes: 1. DSH (MIN) generally occurs during tDQSS (MIN).
2. tDSS (MIN) generally occurs during tDQSS (MAX).
3. WRITE command issued at T0.
4. For x16, LDQS controls the lower byte and UDQS controls the upper byte.

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512MBDDRx4x8x16_2.fm - Rev. K 6/06 EN 82 ©2000–2005 Micron Technology, Inc. All rights reserved.
 512Mb: x4, x8, x16 DDR SDRAM
Initialization

Initialization
To ensure device operation the DRAM must be initialized as described below:
1. Simultaneously apply power to VDD and VDDQ.
2. Apply VREF and then VTT power.
3. Assert and hold CKE at a LVCMOS logic LOW.
4. Provide stable CLOCK signals.
5. Wait at least 200µs.
6. Bring CKE HIGH and provide at least one NOP or DESELECT command. At this point
the CKE input changes from a LVCMOS input to a SSTL2 input only and will remain a
SSTL_2 input unless a power cycle occurs.
7. Perform a PRECHARGE ALL command.
8. Wait at least tRP time; during this time NOPs or DESELECT commands must be given.
9. Using the LMR command program the extended mode register (E0 = 0 to enable the
DLL and E1 = 0 for normal drive or E1 = 1 for reduced drive, E2 through En must be set
to 0; where n = most significant bit).
10. Wait at least tMRD time; only NOPs or DESELECT commands are allowed.
11. Using the LMR command program the mode register to set operating parameters and
to reset the DLL. At least 200 clock cycles are required between a DLL reset and any
READ command.
12. Wait at least tMRD time; only NOPs or DESELECT commands are allowed.
13. Issue a PRECHARGE ALL command.
14. Wait at least tRP time; only NOPs or DESELECT commands are allowed.
15. Issue an AUTO REFRESH command. This may be moved prior to step 13.
16. Wait at least tRFC time; only NOPs or DESELECT commands are allowed.
17. Issue an AUTO REFRESH command. This may be moved prior to step 13.
18. Wait at least tRFC time; only NOPs or DESELECT commands are allowed.
19. Although not required by the Micron device, JEDEC requires an LMR command to
clear the DLL bit (set M8 = 0). If an LMR command is issued, the same operating
parameters should be utilized as in step 11.
20. Wait at least tMRD time; only NOPs or DESELECT commands are allowed.
21. At this point the DRAM is ready for any valid command. At least 200 clock cycles with
CKE HIGH are required between step 11 (DLL RESET) and any READ command.

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 512Mb: x4, x8, x16 DDR SDRAM
Initialization

Figure 44: Initialization Flow Diagram

Step

1 VDD and VDDQ ramp

2 Apply VREF and VTT

3 CKE must be LVCMOS LOW

4 Apply stable CLOCKs

5 Wait at least 200us

6 Bring CKE HIGH with a NOP command

7 PRECHARGE ALL

8 Assert NOP or DESELECT for tRP time

9 Configure extended mode register

10 Assert NOP or DESELECT for tMRD time

11 Configure load mode register and reset DLL

12 Assert NOP or DESELECT for tMRD time

13 PRECHARGE ALL

14 Assert NOP or DESELECT for tRP time

15 Issue AUTO REFRESH command

16 Assert NOP or DESELECT commands for tRFC

17 Issue AUTO REFRESH command

18 Assert NOP or DESELECT for tRFC time

19 Optional LMR command to clear DLL bit

20 Assert NOP or DESELECT for tMRD time

21 DRAM is ready for any valid command

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512MBDDRx4x8x16_2.fm - Rev. K 6/06 EN 84 ©2000–2005 Micron Technology, Inc. All rights reserved.
 512Mb: x4, x8, x16 DDR SDRAM
Timing Diagrams

Timing Diagrams
Figure 45: Initialize and Load Mode Registers
((
))
VDD
((
))
VDDQ
tVTD1
((
VTT1 ))

VREF ((
))

T0 T1 Ta0 Tb0 Tc0 Td0 Te0 Tf0

CK# (( (( (( (( (( (( ((
)) )) )) )) )) )) ))
CK (( (( (( (( (( (( ((
)) tCH tCL )) )) )) )) )) ))

tIS tIH
(( (( (( (( (( ((
LVCMOS )) )) )) )) )) ))
CKE LOW LEVEL (( (( (( (( (( (( ((
)) )) )) )) )) )) ))
tIS tIH
(( (( (( (( (( (( ((
)) )) )) )) )) )) ))
COMMAND6 (( NOP PRE LMR LMR PRE AR AR ACT5
(( (( (( (( (( ((
)) )) )) )) )) )) ))
tCK
(( (( (( (( (( (( ((
)) )) )) )) )) )) ))
DM
(( (( (( (( (( (( ((
)) )) )) )) )) )) ))
tIS tIH
(( (( (( (( (( (( ((
A0–A9, )) )) )) )) )) )) ))
CODE CODE 4 RA
A11, A12 (( (( (( (( (( (( ((
)) )) )) )) )) )) ))
tIS tIH
ALL BANKS ALL BANKS
(( (( (( (( (( (( ((
A10 )) )) )) )) )) )) ))
CODE CODE RA
(( (( (( (( (( (( ((
)) )) )) )) )) )) ))
tIS tIH tIS tIH
tIS tIH
(( (( (( (( (( (( ((
BA0, BA1 )) )) BA0 = H, )) BA0 = L, )) )) )) ))
BA1 = L BA1 = L BA
(( (( (( (( (( (( ((
)) )) )) )) )) )) ))

(( High-Z (( (( (( (( (( ((
DQS )) )) )) )) )) )) ))

(( High-Z (( (( (( (( (( ((
DQ )) )) )) )) )) )) ))
T = 200µs
tRP tMRD tMRD tRP tRFC tRFC5
Power-up: VDD and CK stable Load Extended
Mode Register 200 cycles of CK3
Load Mode
Register2 DON’T CARE

Notes: 1. VTT is not applied directly to the device; however, tVTD should be greater than or equal to
zero to avoid device latch-up. VDDQ, VTT, and VREF, must be equal to or less than VDD +
0.3V. Alternatively, VTT may be 1.35V maximum during power up, even if VDD/VDDQ are 0V,
provided a minimum of 42 ohms of series resistance is used between the VTT supply and
the input pin. Once initialized, VREF must always be powered with in specified range.
2. Reset the DLL with A8 = H while programming the operating parameters.
3. tMRD is required before any command can be applied (during MRD time only NOPs or
deselects are allowed), and 200 cycles of CK are required before a READ command can be
issued.
4. The two AUTO REFRESH commands at Td0 and Te0 may be applied following the LOAD
MODE REGISTER (LMR) command at Ta0.
5. Although not required by the Micron device, JEDEC specifies issuing another LMR com-
mand (A8 = L) prior to activating any bank. If another LMR command is issued, the same
operating parameters, previously issued, must be used.
6. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, AR = AUTO
REFRESH command, ACT = ACTIVE command, RA = Row Address, BA = Bank Address.

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 512Mb: x4, x8, x16 DDR SDRAM
Timing Diagrams

Figure 46: Power-Down Mode

T0 T1 T2 Ta0 Ta1 Ta2

((
CK# ))
CK ((
tCK tCH tCL ))

tIS tIH tIS tIS

1
CKE ((
tIS tIH ))

((
))
COMMAND VALID2 NOP NOP VALID
((
))
tIS tIH
((
))
ADDR VALID VALID
((
))
((
))
DQS
((
))
((
))
DQ ((
))
((
))
DM ((
))
tREFC
Enter 3 Exit
Power-Down Power-Down
Mode Mode

DON’T CARE

Notes: 1. Once initialized, VREF must always be powered with in specified range.
2. If this command is a PRECHARGE (or if the device is already in the idle state), then the
power-down mode shown is precharge power-down. If this command is an ACTIVE (or if at
least one row is already active), then the power-down mode shown is active power-down.
3. No column accesses are allowed to be in progress at the time power-down is entered.

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 512Mb: x4, x8, x16 DDR SDRAM
Timing Diagrams

Figure 47: Auto Refresh Mode

T0 T1 T2 T3 T4 Ta0 Ta1 Tb0 Tb1 Tb2

(( ((
CK# )) ))
(( ((
CK )) ))
tIS tIH CK tCH tCL
(( ((
)) ))
CKE VALID (( (( VALID
tIS tIH )) ))
(( ((
)) ))
COMMAND1 NOP 2 PRE NOP2 NOP2 AR NOP2, 3 AR 6 NOP2, 3 NOP2 ACT
(( ((
)) ))

(( ((
)) ))
A0-A9, RA
(( ((
A11, A121 )) ))
ALL BANKS (( ((
)) ))
A101 RA
(( ((
ONE BANK )) ))

tIS tIH
(( ((
)) ))
BA0, BA11 Bank(s)4 BA
(( ((
)) ))

(( ((
DQS5 )) ))
(( ((
)) ))
(( ((
)) ))
DQ5
(( ((
)) ))
(( ((
)) ))
DM5 (( ((
)) ))
tRP tRFC tRFC5

DON’T CARE

Notes: 1. PRE = PRECHARGE, ACT = ACTIVE, AR = AUTO REFRESH, RA = Row Address, BA = Bank
Address.
2. NOP commands are shown for ease of illustration; other valid commands may be possible
at these times. CKE must be active during clock positive transitions.
3. NOP or COMMAND INHIBIT are the only commands allowed until after tRFC time, CKE
must be active during clock positive transitions.
4. “Don’t Care” if A10 is HIGH at this point; A10 must be HIGH if more than one bank is
active (i.e., must precharge all active banks).
5. DM, DQ, and DQS signals are all “Don’t Care”/High-Z for operations shown.
6. The second AUTO REFRESH is not required and is only shown as an example of two back-
to-back AUTO REFRESH commands.

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512MBDDRx4x8x16_2.fm - Rev. K 6/06 EN 87 ©2000–2005 Micron Technology, Inc. All rights reserved.
 512Mb: x4, x8, x16 DDR SDRAM
Timing Diagrams

Figure 48: Self Refresh Mode

T0 T11 Ta01 Ta1 Ta2 Tb1 Tb2 Tc1

(( (( ((
CK# )) ))
))
CK1 ((
)) ((
((
tCH tCL tCK ))
))
tIS tIH tIS t IS (( ((
)) ))
CKE (( (( ((
)) )) ))
tIS tIH
(( (( ((
)) ))
COMMAND2 NOP AR ))
NOP NOP
((
VALID3 VALID VALID
(( ((
)) )) ))
tIS tIH
(( (( ((
)) )) ))
ADDR (( ((
VALID VALID VALID
((
)) )) ))

(( (( ((
)) )) ))
DQS
(( (( ((
)) )) ))
(( (( ((
)) )) ))
DQ (( ((
((
)) )) ))

(( ((
(( )) ))
DM ))
((
((
(( )) ))
))

tRP4 tXSNR5

tXSRD6

DON’T CARE
Enter Self Refresh Mode7 Exit Self Refresh Mode7
Notes: 1. Clock must be stable until after the SELF REFRESH command has been registered. A change
in clock frequency is allowed before Ta0, provided it is within the specified tCK limits.
Regardless, the clock must be stable before exiting self refresh mode. That is, the clock
must be cycling within specifications by Ta0.
2. NOPs are interchangeable with DESELECT commands, AR = AUTO REFRESH command.
3. Auto refresh is not required at this point, but is highly recommended.
4. Device must be in the all banks idle state prior to entering self refresh mode.
5. tXSNR is required before any non-READ command can be applied. That is only NOP or
DESELECT commands are allowed until Tb1.
6. tXSRD (200 cycles of a valid clock with CKE = HIGH) is required before any READ command
can be applied.
7. As a general rule, any time self refresh mode is exited, the DRAM may not re-enter the self
refresh mode until all rows have been refreshed via the AUTO REFRESH command at the
distributed refresh rate, tREFI, or faster. However, the following exception is allowed. Self
refresh mode may be re-entered anytime after exiting, if the following conditions are all
met:
A. The DRAM had been in the self refresh mode for a minimum of 200ms prior to exit-
ing.
B. tXSNR and tXSRD are not violated.
C. At least two AUTO REFRESH commands are performed during each tREFI interval
while the DRAM remains out of self refresh mode.
8. If the clock frequency is changed during self refresh mode, a DLL reset is required upon
exit.
9. Once the device is initialized, VREF must always be powered within specified range.

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512MBDDRx4x8x16_2.fm - Rev. K 6/06 EN 88 ©2000–2005 Micron Technology, Inc. All rights reserved.
 512Mb: x4, x8, x16 DDR SDRAM
Timing Diagrams

Figure 49: Bank Read – Without Auto Precharge

T0 T1 T2 T3 T4 T5 T5n T6 T6n T7 T8
CK#
CK
tIS tIH tCK tCH tCL

CKE
tIS tIH

COMMAND5 NOP6 ACT NOP6 READ2 NOP6 PRE7 NOP6 NOP6 ACT

tIS tIH

x4: A0–A9, A11, A12

x8: A0–A9, A11 RA Col n RA
x16: A0–A9

x8: A12
x16: A11, A12 RA RA
tIS tIH
ALL BANKS
A10 RA 3 RA
ONE BANK

tIS tIH

BA0, BA1 Bank x Bank x Bank x4 Bank x

tRCD CL = 2

tRAS7 tRP

tRC

DM

tDQSCK (MIN)
Case 1: tAC (MIN) and tDQSCK (MIN)
tRPST
tRPRE
DQS
tLZ (MIN)

DO
DQ1 n

tLZ (MIN)
tAC (MIN)

tDQSCK(MAX)
Case 2: tAC (MAX) and tDQSCK (MAX)
tRPRE tRPST

DQS

DQ1 DO
n

tAC (MAX) tHZ (MAX)

DON’T CARE TRANSITIONING DATA

Notes: 1. DOn = data-out from column n; subsequent elements are provided in the programmed
order.
2. BL = 4 in the case shown.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T5.
5. PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address.
6. NOP commands are shown for ease of illustration; other commands may be valid at these
times.
7. The PRECHARGE command can only be applied at T5 if tRAS minimum is met.
8. Refer to Figure 40 on page 80, Figure 41 on page 81, and Figure 42 on page 82 for
detailed DQS and DQ timing.

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 512Mb: x4, x8, x16 DDR SDRAM
Timing Diagrams

Figure 50: Bank Read – With Auto Precharge

T0 T1 T2 T3 T4 T5 T5n T6 T6n T7 T8
CK#
CK
tIS tIH tCK tCH tCL

CKE
tIS tIH

COMMAND4 NOP5 ACT NOP5 READ2,6 NOP5 NOP5 NOP5 NOP5 ACT

tIS tIH
x4: A0–A9, A11, A12
x8: A0–A9, A11 RA Col n RA
x16: A0–A9

x8: A12
x16: A11, A12 RA RA

3
A10 RA tIS tIH RA

IS IH

BA0, BA1 Bank x Bank x Bank x

tRCD, tRAP6 CL = 2

tRAS tRP7

tRC

DM

Case 1: tAC (MIN) and tDQSCK (MIN) tDQSCK (MIN)

tRPST
tRPRE
DQS
tLZ(MIN)

DO
DQ1 n

tLZ (MIN)
tAC (MIN)

Case 2: tAC (MAX) and tDQSCK (MAX)

tDQSCK (MAX)

tRPRE tRPST

DQS

DQ1 DO
n

tAC (MAX) tHZ (MAX)

DON’T CARE TRANSITIONING DATA

Notes: 1. DOn = data-out from column n; subsequent elements are provided in the programmed
order.
2. BL = 4 in the case shown.
3. Enable auto precharge.
4. ACT = ACTIVE, RA = Row Address, BA = Bank Address.
5. NOP commands are shown for ease of illustration; other commands may be valid at these
times.
6. The READ command can only be applied at T3 if tRAP is satisfied at T3.
7. tRP starts only after tRAS has been satisfied.
8. Refer to Figure 40 on page 80, Figure 41 on page 81, and Figure 42 on page 82 for
detailed DQS and DQ timing.

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 512Mb: x4, x8, x16 DDR SDRAM
Timing Diagrams

Figure 51: Bank Write – Without Auto Precharge

T0 T1 T2 T3 T4 T4n T5 T5n T6 T7 T8
CK#
CK
tIS tIH tCK tCH tCL

CKE
tIS tIH

COMMAND5 NOP6 ACT NOP6 WRITE2 NOP6 NOP6 NOP6 NOP6 PRE

tIS tIH
x4: A0–A9, A11, A12
x8: A0–A9, A11 RA Col n
x16: A0–A9

x8: A12
x16: A11, A12 RA

tIS tIH
ALL BANKS
A10 RA 3
ONE BANK
tIS tIH

BA0, BA1 Bank x Bank x Bank x4

tRCD tWR

tRAS tRP

tDQSS (NOM)

DQS

tWPRES tWPRE tDQSL tDQSH tWPST

DI
DQ1 b

DM

tDS tDH
DON’T CARE TRANSITIONING DATA

Notes: 1. DIn = data-in from column n; subsequent elements are provided in the programmed order.
2. BL = 4 in the case shown.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T8.
5. PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address.
6. NOP commands are shown for ease of illustration; other commands may be valid at these
times.
7. See Figure 43, ”Data Input Timing” on page 82 for detailed DQ timing.

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512MBDDRx4x8x16_2.fm - Rev. K 6/06 EN 91 ©2000–2005 Micron Technology, Inc. All rights reserved.
 512Mb: x4, x8, x16 DDR SDRAM
Timing Diagrams

Figure 52: Bank Write – With Auto Precharge

T0 T1 T2 T3 T4 T4n T5 T5n T6 T7 T8
CK#
CK
tIS tIH tCK tCH tCL

CKE
tIS tIH

COMMAND4 NOP5 ACT NOP5 WRITE2 NOP5 NOP5 NOP5 NOP5 NOP5

tIS tIH

x4: A0–A9, A11, A12 RA Col n

x8: A0–A9, A11
x16: A0–A9

x8: A12 RA
x16: A11, A12
3

A10 RA tIS tIH

tIS tIH

BA0, BA1 Bank x Bank x

tRCD tWR

tRAS tRP

tDQSS (NOM)

DQS

tWPRES tWPRE tDQSL tDQSH tWPST

DI
DQ1 b

DM

tDS tDH
DON’T CARE TRANSITIONING DATA

Notes: 1. DIn = data-out from column n; subsequent elements are provided in the programmed
order.
2. BL = 4 in the case shown.
3. Enable auto precharge.
4. ACT = ACTIVE, RA = Row Address, BA = Bank Address.
5. NOP commands are shown for ease of illustration; other commands may be valid at these
times.
6. See Figure 43 on page 82 for detailed DQ timing.

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512MBDDRx4x8x16_2.fm - Rev. K 6/06 EN 92 ©2000–2005 Micron Technology, Inc. All rights reserved.
 512Mb: x4, x8, x16 DDR SDRAM
Timing Diagrams

Figure 53: Write – DM Operation

T0 T1 T2 T3 T4 T4n T5 T5n T6 T7 T8
CK#
CK
tIS tIH tCK tCH tCL

CKE
tIS tIH

COMMAND5 NOP6 ACT NOP6 WRITE2 NOP6 NOP6 NOP6 NOP6 PRE

tIS tIH

x4: A0–A9, A11, A12

x8: A0–A9, A11 RA Col n
x16: A0–A9

x8: A12 RA
x16: A11, A12
tIS tIH
ALL BANKS
A10 RA 3
ONE BANK
tIS tIH

BA0, BA1 Bank x Bank x Bank x4

tRCD tWR

tRAS tRP

tDQSS (NOM)

DQS

tWPRES tWPRE tDQSL tDQSH tWPST

DI
DQ1 b

DM

tDS tDH

DON’T CARE TRANSITIONING DATA

Notes: 1. DIn = data-in from column n; subsequent elements are provided in the programmed order.
2. BL = 4 in the case shown.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T8.
5. PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address.
6. NOP commands are shown for ease of illustration; other commands may be valid at these
times.
7. See Figure 43 on page 82 for detailed DQ timing.

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512MBDDRx4x8x16_2.fm - Rev. K 6/06 EN 93 ©2000–2005 Micron Technology, Inc. All rights reserved.
 512Mb: x4, x8, x16 DDR SDRAM
Package Dimensions

Package Dimensions
Figure 54: 66-Pin Plastic TSOP (400 mil)

SEE DETAIL A
22.22 ± 0.08
0.71
0.65 TYP
0.10 (2X)

0.32 ± .075 TYP

11.76 ±0.10

10.16 ±0.08

PIN #1 ID +0.03
0.15 -0.02
GAGE PLANE
0.25

+0.10
0.10
-0.05
0.10
0.80 TYP
1.20 MAX
0.50 ±0.10

DETAIL A

Notes: 1. All dimensions are in millimeters.

2. Package width and length do not include mold protrusion; allowable mold protrusion is
0.25mm per side.

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512MBDDRx4x8x16_2.fm - Rev. K 6/06 EN 94 ©2000–2005 Micron Technology, Inc. All rights reserved.
 512Mb: x4, x8, x16 DDR SDRAM
Package Dimensions

Figure 55: 60-Ball FBGA (10 x 12.5mm)

0.85 ±0.05

SEATING PLANE

0.10 C C
SOLDER BALL MATERIAL:
62% Sn, 36% Pb, 2% Ag OR
96.5% Sn, 3% Ag, 0.5% Cu
SOLDER BALL PAD: Ø .33
6.40 NON SOLDER MASK DEFINED
60X Ø .45 SUBSTRATE: PLASTIC LAMINATE
0.80 (TYP) MOLD COMPOUND: EPOXY NOVOLAC
SOLDER BALL DIAMETER
1.80 BALL A1
REFERS TO POST REFLOW
CTR BALL A1 ID
CONDITION. THE PRE-REFLOW
DIAMETER IS Ø 0.40.
1.00
TYP BALL #1 ID
BALL A9
6.25 ±0.05

11.00 CL
12.50 ±0.10
5.50 ±0.05

CL

3.20 ±0.05 5.00 ±0.05

1.20 MAX
10.00 ±0.10

Notes: 1. All dimensions are in millimeters.

2. Topside part marking decoder can be found at www.micron.com/decoder.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range
for production devices. Although considered final, these specifications are subject to change, as further product
development and data characterization sometimes occur.

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512MBDDRx4x8x16_2.fm - Rev. K 6/06 EN 95 ©2000–2005 Micron Technology, Inc. All rights reserved.
 Intel® Embedded Flash Memory (J3 v. D) - Technical Documents

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Documentation AP-846 Migration Guide for Intel StrataFlash® Synchronous Memory (K3) to
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AP 835 - Intel StrataFlash® Memory (J3) to Intel® Embedded Flash Memory
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(J3 v. D) Conversion Guide

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Intel® Embedded Flash Memory (J3 v. D) (32, 64, and 128 Mbit) Datasheet

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256Mb Intel StrataFlash® Memory (J3) to Intel StrataFlash® Memory (P30)

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Intel® Embedded Flash Memory (J3 v. D) (32, 64, and 128 Mbit)
Specification Update

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http://www.intel.com/design/flcomp/products/j3d/techdocs.htm06/03/2007 4:09:58 PM
 Intel® Embedded Flash Memory (J3 v. D) (32, 64, and 128 Mbit) Datasheet

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Intel® Embedded Flash Memory (J3 v. D) (32, 64, and 128 Mbit) Datasheet

This document contains information pertaining to the Intel® Embedded Flash Memory (28FxxxJ3D) device features, operation, and
specifications.

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http://www.intel.com/design/flcomp/datashts/308551.htm06/03/2007 4:10:53 PM