EE-421: Digital System Design

Course Introduction
&
Logistics

Instructor: Dr. Rehan Ahmed [rehan.ahmed@seecs.edu.pk]

DSD Course Placement and Importance

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 Recall: Digital Hardware/System Hierarchy
• Logic circuits are used to build computer hardware, as
well as many other types of products:
– All such products are broadly classified as digital hardware

Digital System/Hardware

datapath control

code state combinational

multiplexer comparator
registers registers logic

register logic

switching
networks
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 Did you build Digital Hardware Before?
• Your DLD Labs

• MPS Assignments

What’s limiting in this approach?

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Your Digital Circuits from DLD

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Your Digital Circuits from DLD

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Your Digital Circuits from DLD

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 Computing Platforms for Digital Systems

Application Specific
Microprocessor and Integrated Circuit [ASIC]
Microcontroller
Field Programmable
Gate Array [FPGA]

Graphics Crefit: Prof. Onur Mutlu, SAFARI ETH 8

 They All Look the Same
Microprocessors FPGAs ASICs

In short: Common building Reconfigurable You customize

block of computers hardware, flexible everything

Slide Credit: Prof. Onur Mutlu, SAFARI ETH 9

 They All Look the Same
Microprocessors FPGAs ASICs

In short: Common building Reconfigurable You customize

block of computers hardware, flexible everything
Program minutes days months
Development Time
Performance o + ++

Slide Credit: Prof. Onur Mutlu, SAFARI ETH 10

 They All Look the Same
Microprocessors FPGAs ASICs

In short: Common building Reconfigurable You customize

block of computers hardware, flexible everything
Program minutes days months
Development Time
Performance o + ++
Good for Ubiquitous Prototyping Mass production,
Simple to use Small volume Max performance

Slide Credit: Prof. Onur Mutlu, SAFARI ETH 11

 They All Look the Same
Microprocessors FPGAs ASICs

In short: Common building Reconfigurable You customize

block of computers hardware, flexible everything
Program minutes days months
Development Time
Performance o + ++
Good for Ubiquitous Prototyping Mass production,
Simple to use Small volume Max performance
Programming Executable file Bit file Design masks
Languages C/C++/Java/… Verilog/VHDL Verilog/VHDL
Main Companies Intel, ARM, AMD Xilinx, Intel (Altera), TSMC, UMC, ST,
Lattice, Microsemi Globalfoundries

Slide Credit: Prof. Onur Mutlu, SAFARI ETH 12

 Course Goal and Game Plan
Microprocessors FPGAs WantASICs
to
build Digital
Hardware
By
programming
these
In short: Common building Reconfigurable You customize
block of computers hardware, flexible everything
Program minutes days months
Development Time
Performance o + ++
Good for Ubiquitous Prototyping Mass production,
Simple to use Small volume Max performance
Using this language
Programming Executable file Bit file Design masks
Languages C/C++/Java/… Verilog Verilog
Main Companies Intel, ARM, AMD Xilinx, Altera, Lattice TSMC, UMC, ST,
Globalfoundries

Slide Credit: Prof. Onur Mutlu, SAFARI ETH 13

What this Course is About: Bird’s-Eye View

Overall, this course is about the art of designing

digital circuits using modern CAD-tool-based methods.

Broad topics include, but not limited to:

• FPGA architecture
• Describing hardware using Verilog (Synthesis
focused)
• Combinational and Sequential design
• Key logic elements such as storage,
clocks, and memory
• How to implement finite state machines
in circuitry
• Designing circuits to perform arithmetic
calculations
• Building complex designs from multiple
functions and FPGA IP
• Power-Performance-Area (PPA)
• Bus Architecture(s)
• FPGA System-on-Chip (SoC) [Soft + Hard up]
• Case Designs + Case Studies

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 Some Goals of This Course
◼ Teach/enable/empower you to:

❑ Understand the principles of digital design

❑ Learn how digital systems are designed using HDL

❑ Learn to systematically design increasingly complex digital

designs

❑ Understand how to analyze and make tradeoffs in a

digital design

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 What Do I Expect From You?
• Required background in Digital Logic Design course:
– Fundamentals concepts in classical manual digital design:
▪ Truth tables
▪ Logic gates and networks
– Synthesis using universal gates
– SOP and POS
▪ Logic Optimization
– Boolean algebra
▪ Target implementation platform:
– Digital IC 7400-series
▪ Combinatorial Logic
▪ Sequential Logic
▪ State Machines
Though manual techniques are not used for complex
designs,
– but grips on fundamentals give an intuitive feeling for how
digital circuits operate

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 What Do I Expect From You?
• Enthusiasm, Dedication and Honesty!!!

• How you prepare and manage your time is very

important !!!

• There will be heavy assignments:

– They will take time
– Start early, work hard

• This will be a heavy course

– However, you will learn a lot of fascinating topics

– And, it will hopefully change how you look at and think

about designs around you

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 Lastly, What Do I Expect From You?

• Learn the material thoroughly

– attend lectures, do the readings, do the exercises, do the
labs
• Work hard: this will be a hard but fun & informative course
• Ask questions, take notes, participate
• Perform the assigned readings
• Come to class on time
• Start early – do not procrastinate
• If you want feedback, come to office hours

• Remember “Chance favors the prepared mind.”

(Pasteur)

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 Course Logistics
• Lectures:
– Wednesday
▪ 11am-12:50pm in CR-18 IAEC
– Thursday (Gp-01 & Gp-02 Combined):
▪ 12pm-12:50pm in in CR-18 IAEC
– Course Website: http://lms.nust.edu.pk/
▪ Lecture Updates: After every lecture or by the end of week

• Labs:
– Please refer to the timetable

• Office Hours:
– By appointment only:
▪ send me an email at rehan.ahmed@seecs.edu.pk

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 Text and Support Books
- [main] Digital System Design with Verilog HDL, 3/e, b
Stephen Brown and Zvonko Vranesic. [S&Z]

• [ref] Digital Design and Computer Architecture, 2/e, by

Harris and Sarah. [H&S]

• [ref] Introduction to Computing Systems, Yale. N Patt &

SanjayJ. Patel. [P&P]

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 Tentative Grading Scheme
Type Weight (%)
Assignments 5-10
Quizzes 5-10
MSE 20-30
Labs 10-15
Project 10-15
Final 35-50

• This scheme *will* be adjusted during the semester!

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 Course Discipline: Ground Rules
• Classroom Etiquettes:
– Students will be punctual for the class.
▪ No attendance if you are late more than 5 mins.

– If a student decides to attend the class, he or she will not disrupt

class by leaving before the lecture has ended.

– All the cell phones must be switched OFF prior to entering the
class room.

• Academic Honesty and Plagiarism: [Both in Class and Labs]

– Plagiarism is considered a serious offence by the university and
severe penalties apply.
– ZERO tolerance. Subject activity will be nullified.

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 Recommended Reading
• S&Z, Chapter-1 and 2.9

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THANK YOU