North South University
Department of Electrical and Computer Engineering
CSE 231L: Digital Logic Design Lab
Lab 02: Combinational Logic Design
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A. Objectives
Familiarize with the analysis of combinational logic network.
Learn the implementation of networks using the two canonical forms.
Devise combinational circuits using universal logic.
Acquaint with basic binary arithmetic circuits –the half and full adders.
B. Theory
Concise theory pertinent to lab experiments to go here to aid students in performing experiments with minimal
supervision. For example, topics for this lab should include definition and steps to:
Analysis of combinational logic design Min terms and max terms
Canonical Forms
Universal gates – bubble pushing, De Morgan’s theorem.
C. Experiment 1: Analysis of a Combinational Logic Circuit
C.1. Equipments:
Trainer Board
1 x IC 7411 Triple 3-input AND gates
1 x IC 7432 Quadruple 2-input OR gates
1 x IC 7404 Hex Inverters (NOT gates)
C.2. Procedure
Input
ࡲ Min term Max term
Reference
0 000 0
1 001 1
2 010 1
3 011 0
4 100 0
5 101 0
6 110 1
7 111 0
Table C.1 Truth table to a combinational circuit
1. Write down all the min terms and max terms of three inputs ܥܤܣin Table C.1.
st nd
2. Write down the function ܨin 1 and 2 Canonical Forms in Table C.2.
Shorthand Notation Function
st
1 Canonical
Form ܨൌȭ ܨൌ
nd
2 Canonical
Form ܨൌȫ ܨൌ
st nd
Table C.2 1 and 2 canonical forms of the combinational circuit of Table C.1
3. Draw the circuits in the space provided below, clearly indicating the pin numbers corresponding to the relevant
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ICs.
st
1 Canonical Form
nd
2 Canonical Form
st nd
Figure C.1 1 and 2 canonical circuit diagrams of the combinational circuit of Table C.1
st
4. Construct the 1 canonical form of the circuit and test it with the truth table.
i. Connect one min term at a time and check its output.
ii. Once all min terms have been connected and verified, OR the min terms for the function output.
C.3. Report
st nd
Simulate above two circuits (1 and 2 canonical forms) in Logisim.
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