8086 Microprocessor

The 8086 is a 16-bit microprocessor. The term 16 bit implies that its arithmetic logic unit, its
internal registers, and most of its instructions are intended to work with 16-bit binary data.
The 8086 has a 16-bit data bus, so it can read data from or write data to memory and ports
either 16 bits or 8 bits at a time. The 8086 has a 20-bit address bus, so it can address any one
of 220, or 1,048,576 memory locations.

Fig: Functional Block Diagram (Architecture) of Intel 8086 microprocessor

Bus Interface Unit (BIU): It handles all transfers of data and addresses on the buses for the
execution unit.

Sends out addresses

Fetches instructions from memory
Read / write data from/to ports and memory i.e. handles all transfers of data and
addresses on the busses

The QUEUE:

When EU is decoding or executing an instruction, bus will be free at that time. BIU pre-
fetches up to 6-instructions bytes to be executed and places them in QUEUE. This
improves the overall speed because in each time of execution of new instruction, instead

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Compiled by: Er. Yuyutshu Banjara
 of sending address of next instruction to be executed to the system memory and waiting
from the memory to send back the instruction byte, EU just picks up the fetched
instruction byte from the QUEUE.

The BIU stores these pre-fetched bytes in a first-in-first-out (FIFO) register set called a
queue. Fetching the next instruction while the current instruction executes is called
pipelining.

Segment Registers:

The BIU contains a dedicated address, which is used to produce the 20-bit address. The bus
control logic of the BIU generates all the bus control signals, such as the READ and WRITE
signals, for memory and I/O. The BIU also has four 16 bit segments registers namely:

Code segment (CS): holds the upper 16-bits of the starting addresses of the segment
from which BIU is currently fetching instruction code bytes.
Stack segment (SS): store addresses and data while subprogram executes
Extra segment (ES): store upper 16-bits of starting addresses of two memory
segments that are used for data.
Data segment(DS): store upper 16-bits of starting addresses of two memory
segments that are used for data.

Code Segment Register (CS) and Instruction Pointer (IP)

All program instructions located in memory are pointed using 16 bits of segment
register CS and 16 bits offset contained in the 16-bit instruction pointer (IP). The BIU
computes the 20-bit physical address internally using the logical address that is the
contents of CS and IP. 16 bit contents of CS will be shifted 4 bits to the left and then
adding the 16 bit contents of IP. Thus, all instructions of the program are relative
contents of IP. Simply stated, CS contains the base or start of the current code segment,
and IP contains the distance or offset from this address to the next instruction byte to
be fetched. Graphically,

Fig: Diagram showing addition of IP to CS to produce the physical address of code byte Stack
Segment Register (SS) and Stack Pointer (SP)

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 A stack is a section of memory to store addresses and data while a subprogram is in
progress. The stack segment registers points to the current stack. The 20-bit physical
stack address is calculated from the SS and SP. The programmer can also use Base
Pointer (BP) instead of SP for addressing. In this case, the 20-bit physical address is
calculated using SS and BP.

Execution Unit (EU)

Tells BIU where to fetch instructions or data from
Decodes instructions
Executes instructions

Instruction Decoder & ALU:

Decoder in the EU translates instructions fetched from the memory into a series of
actions which the EU carries out.16-bit ALU in the EU performs actions such as AND,
OR, XOR, increment, decrement etc.

Flag Register:
It is a 16-bit register. 9-bit are used as different flags, remaining bits unused

Fig: 16-bit flag register

Out of 9-flags, six are conditional (status) flags and three are control flags

Conditional flags:
These are set or reset by the EU on the basis of the results of some arithmetic or logic
operation. 8086 instructions check these flags to determine which of two alternative
actions should be done in executing the instructions.

OF (Overflow flag): is set if there is an arithmetic overflow, i.e. the size of the
result exceeds the capacity of the destination location.
SF (Sign flag): is set if the MSB of the result is 1
ZF (Zero flag): is set if the result is zero
AF (Auxiliary carry flag): is set if there is carry from lower nibble to upper nibble
or from lower byte to upper byte
PF (Parity flag): is set if the result has even parity
CF (Carry flag): is set if there is carry from addition or borrow from subtraction

Control flags:
They are set using certain instructions. They are used to control certain operations of
the processor.

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 TF (Trap flag): for single stepping through the program
IF (Interrupt flag): to allow or prohibit the interruption of a program
DF (Direction flag): Used with string instructions

General purpose Registers

8 General purpose Registers AH, AL (Accumulator), BH, BL, CH, CL, DH, DL are
used to store 8-bit data.
AL register is also called the accumulator
Used individually for the temporary storage of data
General purpose Registers can be used together (as register pair) to store 16-bit data
words. Acceptable register pairs are:
AH-AL pair AX register

BH-BL pair BX register (to store the 16-bit data as well as the base address of the
memory location)

CH-CL pair CX register (to store 16-bit data and can be used as counter register for
some instructions like loop)

DH-DL pair DX register (to store 16-bit data and also used to hold the result of 16-
bit data multiplication and division operation)

Pointer and Index registers:

SP (Stack Pointer), BP (Base pointer), SI (Source Index), DI (Destination index)

Pointer Registers:
The two pointer registers, SP and BP are used to access data in the stack segment. The
SP is used as offset from current Stack Segment during execution of instruction that
involve stack. SP is automatically updated. BP contains offset address and is utilized in
based addressing mode. Overall, these are used to hold the offset address of the stack
address.

Index Registers:
EU also contains a 16-bit source index (SI) register and 16-bit destination index (DI)
register. These registers can be used for temporary storage of data similarly as the
general purpose registers. However, they are specially to hold the 16-bit offset of the
data word. SI and DI are used to hold the offset address of the data segment and extra
segment memory respectively.

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Addressing modes of 8086
The different ways in which a source operand is denoted in an instruction is known as
addressing modes. The different addressing modes in 8086 programming are:

1) Immediate Addressing mode:

Data required for executing the instruction is given directly along with the
instruction.
Example:

MOV AL, 78H

MOV CX, 234AH
ADD AL, 23H

2) Direct Addressing mode:

Data required for executing the instruction is present in the memory location and
the effective address of the memory location is given directly along with instruction.
Example:
MOV AL, [4371H] ; copies 16-bit word into a memory pointed by the
displacement address 4371H to the AL register.

3) Register Addressing mode:

Data required for executing the instruction is present in the register.
Example:

MOV AL, BL ; transfers the content of BL to AL register pair

MOV DX, BX ; transfers the content of BX to DX register pair

4) Register Indirect Addressing mode:

Data required for executing the instruction is present in the memory location and
effective address of this memory location is present in the base or index register
(BX, BP, SI or DI) along with instruction.
Example:

MOV AX, [BX] ; copies the word-sized data from data segment offset
address indexed by BX into AX

Suppose the register BX contains 4123H , then the contents 4123H are moved
to AX

5) Based (Register Relative) Addressing mode:

Data required for executing the instruction is present in the memory location and
effective address of this memory location is obtained by adding the displacement
value (i.e., 8 or 16-bits displacement) with BX/BP register value.
That means, in this addressing mode, the offset address of the operand is given by
the sum of contents of the BX/BP registers and 8-bit/16-bit displacement.
Example
MOV AX, [BX+04]

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6) Indexed Addressing mode:
In this addressing mode, the operands offset address is found by adding the contents
of SI or DI register and 8-bit/16-bit displacements.
Example:
MOV BX, [SI+04], ADD AL, [DI+16]

7) Based-Index (Base-Plus-Index) Addressing mode:

In this addressing modes, data required for executing the instruction is present in
the memory location and effective address of this memory location is obtained by
adding base register and index register value.
Example

MOV AX, [BX+SI]

MOV [BX+SI], CX

8) Based-Index with Displacement Addressing mode:

In this addressing mode, the operands offset is computed by adding the base register
contents. An Index registers contents and 8 or 16-bit displacement.
That means, data required for executing the instruction is present in the memory
location and effective address of this memory location is obtained by adding base
register, index register and 8 or 16-bit displacement.
Example:
MOV AX, [BX+DI+08]
MOV [BX+DI+16], CX

9) Implied (or implicit or Inherent) Addressing mode:

The data value/data address is implicitly associated with the instruction.
Example:
STC ; set carry flag
CLC ; clear (reset) carry flag
AAA ; ASCII adjust after addition

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Physical address calculation in 8086

20-bit physical address (actual address) of memory is generated by adding the segment address
and offset address (displacement value)

Let us consider:

CS= 1234 H
IP = 0022 H

Then,
Physical address = (Segment address x 10) + Offset address
= (1234 H x 10) + 0022 H
= 12340 H + 0022 H
= 12362 H

Note: Segment address is left shifted 4 times (4 bits) instead of multiplying by 10.

Fig: Physical address generation

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