ISSCC 2023 Tutorials

Digital Equalization and Timing Recovery Techniques for

ADC-DSP-based Highspeed Links

Masum Hossain (masumhossain@cunet.carleton.ca)

Masum Hossain T11: ADC-DSP-based Digital Equalization 1 of 108

© 2023 IEEE International Solid-State Circuits Conference

Self Introduction: Masum Hossain
 B.Sc. Bangladesh University of Science and
Technology,2002
 Ph.D. University of Toronto,2010
 2008 – 2013 in industry (Gennum, Rambus etc.)
 2013 – 2022 Associate Prof. at the University of
Alberta
 2022 – Present in Carleton University, Ottawa
 Award:
 Analog device’s Outstanding student designer award
2010
 Best student paper award Custom Integrated Circuits
Conference CICC-2008
 Best paper award IEEE Transaction in Components,
Packaging and Manufacturing, 2021

Masum Hossain T11: ADC-DSP-based Digital Equalization 2 of 108

© 2023 IEEE International Solid-State Circuits Conference

A Philosophical View of SerDes

 Public transport is a clean, low

cost, and fuel-efficient way to
move from place ‘A’ to place ‘B’
 Reduces 37 million metric tons of
carbon dioxide emission annually
in the US.

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© 2023 IEEE International Solid-State Circuits Conference

SerDes and High-speed Link

 In communication systems SerDes is an ‘Information Bus’ - a fast, speedy

and efficient way to transfer information from one ‘chip’ to another ‘chip’
 It is based on ‘time domain multiplexing’ where each unit interval ‘UI’ or ‘bit-
period’ is allocated to a channel.

Masum Hossain T11: ADC-DSP-based Digital Equalization 4 of 108

© 2023 IEEE International Solid-State Circuits Conference

Evolution of SerDes & High-speed Links
[G. Mogensen 1980] [Hitachi 2020]

[source YEA engineering]

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© 2023 IEEE International Solid-State Circuits Conference

Outline
 Motivation & background
 Evolution of timing recovery concepts from analog to digital
 Progression toward digital equalization for multilevel signaling
 Challenges in ADC-DSP receiver
 Effect of latency/delay in the timing recovery
 Effect of ‘ISI’ on data and timing recovery
 Advanced digital equalization
 MLSE: ISI-assisted decoding approach
 SNR Optimization strategy
 Example of MLSE Implementation
 Summary and future direction

Masum Hossain T11: ADC-DSP-based Digital Equalization 6 of 108

© 2023 IEEE International Solid-State Circuits Conference

 Recent Trend in High-speed Link

Analog-Mixed Signal Analog-Mixed Signal

Data Rate (Gb/s)

Data Rate (Gb/s)

ADC-DSP ADC-DSP

Year Gate length (nm)

 ADC-DSP solutions in recent years are being rapidly deployed at 56+ Gb/s
data rate in nanometer finFET technology
Masum Hossain T11: ADC-DSP-based Digital Equalization 7 of 108

© 2023 IEEE International Solid-State Circuits Conference

Source of Inter Symbol Interference (ISI)
0 0 1 0 0

1 UI = 100 ps @ 10 Gb/s

0 0 1 0 0

Channel Response (dB)

10 Gb/s

 Freq. dependent Loss  Dispersion 

Inter Symbol Interference (ISI) Noise

Frequency (GHz)
Masum Hossain T11: ADC-DSP-based Digital Equalization 8 of 108

© 2023 IEEE International Solid-State Circuits Conference

 Impact of ISI on Voltage Margin
Constellation
Channel response D[n]D[n-1] S[n]

h0+h1
h0
1 1 h0-h1
1 0
0 1 Decision threshold
h1
0 0
-h0+h1
-h0-h1

 Reduction in eye margin by the post cursor ISI (h1)

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© 2023 IEEE International Solid-State Circuits Conference

 Impact of ISI on Zero Crossing
Zero crossings
Channel response D[n]D[n-1] S[n-1] S[n]
h0+h1
h0
1 1 h0-h1
1 0
0 1
h1
0 0
-h0+h1
-h0-h1

 Due to ISI, the transition between them also causes

‘Data Dependent Jitter (DDJ)’

Masum Hossain T11: ADC-DSP-based Digital Equalization 10 of 108

© 2023 IEEE International Solid-State Circuits Conference

 ISI Impact with Random Data Pattern
Channel response

h0
Combines ‘Noise’
and ‘ISI’ PDFs can
extended to estimate
h1
achievable ‘BER’

 The ISI components are captured in the eye diagram and

reflected by the statistics
Masum Hossain T11: ADC-DSP-based Digital Equalization 11 of 108

© 2023 IEEE International Solid-State Circuits Conference

Inter Symbol Interference (ISI)

 ISI reduces voltage and timing margin,

meaning the tolerance to make correct
decisions in the presence of noise

Masum Hossain T11: ADC-DSP-based Digital Equalization 12 of 108

© 2023 IEEE International Solid-State Circuits Conference

Optimal Sampling for Data Detection and Jitter Tracking

Rx

CDR

 For data decision, we

should sample in the
middle of the eye –
Max SNR.
 For timing noise
Decision Conf.
tracking, we should
Arbitrary Unit

Signal slope
sample where the
slope is max.

Masum Hossain T11: ADC-DSP-based Digital Equalization 13 of 108

© 2023 IEEE International Solid-State Circuits Conference

Background on Clock and Data Recovery (CDR)

Rx

CDR
Data

Recovered
clock

 Basic functionality of CDR is to ‘recover’ and ‘track’

‘optimum’ sampling point from the given data sequence

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© 2023 IEEE International Solid-State Circuits Conference

CDR Tracking Bandwidth

Rx
HCDR

fCDR f

Data

Recovered
clock
 Within the tracking
bandwidth (fjitter << fCDR) Data Recovered clock
CDR can track several UI of zero crossing HCDR zero crossing

jitter without losing timing

margin high tolerance to time time
f
fCDR
jitter on the data sequence

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© 2023 IEEE International Solid-State Circuits Conference

CDR Tracking Bandwidth

Rx
HCDR

fCDR f

Data

Recovered
 Outside the tracking clock

bandwidth (fjitter >> fCDR) Data Recovered clock

CDR can only tolerate 0.5 zero crossing HCDR zero crossing

UI of Jitter
time time
f
fCDR

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© 2023 IEEE International Solid-State Circuits Conference

Jitter Tolerance of CDR

Rx
HCDR

fCDR f

|HCDR|

 Higher tracking bandwidth

makes it easier to meet jitter f
tolerance Mask fCDR

 At high frequencies theoretical 0.5

IJT =
limit of Input Jitter Tolerance 1-HCDR

(IJT) is 0.5 UI peak. However,

in reality, we can achieve ~ f
0.3 UI peak for NRZ.

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© 2023 IEEE International Solid-State Circuits Conference

Jitter Tolerance of CDR

Rx
HCDR

fCDR f

|HCDR|

 ‘Loop latency’ degrades phase

margin and causes ‘peaking’ f
fCDR
in the Jitter transfer
 ‘Peaking’ in the transfer IJT =
0.5
1-HCDR
function translates to ‘dip’ in
the jitter tolerance plot which f
may become an issue

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© 2023 IEEE International Solid-State Circuits Conference

Equalization
 How to make decisions in the presence of ISI 
‘Equalization’
 Pre-distortion using transmit FFE
 Continuous time ‘peaking’ equalizer Complexity
& performance
 Decision Feedback Equalizer (DFE)
 DSP-based digital equalization – FFE and DFE
 Maximum Likelihood Sequence Estimator (MLSE)
 Timing recovery in the presence of ISI 
 Edge equalization
 Data Dependent Jitter (DDJ) filter

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© 2023 IEEE International Solid-State Circuits Conference

Equalization with ‘Pre-distortion’  Tx FIR
0 0 1 0 0

 Based on prior knowledge transmitted signal can be distorted such

that the ISI components are ‘zero’ after the channel
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© 2023 IEEE International Solid-State Circuits Conference

Performance Improvement with Tx-FIR

w/o TX FIR (10 Gb/s) with TX FIR (10 Gb/s)

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© 2023 IEEE International Solid-State Circuits Conference

 Limitation of Tx FIR  Signal Amplitude Reduction

 Tx FIR is improving Signal to ISI ratio at

the cost of Signal to Noise Ratio (SNR)

w/o TX FIR (15 Gb/s) with TX FIR (15 Gb/s)

Channel Response (dB)

Frequency (GHz)

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© 2023 IEEE International Solid-State Circuits Conference

Alternative Approach: ‘Peaking Equalizer’ or CTLE

1 + s 
 ω z 
A = ADC  RL
CL
1 + s 1 + s 
 ω  ω 
 P1  P2 

M1

1
ωZ =
RC
gm 1 + gm R
ADC = g m −eff RL = RL ω P1 = 2
gm R RC
1+
2 1
ωP 2 =
RL C L

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© 2023 IEEE International Solid-State Circuits Conference

Performance of a ‘Peaking Equalizer’ or CTLE

1 + s 
 ω 
A = ADC  z

1 + s 1 + s 
 
ω P1  ω P 2 


w/o Eq (15 Gb/s) with Linear Eq (15 Gb/s)

Channel Response (dB)

 Peaking equalizer can boost the high-frequency

Frequency (GHz) component relatively less expensively.

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© 2023 IEEE International Solid-State Circuits Conference

Decision Feedback Equalization (DFE)

Single Bit Response with DFE @ 20 Gb/s

 DFE can compensate post-cursor ISI without

adding noise
 DFE is causal – so ‘only’ cancels post cursor
no ‘pre-cursor’ cancellation

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© 2023 IEEE International Solid-State Circuits Conference

Decision Feedback Equalization (DFE)+CTLE for 20 Gb/s

 Combination of DFE +
CTLE can achieve 20 Gb/s
compensating 20 dB Loss

20 Gb/s eye with Linear Eq + DFE

Channel Response (dB)

Frequency (GHz)

Masum Hossain T11: ADC-DSP-based Digital Equalization 26 of 108

© 2023 IEEE International Solid-State Circuits Conference

 Summary of Equalization Techniques

Tx FIR ‘only’ Tx FIR + CTLE Tx FIR + CTLE +DFE

Data rate: 10 Gb/s Data rate: 15 Gb/s Data rate: 20 Gb/s

Timing_Margin (ps) : 18.457 Timing_Margin (ps) : 20.2344 Timing_Margin (ps) : 21.4648
Voltage_Margin (mV) : 53 Voltage_Margin (mV) : 140 Voltage_Margin (mV) : 194

 Equalization fundamentals remain same between ‘analog’ and ‘digital’ domain

 These equalization techniques will be translated into the digital domain

Masum Hossain T11: ADC-DSP-based Digital Equalization 27 of 108

© 2023 IEEE International Solid-State Circuits Conference

Outline
 Motivation & background
 Evolution of timing recovery concepts from analog to digital
 Progression toward digital equalization for multilevel signaling
 Challenges in ADC-DSP receiver
 Effect of latency/delay in the timing recovery
 Effect of ‘ISI’ on data and timing recovery
 Advanced digital equalization
 MLSE: ISI-assisted decoding approach
 SNR optimization strategy
 Example of MLSE implementation
 Summary and future direction

Masum Hossain T11: ADC-DSP-based Digital Equalization 28 of 108

© 2023 IEEE International Solid-State Circuits Conference

Limitation of Analog CDR

Large loop filter capacitance is difficult to integrate

Leaky loop filter is a concern
Supply scaling makes charge pump design challenging
Requires additional frequency locking loop
VCO Supply noise sensitivity
Tradeoff between input Jitter and VCO phase noise filtering
Conventional analog CDRs are not portable and
difficult to scale

Masum Hossain T11: ADC-DSP-based Digital Equalization 29 of 108

© 2023 IEEE International Solid-State Circuits Conference

Evolution Towards Digital CDR

[Sontag’06]
Area efficient Noise less digital accumulator + DPC
Synthesizable and portable Less supply sensitivity

Masum Hossain T11: ADC-DSP-based Digital Equalization 30 of 108

© 2023 IEEE International Solid-State Circuits Conference

 Discrete Time Phase Accumulator
PFD
fREF CP+LF Q Direction of Rotation
Quad 2 Quad 1 I Q IB QB I
Dir. of

Phase
Rotation Q-clk
IB I PI clk
I-clk
Dig. Clk I Q Quad 3 Quad 4
QB
+1/ 0 /-1 Time
VDD

PI clk
OUTMIX
 DT Phase Accumulator = Digital accumulator + OUTBMIX
digital to Phase converter (Mixer) MUXI MUXIB MUXQ MUXQB

 Accumulator clock and phase step size set IMixer-I IMixer-Q

accumulation rate.

Masum Hossain T11: ADC-DSP-based Digital Equalization 31 of 108

© 2023 IEEE International Solid-State Circuits Conference

 Analog vs Digital CDR
A.Ong J.Kim L. Rodini
JSSC, 2003 JSSC, 2009 JSSC,2009
1.7 mm
Data Rate 40-43 Gb/s 39 Gb/s 6-44 Gb/s

Architecture PLL per Lane PLL per Lane Shared PLL

DLL per Lane
Technology 0.18 um 0.13 um CMOS 90nm CMOS
2.9 mm

BiCMOS
Power 7.5 W 2.04 W 0.230 W
(180 pJ/bit) (50pJ/bit) (5.74 pJ/bit)
(w/o CMU )
Area 1.7mm X 2 1.7mm x 0.57 mm x 0.32 mm
mm 2.9mm Digital Loop filter
Passive Loop Passive Loop
filter filter

Digital CDR enables 10x improvement in power and area

Masum Hossain T11: ADC-DSP-based Digital Equalization 32 of 108

© 2023 IEEE International Solid-State Circuits Conference

 Analog vs Digital CDR
40 Gb/s 40 Gb/s 6-44 Gb/s 4x40Gb/s
Analog CDR Analog CDR Digital CDR Digital CDR
0.18um BiCMOS 0.13 um CMOS 90 nm CMOS 28nm CMOS
Power 7.5 W 2.04 W 0.230 W 0.175 W
(180 pJ/bit) (50pJ/bit) (5.74 pJ/bit) (w/o
CMU)
Area 1.7mm X 2 mm 1.7mm x 2.9mm 0.57 mm x 0.32 mm 0.22 mm X 0.22um
Passive Loop filter Passive Loop filter Digital Loop filter Digital Loop filter
Jitter Tracking 40 MHz 20+ MHz 4 MHz or less 8 MHz
Bandwidth
Jitter Tolerance 0.3 UI 0.2 UI 0.15 UI @ 24 Gb/s 0.2 UI
0.1 UI @ 40 Gb/s
Frequency offset 2000 ppm 1000+ ppm 300 ppm @ 40 Gb/s 700 ppm
tracking
Scalability Poor (1/chip) Poor (1/chip) Excellent Excellent
(4 to 8 per chip) (4 to 8 per chip)

 Digital CDR bandwidth can improve significantly with technology scaling

 Frequency offset tracking can be improved with frac-N technique [M.Hossain’2014]
Masum Hossain T11: ADC-DSP-based Digital Equalization 33 of 108

© 2023 IEEE International Solid-State Circuits Conference

Outline
 Motivation & background
 Evolution of timing recovery concepts from analog to digital
 Progression toward digital equalization for multilevel signaling
 Challenges in ADC-DSP receiver
 Effect of latency/delay in the timing recovery
 Effect of ‘ISI’ on data and timing recovery
 Advanced digital equalization
 MLSE: ISI-assisted decoding approach
 SNR optimization strategy
 Example of MLSE implementation
 Summary and future direction

Masum Hossain T11: ADC-DSP-based Digital Equalization 34 of 108

© 2023 IEEE International Solid-State Circuits Conference

 Limitations in Mixed Signal Equalization

 Tx FIR Filter:  Peaking equalizer :  Decision Feedback Eq.:

 Modulation specific  Limited by gain-BW  Latency constrained
 Limited by supply voltage  Difficult for multilevel
 Limited configurability
signaling
 PVT variation

Existing equalization strategy does not scale well with technology, channel loss and data rate

Masum Hossain T11: ADC-DSP-based Digital Equalization 35 of 108

© 2023 IEEE International Solid-State Circuits Conference

Motivation for Multilevel Signaling

 2-bit information is
encoded in 1-UI
 2x improvement in
spectral efficiency
 3X reduction in
eye height

Masum Hossain T11: ADC-DSP-based Digital Equalization 36 of 108

© 2023 IEEE International Solid-State Circuits Conference

 ISI Impact NRZ vs PAM-4
h0 S[n-1] S[n]
Channel response PAM-4
+3
h1 ISI Impact is 3X in PAM-4
compared to NRZ

+1
S[n-1] S[n]
NRZ
+1
-1

Eye-opening -3

-1

Masum Hossain T11: ADC-DSP-based Digital Equalization 37of 108

© 2023 IEEE International Solid-State Circuits Conference

LR Channel Characteristics
 LR channel exhibits
significant pre-cursor
ISI and post-cursor
ISI tail

Channel
37.5 Response
dB Loss Single Bit Response (SBR)
@ 28 GHz
-37.5 dB @ 28 GHz

Frequency Time (sec)

Masum Hossain T11: ADC-DSP-based Digital Equalization 38 of 108

© 2023 IEEE International Solid-State Circuits Conference

 Equalization Consideration
 TxFIR + CTLE can
somewhat flatten the
channel response but still
leaves residue ISI  need
more EQ in DSP domain

TxFIR
Frequency Response (dB)

Channel Single Bit Response

(Channel only)
Channel+TxFIR+CTLE
Channel+TxFIR
Single Bit Response
(Channel + TxFIR + CTLE)

Frequency (normalized to baud rate) Time (second)

Masum Hossain T11: ADC-DSP-based Digital Equalization 39 of 108

© 2023 IEEE International Solid-State Circuits Conference

NRZ vs PAM4 Performance with Analog EQ
 PAM4 is 3x more susceptible
to residual ISI
 Compared to NRZ, PAM-4
requires much more precise
ISI cancellation

NRZ PAM4

Single Bit Response

(Channel only)

Single Bit Response

(Channel + TxFIR + CTLE)

Time (second)
Masum Hossain T11: ADC-DSP-based Digital Equalization 40 of 108

© 2023 IEEE International Solid-State Circuits Conference

ADC-DSP PAM4 Receiver w/ Digital FFE
 DSP is effective in eliminating
residue ISI through precise
control of freq. response.
Noise can be amplified as well.

Before DSP EQ

Sampled SBR
after CTLE
Freq response of DSP FFE

Sampled DSP
h.f. boost
FFE Response After DSP EQ

Sampled SBR
after FFE-only DSP

Masum Hossain T11: ADC-DSP-based Digital Equalization 41 of 108

© 2023 IEEE International Solid-State Circuits Conference

Recent Trend – Transition to ADC-DSP
Analog-Mixed Signal
ADC-DSP

Channel loss (dB)

[S. Mirabbasi ‘2022] Data Rate (Gb/s)

 Data converter speed and performance are progressively improving

 ADC-DSP solutions have compensated higher-loss compared to mixed signal
solutions

Masum Hossain T11: ADC-DSP-based Digital Equalization 42 of 108

© 2023 IEEE International Solid-State Circuits Conference

Analog Tx FIR to DSP-DAC

 Number of Tap values  Move equalization to DSP

tied to the number of domain for added flexibility in
driver segments terms of # of taps and
modulations

Masum Hossain T11: ADC-DSP-based Digital Equalization 43 of 108

© 2023 IEEE International Solid-State Circuits Conference

 DSP based Tx FIR

4 levels
Without
Equalization

hmain 7 bit
DAC

• LUT for each tap

– Each LUT has 4 entries corresponding to the PAM4
symbols

Masum Hossain T11: ADC-DSP-based Digital Equalization 44 of 108

© 2023 IEEE International Solid-State Circuits Conference

 DSP based Tx FIR
Values are + and - stored as
2’s compliment, can use a
simple adder

Z-1 hmain 8 bit 7 bit

DAC

Z-1 hpost,1

hpost,N 8 bit
Z-1

Masum Hossain T11: ADC-DSP-based Digital Equalization 45 of 108

© 2023 IEEE International Solid-State Circuits Conference

 DSP based Tx FIR
Values are + and - stored as
hpre,N
2’s compliment, can use a
simple adder
Z-1
8 bit

hpre,1
Z-1

Z-1 hmain 8 bit 7 bit

DAC

Z-1 hpost,1

hpost,N 8 bit
Z-1

Masum Hossain T11: ADC-DSP-based Digital Equalization 46 of 108

© 2023 IEEE International Solid-State Circuits Conference

 DSP based Tx FIR
Values are + and - stored as
hpre,N
2’s compliment, can use a
simple adder
Z-1
8 bit

hpre,1
Z-1

Z-1 hmain 8 bit 7 bit

DAC

Z-1 hpost,1

8 bit
Add an offset value in all pre2
hpost,N
Z-1
entries to re-center to 0-127

Offset
Masum Hossain T11: ADC-DSP-based Digital Equalization 47 of 108

© 2023 IEEE International Solid-State Circuits Conference

Example of DSP DAC Transmitter
[E. Groen’ 2022]
Components Power
(mW)
Driver 15

Pre-driver 17

Level shifter+2:1 mux 20

Serializer 11
DSP based TxFIR 15
Clock buffer, DCD 40
Tx PLL 45
Bias circuit 5
Amortized global clocking 48/4 = 12
Total 175 mW

 DSP part of the transmitter power is progressively reducing with technology scaling

Masum Hossain T11: ADC-DSP-based Digital Equalization 48 of 108

© 2023 IEEE International Solid-State Circuits Conference

112Gb/s Transmitter Measurements

 Peak-to-peak swing is 1.2Vdpp

Masum Hossain T11: ADC-DSP-based Digital Equalization 49 of 108

© 2023 IEEE International Solid-State Circuits Conference

Example of 224 Gb/s DSP-DAC Tx
[J. KIM’ 2022]

 DSP DAC based Architecture impressively scales beyond 200 Gb/s

 Significant part of the power is consumed in clocking and serialization

Masum Hossain T11: ADC-DSP-based Digital Equalization 50 of 108

© 2023 IEEE International Solid-State Circuits Conference

Example of DSP-DAC based Transmitter

[T. Dickson’ 2022]

 4nm implementation
Achieves 200+ Gb/s data-
rate with flexibility of
modulation from PAM to
OFDM

Masum Hossain T11: ADC-DSP-based Digital Equalization 51 of 108

© 2023 IEEE International Solid-State Circuits Conference

High-speed signal path

 The Tx-FIR and CTLE only partially compensate for the loss – ‘eye’ will remain closed

Masum Hossain T11: ADC-DSP-based Digital Equalization 52 of 108

© 2023 IEEE International Solid-State Circuits Conference

Introduction to Rx FFE

 The objective is to combine the

shifted pulse responses with
appropriate weighting factors to
bring the response to a ‘single
tap’  ISI-free response

Masum Hossain T11: ADC-DSP-based Digital Equalization 53 of 108

© 2023 IEEE International Solid-State Circuits Conference

ADC Examples
 SAR ADC  Two-step sub-ranging ADC
 64 x 0.875 = 56 GS/s, time-interleaved  16 x 3.5 GS/s = 56 GS/s, time-interleaved
 6-bit or 7-bit ADC  7-bit ADC = 3-bit coarse + 4-bit fine
[J. Hudner’2018]
 Only 12 comparators based on the
interpolation technique described in [J. Kim’
2015]
[H, Lin ‘2021]
ICAL : initial calibration
PCAL : periodic calibration

Masum Hossain T11: ADC-DSP-based Digital Equalization 54 of 108

© 2023 IEEE International Solid-State Circuits Conference

DSP Based FFE Implementation

 Time-interleaved ADCs
outputs can also be
used as delayed a
version of the data.
 It is easier to
understand the
equalization with
samples single-bit
response

Masum Hossain T11: ADC-DSP-based Digital Equalization 55 of 108

© 2023 IEEE International Solid-State Circuits Conference

DSP Based FFE Implementation

 On each sample (i.e. each ADC output), we have a superposition of Signal

and ISI  Need to ‘synchronize’ them with retimer

Masum Hossain T11: ADC-DSP-based Digital Equalization 56 of 108

© 2023 IEEE International Solid-State Circuits Conference

DSP Based FFE Implementation

𝑄𝑄𝑛𝑛(𝑚𝑚)
0

= � 𝑐𝑐𝑚𝑚, 𝑙𝑙 𝑟𝑟𝑛𝑛(𝑚𝑚+𝑙𝑙) , 𝑚𝑚 = 0, 1, . . , 𝑀𝑀 − 1
𝑙𝑙=−𝑁𝑁+1

[Agazzi’JSSC 2008]

 FFE output can also be viewed as a MIMO system

Masum Hossain T11: ADC-DSP-based Digital Equalization 57 of 108

© 2023 IEEE International Solid-State Circuits Conference

Noise Amplification in FFE

 Common amplification factor of

all noises is FFE to reduce noise
amplification, we need to address
this.

Noise Sources Constraint Transfer Gain Solutions

Power, Gain, BW,
NLEQ LEQ+FFE AFE, CTLE gain
Linearity
Φ𝑁𝑁 CDR BW, clocking power FFE Low latency, high-BW CDR
NADC Power, settling time FFE Reduced FFE gain
NQZ ADC resolution FFE Reduced FFE gain
Masum Hossain T11: ADC-DSP-based Digital Equalization 58 of 108

© 2023 IEEE International Solid-State Circuits Conference

Quantization Noise Impact

2 N 2 Q Pr eW 2 Pr e + N 2 QMainW 2 Main + N 2 QPostW 2 Post

N QZ ,out = N QZ ⋅ hFFE +
3
hX
WX = , x = Pr e, Main, Post
h pre + hmain + h post
0
FFT at the ADC Output (Simulated)
-10 FFT at the FFE Output (Simulated)
ADC quantization Noise Floor (Theoretical)
-20 Quantization noise floor at the FFE output (Theoretical)
-30
AMPLITUDE (dB)

-40

-50

-60

-70

-80

-90

-100
1 2 3 4 5 6 7
ANALOG INPUT FREQUENCY (GHz)

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How to reduce ADC quantization noise impact?

Although Digital FFE output can be 2N bit, If FFE can be moved ahead of the ADC then
ADC’s N-bit resolution still limits us we can Minimize ADC’s quantization noise penalty

How can we build a digital FFE with a resolution better than the ADC?

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© 2023 IEEE International Solid-State Circuits Conference

 LUT Based FFE Implementation Example
3-tap FFE output distribution
400

300

200

100
512
Selected

FFE output
FFE output
FFE output
0
Entries
-100
- To LUT
-200

-300

-400
0 20 40 60 80
Occurance (Times)

 From 2M possible outputs we select 2N statistically

most likely outcomes.
 Does not eliminate the worst-case quantization noise
impact occurrence but make it highly unlikely
 Reduces both power consumption and noise impact

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© 2023 IEEE International Solid-State Circuits Conference

LUT Based FFE Implementation Example

• LUT based first three taps reduces

quantization noise impact
• 3 to 8 taps does not significantly
amplify quantization noise

Masum Hossain T11: ADC-DSP-based Digital Equalization 62 of 108

© 2023 IEEE International Solid-State Circuits Conference

 DSP Synthesis vs Customize Layout
8-tap Conventional 3-tap LUT + 5-tap Conventional
500 µm 1300 µm

1000 µm
500 µm

• Area increases by 4x but

• Standard cell SRAM will reduce it by 25%
• Area will scale significantly with technology

Masum Hossain T11: ADC-DSP-based Digital Equalization 63 of 108

© 2023 IEEE International Solid-State Circuits Conference

 Example of variable Resolution solution
[Aurangozeb’ 2018]

 Required ADC resolution and EQ complexity are highest for 30 dB loss channels
 Opportunistic power savings for less lossy channels by reducing ADC resolution and
DSP resolution.

Masum Hossain T11: ADC-DSP-based Digital Equalization 64 of 108

© 2023 IEEE International Solid-State Circuits Conference

 Example of Variable resolution DSP
[P. Upadhyaya’2018]

 DSP power reduces from 225 mW to 64 mW

Masum Hossain T11: ADC-DSP-based Digital Equalization 65 of 108

© 2023 IEEE International Solid-State Circuits Conference

 Example of lower power DSP
[A. Shafik ’2016]

 Opportunistic power savings –

turn off the EQ when possible

Masum Hossain T11: ADC-DSP-based Digital Equalization 66 of 108

© 2023 IEEE International Solid-State Circuits Conference

 Latency Constrain in Direct Feedback DFE

 For direct feedback, Strong-Arm is part of the FB.

 Strong-Arm + Summing node < 1 UI
 Strong-Arm Comparator decision time is signal dependent

Masum Hossain T11: ADC-DSP-based Digital Equalization 67 of 108

© 2023 IEEE International Solid-State Circuits Conference

 Loop-unrolled DFE

[S.Kasturia’1991]

 For direct feedback, strong arm delay is part of the FB.

h0+h+1
 Strong-Arm + Summing node < 1 UI
h0-h+1
 For loop unrolled DFE strong Arm is out of the FB. h0
 1 D-FF+ Mux < 1 UI h0
 Make both decisions ‘speculatively’ -h0+h+1
 In the presence of h+1 , the margin still remain h0 -h0-h+1

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© 2023 IEEE International Solid-State Circuits Conference

PAM-4 Loop-unrolled DFE
 Number of comparators for N tap DFE = (L-1) x L^N
 For NRZ (2 Level) signalling – (2-1) x 2N = 2N
 For PAM-4 (4 Level) signalling – (4-1) x 4N = 3x4N

 Exponential increase in number of comparisons with taps

Masum Hossain T11: ADC-DSP-based Digital Equalization 69 of 108

© 2023 IEEE International Solid-State Circuits Conference

1 tap Loop-unrolled DFE in DSP

 Loop unrolled
architecture can
be implemented
in the digital
domain.
 N-Mux and flop
delay should be
less than N UI to
meet the timing
requirements

Masum Hossain T11: ADC-DSP-based Digital Equalization 70 of 108

© 2023 IEEE International Solid-State Circuits Conference

Outline
 Motivation & background
 Evolution of timing recovery concepts from analog to digital
 Progression toward digital equalization for multilevel signaling
 Challenges in ADC-DSP receiver
 Effect of latency/delay in the timing recovery
 Effect of ‘ISI’ on data and timing recovery
 Advanced digital equalization
 MLSE: ISI-assisted decoding approach
 SNR Optimization strategy
 Example of MLSE Implementation
 Summary and future direction

Masum Hossain T11: ADC-DSP-based Digital Equalization 71 of 108

© 2023 IEEE International Solid-State Circuits Conference

MMSE Algorithm for Baud-Rate Timing Recovery
slope [F. Musa’2003]
Data Error Timing Error =
Sample Slope =Sample-Dlev Slope*Error
A B Point
DLev
C D A -1 +1 Early
B +1 +1 Late
C +1 -1 Early
D -1 -1 Late

 Baud-rate sampling – no extra clock phase needed

 Locks at the lowest slope point – Low PD gain, reduced jitter tracking

Masum Hossain T11: ADC-DSP-based Digital Equalization 72 of 108

© 2023 IEEE International Solid-State Circuits Conference

Edge Sample Based Timing Recovery
slope
Edge Error Timing Error =
Sample Slope =Sample-Dlev Slope*Error
Point
A B A -1 +1 Early
DLev
C D B +1 +1 Late
C +1 -1 Early
D -1 -1 Late

 2X sampling – one extra clock phase is needed in addition to data sampling

 Locks at the highest slope point – high PD gain, good jitter tracking

Masum Hossain T11: ADC-DSP-based Digital Equalization 73 of 108

© 2023 IEEE International Solid-State Circuits Conference

Timing Recovery Challenge in ADC-DSP Rx

 At the sampling point, the eye is ‘un-equalized’  corrupted with ISI

 Equalized eye is available after the ‘digital EQ’  significant latency
 Clock recovery becomes challenging due to two factors ‘ISI’ and ‘latency’

Masum Hossain T11: ADC-DSP-based Digital Equalization 74 of 108

© 2023 IEEE International Solid-State Circuits Conference

Latency Estimate in ADC-Based Receiver

 CDR loop latency estimate:

 ADC – 2 parallel clock cycles
 FFE (8-tap FFE) 3 parallel clock cycles
 MMPD – 1 parallel clock cycle
 Digital Loop Filter – 2 parallel clock cycles
 Total: 8 parallel clock cycles
 For 875 MHz DSP @ 112 Gb/s  8*28GHz/875MHz = 256 UI
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© 2023 IEEE International Solid-State Circuits Conference

Effect of Loop Latency
 Long loop latency
causes ‘limit cycle jitter’
 Difficult to meet JTOL
 Limited solution space:
BW, dithering, & jitter peaking
trade-off

Jitter Tol. (UIpp)

Norm. Phase Code

Cycles Jitter Frequency (Hz)

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© 2023 IEEE International Solid-State Circuits Conference

Effect of Loop Latency (Cont’d)
 Reducing Kp
 lower dithering
 reduce jitter peaking
 lower BW 
affects l.f. SJ tracking
 Better approach: ower loop latency
Norm. phase code

Jitter tol. (UIpp)

Reduce Kp
Reduce Kp

Cycles Jitter Frequency (Hz)

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© 2023 IEEE International Solid-State Circuits Conference

Option: 1 Example of Reducing Latency

𝝃𝝃 = 𝑬𝑬[𝒆𝒆𝟐𝟐]
Pi(n) = Pi(n−1)+2µ𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠 𝑒𝑒 𝑆𝑆i

 Unlike Data decision, Timing recovery does not require every PD decision to
be correct. So we can under-equalize to reduce latency – use a simpler
dedicated 3-tap FFE, this saves a couple of cycles.

Masum Hossain T11: ADC-DSP-based Digital Equalization 78 of 108

© 2023 IEEE International Solid-State Circuits Conference

Example of Dedicated FFE for Timing Recovery
[Z,Guo’ 2022]

 Short FFE for timing

recovery –
 Reduces loop latency
 Decouples phase from data

 Achieves 4 MHz CDR BW

 504 mW/Lane
 Equalization:
 22-tap FFE + 7-tap floating
 1-tap speculative DFE
 Compensates >50 dB loss

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© 2023 IEEE International Solid-State Circuits Conference

 Option:2 TDC and ISI filter

 Add a dedicated CDR path w/t EQ

 CDR loop latency calculation:
 TDC comparator – 1
 Phase detector – 1
 Digital loop filter – 1
 Total: 3 clock cycles = 96 UI (3x32)

 Latency can be significantly improved if CDR can handle ISI and DDJ

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© 2023 IEEE International Solid-State Circuits Conference

ISI and DDJ filtering

 Zero-crossing distribution can be decomposed into distribution

associated with specific data patterns. For examples:
 1100 gives best zero-crossing point (i.e. ISI free)
 1101 & 0101 result in bimodality (i.e. ISI-affected)

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© 2023 IEEE International Solid-State Circuits Conference

ISI and DDJ filtering

2-bit TDC table

 Use (adaptive) D+1, D0, & D-1 to identify ISI-free edges

 Use (adaptive) E+1, E0, & E-1 to align zero-crossing edges
 With appropriately adjusting the edge crossing thresholds, we can align the
distributions for tighter distribution & higher gain

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© 2023 IEEE International Solid-State Circuits Conference

How to Reduce DDJ Impact?
EQ out EYE filtered

0.3

Threshold 0.2

Adjust D+1
D+1 0.1

D-1

amplitude (V)
D-1
-0.1

-0.2

-0.3

-1 -0.5 0 0.5 1

time (UI)

No D+1 / D-1 Smaller D+1 / D-1 Thresholds Larger D+1 / D-1 Thresholds

 Higher data threshold results in tighter edge distribution (good for DDJ perf.) but
reduces CDR bandwidth & may impact l.f. SJ tracking
 By appropriately adjusting the data threshold it is possible to improve the DDJ
seen by the phase detector
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© 2023 IEEE International Solid-State Circuits Conference

 Example of Adaptive Jitter Filtering
[M. Hossain 2019]

 Both data and edge thresholds are adapted to maximize proportional gain without
exceeding jitter target

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© 2023 IEEE International Solid-State Circuits Conference

Multi-bit TDC Benefits

 Finer phase Error Quantization

Lower in-band noise.
 Linearizes the loop  Less input
jitter dependency
 Improves Jitter Tolerance

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© 2023 IEEE International Solid-State Circuits Conference

 Example TDC-based recovery @ 112 Gb/s
[H. Lin’2021]

Comp. Power
AFE 80 mW
ADC 195 mW
Ring PLL 35 mW
 ‘TDC’ power is overhead but it can
TDC + CDR 20 mW
be kept low compared to the ‘ADC’
Misc 8 mW
 10% overhead (195mW vs 20mW) Total 338 mW

Masum Hossain T11: ADC-DSP-based Digital Equalization 86 of 108

© 2023 IEEE International Solid-State Circuits Conference

Jitter tolerance over different data rates
AFE Output Eye

Data Edge
Sampled

PD output
MMPD

 2-bit TDC improves dithering jitter.

 Filtering ISI-affected edges improve DDJ. Skew
 Phase interpolation through PLL improves DNL/INL.
 PLL BW is set beyond 200 MHz, and CDR BW is around 20 MHz
Masum Hossain T11: ADC-DSP-based Digital Equalization 87 of 108

© 2023 IEEE International Solid-State Circuits Conference

Outline
 Motivation & background
 Evolution of timing recovery concepts from analog to digital
 Progression toward digital equalization for multilevel signaling
 Challenges in ADC-DSP receiver
 Effect of latency/delay in the timing recovery
 Effect of ‘ISI’ on data and timing recovery
 Advanced digital equalization
 MLSE: ISI-assisted decoding approach
 SNR optimization strategy
 Example of MLSE implementation
 Summary and future direction

Masum Hossain T11: ADC-DSP-based Digital Equalization 88 of 108

© 2023 IEEE International Solid-State Circuits Conference

SNR Penalty ‘FFE only’ Equalization

FFE only EQ. (1 tap)

@ FFE input SNR Penalty

SBR
Symbol Error Rate

@ PAM-4
Slicer input

Measurement

Time (ns)
 SNR vs BER correlates well with the
theoretical plot at the decision point.
 At the FFE input SNR vs BER plot is
offset by the FFE amplification factor
SNR (dB)
Masum Hossain T11: ADC-DSP-based Digital Equalization 89 of 108

© 2023 IEEE International Solid-State Circuits Conference

 Strategy for SNR Improvement
FFE only EQ. (1 tap)
Single Bit Response
@ 40 dB loss
FFE Responses
Chanel
Short. EQ
SNR Penalty

FFE &
1 tap DFE

FFE only
Channel Shortening to 4 taps
Signal attenuation
Time (ns) Freq (Hz)

 Equalizing to a single tap mandates significant high-

frequency boost  noise and crosstalk noise amplification
 Significant SNR improvement is achievable if the pre- and
post-cursors can be accommodated in the decision process
Time (ns)

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© 2023 IEEE International Solid-State Circuits Conference

Maximum Likelihood Sequence Estimator (MLSE)

Tx

h0
h-1 h+1
𝑟𝑟 𝑘𝑘 = 𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟 𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠
r[k] includes both signal
and noise

time

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© 2023 IEEE International Solid-State Circuits Conference

Maximum Likelihood Sequence Estimator (MLSE)

Prev. Current Next Tx

bit bit bit
B+1 B0 B-1
h0
h-1 h+1
111 𝑟𝑟 𝑘𝑘 = 𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟 𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠
110 r[k] includes both signal
and noise
011

101
010

100
001

000 time

Masum Hossain T11: ADC-DSP-based Digital Equalization 92 of 108

© 2023 IEEE International Solid-State Circuits Conference

Maximum Likelihood Sequence Estimator (MLSE)

Prev. Current Next Tx

bit bit bit
B+1 B0 B-1
h0
h-1 h+1
111 𝑟𝑟 𝑘𝑘 = 𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟 𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠
110 Noiseless expected signal level
011 𝑟𝑟� 𝑀𝑀
𝑖𝑖𝑖𝑖 [𝑘𝑘] = ∑𝑖𝑖=0 ℎ 𝑖𝑖 𝑠𝑠𝑠𝑠𝑠𝑠(𝑘𝑘 − 𝑖𝑖)

101
2
010 𝑒𝑒𝑖𝑖𝑖𝑖 = 𝑟𝑟�
𝑖𝑖𝑖𝑖 [𝑘𝑘] − 𝑟𝑟[𝑘𝑘]
Branch
100 eij indicates how ‘likely’
Matric
it is that the received sample
001 belonging to a particular seq.

000 time

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© 2023 IEEE International Solid-State Circuits Conference

Maximum Likelihood Sequence Estimator (MLSE)

Prev. Current Next Tx

0 0 1 0 1 1 1 1 bit bit bit
0 0 1 0 1 0 1 1 B+1 B0 B-1
0 0 0 1 0 1 1 1 h0
111 h-1 h+1
𝑟𝑟 𝑘𝑘 = 𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟 𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠
110
011 𝑟𝑟� 𝑀𝑀
𝑖𝑖𝑖𝑖 [𝑘𝑘] = ∑𝑖𝑖=0 ℎ 𝑖𝑖 𝑠𝑠𝑠𝑠𝑠𝑠(𝑘𝑘 − 𝑖𝑖)
2
𝑒𝑒𝑖𝑖𝑖𝑖 = 𝑟𝑟�
𝑖𝑖𝑖𝑖 [𝑘𝑘] − 𝑟𝑟[𝑘𝑘]
101
010 Accumulate the ‘likeness’ or ‘likelihood’
over a ‘sequence’ and then pick the
Most likely sequence. Branch
100 Matric
Max. Probability  Min distance
001
𝐶𝐶𝑖𝑖 = ∑𝐾𝐾
𝑙𝑙=0 |𝑒𝑒 𝑙𝑙 |
2
000 Accumulate
time 𝐼𝐼𝑗𝑗 = 𝑀𝑀𝑀𝑀𝑀𝑀(𝑒𝑒𝑖𝑖𝑖𝑖 + 𝐶𝐶𝑖𝑖 ) Compare
select

Masum Hossain T11: ADC-DSP-based Digital Equalization 94 of 108

© 2023 IEEE International Solid-State Circuits Conference

 Example of MLSE Implementation
[H. Yueksel’ 2018]

 Implementation of full-blown Viterbi Algorithm PAM-N can be power-hungry

and area-consuming.
 Reduced state Viterbi in 10nm or lower finFET node is becoming more
affordable

Masum Hossain T11: ADC-DSP-based Digital Equalization 95 of 108

© 2023 IEEE International Solid-State Circuits Conference

Computational Cost & Power Reduction
Number of States S = Α𝑀𝑀−1
𝐴𝐴 = Possible Symbols (A=2 for NRZ)
M = Channel Memory (Number of taps)
L = Trellis length (sequence length)
𝑆𝑆 2
BM Calculation (for L) = (L−1)
2
 Reduce Channel Length M
 Channel Shortening (Agazi JSSC
2008)
 DDFSE(AD Hallen 1989 Trans. Comm)
 1+D approach
 Reduce the Number of States ‘S’
 Set Partition (Vedat 1988)
 Reduce BM calculation complexity
 Simplify Computation
 Radix 2 etc.

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© 2023 IEEE International Solid-State Circuits Conference

Analog to Sequence Converter

h0
h-1 h+1
 ADC + BM Cal.
= Analog to seq. conv.
 Directly calculating
the ‘probability’ achieves
 Reduced computation
 Less quantization
noise effect
 Bit-wise operation

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© 2023 IEEE International Solid-State Circuits Conference

Example of Analog to Seq. Converter
[A.D. Hossain’ 2016] [Aurangozeb’ 2018]

 Low-cost sequence set and Branch  1-bit Branch Matric based short (1 UI)
Matric. Generation for NRZ. traceback error correction
 35 mW @ 10 Gb/s NRZ in 65nm  82 mW @ 28 Gb/s PAM-4 in 28nm
CMOS CMOS

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© 2023 IEEE International Solid-State Circuits Conference

 1+D Sequence Encoding

 Each signal level indicates multiple symbol possibilities

that must be resolved
 But the trellis is self converging to 000 and 111.
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© 2023 IEEE International Solid-State Circuits Conference

 1+D Trellis Decoding
+3

+1

-1

-3

Decoded
State

Corresponding
3b Trellis

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© 2023 IEEE International Solid-State Circuits Conference

 1+D Trellis Decoding
+3

+1

-1

-3

Decoded
State

Corresponding
3b Trellis

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© 2023 IEEE International Solid-State Circuits Conference

 1+D Trellis Decoding
+3

+1

-1

-3

Decoded
State

Corresponding
3b Trellis

Masum Hossain T11: ADC-DSP-based Digital Equalization 102 of 108

© 2023 IEEE International Solid-State Circuits Conference

Example of 1+D Sequence Coded Signaling

[Aurangozeb’ 2020]

Masum Hossain T11: ADC-DSP-based Digital Equalization 103 of 108

© 2023 IEEE International Solid-State Circuits Conference

Outline
 Motivation & background
 Evolution of timing recovery concepts from analog to digital
 Progression toward digital equalization for multilevel signaling
 Challenges in ADC-DSP receiver
 Effect of latency/delay in the timing recovery
 Effect of ‘ISI’ on data and timing recovery
 Advanced digital equalization
 MLSE: ISI-assisted decoding approach
 SNR optimization strategy
 Example of MLSE implementation
 Summary and future direction

Masum Hossain T11: ADC-DSP-based Digital Equalization 104 of 108

© 2023 IEEE International Solid-State Circuits Conference

Summary
 Equalization is an evolving process that needs to be customized
according to the solution space.
 SNR penalty in multilevel signaling is significant that requires
more precise ISI cancellation.
 ADC-DSP-based equalization is particularly suitable for multilevel
signaling in extremely scaled devices.
 ‘ISI cancellation’ based equalization is conceptually more
straightforward but suffers from SNR penalty or error propagation.
 ISI-assisted symbol detection is a more SNR-friendly approach but
potentially more complicated.

Masum Hossain T11: ADC-DSP-based Digital Equalization 105 of 108

© 2023 IEEE International Solid-State Circuits Conference

ISSCC 2023 Papers
 6.1 A 112Gb/s Serial Link Transceiver With 3-tap FFE and 18-tap DFE
Receiver for up to 43dB Insertion Loss Channel in 7nm FinFET Technology
 1+D encoding
 6.2 A 4.63pJ/b 112Gb/s DSP-Based PAM-4 Transceiver for a Large-Scale
Switch in 5nm FinFET
 DSP scaling with technology node

Masum Hossain T11: ADC-DSP-based Digital Equalization 106 of 108

© 2023 IEEE International Solid-State Circuits Conference

Key References
 A. Ong et al., "A 40-43-Gb/s clock and data recovery IC with integrated SFI-5 1:16 demultiplexer in SiGe technology," in IEEE Journal of
Solid-State Circuits, vol. 38, no. 12, pp. 2155-2168, Dec. 2003
 A. Shafik, E. Zhian Tabasy, S. Cai, K. Lee, S. Hoyos and S. Palermo, "A 10 Gb/s Hybrid ADC-Based Receiver With Embedded Analog
and Per-Symbol Dynamically Enabled Digital Equalization," in IEEE Journal of Solid-State Circuits, vol. 51, no. 3, pp. 671-685, March 2016
 A. D. Hossain, Aurangozeb, M. Mohammad and M. Hossain, "A 35 mW 10 Gb/s ADC-DSP less direct digital sequence
detector and equalizer in 65nm CMOS," 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), Honolulu, HI, USA,
2016, pp. 1-2
 Aurangozeb, A. D. Hossain, M. Mohammad and M. Hossain, "Channel-Adaptive ADC and TDC for 28 Gb/s PAM-4 Digital Receiver," in
IEEE Journal of Solid-State Circuits, vol. 53, no. 3, pp. 772-788, March 2018.
 Aurangozeb, C. R. Dick, M. Mohammad and M. Hossain, "Sequence-Coded Multilevel Signaling for High-Speed Interface," in IEEE
Journal of Solid-State Circuits, vol. 55, no. 1, pp. 27-37, Jan. 2020.
 Aurangozeb, M. Mohammad and M. Hossain, "Analog to Sequence Converter-Based PAM-4 Receiver With Built-In Error Correction," in
IEEE Journal of Solid-State Circuits, vol. 53, no. 10, pp. 2864-2877, Oct. 2018.
 E. Groen et al., "10-to-112-Gb/s DSP-DAC-Based Transmitter in 7-nm FinFET With Flex Clocking Architecture," in IEEE Journal of Solid-
State Circuits, vol. 56, no. 1, pp. 30-42, Jan. 202
 F. A. Musa and A. C. Carusone, "Clock recovery in high-speed multilevel serial links," Proceedings of the 2003 International Symposium
on Circuits and Systems, 2003. ISCAS '03., 2003
 G. Mogensen, "Wide-band optical fibre local distribution systems." Optical and Quantum Electronics 12.5 (1980): 353-381.
 H. Lin et al., "ADC-DSP-Based 10-to-112-Gb/s Multi-Standard Receiver in 7-nm FinFET," in IEEE Journal of Solid-State Circuits, vol. 56,
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