module brent_kung_csa_16bit (
input wire [15:0] a,
input wire [15:0] b,
output reg [15:0] sum,
output reg carry_out
);
reg [7:0] sum_low, sum_high, sum_high_with_carry1;
reg carry_out_low, carry_out_high, carry_out_high_with_carry1;
wire [7:0] a_low = a[7:0];
wire [7:0] b_low = b[7:0];
wire [7:0] a_high = a[15:8];
wire [7:0] b_high = b[15:8];
always @* begin
{carry_out_low, sum_low} = a_low + b_low;
{carry_out_high, sum_high} = a_high + b_high + 1'b0;
{carry_out_high_with_carry1, sum_high_with_carry1} = a_high + b_high + 1'b1;
sum = {carry_out_low ? sum_high_with_carry1 : sum_high, sum_low};
carry_out = carry_out_low ? carry_out_high_with_carry1 : carry_out_high;
end
endmodule
module brent_kung_adder_8bit (
input wire [7:0] a,
input wire [7:0] b,
input wire carry_in,
output reg [7:0] sum,
output reg carry_out
);
reg [7:0] g, p;
reg [7:0] c;
always @* begin
g = a & b;
p = a ^ b;
c[0] = carry_in; // Use carry_in for the first carry
c[1] = g[0] | (p[0] & c[0]);
c[2] = g[1] | (p[1] & c[1]);
c[3] = g[2] | (p[2] & c[2]);
c[4] = g[3] | (p[3] & c[3]);
c[5] = g[4] | (p[4] & c[4]);
c[6] = g[5] | (p[5] & c[5]);
c[7] = g[6] | (p[6] & c[6]);
carry_out = g[7] | (p[7] & c[7]);
sum = p ^ c;
end
endmodule