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Uart Implementation: Harish Madupu 114513

This document describes the implementation of a UART module for asynchronous serial communication. It discusses the transmitter and receiver pins, transmission and reception processes, and clock division needed to achieve the desired baud rate. Code is provided for transmitter and receiver entities, and the design is meant to allow serial transmission and reception of data between external devices and a PC.

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Harish Madupu
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98 views31 pages

Uart Implementation: Harish Madupu 114513

This document describes the implementation of a UART module for asynchronous serial communication. It discusses the transmitter and receiver pins, transmission and reception processes, and clock division needed to achieve the desired baud rate. Code is provided for transmitter and receiver entities, and the design is meant to allow serial transmission and reception of data between external devices and a PC.

Uploaded by

Harish Madupu
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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UART IMPLEMENTATION

UNDER THE GUIDENCE OF MS. P PRUTHVI

By

HARISH MADUPU 114513


M.Tech. I SEM EI

WHAT AND WHY?


The UART (universal asynchronous receiver and

transmitter) module provides asynchronous serial communication with external devices such as modems and other computers The UART can be used to control the process of breaking parallel data from the PC down into serial data that can be transmitted and vice versa for receiving data. The UART allows the devices to communicate without the need to be synchronized
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The Complete Block

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Transmitter Pins
Mclkx16 => Master input clock for internal baud

rate generation

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Clock division
There should be a clock divider running at 16 times the

baud rate driving the UART modules. The transmitter and receiver modules with a clock divider inside runs 16 times slower than the clock signal sent to it. If for example, you want to transmit at 33.6 kbps and the FPGA board runs at 25.175 MHz then: Baud rate x 16 = 33600 x 16 = 537600 Clock division ratio = 25175000 / 537600 = 46 Clock divisor = 46 / 2 = 23 Therefore, the clock divider used to clock the UART would have a divisor of 23. This would give a transmission rate of about 34.2 kbps.
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Transmitter Pins
Reset => Master reset

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Transmitter Pins
Txrdy => Indicates new data has been written to

the transmitter

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Transmitter Pins
Write => Active low strobe signal, used for

writing data in to transmitter

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Transmitter Pins
data (7 down to 0) => Bi-directional data bus for

sending/receiving data across the UART

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Transmitter Pins
Tx => Transmitter serial output. Held high when

no transmission occurring and when resetting

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Transmission Format
This implementation of the UART transmits in

blocks of 11 bits

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In the transmission of a sequence the active low start

bit indicates to the receiving UART that a new sequence of data is on its way The parity can be set as even or odd and is used to indicate whether or not there has been an error in the received data bits The data is transmitted LSB first

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Receiver Pins
Parityerr => Indicates whether a parity error was

detected during the receiving of a data frame

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Receiver Pins
Framingerr => Indicates if the serial data format sent

to the rx input did not match the proper UART data format

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Receiver Pins
Overrun => Indicates whether new data sent in is

overwriting the previous data received that has not been read out yet.

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Receiver Pins
Rxrdy => Indicates new data has been received

and is ready to be read out.

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Receiver Pins
Read => Active low strobe signal, used for

reading data out from the receiver.

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Receiver Pins
Rx => Receiver serial input. Pulled-up when no

transmissions taking place

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Implementational Architecture

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Process of Transmission
transmitting data through the UART begins by first

checking the txrdy line. A high txrdy signal indicates that new data can be written to the transmitter To write to the transmitter place the data to be transmitted on the data line. The data is then latched into the UART's transmit module by a leading low signal to the write line. The next data sequence can be latched once the txrdy line goes high again.

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Process of Transmission
while not transmitting, the data line must not be

driven but left floating to avoid dealing with tri-state buffers, modify the UART module by giving it separate parallel input and output ports.

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Transmitter Entity
Pi => data (7 downto 0) Clk => Mclkx16 Wrt => Write

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Initializing Transmitter
Txrdy signal will be high for every 16 clock cycles.

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Transmit Data Serially


Start ,parity and stop bits are added to data and

transmitted serially

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Transmitter Output

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Process of reception
The process of receiving data through the UART

begins by waiting for the rxrdy line to go high. A high rxrdy indicates that data has been received and is ready to be read out. To read the data out from the UART's data line assert a low signal to the read line. This will latch the received data from the receiver to the data line allowing you to read it.

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Process of Reception
The parityerr, framingerr, and overrun lines

indicate any problems with the current received data The next data received can be read out once rxrdy goes high again.

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Receiver Entity

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Expected results
Receiver output

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