Modes of 8086

 Minimum mode –when used in uniprocessor

configuration

 Maximum mode –when used in multiprocessor

configuration
Memory and I / O
 The 8086 generates control signals for reading and writing, but does not
distinguish between memory and I/O operations
 For this additional logic is used .
Clock Generation

 One cycle of the clock is called a T state, and all timings and delays are
multiples of this T state duration.

 There is no circuitry inside the processor for this, and so an external clock
generator IC is used.

 Intel has provided the clock generator IC 8284A which is compatible with
8086 / 8088.
Pin configuration of the clock generator 8284A
Clock generator IC
 The clock generator IC performs a few more functions than just supplying
the clock frequency to the processor

 The crystal is connected between the X1 and X2 pins.

 The READY output pin of 8284A is connected to the READY input pin of
8086.

 This pin is used to overcome the timing inconsistencies that are possible
when a slow peripheral / memory device is connected to the processor.
Connections of the clock generator IC to 8086
 Reset

 An active low reset signal from the control bus is sent to the 8284 which
synchronizes it with the trailing edge of the clock.

 Most systems include a line that goes to all system components and
possibly controlled by an operator push button (or just after power on),
which causes a low signal on the RESET pin of the clock generator.
Reset Timings and reset vector
 The RESET line of 8086 must remain high for at least 4 clock periods.

 The 8086 will terminate operations on the high-going edge of RESET and will remain
dormant as long as RESET is HIGH.

 A high on the RESET pin of the processor causes all system components to be reset, and
inside it, the instruction queue, PSW, DS, SS, ES and IP are cleared.

 CS gets a value of FFFFH and with IP = 0000, the first instruction will be executed from
the location FFFF0H.
‘Power on reset’ circuit
Meeting the reset pulse specifications

By this, we are designing a reset pulse of 50 m secs, which is

higher than the minimum requirements of the reset pulse for
the clock frequency of 5 MHz shown in previous Fig.
Machine/Bus cycles
 Any read or write cycle is called a bus cycle. For 8086, a bus cycle takes 4 T
states, where one T state is defined as the ‘period’ of the one clock cycle.

 If the clock frequency is 10 MHz, one T state = 0.1 u secs or 100 n secs.

 A bus cycle is also called a machine cycle.

 During a machine cycle, a specific operation – say, reading or writing is

accomplished.
 Typical machine cycles
 Memory Read
 Memory Write
 I / O Read
 I / O Write
 Interrupt Acknowledge
 Read Machine Cycle
 Place on the address bus, the address of the location whose content is to
be read. This action is performed by the processor.

 Assert the read control signal which is part of the control bus.

 Wait until the content of the addressed location appears on the data bus.

 Transfer the data on the data bus to the processor.

• De-activate the read control signal. The read operation is over and the
address on the address bus is not relevant anymore.
Read machine cycle timing diagram
 Wait Cycles
 If the access time for a device is longer than that permitted by 8086 timing,
extra clock cycles termed ‘wait states’ have to be inserted in the bus cycle.
 Sample the READY line at the end of T2. If the READY signal is found low,
an extra T state is inserted into the bus cycle, between T3 and T4 , which is
designated as TW .
 All signals on the bus remain unchanged during this extra wait state (TW).

 In the middle of TW , once again the READY signal is checked. If it is at

logic 1, the next T state will be T4 – otherwise another wait state TW will be
inserted.
Sampling the READY signal and inserting wait states
Insertion of a wait state generator to add wait states
Example
 What is the duration of the bus-cycle in an 8086 based microcomputer, if
the clock frequency is 12 MHz and three wait states are inserted?

In the 8086, a bus cycle normally takes 4 clock cycles (without wait states). Hence, the normal
duration of the bus cycle is: 4×T=4×83.33 ns=333.32 ns

3 wait states inserted, the total number of clock cycles per bus cycle increases by 3. Therefore, the
total number of clock cycles for the bus cycle is:

Total Bus Cycles=4+3=7 clock cycles

Bus Cycle Duration=7×T=7×83.33ns=583.31ns

The duration of the bus cycle is 583.31 nanoseconds when the clock frequency is 12 MHz and
three wait states are inserted.
Other Processor Activities

 Interrupt Lines

 It has an INTR line and an NMI (Non maskable Interrupt) line for external
interrupts
DIRECT MEMORY ACCESS(DMA)

 This is the method of transferring data between the memory and a

peripheral without involving the processor.

 During the time of DMA, the buses of the processor are tri-stated.

 The pins HOLD and HLDA are devoted to DMA operation.

Concept of direct memory access
Timing of the HOLD and HLDA signals
TEST and BHE pins
 Both these pins are active low.

 The TEST pin is used to synchronize the activities of the 8086 with an
arithmetic co-processor 8087.

 The BHE (Bus High Enable) is used to enable high bank of memory.
Halt Machine Cycle
 Another machine cycle is the HALT machine cycle. The processor enters
this machine cycle in response to a HLT (Halt) instruction.

 To bring the processor out of this state, an interrupt or

a RESET signal must be issued.
Maximum mode case
Pin diagram of the bus controller IC 8288
Connection between the 8086 and 8288
REQUEST/GRANT pins
 These are two bi-directional, active low pins, on which other processors
in a multi processing system can place their bus requests.

 As the name implies, they cater to ‘request’ and ‘grant’.

 In the minimum mode, HOLD is for bus request, and HLDA is for bus
grant.
Timing associated with the 𝑅𝑄/𝐺𝑇
 Three pulses are needed to complete a request / grant / release of the bus.

 The RQ / GT pins are examined at the rising edge of each clock pulse.
 Queue Status pins QS0 , QS1

 These pins are inputs to the 8086.

 It becomes useful when an arithmetic coprocessor is the second

processor in the system.

 Since the co-processor is expected to work in step with 8086, the co-
processor can interrogate the 8086 about its queue status, on these lines,
and decide its course of action accordingly.
The LOCK signal
 The active low LOCK signal can be used to prevent other bus masters
from acquiring the bus of the 8086.
 For example, if the 8086 wants to retain the bus until a string transfer is
completed fully, it can use the instruction (say) LOCK REP MOVSB.
 So the processor does not have to relinquish the bus after one bus cycle, as
may be the case if the LOCK prefix is not used.
 Instead, the bus is retained until the complete string operation is over.
Maximum mode configuration of the 8086
 Instruction Cycle
 The time taken by the processor to execute an instruction is called an
instruction cycle, and it is specified in terms of the number of clock cycles
needed to do it.

 The operation of the CPU is just ‘fetch, decode and execute’.

 Once an instruction is fetched and is ready for execution, it will be

decoded immediately, and after that, execution can be set in motion.
Instruction Cycle
 FETCH –EXECUTE CYCLE
 The fetch-execute cycle can be decomposed into 6 stages
FI – Fetch instruction
DI – Decode instruction
CO – Calculate operand addresses
FO – Fetch operands
EI – Execute instruction
WO – Write or store result in memory
 The time for all these activities should constitute the ‘instruction cycle’.
Execution Times of Some Sample Instructions
Number of Cycles Expended in Calculating the ‘Effective Address’
Thank You