Digital Lab Sheet

Decoders:
➢ Explain the basic operation of a 2 to 4 decoder (with the aid of truth table and logic symbol)
• If an active low output is required, what are the logic gates used in the implementation of decoder circuit
• If an active high output is required, what are the logic gates used in the implementation of decoder circuit

➢ When a HIGH is on the output of each of the decoding gates in the following Figure, what is the binary code
appearing on the inputs? The MSB is A3.

➢ Develop the decoding logic for each of the following codes if an active-HIGH (1) output is required:

(a) 1101 (b) 1001 (c) 0111

➢ Develop the decoding logic for each of the following codes if an active-LOW (0) output is required:

(a) 1101 (b) 1001 (c) 0111

➢ The 74HC42 is an IC decoder with four BCD inputs and ten decimal outputs. The logic symbol is shown below
Write the truth table For the following input combinations applied to the IC

INPUTS OUTPUTS
A3 A2 A1 A0 0 1 2 3 4 5 6 7 8 9
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

➢ What is the difference between BCD and Binary numbers illustrate your answer with an example?

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Multiplexers:
➢ Explain the basic operation (with the aid of truth table and logic symbol) of
• 2 to 1 multiplexer
• 4 to 1 multiplexer
• 8 to 1 multiplexer

➢ For multiplexer shown in figure, what is the output for each input combination applied to data select lines

A2 A1 A0 Y
0 0 0
Data Select Inputs 0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

Flip-Flops:
➢ Explain how to implement an active high input S-R latch and active low input 𝑆̅ 𝑅̅ latch

➢ Explain the difference between a flip-flop and a latch

➢ Discuss and compare the operation of S-R flip-flop, D flip-flop and J-K flip-flop
(Explain the differences in their truth tables and logic symbol)

➢ Discuss the asynchronous inputs (Preset & Reset) of a flip-flop

➢ For a positive edge-triggered S-R flip-flop with the input as shown in Figure, determine the Q output relative to
the clock. Assume that Q starts LOW.

➢ For a positive edge-triggered D flip-flop with the input as shown in Figure, determine the Q output relative to
the clock. Assume that Q starts LOW.

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➢ A negative edge-triggered J-K flip-flop is shown in the following Figure. If the inputs are as shown, draw the Q
output of flip-flop relative to the clock. The flip-flop is initially RESET.

➢ Explain how J-K flipflop is used for frequency division

➢ Explain how J-K flipflops are used in basic counter applications

Counters:
➢ How does a synchronous counter differ from an asynchronous counter?

➢ What is the difference between 4-bit binary counter and decade counter?

➢ For the counter shown in figure:

• What is the type of this counter?
• What is the maximum count and number of output states?
• Is this counter up or down?
• How to modify it to count in the opposite direction?

➢ For the counter shown in figure:

• What is the type of this counter?

• What is the maximum count and number of output states?
• Is this counter up or down?
• How to modify it to count in the opposite direction?

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➢ For the counter shown in figure:
• What is the type of this counter?
• What is the maximum count and number of output states?
• Explain the purpose of NAND gate shown in Figure
• What is the modification needed to make this counter counts up to 12 (1100) 2 and then recycles?

➢ How many states does a modulus-14 counter have? What is the maximum count? What is the minimum number
of flip-flops required?

➢ Determine the overall modulus of the three cascaded counter configurations in Figure

➢ Explain the function of the load feature of counters such as the 74LS193.

➢ A 4-bit up/down binary counter is in the DOWN mode and in the 1010 state. On the next clock pulse, to what
state does the counter go?

➢ How many decade counters are necessary to implement a divide-by-1000 (modulus-1000) counter?