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Octopus_A_Yorp_DVT
SCH: 650-01771-03-SCH
ASSY:650-01771-03
D PCB: 651-01771-03 D

TABLE OF CONTENTS TABLE OF CONTENTS

SHEET NO. SHEET NAME SHEET NO. SHEET NAME
1 TABLE OF CONTENTS 31 USB C CONNECTOR ( MLB )
2 SYSTEM BLOCK DIAGRAM 32 USB C VBUS CONTROL
3 USB TYPE-C BLOCK DIAGRAM 33 PMIC ( 0PTION 1)
4 POWER TREE 34 POWER: 1.8V(EC) 3.3V AND 5V
5 I2C MAP 35 POWER - LOAD SWITCHES
6 SOC DRAM I/F 36 INAs
C
7 SOC EDP/MIPI/DDI 37 BATTERY CHARGER (OPTION 1) C

8 SOC PCIE/USB/SATA 38 LTE, STEST（REMOVED）

9 SOC AUDIO/EMMC/LPC/SPI 39 CONNECTORS TO SUB BOARD
10 SOC I2C/CNVI/UART/SPI 40 SUB BOARD SCH:G sensor DB
11 SOC PMU/RTC/SVID/THERMAL/MISC 41 WOV DIAGRAM
12 SOC JTAG/GPIO/ITP 42 POWER SEQUENCE
13 SOC GROUND 43 SOC STRAPPING
14 SOC POWER
15 SOC DECOUPLING
16 MEMORY CH 00/01 LPDDR4
17 MEMORY CH 10/11 LPDDR4
18 EC-NUVOTON
19 SPI ROM
B
20 MIPI60 DEBUG HEADER B

21 H1 SECURE MICROCONTROLLER
22 SERVO
23 eMMC/SD
24 AUDIO
25 KB, TPD
26 LID: eDP, CAM, TOUCH, SENSOR, PEN
27 SENSOR: COMPASS, GYRO (OPTION 1)
28 WIFI/BT CONNECTOR
29 USB C TCPC/MUX (OPTION 2)
30 USB A CONNECTIONS (MLB)

A A

Bitland Information Technology Co.,Ltd.

Page Name
TABLE OF CONTENTS
Size Project Name Rev
C
Phaser 1.3
Date: Thursday, November 22, 2018 Sheet 1 of 43
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

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was obtained with the expressed written consent of Bitland

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 RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
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Octopus(Gemini Lake)
Block Diagram ver.0.5
Jan,14,2018 DISPLAY(EDP)11.6" ?
CAMERA Sensor Stylus
1366x768 ?
Backlight DMIC
(B-Panel) (ALS) (EMR) (Dual?)
TOUCH
SCREEN EDP
MAX 8GB DDR4 OR LPDDR4
D D
UART-AP

EDP(2 Lnes)
UART

LPDDR4 LPDDR4 LPDDR4 LPDDR4 USB2.0 BACKLIT CTL UART-EC robx

x32 x32 x32 x32 UART

I2C

I2C

I2C

PDM
(2400) (2400) (2400) (2400) SBU1,2 H1
2GB 2GB 2GB 2GB USB
I2C
I2C INA
SPI-AP-SPI
SPI
USB2-6 I2C-1 I2C-0 I2C-7 EDP
DRAM PDM/I2S
DRAM I/F
SPI

EMMC I2C
EMMC 32GB EMMC 5.1* AP SPI ROM Servo Header
(BIOS) 16MB
Keyboard
UART-AP

WiFi-BT Module
PCIe Gen2 x1
PCIe0-Gen2
GLK UART-0
UART-EC EC-SPI
(2x2 801.11AC) USB2.0
PCIE M.2 1216 USB2-2
CNVi I2S (WoV) GMR/Hall
JFP2 CNVi CNVi DMIC
C Sensor C

EC(Nuvoton)
I2S
NPCX796F
USB-to-SD USB3.0 USB2-5 I2S-0 I2S SPI-Sensor IMU/Accel I2C
Micro-SD GL3213S (6-Axis)
(104MB/s) USB3-5
SPI-AP-EC With option I2C-Sensor
eSPI of WoV
I2C-Battery
MIPI60 Debug Header Debug
E-Compass
I2C-Charger (Optional)

I2C I2C-PMIC
Track Pad I2C-6 I2C
USB2-4 Lid Accel
USB3-4
I2C
I2C-5
Audio Audio Jack DDI-1
Jack Codec DA7219 I2S
I2S-2
USB2.0
USB2-0
USB3.0 Li-lon
B USB3-0 Charger B
Battery
I2S DP (Buck-Boost) Pack
Speaker Amp. I2S-1 DDI-0 I2C I2C
Speakers x2 3s1p
Max98357A x2 USB2-3 USB2-1 ISL9238 42whrs
USB2-7 USB3-3 USB3-1
USB2.0

USB2.0

USB3.0

USB2.0

USB3.0

USB3.0

USB2.0

SBU1,2

USB3.0

USB2.0
I2C
I2C
DP

DP
PMIC
RT5077A

BC1.2 BC1.2 TCPC+Mux+VCONN BC1.2 TCPC+Mux+VCONN BC1.2

Camera-W SN1702001 SN1702001 ANX3447 MAX14637 PS8751BQFN52GTR MAX14637
-A3-GG0A02

SS SS

TYPE-A TYPE-A TYPE-C TYPE-C

Port0 Port1 CC/SBU Port0 CC/SBU Port1
A A

PPC PPC
NX20P3483 NX20P3483 Bitland Information Technology Co.,Ltd.
Page Name
SYSTEM BLOCK DIAGRAM
PPVAR_PWR_IN Size Project Name Rev
C
Phaser 1.3
PP5000_A Date: Thursday, November 22, 2018 Sheet 2 of 43
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
was obtained with the expressed written consent of Bitland

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D D

PPVAR_PWR_IN
Charger Vout
PP5000_A
NX20P3483 PPVAR_Cx_VBUS

Vin (Power Mux)

Vbus Sink/Source

C C

EC I2C
CC 1,2
ANX3447
SBU 1,2
DDI(0,1,2,3)
-SS Mux
SSRX1 USB-C
AUX SSRX0
-VCONN
SSTX1
USB3-AP -Sink control
(SSTX) SSTX0
SoC USB3-AP -Source control
(SSRX)
HPD

USB2.0
B
USB2.0 MAX14637 B

(BC 1.2)

A A

Bitland Information Technology Co.,Ltd.

Page Name
USB TYPE-C BLOCK DIAGRAM
Size Project Name Rev
C
Phaser 1.3
Date: Thursday, November 22, 2018 Sheet 3 of 43
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
was obtained with the expressed written consent of Bitland

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Power Tree

Power 3.3V
PP3300_A
PP3300_EC
D System 3.3V PP3300_A EC EMMC D

PP3300_SOC_A PP1800_EC
PP1800_A TBD
3.3V 8A NPCX796FB
PP1800_A
RT6258C DMIC
PP3300_RTC
Secure uC
PP1800_EC PP1800_A AP SPI ROM
UB0605B-FT021 GD25LQ128DSIGT
Load switch Load switch
PP3300_EC PP3300_A
RT9742 RT9742 PP3300_PD_A Audio Codec
PP1800_A DA7219
Charger PPVAR_SYS

ISL9238B PP3300_RTC PP3300_A PP1800_SENSOR

1.8V DC/LDO FET Sensors
PP1800_RTC Load switch PP1800_EC
PP3300_LDO 1.8V 0.3A PP3300_A PP3300_CAMERA_S
C
PPVAR_PWR_IN TPS22929 FET WF Camera C

PP3300_EC_VSBY RT9078N-08
PPVAR_BAT UF Camera
Power 5.0V
Charger System 5.0V PP3300_A PP3300_TOUCHSCREEN
PP5000_A FET Touchscreen
ISL9238B 5.0V 8A
Stylus
RT6258B PP5000_LDO
PP3300_A PP3300_EDP_DX
FET EDP Display

PP3300_A
SD Controller
LPDDR4
PP1100_VDDQ PP3300_A PP3300_TRACKPAD_DX
LPDDR4 FET Trackpad
B PP1800_DRAM B
K4F8E304HB-MGCH PP3300_A PP3300_PD_A
FET ANX3447
PP3300_SOC_A
+3.0V PP5000_A PS8751
PPVAR_VNN
VNN VNN
PP5000_A PP5000_VBUS_A0
PPVAR_VCCGI BC1.2 switch USB A Port0
VCCGI VCCGI
PP1050_VCC
VCCIOA VCCIOA PP5000_A PP5000_VBUS_A1
BC1.2 switch USB A Port1
PP5000_A PP1100_VDDQ
VDDQ VDDQ
PP5000_A PPVAR_VBUS_C0
PP1050_S Vbus FET USB C Port0
+1.05V +1.05V
PP1200_A
+1.20V +1.20V PP5000_A PPVAR_VBUS_C1
Vbus FET USB C Port1
PP1800_A
+1.80V +1.80V
A
PP1800_A PP1800_DRAM A

Load switch +1.80V

RT5077a GLK SOC Bitland Information Technology Co.,Ltd.

Page Name
POWER TREE
Size Project Name Rev
C
Phaser 1.3
Date: Thursday, November 22, 2018 Sheet 4 of 43
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
was obtained with the expressed written consent of Bitland

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D D

Master Port Net Name Slave Device(S) Speed

EC I2C0 0 EC_I2C_BATTERY_3V3 BATTERY(TBD) 100KHz
EC I2C1 0 EC_I2C_USB_C0_MUX ANX7447,NX20P3483 100KHz
EC I2C2 0 EC_I2C_USB_C1_MUX PS8751B 100KHz
EC I2C3 0 EC_I2C_EEPROM M34E02 100KHz
EC I2C4 1 EC_I2C_CHARGER_3V3 ISL8238B 100KHz
EC I2C5 0 -
C C

I2C7 0 EC_I2C_SENSOR_U LSM6DS3TR, 400KHz

EC LIS2DE12TR
AP LPSS I2C0 PCH_I2C_PEN STYLUS(TBD) 400KHz
AP LPSS I2C1 - -
AP LPSS I2C2 -
AP LPSS I2C3 DBG_PCH_I2C TBD TBD
AP LPSS I2C4 PCH_I2C_H1 UR0605B 100KHz
AP LPSS I2C5 PCH_I2C_AUDIO DA7219 100KHz
AP LPSS I2C6 PCH_I2C_TRACPAD TRACPAD(TBD) 100KHz

LPSS I2C7 PCH_I2C_TOUCHSCREEN TOUCHSCREEN 100KHz

B
AP (TBD) B

AP PMC I2C PCH_PMIC_I2C RT5077A 100KHz

A A

Bitland Information Technology Co.,Ltd.

Page Name
I2C MAP
Size Project Name Rev
C
Phaser 1.3
Date: Thursday, November 22, 2018 Sheet 5 of 43
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

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D D

U4B
DDR4_LP3_LP4 DDR4_LP3_LP4
U4A DDR_1B_DQ<8> AY3 BJ24 DDR_1A_DQS_0_P
17 DDR_1B_DQ<8> DDR_1B_DQ<9> MEM_CH1_DQB8 MEM_CH1_DQSA0_P DDR_1A_DQS_0_P 17
DDR4_LP3_LP4 DDR4_LP3_LP4 BD3 BK25 DDR_1A_DQS_0_N
DDR_0B_DQ<8> DDR_0A_DQS_0_P 17 DDR_1B_DQ<9> DDR_1B_DQ<10> MEM_CH1_DQB9 MEM_CH1_DQSA0 DDR_1A_DQS_0_N 17
BJ36 AT53 BD1
16 DDR_0B_DQ<8> DDR_0B_DQ<9> MEM_CH0_DQB8 MEM_CH0_DQSA0_P DDR_0A_DQS_0_N DDR_0A_DQS_0_P 16 17 DDR_1B_DQ<10> DDR_1B_DQ<11> MEM_CH1_DQB10
16 DDR_0B_DQ<9> BK37 AT55 17 DDR_1B_DQ<11> BC3 BD25 DDR_1A_DQS_1_P
DDR_0B_DQ<10> BJ35 MEM_CH0_DQB9 MEM_CH0_DQSA0 DDR_0A_DQS_0_N 16 DDR_1B_DQ<12> AY1 MEM_CH1_DQB11 MEM_CH1_DQSA1_P BF25 DDR_1A_DQS_1_N DDR_1A_DQS_1_P 17
16 DDR_0B_DQ<10> DDR_0B_DQ<11> MEM_CH0_DQB10 DDR_0A_DQS_1_P 17 DDR_1B_DQ<12> DDR_1B_DQ<13> MEM_CH1_DQB12 MEM_CH1_DQSA1 DDR_1A_DQS_1_N 17
16 DDR_0B_DQ<11> BL36 AW49 17 DDR_1B_DQ<13> BA3
DDR_0B_DQ<12> BJ39 MEM_CH0_DQB11 MEM_CH0_DQSA1_P AW48 DDR_0A_DQS_1_N DDR_0A_DQS_1_P 16 DDR_1B_DQ<14> BA2 MEM_CH1_DQB13 BL18 DDR_1A_DQS_2_P
16 DDR_0B_DQ<12> DDR_0B_DQ<13> MEM_CH0_DQB12 MEM_CH0_DQSA1 DDR_0A_DQS_1_N 16 17 DDR_1B_DQ<14> DDR_1B_DQ<15> MEM_CH1_DQB14 MEM_CH1_DQSA2_P DDR_1A_DQS_2_P 17
BL40 BE2 BJ18 DDR_1A_DQS_2_N
16 DDR_0B_DQ<13> DDR_0B_DQ<14> MEM_CH0_DQB13 DDR_0A_DQS_2_P 17 DDR_1B_DQ<15> DDR_1B_DQ<0> MEM_CH1_DQB15 MEM_CH1_DQSA2 DDR_1A_DQS_2_N 17
16 DDR_0B_DQ<14> BJ40 BC54 17 DDR_1B_DQ<0> AR8
DDR_0B_DQ<15> BK41 MEM_CH0_DQB14 MEM_CH0_DQSA2_P BB53 DDR_0A_DQS_2_N DDR_0A_DQS_2_P 16 DDR_1B_DQ<1> AN15 MEM_CH1_DQB0 AV19 DDR_1A_DQS_3_P
16 DDR_0B_DQ<15> DDR_0B_DQ<0> MEM_CH0_DQB15 MEM_CH0_DQSA2 DDR_0A_DQS_2_N 16 17 DDR_1B_DQ<1> DDR_1B_DQ<2> MEM_CH1_DQB1 MEM_CH1_DQSA3_P DDR_1A_DQS_3_P 17
16 DDR_0B_DQ<0> BA35 17 DDR_1B_DQ<2> AN17 AV21 DDR_1A_DQS_3_N
DDR_0B_DQ<1> AY33 MEM_CH0_DQB0 AR41 DDR_0A_DQS_3_P DDR_1B_DQ<3> AU12 MEM_CH1_DQB2 MEM_CH1_DQSA3 DDR_1A_DQS_3_N 17
16 DDR_0B_DQ<1> DDR_0B_DQ<2> MEM_CH0_DQB1 MEM_CH0_DQSA3_P DDR_0A_DQS_3_N DDR_0A_DQS_3_P 16 17 DDR_1B_DQ<3> DDR_1B_DQ<4> MEM_CH1_DQB3
BA33 AR43 AN12 AR13 DDR_1B_DQS_0_P
16 DDR_0B_DQ<2> DDR_0B_DQ<3> MEM_CH0_DQB2 MEM_CH0_DQSA3 DDR_0A_DQS_3_N 16 17 DDR_1B_DQ<4> DDR_1B_DQ<5> MEM_CH1_DQB4 MEM_CH1_DQSB0_P DDR_1B_DQS_0_P 17
16 DDR_0B_DQ<3> AY35 17 DDR_1B_DQ<5> AN13 AR15 DDR_1B_DQS_0_N
DDR_0B_DQ<4> BA37 MEM_CH0_DQB3 AV37 DDR_0B_DQS_0_P DDR_1B_DQ<6> AU13 MEM_CH1_DQB5 MEM_CH1_DQSB0 DDR_1B_DQS_0_N 17
16 DDR_0B_DQ<4> DDR_0B_DQ<5> MEM_CH0_DQB4 MEM_CH0_DQSB0_P DDR_0B_DQS_0_N DDR_0B_DQS_0_P 16 17 DDR_1B_DQ<6> DDR_1B_DQ<7> MEM_CH1_DQB6
16 DDR_0B_DQ<5> AY37 AV35 17 DDR_1B_DQ<7> AU15 BB3 DDR_1B_DQS_1_P
DDR_0B_DQ<6> AY39 MEM_CH0_DQB5 MEM_CH0_DQSB0 DDR_0B_DQS_0_N 16 DDR_1B_DQ<24> AP3 MEM_CH1_DQB7 MEM_CH1_DQSB1_P BC2 DDR_1B_DQS_1_N DDR_1B_DQS_1_P 17
16 DDR_0B_DQ<6> DDR_0B_DQ<7> MEM_CH0_DQB6 DDR_0B_DQS_1_P 17 DDR_1B_DQ<24> DDR_1B_DQ<25> MEM_CH1_DQB24 MEM_CH1_DQSB1 DDR_1B_DQS_1_N 17
BA39 BL38 AU2
16 DDR_0B_DQ<7> DDR_0B_DQ<24> MEM_CH0_DQB7 MEM_CH0_DQSB1_P DDR_0B_DQS_1_N DDR_0B_DQS_1_P 16 17 DDR_1B_DQ<25> DDR_1B_DQ<26> MEM_CH1_DQB25
16 DDR_0B_DQ<24> BL34 BJ38 17 DDR_1B_DQ<26> AV3 AW7 DDR_1B_DQS_2_P
DDR_0B_DQ<25> BL30 MEM_CH0_DQB24 MEM_CH0_DQSB1 DDR_0B_DQS_1_N 16 DDR_1B_DQ<27> AW3 MEM_CH1_DQB26 MEM_CH1_DQSB2_P AW8 DDR_1B_DQS_2_N DDR_1B_DQS_2_P 17
16 DDR_0B_DQ<25> DDR_0B_DQ<26> MEM_CH0_DQB25 DDR_0B_DQS_2_P 17 DDR_1B_DQ<27> DDR_1B_DQ<28> MEM_CH1_DQB27 MEM_CH1_DQSB2 DDR_1B_DQS_2_N 17
16 DDR_0B_DQ<26> BJ29 BF31 17 DDR_1B_DQ<28> AN2
DDR_0B_DQ<27> BK29 MEM_CH0_DQB26 MEM_CH0_DQSB2_P BD31 DDR_0B_DQS_2_N DDR_0B_DQS_2_P 16 DDR_1B_DQ<29> AP1 MEM_CH1_DQB28 AT1 DDR_1B_DQS_3_P
16 DDR_0B_DQ<27> DDR_0B_DQ<28> MEM_CH0_DQB27 MEM_CH0_DQSB2 DDR_0B_DQS_2_N 16 17 DDR_1B_DQ<29> DDR_1B_DQ<30> MEM_CH1_DQB29 MEM_CH1_DQSB3_P DDR_1B_DQS_3_P 17
BJ33 AR3 AT3 DDR_1B_DQS_3_N
16 DDR_0B_DQ<28> DDR_0B_DQ<29> MEM_CH0_DQB28 DDR_0B_DQS_3_P 17 DDR_1B_DQ<30> DDR_1B_DQ<31> MEM_CH1_DQB30 MEM_CH1_DQSB3 DDR_1B_DQS_3_N 17
16 DDR_0B_DQ<29> BK33 BJ32 17 DDR_1B_DQ<31> AV1
DDR_0B_DQ<30> BJ34 MEM_CH0_DQB29 MEM_CH0_DQSB3_P BK31 DDR_0B_DQS_3_N DDR_0B_DQS_3_P 16 DDR_1B_DQ<16> AR5 MEM_CH1_DQB31 BH9
16 DDR_0B_DQ<30> DDR_0B_DQ<31> MEM_CH0_DQB30 MEM_CH0_DQSB3 DDR_0B_DQS_3_N 16 17 DDR_1B_DQ<16> DDR_1B_DQ<17> MEM_CH1_DQB16 DDR1 NCTF9
16 DDR_0B_DQ<31> BJ30 17 DDR_1B_DQ<17> BA8 BC13
DDR_0B_DQ<16> BD29 MEM_CH0_DQB31 BG54 DDR_0B_CKE<1> DDR_1B_DQ<18> AU7 MEM_CH1_DQB17 NCTF3 BD11 DDR_1B_CA<5>
16 DDR_0B_DQ<16> DDR_0B_DQ<17> MEM_CH0_DQB16 MEM_CH0_CKE1B DDR_0B_CKE<0> DDR_0B_CKE<1> 16 17 DDR_1B_DQ<18> DDR_1B_DQ<19> MEM_CH1_DQB18 MEM_CH1_CAB5 DDR_1B_CA<5> 17
BF29 DDR0 BH54 AU5 BD13
16 DDR_0B_DQ<17> DDR_0B_DQ<18> MEM_CH0_DQB17 MEM_CH0_CKE0B DDR_0B_CS<0> DDR_0B_CKE<0> 16 17 DDR_1B_DQ<19> DDR_1B_DQ<20> MEM_CH1_DQB19 NCTF6
16 DDR_0B_DQ<18> BH29 BJ42 17 DDR_1B_DQ<20> BA5 BF11
DDR_0B_DQ<19> BF33 MEM_CH0_DQB18 MEM_CH0_CS0B BF39 DDR_0B_CS<0> 16 DDR_1B_DQ<21> BA7 MEM_CH1_DQB20 NCTF7 BE5 DDR_1B_CA<0>
16 DDR_0B_DQ<19> DDR_0B_DQ<20> MEM_CH0_DQB19 NCTF5 DDR_0B_CS<1> 17 DDR_1B_DQ<21> DDR_1B_DQ<22> MEM_CH1_DQB21 MEM_CH1_CAB0 DDR_1B_CA<0> 17
16 DDR_0B_DQ<20> BC29 BK43 17 DDR_1B_DQ<22> AU8 BH5 DDR_1B_CA<3>
DDR_0B_DQ<21> BD33 MEM_CH0_DQB20 MEM_CH0_CS1B DDR_0B_CS<1> 16 DDR_1B_DQ<23> BA10 MEM_CH1_DQB22 MEM_CH1_CAB3 BH6 DDR_1B_CA<4> DDR_1B_CA<3> 17
16 DDR_0B_DQ<21> DDR_0B_DQ<22> MEM_CH0_DQB21 DDR_0A_CS<1> 17 DDR_1B_DQ<23> MEM_CH1_DQB23 MEM_CH1_CAB4 DDR_1B_CA<4> 17
BF35 BL44 BF13
16 DDR_0B_DQ<22> DDR_0B_DQ<23> MEM_CH0_DQB22 MEM_CH0_CS1A DDR_0A_CS<1> 16 DDR_1A_DQ<0> NCTF8
C 16 DDR_0B_DQ<23> BH35 BD39 17 DDR_1A_DQ<0> BJ26 BG4 DDR_1B_CA<2> C
MEM_CH0_DQB23 NCTF3 BJ43 DDR_0A_CS<0> DDR_1A_DQ<1> BL26 MEM_CH1_DQA0 MEM_CH1_CAB2 BE7 DDR_1B_CA<1> DDR_1B_CA<2> 17
DDR_0A_DQ<0> MEM_CH0_CS0A DDR_0A_CKE<1> DDR_0A_CS<0> 16 17 DDR_1A_DQ<1> DDR_1A_DQ<2> MEM_CH1_DQA1 MEM_CH1_CAB1 DDR_1B_CA<1> 17
16 DDR_0A_DQ<0> AR53 BF54 17 DDR_1A_DQ<2> BJ27
DDR_0A_DQ<1> AP55 MEM_CH0_DQA0 MEM_CH0_CKE1A BF55 DDR_0A_CKE<0> DDR_0A_CKE<1> 16 DDR_1A_DQ<3> BK27 MEM_CH1_DQA2 BK11
16 DDR_0A_DQ<1> DDR_0A_DQ<2> MEM_CH0_DQA1 MEM_CH0_CKE0A DDR_0A_CKE<0> 16 17 DDR_1A_DQ<3> DDR_1A_DQ<4> MEM_CH1_DQA3 NCTF13
AP53 BJ23 BJ12
16 DDR_0A_DQ<2> DDR_0A_DQ<3> MEM_CH0_DQA2 DDR_0B_CLK_P 17 DDR_1A_DQ<4> DDR_1A_DQ<5> MEM_CH1_DQA4 NCTF11
16 DDR_0A_DQ<3> AN54 BE49 17 DDR_1A_DQ<5> BK23 BK9
DDR_0A_DQ<4> AU54 MEM_CH0_DQA3 MEM_CH0_CLKB_P BE51 DDR_0B_CLK_N DDR_0B_CLK_P 16 DDR_1A_DQ<6> BJ22 MEM_CH1_DQA5 NCTF14 BJ11
16 DDR_0A_DQ<4> DDR_0A_DQ<5> MEM_CH0_DQA4 MEM_CH0_CLKB DDR_0B_CLK_N 16 17 DDR_1A_DQ<6> DDR_1A_DQ<7> MEM_CH1_DQA6 NCTF10 DDR_1A_CA<5>
16 DDR_0A_DQ<5> AV53 17 DDR_1A_DQ<7> BL22 BJ10
DDR_0A_DQ<6> AV55 MEM_CH0_DQA5 BC49 DDR_0A_CLK_P DDR_1A_DQ<8> BD27 MEM_CH1_DQA7 MEM_CH1_CAA5 BJ4 DDR_1A_CA<5> 17
16 DDR_0A_DQ<6> DDR_0A_DQ<7> AW53 MEM_CH0_DQA6 MEM_CH0_CLKA_P DDR_0A_CLK_N DDR_0A_CLK_P 16 17 DDR_1A_DQ<8> DDR_1A_DQ<9> MEM_CH1_DQA8 NCTF12 DDR_1A_CA<2>
BC48 BF27 BL6
16 DDR_0A_DQ<7> DDR_0A_DQ<8> MEM_CH0_DQA7 MEM_CH0_CLKA DDR_0A_CLK_N 16 17 DDR_1A_DQ<9> DDR_1A_DQ<10> MEM_CH1_DQA9 MEM_CH1_CAA2 DDR_1A_CA<1> DDR_1A_CA<2> 17
16 DDR_0A_DQ<8> AU51 17 DDR_1A_DQ<10> BH27 BJ5
DDR_0A_DQ<9> AU48 MEM_CH0_DQA8 BD45 DDR_1A_DQ<11> BC27 MEM_CH1_DQA10 MEM_CH1_CAA1 BJ9 DDR_1A_CA<3> DDR_1A_CA<1> 17
16 DDR_0A_DQ<9> DDR_0A_DQ<10> AU49 MEM_CH0_DQA9 NCTF4 17 DDR_1A_DQ<11> DDR_1A_DQ<12> MEM_CH1_DQA11 MEM_CH1_CAA3 DDR_1A_CA<0> DDR_1A_CA<3> 17
16 DDR_0A_DQ<10> BH50 17 DDR_1A_DQ<12> BH21 BJ6
DDR_0A_DQ<11> BA46 MEM_CH0_DQA10 NCTF8 BH47 DDR_0B_CA<5> DDR_1A_DQ<13> BF23 MEM_CH1_DQA12 MEM_CH1_CAA0 BJ8 DDR_1A_CA<4> DDR_1A_CA<0> 17
16 DDR_0A_DQ<11> DDR_0A_DQ<12> BA48 MEM_CH0_DQA11 MEM_CH0_CAB5 DDR_0B_CA<5> 16 17 DDR_1A_DQ<13> DDR_1A_DQ<14> MEM_CH1_DQA13 MEM_CH1_CAA4 DDR_1A_CA<4> 17
BF45 BD23
16 DDR_0A_DQ<12> DDR_0A_DQ<13> BA49 MEM_CH0_DQA12 NCTF6 DDR_0B_CA<0> 17 DDR_1A_DQ<14> DDR_1A_DQ<15> MEM_CH1_DQA14
16 DDR_0A_DQ<13> BH43 17 DDR_1A_DQ<15> BF21 BF17 DDR_1B_CLK_P
DDR_0A_DQ<14> BA51 MEM_CH0_DQA13 MEM_CH0_CAB0 BD41 DDR_0B_CA<3> DDR_0B_CA<0> 16 DDR_1A_DQ<16> BK19 MEM_CH1_DQA15 MEM_CH1_CLKB_P BD17 DDR_1B_CLK_N DDR_1B_CLK_P 17
16 DDR_0A_DQ<14> DDR_0A_DQ<15> AR51 MEM_CH0_DQA14 MEM_CH0_CAB3 DDR_0B_CA<3> 16 17 DDR_1A_DQ<16> DDR_1A_DQ<17> MEM_CH1_DQA16 MEM_CH1_CLKB DDR_1B_CLK_N 17
16 DDR_0A_DQ<15> BH51 17 DDR_1A_DQ<17> BJ20
DDR_0A_DQ<16> AY55 MEM_CH0_DQA15 NCTF9 BD43 DDR_0B_CA<4> DDR_1A_DQ<18> BL20 MEM_CH1_DQA17 BF15 DDR_1A_CLK_P
16 DDR_0A_DQ<16> DDR_0A_DQ<17> BA54 MEM_CH0_DQA16 MEM_CH0_CAB4 DDR_0B_CA<2> DDR_0B_CA<4> 16 17 DDR_1A_DQ<18> DDR_1A_DQ<19> MEM_CH1_DQA18 MEM_CH1_CLKA_P DDR_1A_CLK_P 17
BF43 BJ21 BH15 DDR_1A_CLK_N
16 DDR_0A_DQ<17> DDR_0A_DQ<18> BA53 MEM_CH0_DQA17 MEM_CH0_CAB2 DDR_0B_CA<1> DDR_0B_CA<2> 16 17 DDR_1A_DQ<19> DDR_1A_DQ<20> MEM_CH1_DQA19 MEM_CH1_CLKA DDR_1A_CLK_N 17
16 DDR_0A_DQ<18> BF41 17 DDR_1A_DQ<20> BJ17
DDR_0A_DQ<19> AY53 MEM_CH0_DQA18 MEM_CH0_CAB1 BG52 DDR_0B_CA<1> 16 DDR_1A_DQ<21> BJ16 MEM_CH1_DQA20 BJ13 DDR_1B_CKE<0>
16 DDR_0A_DQ<19> DDR_0A_DQ<20> BC53 MEM_CH0_DQA19 NCTF7 17 DDR_1A_DQ<21> DDR_1A_DQ<22> MEM_CH1_DQA21 MEM_CH1_CKE0B DDR_1B_CKE<1> DDR_1B_CKE<0> 17
16 DDR_0A_DQ<20> 17 DDR_1A_DQ<22> BK15 BL12
DDR_0A_DQ<21> BD55 MEM_CH0_DQA20 BK45 DDR_1A_DQ<23> BL16 MEM_CH1_DQA22 MEM_CH1_CKE1B BF1 DDR_1B_CS<0> DDR_1B_CKE<1> 17
16 DDR_0A_DQ<21> DDR_0A_DQ<22> BE54 MEM_CH0_DQA21 NCTF14 DDR_0A_CA<2> 17 DDR_1A_DQ<23> DDR_1A_DQ<24> MEM_CH1_DQA23 MEM_CH1_CS0B DDR_1B_CS<1> DDR_1B_CS<0> 17
BJ46 BA21 BF2
16 DDR_0A_DQ<22> DDR_0A_DQ<23> BD53 MEM_CH0_DQA22 MEM_CH0_CAA2 DDR_0A_CA<1> DDR_0A_CA<2> 16 17 DDR_1A_DQ<24> DDR_1A_DQ<25> MEM_CH1_DQA24 MEM_CH1_CS1B DDR_1B_CS<1> 17
16 DDR_0A_DQ<23> BJ44 17 DDR_1A_DQ<25> AY23 BC7
DDR_0A_DQ<24> AN43 MEM_CH0_DQA23 MEM_CH0_CAA1 BJ47 DDR_0A_CA<3> DDR_0A_CA<1> 16 DDR_1A_DQ<26> BA23 MEM_CH1_DQA25 NCTF4
16 DDR_0A_DQ<24> DDR_0A_DQ<25> AN44 MEM_CH0_DQA24 MEM_CH0_CAA3 DDR_0A_CA<0> DDR_0A_CA<3> 16 17 DDR_1A_DQ<26> DDR_1A_DQ<27> MEM_CH1_DQA26 DDR_1A_CS<0>
16 DDR_0A_DQ<25> BJ45 17 DDR_1A_DQ<27> BA17 BH2
DDR_0A_DQ<26> AR48 MEM_CH0_DQA25 MEM_CH0_CAA0 BK47 DDR_0A_CA<4> DDR_0A_CA<0> 16 DDR_1A_DQ<28> AY21 MEM_CH1_DQA27 MEM_CH1_CS0A BC8 DDR_1A_CS<0> 17
16 DDR_0A_DQ<26> DDR_0A_DQ<27> AU41 MEM_CH0_DQA26 MEM_CH0_CAA4 DDR_0A_CA<4> 16 17 DDR_1A_DQ<28> DDR_1A_DQ<29> MEM_CH1_DQA28 NCTF5 DDR_1A_CS<1>
BJ51 AY17 BG2
16 DDR_0A_DQ<27> DDR_0A_DQ<28> AU43 MEM_CH0_DQA27 NCTF12 17 DDR_1A_DQ<29> DDR_1A_DQ<30> MEM_CH1_DQA29 MEM_CH1_CS1A DDR_1A_CKE<0> DDR_1A_CS<1> 17
16 DDR_0A_DQ<28> BJ52 17 DDR_1A_DQ<30> AY19 BK13
DDR_0A_DQ<29> AN41 MEM_CH0_DQA28 NCTF13 BJ48 DDR_1A_DQ<31> BA19 MEM_CH1_DQA30 MEM_CH1_CKE0A BJ14 DDR_1A_CKE<1> DDR_1A_CKE<0> 17
16 DDR_0A_DQ<29> DDR_0A_DQ<30> AN39 MEM_CH0_DQA29 NCTF10 17 DDR_1A_DQ<31> MEM_CH1_DQA31 MEM_CH1_CKE1A DDR_1A_CKE<1> 17
16 DDR_0A_DQ<30> BJ50
DDR_0A_DQ<31> AU44 MEM_CH0_DQA30 NCTF11 BL50 DDR_0A_CA<5> AY29 DDR_RCOMP_CH0
16 DDR_0A_DQ<31> MEM_CH0_DQA31 MEM_CH0_CAA5 DDR_0A_CA<5> 16 MEM_CH0_RCOMP
AY31 DDR_VREF_DQ_CH0 BC15 DDR_RST_CH1_L
NCTF2 AV29 DDR_VREF_CA_CH0 TP141 MEM_CH1_RESET AY27 DDR_RCOMP_CH1 DDR_RST_CH1_L 17
NCTF1 TP142 MEM_CH1_RCOMP
B DDR_VREF_CA_CH1 B
AV27
1 OF 13 NCTF1 AY25 DDR_VREF_DQ_CH1 TP143
bga1090-intel-gemini-lake NCTF2 TP144
BC43 DDR_RST_CH0_L
MEM_CH0_RESET DDR_RST_CH0_L 16

2 OF 13

DDR_RCOMP_CH0
DDR_RCOMP_CH1
PP1100_VDDQ

R307 R309
110_F 110_F
R0402 R0402 R26 R29
1K_F 1K_F
R0201 R0201
ns ns

GND GND DDR_RST_CH0_L

DDR_RST_CH1_L

PLACE AS CLOSE TO SOC AS POSSIBLE

A A

Bitland Information Technology Co.,Ltd.

Page Name
SOC DRAM I/F
Size Project Name Rev
C
Phaser 1.3
Date: Thursday, November 22, 2018 Sheet 6 of 43
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
5 4 3 2 1

D D

U4C

DDI0_TX0_P AH1 AL2 TP_MDSIA_CLKP

29 DDI0_TX0_P DDI0_TX0_N AH3 DDI0_TXP_0 MDSI_A_CLKP AM3 TP_MDSIA_CLKN
29 DDI0_TX0_N DDI0_TXN_0 MDSI_A_CLKN
PP3300_PD_A DDI0_TX1_P AE2 AG13 TP_MDSIC_CLKP
29 DDI0_TX1_P DDI0_TX1_N AE3 DDI0_TXP_1 MDSI_C_CLKP AG12 TP_MDSIC_CLKN
USB C PORT 0 29 DDI0_TX1_N DDI0_TXN_1 DDI0/DDI_B MDSI_C_CLKN
DDI0_TX2_P AJ2
R21 29 DDI0_TX2_P DDI0_TX2_N AJ3 DDI0_TXP_2 AN5 TP_MDSIA_D0_P
29 DDI0_TX2_N DDI0_TXN_2 MDSI_A_DP_0 AN7 TP_MDSIA_D0_N
100K_J MDSI_A_DN_0
DDI0_TX3_P AG2
R0201 29 DDI0_TX3_P DDI0_TX3_N DDI0_TXP_3 TP_MDSIA_D1_P
AG3 AJ15
29 DDI0_TX3_N DDI0_TXN_3 MDSI_A_DP_1 AJ17 TP_MDSIA_D1_N
DDI0_AUX_P C336 0.1uF/16V/X5R C0201 DDI0_AUX_C_P AC12 MDSI MDSI_A_DN_1
29 DDI0_AUX_P DDI0_AUX_N C337 0.1uF/16V/X5R C0201 DDI0_AUX_C_N AC10 DDI0_AUXP AJ7 TP_MDSIA_D2_P
29 DDI0_AUX_N DDI0_AUXN MDSI_A_DP_2 AJ5 TP_MDSIA_D2_N
18,29 USB_C0_HPD_1V8_ODL
USB_C0_HPD_1V8_ODL C39
DDI0_HPD 3.3(Default)/1.8V
MDSI_A_DN_2
TP_MDSIA_D3_P
ALL NC
R22 AJ10
B43 MDSI_A_DP_3 AJ12 TP_MDSIA_D3_N
100K_J DDI0_DDC_SCL 3.3(Default)/1.8V MDSI_A_DN_3
C43
R0201 DDI0_DDC_SDA 3.3(Default)/1.8V TP_MDSIC_D0_P
AG15
MDSI_C_DP_0 AG17 TP_MDSIC_D0_N
DDI1_TX0_P AA2 MDSI_C_DN_0
39 DDI1_TX0_P DDI1_TX0_N AA3 DDI1_TXP_0 AG8 TP_MDSIC_D1_P
GND 39 DDI1_TX0_N DDI1_TXN_0 MDSI_C_DP_1 AG10 TP_MDSIC_D1_N
PP3300_PD_A DDI1_TX1_P Y3 MDSI_C_DN_1
39 DDI1_TX1_P DDI1_TX1_N Y1 DDI1_TXP_1 DDI1/DDI_C AG7 TP_MDSIC_D2_P
39 DDI1_TX1_N DDI1_TXN_1 MDSI_C_DP_2 AG5 TP_MDSIC_D2_N
DDI1_TX2_P AD1 MDSI_C_DN_2
C C
USB C PORT 1 R459 39 DDI1_TX2_P
39 DDI1_TX2_N
DDI1_TX2_N AD3 DDI1_TXP_2
DDI1_TXN_2 MDSI_C_DP_3
AE15 TP_MDSIC_D3_P
100K_J AE17 TP_MDSIC_D3_N
DDI1_TX3_P AC2 MDSI_C_DN_3
R0201 39 DDI1_TX3_P DDI1_TX3_N DDI1_TXP_3
AC3
39 DDI1_TX3_N DDI1_TXN_3
ns
DDI1_AUX_P C338 0.1uF/16V/X5R C0201 DDI1_AUX_C_P AC7
39 DDI1_AUX_P DDI1_AUX_N C339 0.1uF/16V/X5R C0201 DDI1_AUX_C_N AC5 DDI1_AUXP
39 DDI1_AUX_N DDI1_AUXN
C42 R53 TP_PCH_GPIO47
DDI1_DDC_SCL 3.3(Default)/1.8V 1.8V MIPI_I2C_SCL TP31
R460 A42
USB_C1_HPD_1V8_ODL C38 DDI1_DDC_SDA 3.3(Default)/1.8V R54 TP_PCH_GPIO46
100K_J 18,39 USB_C1_HPD_1V8_ODL DDI1_HPD MIPI_I2C_SDA TP37
3.3(Default)/1.8V 1.8V
R0201
ns GP_INTD_DSI_TE2 20
CHANGE C338, C339 TO ZERO OHM R IF SUB-BOARD HAS CAPS T53 R502 0_J R0201 GP_INTD_DSI_TE2
DNS R459, R460 IF SUB-BOARD HAS CAPS EDP_TX0_P 1.8V MDSI_C_TE TP_WIFI_RST_N TP72
AE12 T55
26 EDP_TX0_P EDP_TX0_N AE13 EDP_TXP_0 1.8V MDSI_A_TE TP135
GND 26 EDP_TX0_N EDP_TXN_0
EDP_TX1_P AC15
26 EDP_TX1_P EDP_TX1_N AC17 EDP_TXP_1 eDP/DDI_A
26 EDP_TX1_N EDP_TXN_1 AL5 MCSI1_RCOMP
EDP_TX2_P AE10 MDSI_RCOMP
26 EDP_TX2_P EDP_TX2_N AE8 EDP_TXP_2
26 EDP_TX2_N EDP_TXN_2 R1
LOCAL DISPLAY PANEL 26 EDP_TX3_P
EDP_TX3_P AE5
EDP_TXP_3 150.0_F
EDP_TX3_N AE7
26 EDP_TX3_N EDP_TXN_3 r0201
EDP_AUX_PANEL_P W17
26 EDP_AUX_PANEL_P EDP_AUX_PANEL_N W15 EDP_AUXP
26 EDP_AUX_PANEL_N EDP_AUXN
EDP_HPD_PANEL_1V8_ODL B39 GND
EDP_HPD 3.3/1.8(Default)V
SOC_EDP_BKLTCTL_1V8 B41
26 SOC_EDP_BKLTCTL_1V8 SOC_EDP_BKLTEN C40 PNL0_BKLCTL 3.3(Default)/1.8V
26 SOC_EDP_BKLTEN EN_PP3300_EDP_DX C41 PNL0_BKLTEN 3.3(Default)/1.8V
35 EN_PP3300_EDP_DX PNL0_VDDEN 3.3(Default)/1.8V
EDP_PLLOBS_DP AA5
EDP_RCOMP_P
B EDP_PLLOBS_DN B
AA7
R2 EDP_RCOMP
100_F 3 OF 13
R0201

PP1800_SOC_A

(LDS) R731
100K_J
R0201

EDP_HPD_PANEL_1V8_ODL

3
D
Q78
EDP_HPD_PANEL 1 LSI1012N3T5G
26 EDP_HPD_PANEL
G S sot883

2
GND

A A

Bitland Information Technology Co.,Ltd.

Page Name
SOC EDP/MIPI/DDI
Size Project Name Rev
C
Phaser 1.3
Date: Thursday, November 22, 2018 Sheet 7 of 43
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
5 4 3 2 1

CLKDRV_RCOMP

U4D
SD CARD I/F FOR HIGHER SPEED DEVICE
R7
56_F L10 H1 USB3_P5_SD_TX_C_P C346 0.1uF/10V/X5R C0201
PCIE_REF_CLK_RCOMP SATA_P1_USB3_P5_TXP H2 USB3_P5_SD_TX_C_N C349 0.1uF/10V/X5R C0201 USB3_P5_SD_TX_P 23
r0201 SATA_P1_USB3_P5_TXN USB3_P5_SD_TX_N 23
R12
TP162
TP163
R10 PCIE_CLKOUT0P
PCIE_CLKOUT0N
SATA/USB3
SATA_P1_USB3_P5_RXP
H4 USB3_P5_SD_RX_P
USB3_P5_SD_RX_P 23
SD CARD
G5 USB3_P5_SD_RX_N
N7 SATA_P1_USB3_P5_RXN USB3_P5_SD_RX_N 23
TP112 PCIE_CLKOUT1P
GND N5 C272, C303 USE 0R PER AE RECOMMENDED
D TP113 PCIE_CLKOUT1N D
PCIe B15 USB3_P0_C0_TX_C_P C272 0_J R0201
R7 USB3_P0_TXP C15 USB3_P0_C0_TX_C_N C303 0_J R0201 USB3_P0_C0_TX_P 29
R5 PCIE_CLKOUT2P USB3_P0_TXN USB3_P0_C0_TX_N 29
PCIE_CLKOUT2N F15 USB3_P0_C0_RX_P
28 PCIE_WLAN_CLK_P
PCIE_WLAN_CLK_P N8
PCIE_CLKOUT3P
USB3_P0_RXP
USB3_P0_RXN
D15 USB3_P0_C0_RX_N
USB3_P0_C0_RX_P
USB3_P0_C0_RX_N
29
29
TYPE C PORT 0
PCIE_WLAN_CLK_N N10
28 PCIE_WLAN_CLK_N PCIE_CLKOUT3N USB3 C14 USB3_P1_A0_TX_C_P C305 0.1uF/10V/X5R C0201
USB3_P1_TXP A14 USB3_P1_A0_TX_C_N C307 0.1uF/10V/X5R C0201 USB3_P1_A0_TX_P 30
PCIE_PCH_TX_WLAN_RX_C_P E2 USB3_P1_TXN USB3_P1_A0_TX_N 30
28 PCIE_PCH_TX_WLAN_RX_C_P PCIE_PCH_TX_WLAN_RX_C_N F2 PCIE_P0_TXP J11 USB3_P1_A0_RX_P
28 PCIE_PCH_TX_WLAN_RX_C_N PCIE_P0_TXN USB3_P1_RXP
USB3_P1_RXN
H11 USB3_P1_A0_RX_N
USB3_P1_A0_RX_P
USB3_P1_A0_RX_N
30
30
TYPE A PORT 0
PCIE_PCH_RX_WLAN_TX_P G7
28 PCIE_PCH_RX_WLAN_TX_P PCIE_PCH_RX_WLAN_TX_N PCIE_P0_RXP
28 PCIE_PCH_RX_WLAN_TX_N H6
PCIE_P0_RXN C10 USB3_P4_C1_TX_C_P R266 0_J R0201
PCIE_P3_USB3_P4_TXP A10 USB3_P4_C1_TX_C_N R277 0_J R0201 USB3_P4_C1_TX_P 39
A7 PCIE_P3_USB3_P4_TXN USB3_P4_C1_TX_N 39
C7 PCIE_P1_TXP PCIe/USB3 H9 USB3_P4_C1_RX_P
PCIE_P1_TXN PCIE_P3_USB3_P4_RXP
PCIE_P3_USB3_P4_RXN
F9 USB3_P4_C1_RX_N USB3_P4_C1_RX_P
USB3_P4_C1_RX_N
39
39
TYPE C PORT 1, sub board
D4
E5 PCIE_P1_RXP C11 USB3_P3_A1_TX_C_P R279 0_J R0201
PCIE_P1_RXN PCIE_P4_USB3_P3_TXP B11 USB3_P3_A1_TX_C_N R280 0_J R0201 USB3_P3_A1_TX_P 39
C9 PCIE_P4_USB3_P3_TXN USB3_P3_A1_TX_N 39
B9 PCIE_P2_TXP D11 USB3_P3_A1_RX_P
PCIE_P2_TXN PCIE_P4_USB3_P3_RXP
PCIE_P4_USB3_P3_RXN
F11 USB3_P3_A1_RX_N USB3_P3_A1_RX_P
USB3_P3_A1_RX_N
39
39
TYPE A PORT 1, sub board
E7
F6 PCIE_P2_RXP B13 USB3_P2_TX_C_P C365 0.1uF/10V/X5R C0201 USB3_P2_WCAM_TX_P
PCIE_P2_RXN PCIE_P5_USB3_P2_TXP C13 USB3_P2_TX_C_N USB3_P2_WCAM_TX_N TP168
C410 0.1uF/10V/X5R C0201
PCIE_P5_USB3_P2_TXN TP169
F13 USB3_P2_WCAM_RX_P
PCIE_P5_USB3_P2_RXP D13 USB3_P2_WCAM_RX_N
TP166 WFC CAMERA
PCIE_CLKREQ0_ODL PCIE_P5_USB3_P2_RXN TP167
A46
TP157 PCIE_CLKREQ1_ODL C45 PCIE_CLKREQ0 3.3(Default)/1.8V
C5
TP145 PCIE_CLKREQ2_ODL PCIE_CLKREQ1 3.3/1.8(Default)V PCIE2_USB3_SATA3_RCOMP
B45 C6
TP171 WLAN_PCIE_CLKREQ_ODL C44 PCIE_CLKREQ2 3.3(Default)/1.8V PCIE2_USB3_SATA3_RCOMP_P
PCIE_CLKREQ3 3.3(Default)/1.8V
R3 IF YOU KEEP CAPS ON THE MLB FOR TYPE-A AND TYPE-C TX LINES
WIFI_DISABLE_L F47 AA10 100_F
28 WIFI_DISABLE_L LTE_WAKE_L D47 PCIE_WAKE0 3.3(Default)/1.8V NC1 AA8 MAKE SURE TO REMOVE THEM FROM THE DAUGHTERBOARD
TP103 PCIE_WAKE1 3.3/1.8(Default)V NC2 R0201
C F45 C
TP164 WLAN_PCIE_WAKE_ODL D50 PCIE_WAKE2 3.3(Default)/1.8V W13
PCIE_WAKE3 3.3(Default)/1.8V SSIC NC5 W12
NC4

3V3 IO TOLERANT SATA NC3

U15

J3 U7
J2 SATA_P0_TXP USB2_DP0 U5 USB2_P0_C0_P 31
SATA_P0_TXN USB2_DN0 USB2_P0_C0_N 31 TYPE C PORT 0
J7 N2
SATA_P0_RXP USB2_DP1 USB2_P1_A0_P 30
J5 N3
SATA_P0_RXN USB2_DN1 USB2_P1_A0_N 30 TYPE A PORT 0
L2
USB2_DP2 USB2_P2_BT_P 28
L3
USB2_DN2 USB2_P2_BT_N 28 WIFI-BT
R13
USB2_DP3 USB2_P3_A1_P 39
USB2 R15
USB2_DN3 USB2_P3_A1_N 39 TYPE A PORT 1
M1
USB2_DP4 M3 USB2_P4_C1_P 39
USB2_DN4 USB2_P4_C1_N 39 TYPE C PORT 1
R2
USB2_DP5 R3 USB2_P5_SD_P 23
USB2_DN5 USB2_P5_SD_N 23 USB-SD CARD
P1
USB2_DP6 USB2_P6_UCAM_P 26
P3
USB2_DN6 USB2_P6_UCAM_N 26 CAMERA UFC
U8
USB2_DP7 USB2_P7_WCAM_P 26
U10
USB2_DN7 USB2_P7_WCAM_N 26 CAMERA WFC
U12 USB2_RCOMP
USB2_RCOMP
V1 USB_OTG_ID_HOSTORSLAVE R747 0_J R0201
USB2_DUALROLE V3 USB_OTG R9
USB2_VBUS_SNS U54 USB_A_OC_ODL R331 0_J R0201
1.8V USB2_OC0 USB_A0_OC_ODL 30 113_F
U53 R332 0_J R0201 PP1800_SOC_A
B 1.8V USB2_OC1 USB_A1_OC_ODL 39 R0201 B
USB_C_OC_ODL R326 0_J R0201
USB_C_OC 18
4 OF 13 USB_C1_OC_ODL
R329 0_J R0201
INTERNAL PULL-UP GND R9093
100K_J
R0201
left NC and keep component being
stuffed for debug purpose
USB_OTG
PP1800_SOC_A

PP3300_WLAN_DX
(NGF)
R10
10K_F
r0201
2

5
G

WLAN_PCIE_CLKREQ_ODL 1 6 3 4
WLAN_PCIE_CLKREQ_3V3_ODL 28
S

Q1B
LBSS138DW1T1G Q1A
sot363 LBSS138DW1T1G
ns sot363
ns

PP1800_SOC_A

PP3300_WLAN_DX

A R11 A
10K_F
r0201
2

5
G

WLAN_PCIE_WAKE_ODL 1 6 3 4 WLAN_PCIE_WAKE_3V3_ODL 28
S

Bitland Information Technology Co.,Ltd.

D

Q2B
LBSS138DW1T1G Q2A Page Name
sot363 LBSS138DW1T1G SOC PCIE/USB/SATA
ns sot363 Size
ns Project Name Rev
C
Phaser 1.3
AVOIDS ANY LEAKAGE WITHOUT SOFTWARE EFFORTS Date: Tuesday, November 27, 2018 Sheet 8 of 43
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
5 4 3 2 1

(MIC)
DMIC_CLK1 26

PCH_SLP_S0_L PCH_SLP_S0_L 11,33

TP66
Q40

1
LSI1012N3T5G
D D
sot883

G
DMIC_CLK1_R R300 20_J R0402 DMIC_CLK1 3 2
DMIC_CLK1_G 26

S
R173 0_J R0201
ns
WITH WOV WITH EC:
STUFF: R299, R172
DNS: R300, 317
18 EC_I2S_SCLK
R281 20_J R0402 I2S0_SCLK_R
I2S0_SFRM_R
WOV
R295 20_J R0402
18 EC_I2S_SFRM R298 20_J R0402 I2S0_PCH_RX
18 EC_I2S_TX_PCH_RX WITHOUT WOV WITH EC:
C571 C572 C573 DMIC_DATA_R R317 20_J R0402 DMIC_DATA
DMIC_DATA 26
STUFF:R300, 317
2.2pF/25V/NPO 2.2pF/25V/NPO 2.2pF/25V/NPO DNS: R299, R172
C0402 C0402 C0402

GND GND GND PP1800_SOC_A

R407 R187 R283 R358 R363

20K_F 20K_F 20K_F 20K_F 20K_F
r0201 r0201 r0201 r0201 r0201
ns ns ns ns

ESPI_CS_L
ESPI_IO0
C ESPI_IO1 C
ESPI_IO2
ESPI_IO3

ESPI_CLK

U4G
R365
C26 L29 20K_F
TP70 I2S0_SCLK_R AVS_I2S0_MCLK 1.8V SDCARD SDCARD_CLK
B25 r0201
TP53 I2S0_SFRM_R C25 AVS_I2S0_BCLK 1.8V M29
TO-EC TP54
TP57
I2S0_PCH_RX
I2S0_PCH_TX
C24 AVS_I2S0_WS_SYNC
AVS_I2S0_SDI
1.8V
1.8V
SDCARD_D0
SDCARD_D1
P29
B23 M27
TP59 AVS_I2S0_SDO 1.8V AUDIO-AVS SDCARD_D2 P27
LTE_OFF_ODL M23 SDCARD_D3 L27 GND
TP96 I2S_SCLK_SPKR L21 AVS_I2S1_MCLK 1.8V SDCARD_CMD L25
24 I2S_SCLK_SPKR I2S_SFRM_SPKR J21 AVS_I2S1_BCLK 1.8V 1.8V SDCARD_CD P25
SPEAKER AMP 24 I2S_SFRM_SPKR
28 WLAN_PE_RST
WLAN_PE_RST
I2S_PCH_TX_SPKR_RX
M21 AVS_I2S1_WS_SYNC
AVS_I2S1_SDI
1.8V
1.8V
3.3(Default)/1.8V
1.8V
SDCARD_LVL_WP
SDCARD_PWR_DWN
L23
P23

I2S_SCLK_HP
24 I2S_PCH_TX_SPKR_RX
I2S2_SCLK_R
AVS_I2S1_SDO 1.8V
SDCARD_RCOMP
J25 native SD card support dropped
R32 20_J R0402 A22
24 I2S_SCLK_HP I2S_SFRM_HP I2S2_SFRM_R AVS_HDA_BCLK 1.8V
R33 20_J R0402 C23 1.8V
24 I2S_SFRM_HP I2S_PCH_RX_HP_TX R36 20_J R0402 I2S2_PCH_RX B21 AVS_HDA_WS_SYNC
HEADPHONE 24 I2S_PCH_RX_HP_TX
24 I2S_PCH_TX_HP_RX
I2S_PCH_TX_HP_RX R37 20_J R0402 I2S2_PCH_TX C22 AVS_HDA_SDI
AVS_HDA_SDO
1.8V
1.8V 3.3(Default)/1.8V LPC_CLKOUT0
C37 ESPI_CLK_R R285 33_J R0201 ESPI_CLK
ESPI_CLK 18
I2S_MCLK_HP R40 20_J R0402 I2S2_MCLK_R C21 A38 R67 ns 33_J R0201
24 I2S_MCLK_HP AVS_HDA_RST 1.8V 3.3(Default)/1.8V LPC_CLKOUT1
DMIC_CLK1_R B19 LPC/eSPI A34 ESPI_IO0_R R71 33_J R0201 ESPI_IO0
TP51 DMIC_CLK2 DMIC_CLK2_R AVS_DMIC_CLK_A1 1.8V 3.3(Default)/1.8V LPC_AD0 ESPI_IO1_R ESPI_IO1 ESPI_IO0 18
R189 33_F R0201 C20 C34 R73 33_J R0201
26 DMIC_CLK2 DMIC_DATA_R AVS_DMIC_CLK_B1 1.8V 3.3(Default)/1.8V LPC_AD1 ESPI_IO2_R ESPI_IO2 ESPI_IO1 18
C19 B35 R74 33_J R0201
PP1800_SOC_A TP52 TP_GPIO_174 AVS_DMIC_DATA_1 1.8V 3.3(Default)/1.8V LPC_AD2 ESPI_IO3_R ESPI_IO3 ESPI_IO2 18
C18 C35 R76 33_J R0201
TP61 DMIC_CAM2_DATA A18 AVS_DMIC_CLK_AB2 1.8V 3.3(Default)/1.8V LPC_AD3 ESPI_IO3 18 TO-EC
R282 4.7K_J R0201 26 DMIC_CAM2_DATA AVS_DMIC_DATA_2 1.8V C33 R90 ns 33_J R0201
DMIC'S 23 EMMC_CLK EMMC_CLK
3.3(Default)/1.8V
3.3(Default)/1.8V
LPC_CLKRUN
LPC_FRAME
B33 ESPI_CS_L_R R93 33_J R0201 ESPI_CS_L
ESPI_CS_L 18
J13 B37 ESPI_RESET_L_R R128 33_J R0201 ESPI_RESET_L
TP44 EMMC_RCLK EMMC_CLK 1.8V 3.3(Default)/1.8V LPC_SERIRQ ESPI_RESET_L 18
L15
TP41 EMMC_RCLK 1.8V
23 EMMC_RCLK EMMC_DAT0
23 EMMC_DAT0 M19 1.8V R198
B EMMC_DAT1 H19 EMMC_D0 B29 PCH_SPI_CLK_R R591 33_J R0201 PCH_SPI_CLK B
23 EMMC_DAT1 EMMC_D1 1.8V 1.8V FST_SPI_CLK PCH_SPI_CLK 19 100K_F
R590 EMMC_DAT2 J19
TP42 EMMC_DAT3 EMMC_D2 1.8V R0201
Quanta: suggest to 100K_F 23 EMMC_DAT2 23 EMMC_DAT3 P17 1.8V B31 PCH_SPI_MOSI_R R592 33_J R0201 PCH_SPI_MOSI
PCH_SPI_MOSI 19
EMMC_DAT4 EMMC_D3 1.8V FST_SPI_MOSI_IO0
P19 C30 PCH_SPI_MISO R593 33_J R0201 PCH_SPI_MISO_R
replace with 0201 R0201 23 EMMC_DAT4 EMMC_DAT5 EMMC_D4 1.8V eMMC FAST_SPI
1.8V FST_SPI_MISO_IO1 PCH_SPI_MISO_R 19
23 EMMC_DAT5 J15 1.8V 1.8V A30 R640 ns 33_J R0201
EMMC_DAT6 EMMC_D5 FST_SPI_IO2
package L17 C29 R642 ns 33_J R0201
23
23
EMMC_DAT6
EMMC_DAT7
EMMC_DAT7
EMMC_CMD
M17 EMMC_D6
EMMC_D7
1.8V
1.8V
1.8V FST_SPI_IO3 GND TO-FLASH
M13 1.8V C31 PCH_SPI_CS0_L_R R643 33_J R0201 PCH_SPI_CS0_L
PCH_SPI_CS0_L 19
TP43 EMMC_CMD 1.8V FST_SPI_CS0 C32 SPK_PA_EN_R SPK_PA_EN
GND 1.8V R644 33_J R0201 SPK_PA_EN 24
23 EMMC_CMD EMMC_RST_ODL U44 FST_SPI_CS1
23 EMMC_RST_ODL TP_EN_PP3300_EMMC EMMC_RST 1.8V
G51
TP30 RCOMP_EMMC0 L13 EMMC_PWR_EN 3.3(Default)/1.8V
EMMC_RCOMP

R284 7 OF 13
TEST POINTS ON EMMC CLOSE TO SOC 200_F
R0201

GND

A A

Bitland Information Technology Co.,Ltd.

Page Name
SOC AUDIO/EMMC/LPC/SPI
Size Project Name Rev
C
Phaser 1.3
Date: Tuesday, November 27, 2018 Sheet 9 of 43
No extermal PU/PD on GPIO_174, using internal PD for setting VDD2 to 1.2v (GPIO_174) PROPERTY NOTE: this document contains information confidential and property to
R282 is for strapping high to enable eSPI mode (GPIO_175) Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
was obtained with the expressed written consent of Bitland

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 RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
5 4 3 2 1

PP1800_SOC_A

I2C MAY BE PROBLEM IF THE I2C PULL-UP VOLTAGE IS TURNED OFF WHEN DEVICE IS OFF MODE SELECTION: PULL HI =1.8V
PP1800_SOC_A
R395 R396 R660 R661 R312 R313
2.2K_F 2.2K_F 4.7K_J 4.7K_J 2.2K_F 2.2K_F
r0201 r0201 R0201 R0201 r0201 r0201
ns ns R438
U4F 4.7K_J
PCH_I2C_PEN_SCL R0201
U49 M39 H1_SLAVE_SPI_CLK_R
PCH_I2C_PEN_SDA U51 SIO_I2C0_SCL 1.8V 1.8V SIO_SPI_0_CLK H1_SLAVE_SPI_CLK_R 21
LPSS_SPI
SIO_I2C0_SDA 1.8V
J37 H1_SLAVE_SPI_MOSI_R
PCH_I2C_P_SENSOR_SCL U46 LPSS_I2C 1.8V SIO_SPI_0_TXD L39 H1_SLAVE_SPI_MISO H1_SLAVE_SPI_MOSI_R 21
PCH_I2C_P_SENSOR_SDA U48 SIO_I2C1_SCL 1.8V 1.8V SIO_SPI_0_RXD H1_SLAVE_SPI_CS_L_R H1_SLAVE_SPI_MISO 21
L37
D SIO_I2C1_SDA 1.8V 1.8V SIO_SPI_0_FS0 GPIO_81_DEBUG H1_SLAVE_SPI_CS_L_R 21 D
J39
AA39
1.8V SIO_SPI_0_FS1 GPIO_81_DEBUG 12
R239 33_J R0201
TP77 SIO_I2C2_SCL 1.8V TP64
AA41 M37 R23 3.3K_J r0201
TP78 SIO_I2C2_SDA 1.8V 1.8V SIO_SPI_2_CLK
DBG_PCH_I2C_SCL R44 M33 R230 33_J R0201
20 DBG_PCH_I2C_SCL DBG_PCH_I2C_SDA SIO_I2C3_SCL 1.8V 1.8V SIO_SPI_2_TXD TP50
R43 P35 GND
20 DBG_PCH_I2C_SDA SIO_I2C3_SDA 1.8V 1.8V SIO_SPI_2_RXD TP62
P33 R231 33_J R0201
PCH_I2C_H1_SCL 1.8V SIO_SPI_2_FS0 TP63
21 PCH_I2C_H1_SCL R49 P37
PCH_I2C_H1_SDA R51 SIO_I2C4_SCL 1.8V 1.8V SIO_SPI_2_FS1 L35 TP_PCH_GPIO_87_PD DURING RSMRST TP47
21 PCH_I2C_H1_SDA SIO_I2C4_SDA 1.8V 1.8V SIO_SPI_2_FS2 TP36
PCH_I2C_AUDIO_SCL_Q C50 PP1800_SOC_A
PCH_I2C_AUDIO_SDA_Q A50 SIO_I2C5_SCL 3.3/1.8(Default)V
ISH
STEST CONNECTION
SIO_I2C5_SDA 3.3/1.8(Default)V
PCH_I2C_TRACKPAD_SCL C48
PCH_I2C_TRACKPAD_SDA C47 SIO_I2C6_SCL 3.3/1.8(Default)V ISH N54 R327 0_J R0201 R311
SIO_I2C6_SDA 3.3/1.8(Default)V 1.8V SIO_UART0_TXD P53 R328 0_J R0201 PCHTX_MIPI60RX_UART 10,20
1.8V SIO_UART0_RXD PCHRX_MIPI60TX_UART 10,20 4.7K_J
PP1800_SOC_A PCH_I2C_TOUCHSCREEN_SCL B47 N53
PCH_I2C_TOUCHSCREEN_SDA SIO_I2C7_SCL 3.3/1.8(Default)V 1.8V SIO_UART0_RTS TP48 R0201
C46 M55 H1_PCH_INT_ODL ns
SIO_I2C7_SDA 3.3/1.8(Default)V 1.8V SIO_UART0_CTS H1_PCH_INT_ODL 21
R5 10K_F r0201 TP_SMB_ALERT_N A26 L54 PCHTX_UART2 GPIO65 USED FOR DNXMODE WITH PULL-UP
TP_PCH_SMB_CLK SMB_ALERT 3.3(Default)/1.8V 1.8V SIO_UART2_TXD
B27 M53 PCHRX_UART2
TP160 EN_PP3300_WLAN_L C27 SMB_CLK 3.3(Default)/1.8V LPSS SMBus 1.8V SIO_UART2_RXD K53
TP161 SMB_DATA 3.3(Default)/1.8V 1.8V SIO_UART2_RTS TP1
L53 EN_PP3300_DX_LTE_SOC
35 EN_PP3300_WLAN_L 1.8V SIO_UART2_CTS TP101
PLACE R573 NEAR M.2 R336 0_J R0201
H29 R337 0_J R0201 PCHTX_SERVORX_UART 21,22
28 CNVI_CLK_PCH_RX_WLAN_TX_P H31 CNV_WGR_CLK_P PCHTX_MIPI60RX_UART 10,20
28 CNVI_CLK_PCH_RX_WLAN_TX_N CNV_WGR_CLK
ns
PP1800_SOC_A R338 0_J R0201
M31 PCHRX_SERVOTX_UART 21,22
R342 0_J R0201
28 CNVI_D0_PCH_RX_WLAN_TX_P CNV_WGR_D0_P LPSS_UART PCHRX_MIPI60TX_UART 10,20
P31 ns
28 CNVI_D0_PCH_RX_WLAN_TX_N CNV_WGR_D0
R573 D29
28 CNVI_D1_PCH_RX_WLAN_TX_P CNV_WGR_D1_P
20K_F F29
28 CNVI_D1_PCH_RX_WLAN_TX_N CNV_WGR_D1 CNVI
r0201
F35
28 CNVI_CLK_PCH_TX_WLAN_RX_P D35 CNV_WT_CLK_P
CNVI_BRI_DT_R R574 33_J R0201 28 CNVI_CLK_PCH_TX_WLAN_RX_N CNV_WT_CLK
CNVI_RGI_DT_R R575 33_J R0201 CNVI_BRI_DT 28 J35
C C
CNVI_RGI_DT 28 28 CNVI_D0_PCH_TX_WLAN_RX_P H35 CNV_WT_D0_P
28 CNVI_D0_PCH_TX_WLAN_RX_N CNV_WT_D0
L31
28 CNVI_D1_PCH_TX_WLAN_RX_P J31 CNV_WT_D1_P PCH_I2C_AUDIO_SCL_Q R8Q 0_J R0201
28 CNVI_D1_PCH_TX_WLAN_RX_N CNV_WT_D1 PCH_I2C_AUDIO_SCL 24
R156 0_J R0402 WLAN_CLKOUT_LCP_L J29
28 WLAN_CLKOUT_LCP F19 CLKIN_XTAL_LCP
28 WLAN_CLKREQ0 XTAL_CLKREQ 1.8V PCH_I2C_AUDIO_SDA_Q R9Q 0_J R0201
CNVI_BRI_DT_R PCH_I2C_AUDIO_SDA 24
C503 R717 H17
CNVI_BRI_RSP J17 CNV_BRI_DT 1.8V
4.7pF/25V/NPO 10K_F 28 CNVI_BRI_RSP CNV_BRI_RSP 1.8V
CNVI_RGI_DT_R D19
C0201 r0201 CNVI_RGI_RSP CNV_RGI_DT 1.8V
ns 28 CNVI_RGI_RSP D17 1.8V
CNVI_RF_RESET_L F17 CNV_RGI_RSP
28 CNVI_RF_RESET_L CNV_RF_RESET 1.8V
GND
CNVI_WT_RCOMP F33
PP1800_SOC_A PP1800_SOC_A CNV_WT_RCOMP
GND
R6
R1132
150.0_F 6 OF 13
R422 R287 75K_F
r0201
20K_F 20K_F R0201
r0201 r0201
ns ns
PLACEMENMT OF THE LEVEL SHIFTERS AND PULL-UPS DON'T NEED TO BE NEAR AP
GND GND
CNVI_RGI_RSP CNVI_BRI_RSP

PP1800_SOC_A PP1800_PEN_DX
(PEN)
B B

2
PP1800_SOC_A PP3300_TRACKPAD_DX R110 R155
PP1800_SOC_A PP3300_TOUCHSCREEN_DX 2.2K_F 1.5K_J
(TPD) r0201 R0201

5
G
Phaser360s Phaser360s
(TSN)

1
2

R638 R555 PCH_I2C_PEN_SCL 3 4 PCH_I2C_PEN_1V8_SCL 26

S
R100 R104 2.2K_F 1.5K_J
2.2K_F 1.5K_J r0201 R0201
2

5
Q36A
r0201 R0201B
2

LBSS138DW1T1G
G

G
sot363
G

PCH_I2C_TRACKPAD_SCL 1 6 3 4
G

Phaser360/360s Phaser360/360s PCH_I2C_TRACKPAD_3V3_SCL 25

1

PCH_I2C_TOUCHSCREEN_SCL
S

1 6 3 4

S
PCH_I2C_TOUCHSCREEN_3V3_SCL 26 Phaser360s
Q14B
S

Q11B Q11A LBSS138DW1T1G Q14A R4Q 0_J R0201

LBSS138DW1T1G LBSS138DW1T1G sot363 LBSS138DW1T1G ns
sot363 sot363 sot363
Phaser360/360s Phaser360/360s
PP1800_SOC_A PP1800_PEN_DX
PP1800_SOC_A PP3300_TOUCHSCREEN_DX PP1800_SOC_A PP3300_TRACKPAD_DX

2
2

R143 R160
R101 R105 R554 R556 2.2K_F 1.5K_J
2.2K_F 1.5K_J 2.2K_F 1.5K_J r0201 R0201

2
r0201 R0201B r0201 R0201
2

G
Phaser360/360s Phaser360s Phaser360s

1
G

PCH_I2C_PEN_SDA 6 1
G

Phaser360/360s PCH_I2C_PEN_1V8_SDA 26
1

PCH_I2C_TOUCHSCREEN_SDA 1 6 3 4 PCH_I2C_TRACKPAD_SDA 1 6 3 4

S
PCH_I2C_TOUCHSCREEN_3V3_SDA 26 PCH_I2C_TRACKPAD_3V3_SDA 25
S

D
D

Q30B Q15B Q36B

LBSS138DW1T1G Q30A LBSS138DW1T1G Q15A LBSS138DW1T1G
sot363 LBSS138DW1T1G sot363 LBSS138DW1T1G sot363
Phaser360/360s sot363 sot363 Phaser360s
Phaser360/360s
A R5Q 0_J R0201 A
ns

Bitland Information Technology Co.,Ltd.

Page Name
SOC I2C/CNVI/UART/SPI
Size Project Name Rev
C
Phaser 1.3
Date: Tuesday, November 27, 2018 Sheet 10 of 43
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
5 4 3 2 1

PP1800_SOC_A
MEMORY TYPE CONFIG3 CONFIG2 CONFIG1 CONFIG0

SAMSUNG 8GB K4F6E3S4HM-MGCJ 0 0 0 1

R371 R376 R382 R399 PCH_RTC_X2
DRAM_ID3 DRAM_ID2 DRAM_ID1 DRAM_ID0 100K_J 100K_J 100K_J 100K_J
SAMSUNG 4GB K4F8E304HB-MGCJ 0 0 0 0 X2
RAM ID R0201 R0201
ns
R0201 R0201
ns PCH_RTC_X1 1 2
R399 R402 R382 R385 R376 R378 R371 R373 DRAM_ID0 DRAM_ID3
DRAM_ID1 DRAM_ID2
SAMSUNG 8GB K4F6E304HB-MGCJ 0 0 1 0 32.768KHZ
y_2p_smd3215
0 DNS Stuff DNS Stuff DNS Stuff DNS Stuff
R45 10M_F r0201
D
1 DNS Stuff DNS Stuff DNS Stuff Stuff DNS R373 R378 R385 R402 MICRON 8GB MT53E512M32D2NP-046 0 0 0 1 D

100K_J 100K_J 100K_J 100K_J

1
R0201 R0201 R0201 R0201 C2 C3
2 DNS Stuff DNS Stuff Stuff DNS DNS Stuff ns ns 12pF/50V,COG 12pF/50V,COG
MICRON 4GB MT53B256M32D1NP-053 0 0 0 0 c0201 c0201

2
3 DNS Stuff DNS Stuff Stuff DNS Stuff DNS
GND GND GND GND MICRON 8GB MT53B512M32D2NP-062 0 0 1 0 GND GND
4 DNS Stuff Stuff DNS DNS Stuff DNS Stuff
5 DNS Stuff Stuff DNS DNS Stuff Stuff DNS HYNIX 8GB H9HCNNNBPUMLHR-NME 0 0 1 0
6 DNS Stuff Stuff DNS Stuff DNS DNS Stuff HYNIX 4GB H9HCNNN8KUMLHR-NME 0 0 0 0
PP3300_RTC
7 DNS Stuff Stuff DNS Stuff DNS Stuff DNS
U4H
8 Stuff DNS DNS Stuff DNS Stuff DNS Stuff
R46 B17 EC_IN_RW_OD R8
33 PCH_PMIC_I2C_SCL PMC_I2C_SCL 1.8V 1.8V OSC_CLK_OUT_0 PCH_WP_OD EC_IN_RW_OD 21
R48 C17
9 Stuff DNS DNS Stuff DNS Stuff Stuff DNS 33 PCH_PMIC_I2C_SDA PMC_I2C_SDA 1.8V 1.8V OSC_CLK_OUT_1 U2 PCH_OSCIN PCH_WP_OD 19 100K_J
TP_AP_PMC_SPI_CLK OSCIN PCH_OSCOUT R0201
L48 iCLK T1
DRAM_ID0 N48 PMC_SPI_CLK 1.8V OSCOUT
10 Stuff DNS DNS Stuff Stuff DNS DNS Stuff PP3300_SOC_A DRAM_ID1 N44 PMC_SPI_FS0 1.8V D23 PCH_RTC_X1
PP1050_VCCRAM_S DRAM_ID2 L49 PMC_SPI_FS1 1.8V RTC_X1 F23 PCH_RTC_X2
DRAM_ID3 L51 PMC_SPI_FS2 1.8V RTC RTC_X2 J23 RTC_EXPAD
11 Stuff DNS DNS Stuff Stuff DNS Stuff DNS TP_AP_PMC_SPI_TX N49 PMC_SPI_RXD 1.8V VCC_RTC_EXTPAD H25 INTRUDER
PMC_SPI_TXD 1.8V PMC INTRUDER D25 EC_PCH_PWROK C360
SOC_PW ROK F27 PCH_RSMRST_L EC_PCH_PWROK 18
12 Stuff DNS Stuff DNS DNS Stuff DNS Stuff R557 R276 0.1uF/10V/X5R
D54 RSM_RST F25 PCH_RTEST_ODL PCH_RSMRST_L 11,12,18 PCH_OSCOUT
100K_J 100K_J 12,18,21,23,28 PLT_RST_L PMU_PLTRST 3.3(Default)/1.8V RTC_TEST C0201
R56 R58 R63 E54 D27 PCH_RTCRST_ODL
R0201 R0201 12,18 EC_PCH_PWR_BTN_ODL PMU_PWRBTN 3.3(Default)/1.8V RTC_RST
84.5_F C52 X3
C
13 Stuff DNS Stuff DNS DNS Stuff Stuff DNS 68.0_F 169_F
R0201
9,33 PCH_SLP_S0_L D51 PMU_SLP_S0 3.3(Default)/1.8V
J53 THERMTRIP_L GND PCH_OSCIN 1 3 C
R0201 R0201 33 PCH_SLP_S3_L PMU_SLP_S3 3.3(Default)/1.8V 1.8V THERMTRIP THERMTRIP_L 33
J49 J54 R735 0_J R0201 4 2
33 PCH_SLP_S4_L SUSPWRDNACK F54 PMU_SLP_S4 3.3(Default)/1.8V 1.8V PROCHOT AG43 PCH_PROCHOT_ODL 18,37
14 Stuff DNS Stuff DNS Stuff DNS DNS Stuff 18 SUSPWRDNACK PMU_BATLOW_L J48 SUSPW RDNACK 3.3(Default)/1.8V Thermal NC3 H53 19.2MHZ
C51 PMU_BATLOW 3.3(Default)/1.8V NC15 AG44 y_4p_smd3225
12,18,21,22 SYS_RST_ODL G49 PMU_RSTBTN 3.3(Default)/1.8V NC4 H55
15 Stuff DNS Stuff DNS Stuff DNS Stuff DNS ns ns ns 28 PCH_SUSCLK PMU_SUSCLK 3.3(Default)/1.8V
PMU
NC16
R46
E52 100K_J GND GND
28 BT_DISABLE_L SUS_STAT 3.3(Default)/1.8V A4 R722 200K_F R0201
TP_PCH_GPIO_78 NC1 R0201
F55 BH1
TP81 TP_PCH_GPIO_77 G53 SVID0_CLK 1.05V SVID NC5 A53 C1 C4
TP82 TP_PCH_GPIO_76 G54 SVID0_DATA 1.05V Spare SKTOCC F37 7pF/25V,NPO 7pF/25V,NPO
TP83 SVID0_ALERT 1.05V NC14 BL2 c0402 c0402
D1 NC6 BL3 GND
TP87 D2 DEBUG_PORT_A0 Misc NC7 BL53
TP88 A54 DEBUG_PORT_A1 NC8 C2 GND GND
C54 NC2 NC9 C3
NC11 NC10 R41
NC17

8 OF 13

Rank Dual
RAM ID Memory Speed Density Rank Ch0 Ch0 Part Number
MT53B256M32D1NP-053
/H9HCNNN8KUMLHR-NME
0 4GiB 2400MHz 8Gb N Y Y /K4F8E304HB-MGCJ
MT53E512M32D2NP-046
/K4F6E3S4HM-MGCJ PP3300_A PP3300_A
1 8GiB 2400MHz 16Gb N Y Y
MT53B512M32D2NP-062 PLT_RST_L
/H9HCNNNBPUMLHR-NME
2 8GiB 2400MHz 8Gb Y Y Y /K4F6E304HB-MGCJ R508
R190 R191 499K_F
PCH_RSMRST_L
3 4GiB 2400MHz 16Gb N Y N 100K_F 1K_F 11,12,18 PCH_RSMRST_L R0201
ns
R0201 R0201
B
ns ns B
R587 PCH_RSMRST_OD
4 4GiB 2400MHz 8Gb Y Y N SLP_S3
100K_F

3
R0201

3
D Q80 C447
5 4GiB 2400MHz 16Gb N N Y D Q56 D Q57 LSI1012N3T5G 1uF/6.3V/X5R
LSI1012N3T5G LSI1012N3T5G PCH_RSMRST_L 1 sot883
PCH_SLP_S3_L 11,12,18 PCH_RSMRST_L C0201
1 sot883 1 sot883 G ns ns
6 4GiB 2400MHz 8Gb Y N Y G S ns G S ns GND
S

2
GND

2
GND
GND GND
PCH_RSMRST_OD

Q79
sot23-3

1
WPM2301-3/TR

G
ns
PCH_SLP_S0_L 2 3 SLP_S0_L
SLP_S0_L 18 PCH_RSMRST_OD

D
S
R507 Q81
499K_F sot23-3

1
R516 0_J R0201 R0201 WPM2301-3/TR

G
ns
CHECK RTCRST SIGNAL CHECK RTCRST SIGNAL PCH_SLP_S3_L 2 3 SLP_S3_L
SLP_S3_L 18,35

D
S
PP3300_RTC GND R509
499K_F
PP3300_RTC R517 0_J R0201 R0201
R740
PCH_RSMRST_OD
20K_F
R50 r0201
20K_F Q82 GND
r0201 sot23-3

1
A PCH_RTEST_ODL WPM2301-3/TR A

G
ns

3
PCH_RTCRST_ODL PCH_SLP_S4_L 2 3 SLP_S4_L
SLP_S4_L 18,35

D
S
D Q86 C582
3

LSI1012N3T5G 1uF/25V/X5R
D Q7 C5 EC_PCH_RTCRST 1 R510
sot883 C0201
LSI1012N3T5G 1uF/25V/X5R G S 499K_F Bitland Information Technology Co.,Ltd.
EC_PCH_RTCRST 1 sot883 R518 0_J R0201
18 EC_PCH_RTCRST C0201 R0201

2
G S R739 GND Page Name
100K_F SOC PMU/RTC/SVID/THERMAL/MISC
2

GND R0201 GND Size Project Name Rev

Custom
GND GND Phaser 1.3
Date: Tuesday, November 27, 2018 Sheet 11 of 43
PROPERTY NOTE: this document contains information confidential and property to
GND Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1

RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
 RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
5 4 3 2 1

LAYOUT NOTE: PLACE THE R62, 65, 55, 57, R393

WITHIN 1" OF J5 MIPI60 CONNECTOR.
PP1800_SOC_A

D D

U4E
R65 R393 R62
51_F 150.0_F 51_F AG53 DBG_PTI_CLK0
JTAG 1.8V GPIO_8 AG54 DBG_PTI_DATA_0 DBG_PTI_CLK0 20
R0201 r0201 R0201 1.8V GPIO_9 DBG_PTI_DATA_1 DBG_PTI_DATA_0 20
AE54
TP_GPIO5 1.8V GPIO_10 DBG_PTI_DATA_2 DBG_PTI_DATA_1 20
AH53 AE53
JTAGX 1.8V 1.8V GPIO_11 DBG_PTI_DATA_3 DBG_PTI_DATA_2 20
TCK AM53 AD55 DBG_PTI_DATA_3 20
20 TCK TDI AJ54 JTAG_TCK 1.8V 1.8V GPIO_12 AD53 DBG_PTI_DATA_4
20 TDI JTAG_TDI 1.8V 1.8V GPIO_13 DBG_PTI_DATA_5 DBG_PTI_DATA_4 20
TDO AL53 AC54 DBG_PTI_DATA_5 20
20 TDO TMS AL54 JTAG_TDO 1.8V 1.8V GPIO_14 AC53 DBG_PTI_DATA_6
20 TMS TRST_L JTAG_TMS 1.8V 1.8V GPIO_15 DBG_PTI_DATA_7 DBG_PTI_DATA_6 20
AK53 AB53
20 TRST_L JTAG_TRST 1.8V 1.8V GPIO_16 DBG_PTI_DATA_7 20
AA49 DBG_PTI_CLK1
ITP
1.8V GPIO_17 AC48 DBG_PTI_DATA_8 DBG_PTI_CLK1 20
PP1800_SOC_A 1.8V GPIO_18 DBG_PTI_DATA_9 DBG_PTI_DATA_8 20
R57 R55 AC46
1.8V GPIO_19 AE51 DBG_PTI_DATA_10 DBG_PTI_DATA_9 20
51_F 51_F 1.8V GPIO_20 DBG_PTI_DATA_10 20
CX_PRDY_L AH55 AE49 CNVI_MFUART2_RXD_PTI_11
R0201 R0201 CX_PREQ_L JTAG_PRDY 1.8V 1.8V GPIO_21 CNVI_MFUART2_TXD_PTI_12
ns AJ53 AC51
JTAG_PREQ 1.8V 1.8V GPIO_22 AC49 CNVI_GNSS_PA_BLANKING_PTI_13
R397 R394 1.8V GPIO_23 AA51 DBG_PTI_DATA_14
1.8V GPIO_24 AA46 DBG_PTI_DATA_15 DBG_PTI_DATA_14 20
150.0_F 51_F 1.8V GPIO_25 DBG_PTI_DATA_15 20
r0201 R0201 DBG_PTI_CLK2
GND AE41
1.8V GPIO_26 AE39 DBG_PTI_DATA_16 DBG_PTI_CLK2 20
1.8V GPIO_27 DBG_PTI_DATA_17 DBG_PTI_DATA_16 20
AE46
1.8V GPIO_28 AE44 DBG_PTI_DATA_18 DBG_PTI_DATA_17 20
20 CX_PRDY_L 1.8V GPIO_29 DBG_PTI_DATA_19 DBG_PTI_DATA_18 20
AC41
20 CX_PREQ_L 1.8V GPIO_30 AC39 DBG_PTI_DATA_20 DBG_PTI_DATA_19 20
R362
1.8V GPIO_31 DBG_PTI_DATA_21 DBG_PTI_DATA_20 20
AC44 1K_J
1.8V GPIO_32 DBG_PTI_DATA_22 DBG_PTI_DATA_21 20
AC43
1.8V GPIO_33 DBG_PTI_DATA_23 DBG_PTI_DATA_22 20 R0201
AA44
1.8V GPIO_34 DBG_PTI_DATA_23 20
AA54 DCI_CLK_PTICLK3
1.8V GPIO_35 DCI_DATA_PTITRACE3_0 DCI_CLK_PTICLK3 20
AA53
1.8V GPIO_36 DBG_PTI_DATA_TRACE3_1 DCI_DATA_PTITRACE3_0 20
Y55 GND
1.8V GPIO_37 Y53 DBG_PTI_DATA_TRACE3_2 DBG_PTI_DATA_TRACE3_1 20
1.8V GPIO_38 DBG_PTI_DATA_TRACE3_3 DBG_PTI_DATA_TRACE3_2 20
C W54 C
1.8V GPIO_39 W53 DBG_PTI_DATA_TRACE3_4
1.8V GPIO_40 V53 DBG_PTI_DATA_TRACE3_5
1.8V GPIO_41
L46 TOUCHSCREEN_RST
3.3(Default)/1.8V GPIO_105 H45 EC_AP_INT_ODL TOUCHSCREEN_RST 26
PP1800_A PP3300_A 3.3(Default)/1.8V GPIO_134 H47 TRACKPAD_INT1_1V8_ODL TP65
3.3(Default)/1.8V GPIO_135 PMIC_PCH_INT_1V8_ODL EC_AP_INT_ODL 18 PP1800_SOC_A
L43
3.3(Default)/1.8V GPIO_136 M43 HP_INT_ODL
3.3(Default)/1.8V GPIO_137 H37 PEN_PDCT_ODL HP_INT_ODL 24
3.3/1.8(Default)V GPIO_138 PEN_INT_ODL PEN_PDCT_ODL 26
H43
3.3(Default)/1.8V GPIO_139 J43 PEN_RESET PEN_INT_ODL 26
R380 R391 R392 R289
3.3(Default)/1.8V GPIO_140 D43 EC_PCH_WAKE_1V8_ODL PEN_RESET 26
4.7K_J 1K_J 1K_J 3.3(Default)/1.8V GPIO_141 100K_J
F43 TRACKPAD_INT2_1V8_ODL
R0201 R0201 R0201 3.3(Default)/1.8V GPIO_142 LTE_SAR_ODL R0201
ns H41 ns
3.3(Default)/1.8V GPIO_143 PEN_EJECT TP86 PEN_EJECT 25
F39
3.3/1.8(Default)V GPIO_144 L41 PEN_EJECT TP49
3.3/1.8(Default)V GPIO_145 TP74
10 GPIO_81_DEBUG R340 1K_J R0201 F41 R558 0_J R0201
BOOT_HALT_L 20 3.3/1.8(Default)V GPIO_146 EN_PP3300_CAMERA EN_PP3300_TOUCHSCREEN 25,35
R341 0_J R0201 GPIO H27
11,18,21,22 SYS_RST_ODL DBG_PMU_RSTBTN_L 20 1.8V GPIO_210 TOUCHSCREEN_INT_ODL TP68
R352 0_J R0201 U43
11,18 EC_PCH_PWR_BTN_ODL DBG_PMU_PWRBTN_L 20 1.8V GPIO_212 TP_AP_GPIO213 TOUCHSCREEN_INT_ODL 26 EN_PP3300_CAMERA 35
11,18,21,23,28 PLT_RST_L R361 1K_J R0201 U41
DBG_PMU_PLTRST_L 20 1.8V GPIO_213 U39 P_SENSOR_INT_L TP94
11,18 PCH_RSMRST_L R379 1K_J R0201
DBG_RSMRST_L 20 1.8V GPIO_214 TP69
ns

5 OF 13

B B

PP1800_SOC_A
R524 0_J R0201 TRACKPAD_INT1_1V8_ODL

TRACKPAD_INT_1V8_ODL R531 0_J R0201 TRACKPAD_INT2_1V8_ODL

18,25 TRACKPAD_INT_1V8_ODL
R880
10K_J
PP1800_SOC_A
r0201
PMIC_PCH_INT_1V8_ODL R887 0_J R0201 PMIC_PCH_INT_ODL 33
R14 0_J R0201
CNVI_GNSS_PA_BLANKING 28
R28973 CNVI_GNSS_PA_BLANKING_PTI_13 R16 0_J R0201
DBG_PTI_DATA_13 20
22K_F ns
R0201

EC_AP_INT_ODL
R17 0_J R0201
PP1800_SOC_A CNVI_MFUART2_RXD 28
CNVI_MFUART2_RXD_PTI_11 R24 0_J R0201
DBG_PTI_DATA_11 20
ns

R881
10K_J
r0201 R25 0_J R0201
CNVI_MFUART2_TXD 28
ns
CNVI_MFUART2_TXD_PTI_12 R61 0_J R0201
EC_PCH_WAKE_1V8_ODL R888 0_J R0201 DBG_PTI_DATA_12 20
EC_PCH_WAKE_ODL 18 ns

A A

Bitland Information Technology Co.,Ltd.

Page Name
SOC JTAG/GPIO/ITP
Size Project Name Rev
C
Phaser 1.3
Date: Thursday, November 22, 2018 Sheet 12 of 43
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
5 4 3 2 1

D D

U4K U4L
U4M
A3 AF44 AN48 BC11 AL23
A6 VSS6 VSS53 AF45 AN49 VSS_111 VSS_165 BC17 BJ54 VSS1 J51
A12 VSS13 VSS54 AF47 AN51 VSS_112 VSS_166 BC19 BK1 VSS2 VSS51 K1
A16 VSS1 VSS55 AF48 AN53 VSS_113 VSS_167 BC21 BK17 VSS3 VSS53 K3
A20 VSS2 VSS56 AF50 AP23 VSS_114 VSS_168 BC23 BK21 VSS4 VSS55 K28
A24 VSS3 VSS57 AF52 AP27 VSS_115 VSS_169 BC25 BK35 VSS5 VSS54 K55
A28 VSS4 VSS58 AF53 AP28 VSS_116 VSS_170 BC31 BK39 VSS6 VSS56 L5
A32 VSS5 VSS59 AF55 AP29 VSS_117 VSS_171 BC33 BK55 VSS7 VSS59 L7
A36 VSS7 VSS60 AG20 AP33 VSS_118 VSS_172 BC35 BL5 VSS8 VSS60 L8
A40 VSS8 VSS64 AL21 AP35 VSS_119 VSS_173 BC37 BL8 VSS17 VSS61 L19
A44 VSS9 VSS87 AG25 AR2 VSS_120 VSS_174 BC39 BL10 VSS19 VSS57 L33
A48 VSS10 VSS65 AG29 AR7 VSS_124 VSS_175 BC41 BL14 VSS9 VSS58 M15
A51 VSS11 VSS66 AG35 AR10 VSS_130 VSS_176 BC45 BL24 VSS10 VSS62 M25
AA12 VSS12 VSS67 AG38 AR12 VSS_121 VSS_177 BC51 BL28 VSS11 VSS63 M28
AA13 VSS14 VSS68 AJ8 AR17 VSS_122 VSS_179 BD9 BL32 VSS12 VSS64 M35
AA15 VSS15 VSS77 AJ13 AR39 VSS_123 VSS_187 BD15 BL42 VSS13 VSS65 M41
AA17 VSS16 VSS69 AJ18 AR44 VSS_125 VSS_180 BD19 BL46 VSS14 VSS66 N12
AA21 VSS17 VSS70 AJ25 AR46 VSS_126 VSS_181 BD21 BL48 VSS15 VSS67 N28
AA23 VSS18 VSS71 AJ29 AR49 VSS_127 VSS_182 BD28 BL51 VSS16 VSS68 N46
AA25 VSS19 VSS72 AJ36 AR54 VSS_128 VSS_183 BD35 C1 VSS18 VSS69 N51
AA27 VSS20 VSS73 AJ38 AT23 VSS_129 VSS_184 BD37 C12 VSS20 VSS70 P21
AA35 VSS21 VSS74 AJ39 AT33 VSS_131 VSS_185 BD47 C16 VSS21 VSS71 P55
AA43 VSS22 VSS75 AJ44 AU3 VSS_132 VSS_186 BE3 C28 VSS22 VSS72 R8
AA48 VSS23 VSS76 AK1 AU10 VSS_135 VSS_189 BE28 C36 VSS23 VSS74 R28
C C
AB1 VSS24 VSS78 AK3 AU28 VSS_133 VSS_188 BE53 D6 VSS24 VSS73 T27
AB3 VSS25 VSS79 AK55 AU46 VSS_134 VSS_190 BF9 D9 VSS30 VSS75 T38
AB55 VSS26 VSS80 AL3 AU53 VSS_136 VSS_194 BF19 D21 VSS31 VSS77 U13
AC8 VSS27 VSS90 AL7 AV15 VSS_137 VSS_191 BF37 D28 VSS25 VSS78 V27
AC13 VSS33 VSS97 AL8 AV17 VSS_138 VSS_192 BF47 D41 VSS26 VSS80 V38
AC23 VSS28 VSS98 AL10 AV23 VSS_139 VSS_193 BG1 D45 VSS27 VSS81 V55
AC25 VSS29 VSS81 AL12 AV25 VSS_140 VSS_195 BG6 D55 VSS28 VSS82 W2
AC27 VSS30 VSS82 AL13 AV31 VSS_141 VSS_199 BG28 E28 VSS29 VSS84 W3
AC29 VSS31 VSS83 AL15 AV33 VSS_142 VSS_196 BG50 E50 VSS32 VSS85 W5
AE18 VSS32 VSS84 AL17 AV39 VSS_143 VSS_197 BG55 E55 VSS33 VSS93 W7
AE23 VSS34 VSS85 AL20 AV41 VSS_144 VSS_198 BH11 F1 VSS34 VSS95 W8
AE25 VSS35 VSS86 AL25 AW2 VSS_145 VSS_200 BH13 F4 VSS35 VSS96 W10
AE27 VSS36 VSS88 AL29 AW5 VSS_147 VSS_201 BH17 F21 VSS38 VSS83 W39
AE43 VSS37 VSS89 AL39 AW10 VSS_150 VSS_202 BH19 F31 VSS36 VSS86 W41
AE48 VSS38 VSS91 AL41 AW28 VSS_146 VSS_203 BH23 G28 VSS37 VSS87 W43
AF1 VSS39 VSS92 AL43 AW46 VSS_148 VSS_204 BH25 H13 VSS39 VSS88 W44
AF3 VSS40 VSS93 AL44 AW51 VSS_149 VSS_205 BH28 H15 VSS40 VSS89 W46
AF4 VSS49 VSS94 AL46 AW54 VSS_151 VSS_206 BH31 H21 VSS41 VSS90 W48
AF6 VSS50 VSS95 AL51 AY13 VSS_152 VSS_207 BH33 H23 VSS42 VSS91 W49
AF8 VSS61 VSS96 AM1 AY15 VSS_153 VSS_208 BH37 H28 VSS43 VSS92 W51
AF9 VSS62 VSS99 AM21 AY28 VSS_154 VSS_209 BH39 H33 VSS44 VSS94 Y21
AF11 VSS63 VSS100 AM23 AY41 VSS_155 VSS_210 BH41 H39 VSS45 VSS97 Y23
AF12 VSS41 VSS101 AM25 AY43 VSS_156 VSS_211 BH45 J8 VSS46 VSS98 Y25
AF14 VSS42 VSS102 AM29 B2 VSS_157 VSS_212 BJ2 J27 VSS52 VSS99 Y27
AF16 VSS43 VSS103 AM31 B55 VSS_158 VSS_215 BJ15 J33 VSS47 VSS100 Y31
AF18 VSS44 VSS104 AM38 BA27 VSS_159 VSS_213 BJ19 J41 VSS48 VSS101 T3
AF23 VSS45 VSS105 AM55 BA29 VSS_160 VSS_214 BJ25 J45 VSS49 VSS76 U3
AF25 VSS46 VSS106 AN3 BB1 VSS_161 VSS_216 BJ28 VSS50 VSS79
AF29 VSS47 VSS108 AN8 BB28 VSS_162 VSS_217 BJ31
AF40 VSS48 VSS110 AN10 BB55 VSS_163 VSS_218 BJ37 13 OF 13
AF42 VSS51 VSS107 AN46 BC5 VSS_164 VSS_219 BJ41 GND
VSS52 VSS109 VSS_178 VSS_220 GND
11 OF 13
12 OF 13
GND GND GND GND

B B

A A

Bitland Information Technology Co.,Ltd.

Page Name
SOC GROUND
Size Project Name Rev
C
Phaser 1.3
Date: Thursday, November 22, 2018 Sheet 13 of 43
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
5 4 3 2 1

SHOULD CONSIDER SPLITTING THE RAILS FOR NOISE ISOLATION

PP1100_VDDQ_SOC PP1050_VCCRAM_S
U4J

AP18 AC33
AP21 VDDQ1 VCCRAM_1P053 AC35
D
AP36 VDDQ2 VCCRAM_1P054 AE33 D
AP38 VDDQ3 VCCRAM_1P057 AE35
AT18 VDDQ4 VCCRAM_1P058 AE36
AT20 VDDQ5 VCCRAM_1P059 AE38
AT21 VDDQ6 VCCRAM_1P0510 AF27
AT35 VDDQ7 VCCRAM_1P0511 AF28
AT36 VDDQ8 VCCRAM_1P0512 AF36
AT38
BA13
VDDQ9
VDDQ10
3A VCCRAM_1P0513
VCCRAM_1P0514
AF38

BA15
BA25
VDDQ11
VDDQ12
4.5A VCC_1P05_INT2
AG51
AG49
PPVAR_VCCGI PPVAR_VNN
U4I
BA31 VDDQ13 VCC_1P05_INT1
BA41 VDDQ14 AJ51 AA28 AF35
BA43 VDDQ15 VCC_1P05_INT3 AA29 VCC_VCG1 VNN1 AG27
VDDQ16 AA36 AA31 VCC_VCG2 VNN2 AG28
AP25 VCCRAM_1P051 AA38 PP3300_RTC AA33 VCC_VCG3 VNN3 AG36
PP1100_VDDQ_IOA VCCIOA1 VCCRAM_1P052 VCC_VCG4 VNN4
AP31 AC36 AC28 AG46
AT25 VCCIOA2 VCCRAM_1P055 AC38 AC31 VCC_VCG5 VNN5 AG48
AT27 VCCIOA3 VCCRAM_1P056 Y36 AE28 VCC_VCG6 VNN6 AJ27
AT28 VCCIOA4 VCCRAM_1P0515 Y38 C342 C411 AE29 VCC_VCG7 VNN7 AJ28
AT29
AT31
VCCIOA5
VCCIOA6
VCCRAM_1P0516 1uF/16V/X5R 1uF/16V/X5R AE31
AF31
VCC_VCG8
VCC_VCG9
4A VNN8
VNN9
AJ46
AJ48
C0201 C0201
VCCIOA7 AF33 VCC_VCG10 VNN10 AL27
VCCRAM(1.05V) ns VCC_VCG11 VNN11
T21 AG31 AL28
PP1800_SOC_A VCC_1P8V_A3 VCC_VCG12 VNN12
T23 P15 GND GND AG33 AL48
T25 VCC_1P8V_A4
VDD1(1.8V) RTC VCCRTC_3P3V AJ31 VCC_VCG13 VNN13 AL49
V21 VCC_1P8V_A5 AJ33 VCC_VCG14 VNN14 AM27
V23 VCC_1P8V_A6 AJ21 AJ35 VCC_VCG15 VNN15 AM28
V25 VCC_1P8V_A7
VCC_1P8V_A8
0.4A VCC_3P3V_A2
U17
PP3300_SOC_A
AL31
AL33
VCC_VCG16
VCC_VCG17
VNN16

AJ23 VCC_3P3V_A5 AL35 VCC_VCG18

AG23 VCC_1P8V_A2 AM33 VCC_VCG19
VCC_1P8V_A1 AM35 VCC_VCG20

AC21 0.15A AG21

AM36
D31
VCC_VCG21
VCC_VCG22
25A
PP1200_SOC_A VDD2_1P2_MPHY1 VCC_3P3V_A1 VCC_VCG23 NC_VNNAON
AE20 T18 D33 AJ49
AE21 VDD2_1P2_MPHY2 VCC_3P3V_A3 T20 D37 VCC_VCG24 NC1 TP123
AF20 VDD2_1P2_MPHY3 VCC_3P3V_A4 V18 D39 VCC_VCG25
C C
AF21 VDD2_1P2_MPHY4 VCC_3P3V_A6 V20 P39 VCC_VCG26
VDD2_1P2_MPHY5 VDD3(3.3V)
VCC_3P3V_A7 Y18 P41 VCC_VCG27
VCC_3P3V_A8 Y20 T28 VCC_VCG28
AC18 VCC_3P3V_A9 T29 VCC_VCG29
AC20 VDD2_1P2_AUD_ISH1 T31 VCC_VCG30
VDD2_1P2_AUD_ISH2 T33 VCC_VCG31 AW44
VCC_VCG32 NC2 TP89
AW12 T35
VDD2_1P2_DSI_CSI T36 VCC_VCG33 BH55
AL36 V28 VCC_VCG34 NC3 TP90
AL38
AP20
VDD2_1P2_GLM1
VDD2_1P2_GLM2
3A V29
V31
VCC_VCG35
VCC_VCG36 VCC_VCG_SENSE
AG41
AG39
PPVAR_VCCGI_SENSE_P
PPVAR_VCCGI_SENSE_N PPVAR_VCCGI_SENSE_P 33
VDD2_1P2_GLM4 V33 VCC_VCG37 VSS_VCG_SENSE PPVAR_VCCGI_SENSE_N 33
AM20 V35 VCC_VCG38 AJ41 PPVAR_VNN_SENSE_P
VDD2_1P2_GLM3 V36 VCC_VCG39 VNN_SENSE AJ43 PPVAR_VNN_SENSE_N PPVAR_VNN_SENSE_P 33
AL18 Y28 VCC_VCG40 VNN_VSS_SENSE
AM18 VDD2_1P2_PLL1 Y29 VCC_VCG41 BL54
VDD2_1P2_PLL2 VCC_VCG42 NC4 TP91
Y33
AA18 Y35 VCC_VCG43
AA20 VDD2_1P2_VNNAON1 VCC_VCG44
VDD2_1P2_VNNAON2
9 OF 13
AG18
AJ20 VDD2_1P2_USB2
VDD2_1P2_USB3
VDD2(1.2V)
10 OF 13

B
PPVAR_VNN SHOULD CONSIDER SPLITTING THE RAILS FOR NOISE ISOLATION B

R12
100_F
R0201
PP1200_A PP1200_SOC_A
PPVAR_VNN_SENSE_P
PPVAR_VNN_SENSE_N R461 ns 0_J R0603_short
C298
0.01uF/10V,X5R
C293 C295 R13 c0201 PP1050_S PP1050_VCCRAM_S
0.01uF/10V,X5R 0.01uF/10V,X5R 100_F
c0201 c0201 R0201 R464 ns 0_J R0603_short

PP1100_VDDQ_S PP1100_VDDQ_SOC

GND GND GND R465 ns 0_J R0603_short

PLEASE THESE COMPONENTS NEAR THE PMIC FB PINS PPVAR_VCCGI

R476
100_F
R0201

PPVAR_VCCGI_SENSE_P
PPVAR_VCCGI_SENSE_N
C297
0.01uF/10V,X5R
A C294 C296 R477 c0201 A
0.01uF/10V,X5R 0.01uF/10V,X5R 100_F
c0201 c0201 R0201

Bitland Information Technology Co.,Ltd.

GND GND GND
Page Name
SOC POWER
Size Project Name Rev
C
Phaser 1.3
Date: Tuesday, November 27, 2018 Sheet 14 of 43
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
5 4 3 2 1

DECOUPLING VALUES AND NUMBER BASED ON THE REFERENCE DOC

PP1050_VCCRAM_S: 1uF_0402x10 , 22uF_0603 x3
PPVAR_VNN

C28 C37 C46 C129 C29 C83 C38 C47 C51 PP1050_VCCRAM_S PP1050_VCCRAM_S
1uF/6.3V/X5R 1uF/6.3V/X5R 1uF/6.3V/X5R 1uF/6.3V/X5R 1uF/6.3V/X5R 22uF/6.3V/X5R 22uF/6.3V/X5R 22uF/6.3V/X5R 22uF/6.3V/X5R
C0201 C0201 C0201 C0201 C0201 ns C0603 C0603 C0603 C0603
10% 10% 10% 10%
PPVAR_VNN C79 C84 C33 C42
D D
1uF/6.3V/X5R 1uF/6.3V/X5R 1uF/6.3V/X5R 1uF/6.3V/X5R
GND C0201 C0201 C0201 C0201
C277
1uF/6.3V/X5R
VNN: 1uF_0402x5 , 22uF_0603 x4
C0201
GND GND
GND
PP1050_VCCRAM_S
PP1050_VCCRAM_S

C34 C43 C437 C57 C61

C80 C85 C419 C88 1uF/6.3V/X5R 1uF/6.3V/X5R 1uF/6.3V/X5R C0603 C0603
1uF/6.3V/X5R 1uF/6.3V/X5R 1uF/6.3V/X5R C0603 22uF/6.3V/X5R 22uF/6.3V/X5R
C0201 C0201 C0201
22uF/6.3V/X5R ns 10% 10%
C0201 C0201 C0201
PPVAR_VCCGI 10%

GND
C6 C10 C95 C101 C105 C130 C156 C199 C200 C201 C204 GND
1uF/6.3V/X5R 1uF/6.3V/X5R 1uF/6.3V/X5R 1uF/6.3V/X5R 1uF/6.3V/X5R 1uF/6.3V/X5R 1uF/6.3V/X5R C0603 C0603 C0603 C0603
22uF/6.3V/X5R 22uF/6.3V/X5R 22uF/6.3V/X5R 22uF/6.3V/X5R
C0201 C0201 C0201 C0201 C0201 C0201 C0201
10% 10% 10% 10%

GND
PPVAR_VCCGI PP1200_SOC_A
PPVAR_VCCGI

PP1200_SOC_A
C203 C205 C206 C438 C465 C495 C498 C500 C501 C502
C9 C94 C99 C104 C115 C155 C0603 C0603 C0603 1uF/6.3V/X5R 1uF/6.3V/X5R 1uF/6.3V/X5R 1uF/6.3V/X5R C0603 C0603 C0603
1uF/6.3V/X5R 1uF/6.3V/X5R 1uF/6.3V/X5R 1uF/6.3V/X5R 1uF/6.3V/X5R C0603 22uF/6.3V/X5R 22uF/6.3V/X5R 22uF/6.3V/X5R C144 22uF/6.3V/X5R 22uF/6.3V/X5R 22uF/6.3V/X5R
C0201 C0201 C0201 C0201
22uF/6.3V/X5R 10% 10% 10% C0603 10% 10% 10%
C0201 C0201 C0201 C0201 C0201
10% 22uF/6.3V/X5R
C 10% C
GND GND
GND
GND PP1200_SOC_A
PP1200_SOC_A: 1uF_0402x9 , 22uF_0603 x7
PPVAR_VCCGI
PP1200_SOC_A

C440 C493
C207 C278
VCCGI: 1uF_0402x12 , 22uF_0603 x8 , 0.1uF_0402x2 C89 1uF/6.3V/X5R 1uF/6.3V/X5R
C496
C0603
0.1uF/16V/X5R 0.1uF/16V/X5R 1uF/6.3V/X5R 22uF/6.3V/X5R
C0201 C0201
C0201 C0201 C0201 10%

GND GND

GND PP1200_SOC_A

C441 C494 C497 C499

1uF/6.3V/X5R 1uF/6.3V/X5R C0603 C0603
22uF/6.3V/X5R 22uF/6.3V/X5R
C0201 C0201
10% 10%

GND

EDGE CAP FOR EXPOSED POWER PLANES

PP1100_VDDQ_SOC PP1100_VDDQ_SOC
B PP1800_SOC_A: 1uF_0402x4 , 22uF_0603 x1 B

PP1800_SOC_A
C30 C39 C52 C56 C322 C327 C334 C335
1uF/6.3V/X5R 1uF/6.3V/X5R C0603 C0603 0.1uF/16V/X5R 0.1uF/16V/X5R 0.1uF/16V/X5R 0.1uF/16V/X5R
22uF/6.3V/X5R 22uF/6.3V/X5R
C0201 C0201 C0201 C0201 C0201 C0201
10% 10% C97 C100 C98 C102 C106
ns 1uF/6.3V/X5R 1uF/6.3V/X5R 1uF/6.3V/X5R 1uF/6.3V/X5R C0603
22uF/6.3V/X5R
C0201 C0201 C0201 C0201
10%
GND GND

PP1100_VDDQ_SOC PP1100_VDDQ_SOC
GND

C31 C40 C60 C64 C67 C69 C332 C333

1uF/6.3V/X5R 1uF/6.3V/X5R C0603 C0603 C0603 C0603 1uF/6.3V/X5R 1uF/6.3V/X5R
22uF/6.3V/X5R 22uF/6.3V/X5R 22uF/6.3V/X5R 22uF/6.3V/X5R
C0201 C0201 C0201 C0201
10% 10% 10% 10% PP3300_SOC_A PP3300_SOC_A

GND GND C414 C416 C417 C418 C432 C91 C92 C103
1uF/6.3V/X5R 1uF/6.3V/X5R 1uF/6.3V/X5R 1uF/6.3V/X5R C0603 1uF/6.3V/X5R 1uF/6.3V/X5R C0603
22uF/6.3V/X5R 22uF/6.3V/X5R
C0201 C0201 C0201 C0201 C0201 C0201
10% 10%
PP1100_VDDQ_S PP1100_VDDQ_IOA

W1 ns 0_J R0603_short
C288 C289 C291 C304 C313 C319 GND GND
1uF/6.3V/X5R 1uF/6.3V/X5R 1uF/6.3V/X5R C0603 C0603 C0603
22uF/6.3V/X5R 22uF/6.3V/X5R 22uF/6.3V/X5R
C0201 C0201 C0201
10% 10% 10% PP3300_SOC_A PP3300_SOC_A

GND
A C90 C107 A
1uF/6.3V/X5R 1uF/6.3V/X5R
C0201 C0201

VDDQI: 1uF_0402x9 , 22uF_0603 x9 , 0.1uF_0402x4

Bitland Information Technology Co.,Ltd.
GND GND
Page Name
SOC DECOUPLING
Size
PP3300_SOC_A: 1uF_0402x8 , 22uF_0603 x2 C
Project Name Rev
Phaser 1.3
Date: Tuesday, November 27, 2018 Sheet 15 of 43
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
5 4 3 2 1

MATCHING BIT SWAPPING OF INTEL RVP

MATCHING BIT SWAPPING OF INTEL RVP
U22A U23A
U22B F1 P12 K4F8E304HB-MGCH
PP1800_DRAM_U VDD1_1 VSS_27
K4F8E304HB-MGCH U1 G12 BGA200-HYNIX-H9HCNNN8RUMLHR
BGA200-HYNIX-H9HCNNN8RUMLHR G4 VDD1_2 VSS_25 K11 F1 P12
DDR_0A_CS<0> DDR_0A_DQ<7> VDD1_3 VSS_23 PP1800_DRAM_U VDD1_1 VSS_27 G12
H4 B2 T4 P10 U23B U1
6,16 DDR_0A_CS<0> DDR_0A_CS<1> CS0_A DQ0_A C2 DDR_0A_DQ<6> DDR_0A_DQ<7> 6 VDD1_4 VSS_21 VDD1_2 VSS_25 K11
6,16 DDR_0A_CS<1> H3 G9 G10 K4F8E304HB-MGCH G4
D CS1_A DQ1_A E2 DDR_0A_DQ<5> DDR_0A_DQ<6> 6 VDD1_5 VSS_19 VDD1_3 VSS_23 P10 D
K5 T9 K9 BGA200-HYNIX-H9HCNNN8RUMLHR T4
CS2_A DQ2_A F2 DDR_0A_DQ<4> DDR_0A_DQ<5> 6 U12 VDD1_6 VSS_17 G8 DDR_0B_CS<0> H4 B2 DDR_0B_DQ<3> G9 VDD1_4 VSS_21 G10
DQ3_A F4 DDR_0A_DQ<0> DDR_0A_DQ<4> 6 VDD1_7 VSS_15 6,16 DDR_0B_CS<0> DDR_0B_CS<1> CS0_A DQ0_A C2 DDR_0B_DQ<0> DDR_0B_DQ<3> 6 VDD1_5 VSS_19 K9
F12 G5 6,16 DDR_0B_CS<1> H3 T9
DDR_0A_CA<0> H2 DQ4_A E4 DDR_0A_DQ<3> DDR_0A_DQ<0> 6 VDD1_8 VSS_13 K4 K5 CS1_A DQ1_A E2 DDR_0B_DQ<2> DDR_0B_DQ<0> 6 U12 VDD1_6 VSS_17 G8
6,16 DDR_0A_CA<0> DDR_0A_CA<1> CA0_A DQ5_A C4 DDR_0A_DQ<1> DDR_0A_DQ<3> 6 VSS_11 CS2_A DQ2_A F2 DDR_0B_DQ<1> DDR_0B_DQ<2> 6 VDD1_7 VSS_15 G5
6,16 DDR_0A_CA<1> J2 P3 F12
DDR_0A_CA<2> CA1_A DQ6_A B4 DDR_0A_DQ<2> DDR_0A_DQ<1> 6 VSS_9 DQ3_A F4 DDR_0B_DQ<5> DDR_0B_DQ<1> 6 VDD1_8 VSS_13 K4
H9 H1 G3
6,16 DDR_0A_CA<2> DDR_0A_CA<3> CA2_A DQ7_A DDR_0A_DQ<2> 6 PP1100_VDDQ VDD2_1 VSS_7 DDR_0B_CA<0> DQ4_A E4 DDR_0B_DQ<4> DDR_0B_DQ<5> 6 VSS_11 P3
H10 K1 K2 H2
6,16 DDR_0A_CA<3> DDR_0A_CA<4> CA3_A VDD2_2 VSS_5 6,16 DDR_0B_CA<0> DDR_0B_CA<1> CA0_A DQ5_A C4 DDR_0B_DQ<6> DDR_0B_DQ<4> 6 VSS_9 G3
6,16 DDR_0A_CA<4> H11 N1 P1 6,16 DDR_0B_CA<1> J2 PP1100_VDDQ H1
DDR_0A_CA<5> J11 CA4_A B11 DDR_0A_DQ<11> R1 VDD2_3 VSS_3 G1 DDR_0B_CA<2> H9 CA1_A DQ6_A B4 DDR_0B_DQ<7> DDR_0B_DQ<6> 6 K1 VDD2_1 VSS_7 K2
6,16 DDR_0A_CA<5> CA5_A DQ8_A C11 DDR_0A_DQ<12> DDR_0A_DQ<11> 6 VDD2_4 VSS_1 6,16 DDR_0B_CA<2> DDR_0B_CA<3> CA2_A DQ7_A DDR_0B_DQ<7> 6 VDD2_2 VSS_5 P1
K3 J1 6,16 DDR_0B_CA<3> H10 N1
DQ9_A E11 DDR_0A_DQ<13> DDR_0A_DQ<12> 6 VDD2_5 VSS_2 DDR_0B_CA<4> CA3_A VDD2_3 VSS_3 G1
G2 N3 T1 H11 R1
PP1100_VDDQ ODT_A DQ10_A F11 DDR_0A_DQ<14> DDR_0A_DQ<13> 6 VDD2_6 VSS_4 6,16 DDR_0B_CA<4> DDR_0B_CA<5> CA4_A DDR_0B_DQ<12> VDD2_4 VSS_1 J1
A4 N2 J11 B11 K3
DDR_0A_CKE<0> DQ11_A F9 DDR_0A_DQ<8> DDR_0A_DQ<14> 6 VDD2_7 VSS_6 6,16 DDR_0B_CA<5> CA5_A DQ8_A C11 DDR_0B_DQ<13> DDR_0B_DQ<12> 6 VDD2_5 VSS_2 T1
6,16 DDR_0A_CKE<0> J4 AB4 J3 N3
DDR_0A_CKE<1> J5 CKE0_A DQ12_A E9 DDR_0A_DQ<10> DDR_0A_DQ<8> 6 F5 VDD2_8 VSS_8 T3 G2 DQ9_A E11 DDR_0B_DQ<15> DDR_0B_DQ<13> 6 A4 VDD2_6 VSS_4 N2
6,16 DDR_0A_CKE<1> CKE1_A DQ13_A C9 DDR_0A_DQ<15> DDR_0A_DQ<10> 6 VDD2_9 VSS_10 PP1100_VDDQ ODT_A DQ10_A F11 DDR_0B_DQ<14> DDR_0B_DQ<15> 6 VDD2_7 VSS_6 J3
K8 H5 N4 AB4
CKE2_A DQ14_A B9 DDR_0A_DQ<9> DDR_0A_DQ<15> 6 VDD2_10 VSS_12 DDR_0B_CKE<0> DQ11_A F9 DDR_0B_DQ<11> DDR_0B_DQ<14> 6 VDD2_8 VSS_8 T3
R5 T5 J4 F5
DQ15_A DDR_0A_DQ<9> 6 VDD2_11 VSS_14 6,16 DDR_0B_CKE<0> DDR_0B_CKE<1> CKE0_A DQ12_A E9 DDR_0B_DQ<10> DDR_0B_DQ<11> 6 VDD2_9 VSS_10 N4
U5 T8 J5 H5
DDR_0A_CLK_P VDD2_12 VSS_16 6,16 DDR_0B_CKE<1> CKE1_A DQ13_A C9 DDR_0B_DQ<9> DDR_0B_DQ<10> 6 VDD2_10 VSS_12 T5
6,16 DDR_0A_CLK_P J8 F8 N9 K8 R5
DDR_0A_CLK_N J9 CLK_P_A C3 H8 VDD2_13 VSS_18 J10 CKE2_A DQ14_A B9 DDR_0B_DQ<8> DDR_0B_DQ<9> 6 U5 VDD2_11 VSS_14 T8
6,16 DDR_0A_CLK_N CLK_N_A DMI0_A GND VDD2_14 VSS_20 DQ15_A DDR_0B_DQ<8> 6 VDD2_12 VSS_16 N9
C10 R8 T10 F8
DMI1_A U8 VDD2_15 VSS_22 N11 DDR_0B_CLK_P J8 H8 VDD2_13 VSS_18 J10
DDR_0A_DQS_0_P VDD2_16 VSS_24 6,16 DDR_0B_CLK_P DDR_0B_CLK_N CLK_P_A VDD2_14 VSS_20 T10
D3 A9 J12 J9 C3 R8
DQS0_P_A DDR_0A_DQS_0_N DDR_0A_DQS_0_P 6 VDD2_17 VSS_26 6,16 DDR_0B_CLK_N CLK_N_A DMI0_A GND VDD2_15 VSS_22 N11
E3 AB9 T12 C10 U8
DQS0_N_A DDR_0A_DQS_0_N 6 K10 VDD2_18 VSS_28 E1 DMI1_A A9 VDD2_16 VSS_24 J12
D10 DDR_0A_DQS_1_P N10 VDD2_19 VSS1_2 Y1 D3 DDR_0B_DQS_0_P AB9 VDD2_17 VSS_26 T12
DQS1_P_A DDR_0A_DQS_1_P 6 VDD2_20 VSS1_4 DQS0_P_A DDR_0B_DQS_0_P 6 VDD2_18 VSS_28 E1
E10 DDR_0A_DQS_1_N H12 W2 E3 DDR_0B_DQS_0_N K10
DQS1_N_A DDR_0A_DQS_1_N 6 K12 VDD2_21 VSS1_6 AB3 DQS0_N_A DDR_0B_DQS_0_N 6 N10 VDD2_19 VSS1_2 Y1
DDR_0A_CS<0> R4 AA2 DDR_0A_DQ<19> N12 VDD2_22 VSS1_8 W4 D10 DDR_0B_DQS_1_P H12 VDD2_20 VSS1_4 W2
6,16 DDR_0A_CS<0> DDR_0A_CS<1> CS0_B DQ0_B DDR_0A_DQ<16> DDR_0A_DQ<19> 6 VDD2_23 VSS1_10 DQS1_P_A DDR_0B_DQS_1_P 6 VDD2_21 VSS1_6 AB3
R3 Y2 R12 E5 E10 DDR_0B_DQS_1_N K12
6,16 DDR_0A_CS<1> CS1_B DQ1_B DDR_0A_DQ<17> DDR_0A_DQ<16> 6 VDD2_24 VSS1_12 DQS1_N_A DDR_0B_DQS_1_N 6 VDD2_22 VSS1_8 W4
N5 V2 Y5 N12
CS2_B DQ2_B DDR_0A_DQ<18> DDR_0A_DQ<17> 6 VSS1_14 DDR_0B_CS<0> DDR_0B_DQ<19> VDD2_23 VSS1_10 E5
U2 C8 R4 AA2 R12
DDR_0A_CA<0> DQ3_B DDR_0A_DQ<21> DDR_0A_DQ<18> 6 VSS1_16 6,16 DDR_0B_CS<0> DDR_0B_CS<1> CS0_B DQ0_B DDR_0B_DQ<21> DDR_0B_DQ<19> 6 VDD2_24 VSS1_12 Y5
R2 U4 D1 V8 R3 Y2
6,16 DDR_0A_CA<0> DDR_0A_CA<1> CA0_B DQ4_B DDR_0A_DQ<22> DDR_0A_DQ<21> 6 PP1100_VDDQ VDDQ_1 VSS1_18 6,16 DDR_0B_CS<1> CS1_B DQ1_B DDR_0B_DQ<22> DDR_0B_DQ<21> 6 VSS1_14 C8
6,16 DDR_0A_CA<1> P2 V4 W1 AB8 N5 V2
DDR_0A_CA<2> R9 CA1_B DQ5_B Y4 DDR_0A_DQ<23> DDR_0A_DQ<22> 6 B3 VDDQ_2 VSS1_20 W9 CS2_B DQ2_B U2 DDR_0B_DQ<23> DDR_0B_DQ<22> 6 D1 VSS1_16 V8
6,16 DDR_0A_CA<2> DDR_0A_CA<3> CA2_B DQ6_B DDR_0A_DQ<20> DDR_0A_DQ<23> 6 VDDQ_3 VSS1_22 DDR_0B_CA<0> DQ3_B DDR_0B_DQ<16> DDR_0B_DQ<23> 6 PP1100_VDDQ VDDQ_1 VSS1_18 AB8
6,16 DDR_0A_CA<3> R10 AA4 F3 AB10 6,16 DDR_0B_CA<0> R2 U4 W1
DDR_0A_CA<4> CA3_B DQ7_B DDR_0A_DQ<20> 6 VDDQ_4 VSS1_24 DDR_0B_CA<1> CA0_B DQ4_B DDR_0B_DQ<17> DDR_0B_DQ<16> 6 VDDQ_2 VSS1_20 W9
R11 U3 W11 P2 V4 B3
6,16 DDR_0A_CA<4> DDR_0A_CA<5> CA4_B VDDQ_5 VSS1_26 6,16 DDR_0B_CA<1> DDR_0B_CA<2> CA1_B DQ5_B DDR_0B_DQ<18> DDR_0B_DQ<17> 6 VDDQ_3 VSS1_22 AB10
P11 AA3 E12 R9 Y4 F3
6,16 DDR_0A_CA<5> CA5_B DDR_0A_DQ<31> VDDQ_6 VSS1_28 6,16 DDR_0B_CA<2> DDR_0B_CA<3> CA2_B DQ6_B DDR_0B_DQ<20> DDR_0B_DQ<18> 6 VDDQ_4 VSS1_24 W11
C AA11 B5 Y12 6,16 DDR_0B_CA<3> R10 AA4 U3 C
T2 DQ8_B Y11 DDR_0A_DQ<26> DDR_0A_DQ<31> 6 D5 VDDQ_7 VSS1_30 V12 DDR_0B_CA<4> R11 CA3_B DQ7_B DDR_0B_DQ<20> 6 AA3 VDDQ_5 VSS1_26 E12
PP1100_VDDQ ODT_B DQ9_B DDR_0A_DQ<28> DDR_0A_DQ<26> 6 VDDQ_8 VSS1_29 6,16 DDR_0B_CA<4> DDR_0B_CA<5> CA4_B VDDQ_6 VSS1_28 Y12
V11 W5 C12 6,16 DDR_0B_CA<5> P11 B5
DDR_0A_CKE<0> DQ10_B DDR_0A_DQ<27> DDR_0A_DQ<28> 6 VDDQ_9 VSS1_27 CA5_B DDR_0B_DQ<26> VDDQ_7 VSS1_30 V12
P4 U11 AA5 D11 AA11 D5
6,16 DDR_0A_CKE<0> DDR_0A_CKE<1> CKE0_B DQ11_B DDR_0A_DQ<30> DDR_0A_DQ<27> 6 VDDQ_10 VSS1_25 DQ8_B DDR_0B_DQ<27> DDR_0B_DQ<26> 6 VDDQ_8 VSS1_29 C12
P5 U9 B8 A10 T2 Y11 W5
6,16 DDR_0A_CKE<1> CKE1_B DQ12_B DDR_0A_DQ<29> DDR_0A_DQ<30> 6 VDDQ_11 VSS1_23 PP1100_VDDQ ODT_B DQ9_B DDR_0B_DQ<25> DDR_0B_DQ<27> 6 VDDQ_9 VSS1_27 D11
N8 V9 D8 D9 V11 AA5
CKE2_B DQ13_B Y9 DDR_0A_DQ<24> DDR_0A_DQ<29> 6 W8 VDDQ_12 VSS1_21 Y8 DDR_0B_CKE<0> P4 DQ10_B U11 DDR_0B_DQ<31> DDR_0B_DQ<25> 6 B8 VDDQ_10 VSS1_25 A10
DDR_0A_CLK_P DQ14_B DDR_0A_DQ<25> DDR_0A_DQ<24> 6 VDDQ_13 VSS1_19 6,16 DDR_0B_CKE<0> DDR_0B_CKE<1> CKE0_B DQ11_B DDR_0B_DQ<28> DDR_0B_DQ<31> 6 VDDQ_11 VSS1_23 D9
6,16 DDR_0A_CLK_P P8 AA9 AA8 E8 6,16 DDR_0B_CKE<1> P5 U9 D8
DDR_0A_CLK_N CLK_P_B DQ15_B DDR_0A_DQ<25> 6 VDDQ_14 VSS1_17 PP1100_VDDQ CKE1_B DQ12_B DDR_0B_DQ<29> DDR_0B_DQ<28> 6 VDDQ_12 VSS1_21 Y8
P9 B10 AB5 N8 V9 W8
6,16 DDR_0A_CLK_N CLK_N_B VDDQ_15 VSS1_15 CKE2_B DQ13_B DDR_0B_DQ<24> DDR_0B_DQ<29> 6 VDDQ_13 VSS1_19 E8
Y3 F10 V5 Y9 AA8
DMI0_B GND VDDQ_16 VSS1_13 DDR_0B_CLK_P DQ14_B DDR_0B_DQ<30> DDR_0B_DQ<24> 6 VDDQ_14 VSS1_17 AB5 PP1100_VDDQ
Y10 U10 C5 6,16 DDR_0B_CLK_P P8 AA9 B10
DMI1_B AA10 VDDQ_17 VSS1_11 D4 DDR_0B_CLK_N P9 CLK_P_B DQ15_B DDR_0B_DQ<30> 6 F10 VDDQ_15 VSS1_15 V5
DDR_0A_DQS_2_P VDDQ_18 VSS1_9 6,16 DDR_0B_CLK_N CLK_N_B VDDQ_16 VSS1_13 C5
W3 D12 A3 Y3 GND U10
DQS0_P_B DDR_0A_DQS_2_N DDR_0A_DQS_2_P 6 VDDQ_19 VSS1_7 DMI0_B VDDQ_17 VSS1_11 D4
V3 W12 D2 Y10 AA10
DQS0_N_B DDR_0A_DQS_2_N 6 VDDQ_20 VSS1_5 V1 R272 R273 DMI1_B D12 VDDQ_18 VSS1_9 A3
W10 DDR_0A_DQS_3_P A1 VSS1_3 C1 240_F 240_F W3 DDR_0B_DQS_2_P W12 VDDQ_19 VSS1_7 D2
DQS1_P_B DDR_0A_DQS_3_P 6 DNU_1 VSS1_1 GND DQS0_P_B DDR_0B_DQS_2_P 6 VDDQ_20 VSS1_5 V1 R274 R275
V10 DDR_0A_DQS_3_N B1 R0201 R0201 V3 DDR_0B_DQS_2_N
DQS1_N_B DDR_0A_DQS_3_N 6 DNU_2 DQS0_N_B DDR_0B_DQS_2_N 6 VSS1_3 C1
AA1 A1 GND 240_F 240_F
DDR_RST_CH0_L T11 AB1 DNU_3 A5 DDQ_0A_ZQ<0> W10 DDR_0B_DQS_3_P B1 DNU_1 VSS1_1
6,16 DDR_RST_CH0_L RESET_L DNU_4 ZQ0 DQS1_P_B DDR_0B_DQS_3_P 6 DNU_2 R0201 R0201
A2 A8 DDQ_0A_ZQ<1> V10 DDR_0B_DQS_3_N AA1
DNU_5 ZQ1 DQS1_N_B DDR_0B_DQS_3_N 6 DNU_3 DDQ_0B_ZQ<0>
AB2 G11 AB1 A5
A11 DNU_6 ZQ2 DDR_RST_CH0_L T11 A2 DNU_4 ZQ0 A8 DDQ_0B_ZQ<1>
DNU_7 6,16 DDR_RST_CH0_L RESET_L DNU_5 ZQ1 G11
AB11 AB2
A12 DNU_8 A11 DNU_6 ZQ2
B12 DNU_9 AB11 DNU_7
AA12 DNU_10 A12 DNU_8
AB12 DNU_11 B12 DNU_9
DNU_12 AA12 DNU_10
AB12 DNU_11
DNU_12

B B
PP1100_VDDQ
PP1100_VDDQ

C247 C248 C249 C251 C253 C255 C408 C409 C257 C259
C234 C235 C236 C238 C240 C242 C404 C405 C244 C246 C407 1uF/16V/X5R 1uF/16V/X5R 1uF/16V/X5R 1uF/16V/X5R 1uF/16V/X5R 1uF/16V/X5R 0.1uF/50V/X5R 0.1uF/50V/X5R 10UF/10V/X5R 10UF/10V/X5R
1uF/16V/X5R 1uF/16V/X5R 1uF/16V/X5R 1uF/16V/X5R 1uF/16V/X5R 1uF/16V/X5R 0.1uF/50V/X5R 0.1uF/50V/X5R 10UF/10V/X5R 10UF/10V/X5R 10UF/10V/X5R C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0402 C0402
C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0402 C0402 C0402 ns 10% 10%
ns 10% 10% 10%
ns
GND GND GND GND GND GND GND GND GND GND
GND GND GND GND GND GND GND GND GND GND GND

U23 VDD caps:1uFx6, 0.1uFx2, 10uFx2

U22 VDD caps:1uFx6, 0.1uFx2, 10uFx3

PP1800_DRAM_U
PP1800_DRAM_U

C250 C252 C254 C256 C258

C237 C239 C241 C243 C245 C406 1uF/16V/X5R 1uF/16V/X5R 1uF/16V/X5R 1uF/16V/X5R 10UF/10V/X5R
1uF/16V/X5R 1uF/16V/X5R 1uF/16V/X5R 1uF/16V/X5R 10UF/10V/X5R 10UF/10V/X5R C0201 C0201 C0201 C0201 C0402
C0201 C0201 C0201 C0201 C0402 C0402 10%
10% 10%
A A

GND GND GND GND GND

GND GND GND GND GND GND

Bitland Information Technology Co.,Ltd.

U23 VDD caps:1uFx4, 10uFx1 Page Name

MEMORY CH 00/01 LPDDR4
Size
U22 VDD caps:1uFx4, 10uFx2 C
Project Name
Phaser
Rev
1.3
Date: Tuesday, November 27, 2018 Sheet 16 of 43
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
5 4 3 2 1

K4F8E304HB-MGCH
BGA200-HYNIX-H9HCNNN8RUMLHR
U20A K4F8E304HB-MGCH
PP1800_DRAM_U F1 P12 BGA200-HYNIX-H9HCNNN8RUMLHR
U1 VDD1_1 VSS_27 G12 U21A
U20B G4 VDD1_2 VSS_25 K11 U21B F1 P12
VDD1_3 VSS_23 P10 PP1800_DRAM_U VDD1_1 VSS_27 G12
K4F8E304HB-MGCH T4 K4F8E304HB-MGCH U1
BGA200-HYNIX-H9HCNNN8RUMLHR G9 VDD1_4 VSS_21 G10 BGA200-HYNIX-H9HCNNN8RUMLHR G4 VDD1_2 VSS_25 K11
DDR_1A_CS<0> H4 B2 DDR_1A_DQ<23> T9 VDD1_5 VSS_19 K9 DDR_1B_CS<0> H4 B2 DDR_1B_DQ<19> T4 VDD1_3 VSS_23 P10
6,17 DDR_1A_CS<0> DDR_1A_CS<1> CS0_A DQ0_A C2 DDR_1A_DQ<21> DDR_1A_DQ<23> 6 VDD1_6 VSS_17 G8 6,17 DDR_1B_CS<0> DDR_1B_CS<1> CS0_A DQ0_A C2 DDR_1B_DQ<18> DDR_1B_DQ<19> 6 VDD1_4 VSS_21 G10
H3 U12 H3 G9
6,17 DDR_1A_CS<1> CS1_A DQ1_A E2 DDR_1A_DQ<22> DDR_1A_DQ<21> 6 VDD1_7 VSS_15 G5 6,17 DDR_1B_CS<1> CS1_A DQ1_A E2 DDR_1B_DQ<22> DDR_1B_DQ<18> 6 VDD1_5 VSS_19 K9
K5 F12 K5 T9
D CS2_A DQ2_A F2 DDR_1A_DQ<20> DDR_1A_DQ<22> 6 VDD1_8 VSS_13 K4 CS2_A DQ2_A F2 DDR_1B_DQ<16> DDR_1B_DQ<22> 6 VDD1_6 VSS_17 G8 D
U12
DQ3_A F4 DDR_1A_DQ<16> DDR_1A_DQ<20> 6 VSS_11 P3 DQ3_A F4 DDR_1B_DQ<23> DDR_1B_DQ<16> 6 F12 VDD1_7 VSS_15 G5
DDR_1A_CA<0> DQ4_A E4 DDR_1A_DQ<17> DDR_1A_DQ<16> 6 VSS_9 G3 DDR_1B_CA<0> DQ4_A E4 DDR_1B_DQ<17> DDR_1B_DQ<23> 6 VDD1_8 VSS_13 K4
6,17 DDR_1A_CA<0> H2 PP1100_VDDQ H1 6,17 DDR_1B_CA<0> H2
DDR_1A_CA<1> J2 CA0_A DQ5_A C4 DDR_1A_DQ<19> DDR_1A_DQ<17> 6 K1 VDD2_1 VSS_7 K2 DDR_1B_CA<1> J2 CA0_A DQ5_A C4 DDR_1B_DQ<20> DDR_1B_DQ<17> 6 VSS_11 P3
6,17 DDR_1A_CA<1> DDR_1A_CA<2> CA1_A DQ6_A B4 DDR_1A_DQ<18> DDR_1A_DQ<19> 6 VDD2_2 VSS_5 P1 6,17 DDR_1B_CA<1> DDR_1B_CA<2> CA1_A DQ6_A B4 DDR_1B_DQ<21> DDR_1B_DQ<20> 6 VSS_9 G3
6,17 DDR_1A_CA<2> H9 N1 6,17 DDR_1B_CA<2> H9 PP1100_VDDQ H1
DDR_1A_CA<3> CA2_A DQ7_A DDR_1A_DQ<18> 6 VDD2_3 VSS_3 G1 DDR_1B_CA<3> CA2_A DQ7_A DDR_1B_DQ<21> 6 VDD2_1 VSS_7 K2
H10 R1 H10 K1
6,17 DDR_1A_CA<3> DDR_1A_CA<4> CA3_A VDD2_4 VSS_1 J1 6,17 DDR_1B_CA<3> DDR_1B_CA<4> CA3_A VDD2_2 VSS_5 P1
H11 K3 H11 N1
6,17 DDR_1A_CA<4> DDR_1A_CA<5> CA4_A DDR_1A_DQ<24> VDD2_5 VSS_2 T1 6,17 DDR_1B_CA<4> DDR_1B_CA<5> CA4_A DDR_1B_DQ<27> VDD2_3 VSS_3 G1
6,17 DDR_1A_CA<5> J11 B11 N3 6,17 DDR_1B_CA<5> J11 B11 R1
CA5_A DQ8_A C11 DDR_1A_DQ<28> DDR_1A_DQ<24> 6 A4 VDD2_6 VSS_4 N2 CA5_A DQ8_A C11 DDR_1B_DQ<26> DDR_1B_DQ<27> 6 K3 VDD2_4 VSS_1 J1
DQ9_A E11 DDR_1A_DQ<26> DDR_1A_DQ<28> 6 VDD2_7 VSS_6 J3 DQ9_A E11 DDR_1B_DQ<25> DDR_1B_DQ<26> 6 VDD2_5 VSS_2 T1
PP1100_VDDQ G2 AB4 PP1100_VDDQ G2 N3
ODT_A DQ10_A F11 DDR_1A_DQ<25> DDR_1A_DQ<26> 6 VDD2_8 VSS_8 T3 ODT_A DQ10_A F11 DDR_1B_DQ<31> DDR_1B_DQ<25> 6 VDD2_6 VSS_4 N2
F5 A4
DDR_1A_CKE<0> J4 DQ11_A F9 DDR_1A_DQ<30> DDR_1A_DQ<25> 6 H5 VDD2_9 VSS_10 N4 DDR_1B_CKE<0> J4 DQ11_A F9 DDR_1B_DQ<30> DDR_1B_DQ<31> 6 AB4 VDD2_7 VSS_6 J3
6,17 DDR_1A_CKE<0> DDR_1A_CKE<1> CKE0_A DQ12_A E9 DDR_1A_DQ<31> DDR_1A_DQ<30> 6 VDD2_10 VSS_12 T5 6,17 DDR_1B_CKE<0> DDR_1B_CKE<1> CKE0_A DQ12_A E9 DDR_1B_DQ<29> DDR_1B_DQ<30> 6 VDD2_8 VSS_8 T3
6,17 DDR_1A_CKE<1> J5 R5 6,17 DDR_1B_CKE<1> J5 F5
K8 CKE1_A DQ13_A C9 DDR_1A_DQ<27> DDR_1A_DQ<31> 6 U5 VDD2_11 VSS_14 T8 K8 CKE1_A DQ13_A C9 DDR_1B_DQ<24> DDR_1B_DQ<29> 6 H5 VDD2_9 VSS_10 N4
CKE2_A DQ14_A B9 DDR_1A_DQ<29> DDR_1A_DQ<27> 6 VDD2_12 VSS_16 N9 CKE2_A DQ14_A B9 DDR_1B_DQ<28> DDR_1B_DQ<24> 6 VDD2_10 VSS_12 T5
F8 R5
DQ15_A DDR_1A_DQ<29> 6 VDD2_13 VSS_18 J10 DQ15_A DDR_1B_DQ<28> 6 VDD2_11 VSS_14 T8
H8 U5
DDR_1A_CLK_P J8 R8 VDD2_14 VSS_20 T10 DDR_1B_CLK_P J8 F8 VDD2_12 VSS_16 N9
6,17 DDR_1A_CLK_P DDR_1A_CLK_N CLK_P_A VDD2_15 VSS_22 N11 6,17 DDR_1B_CLK_P DDR_1B_CLK_N CLK_P_A VDD2_13 VSS_18 J10
6,17 DDR_1A_CLK_N J9 C3 GND U8 6,17 DDR_1B_CLK_N J9 C3 GND H8
CLK_N_A DMI0_A C10 A9 VDD2_16 VSS_24 J12 CLK_N_A DMI0_A C10 R8 VDD2_14 VSS_20 T10
DMI1_A AB9 VDD2_17 VSS_26 T12 DMI1_A U8 VDD2_15 VSS_22 N11
D3 DDR_1A_DQS_2_P K10 VDD2_18 VSS_28 E1 D3 DDR_1B_DQS_2_P A9 VDD2_16 VSS_24 J12
DQS0_P_A E3 DDR_1A_DQS_2_N DDR_1A_DQS_2_P 6 N10 VDD2_19 VSS1_2 Y1 DQS0_P_A E3 DDR_1B_DQS_2_N DDR_1B_DQS_2_P 6 AB9 VDD2_17 VSS_26 T12
DQS0_N_A DDR_1A_DQS_2_N 6 VDD2_20 VSS1_4 W2 DQS0_N_A DDR_1B_DQS_2_N 6 VDD2_18 VSS_28 E1
H12 K10
D10 DDR_1A_DQS_3_P K12 VDD2_21 VSS1_6 AB3 D10 DDR_1B_DQS_3_P N10 VDD2_19 VSS1_2 Y1
DQS1_P_A DDR_1A_DQS_3_P 6 VDD2_22 VSS1_8 W4 DQS1_P_A DDR_1B_DQS_3_P 6 VDD2_20 VSS1_4 W2
E10 DDR_1A_DQS_3_N N12 E10 DDR_1B_DQS_3_N H12
DQS1_N_A DDR_1A_DQS_3_N 6 VDD2_23 VSS1_10 E5 DQS1_N_A DDR_1B_DQS_3_N 6 VDD2_21 VSS1_6 AB3
R12 K12
DDR_1A_CS<0> R4 AA2 DDR_1A_DQ<11> VDD2_24 VSS1_12 Y5 DDR_1B_CS<0> R4 AA2 DDR_1B_DQ<0> N12 VDD2_22 VSS1_8 W4
6,17 DDR_1A_CS<0> DDR_1A_CS<1> CS0_B DQ0_B DDR_1A_DQ<14> DDR_1A_DQ<11> 6 VSS1_14 C8 6,17 DDR_1B_CS<0> DDR_1B_CS<1> CS0_B DQ0_B DDR_1B_DQ<3> DDR_1B_DQ<0> 6 VDD2_23 VSS1_10 E5
6,17 DDR_1A_CS<1> R3 Y2 6,17 DDR_1B_CS<1> R3 Y2 R12
N5 CS1_B DQ1_B V2 DDR_1A_DQ<13> DDR_1A_DQ<14> 6 D1 VSS1_16 V8 N5 CS1_B DQ1_B V2 DDR_1B_DQ<7> DDR_1B_DQ<3> 6 VDD2_24 VSS1_12 Y5
CS2_B DQ2_B DDR_1A_DQ<15> DDR_1A_DQ<13> 6 PP1100_VDDQ VDDQ_1 VSS1_18 AB8 CS2_B DQ2_B DDR_1B_DQ<6> DDR_1B_DQ<7> 6 VSS1_14 C8
U2 W1 U2
DDR_1A_CA<0> DQ3_B DDR_1A_DQ<12> DDR_1A_DQ<15> 6 VDDQ_2 VSS1_20 W9 DDR_1B_CA<0> DQ3_B DDR_1B_DQ<1> DDR_1B_DQ<6> 6 VSS1_16 V8
R2 U4 B3 R2 U4 D1
6,17 DDR_1A_CA<0> DDR_1A_CA<1> CA0_B DQ4_B DDR_1A_DQ<10> DDR_1A_DQ<12> 6 VDDQ_3 VSS1_22 AB10 6,17 DDR_1B_CA<0> DDR_1B_CA<1> CA0_B DQ4_B DDR_1B_DQ<5> DDR_1B_DQ<1> 6 PP1100_VDDQ VDDQ_1 VSS1_18 AB8
P2 V4 F3 P2 V4 W1
6,17 DDR_1A_CA<1> DDR_1A_CA<2> CA1_B DQ5_B DDR_1A_DQ<9> DDR_1A_DQ<10> 6 VDDQ_4 VSS1_24 W11 6,17 DDR_1B_CA<1> DDR_1B_CA<2> CA1_B DQ5_B DDR_1B_DQ<4> DDR_1B_DQ<5> 6 VDDQ_2 VSS1_20 W9
6,17 DDR_1A_CA<2> R9 Y4 U3 6,17 DDR_1B_CA<2> R9 Y4 B3
DDR_1A_CA<3> R10 CA2_B DQ6_B AA4 DDR_1A_DQ<8> DDR_1A_DQ<9> 6 AA3 VDDQ_5 VSS1_26 E12 DDR_1B_CA<3> R10 CA2_B DQ6_B AA4 DDR_1B_DQ<2> DDR_1B_DQ<4> 6 F3 VDDQ_3 VSS1_22 AB10
6,17 DDR_1A_CA<3> DDR_1A_CA<4> CA3_B DQ7_B DDR_1A_DQ<8> 6 VDDQ_6 VSS1_28 Y12 6,17 DDR_1B_CA<3> DDR_1B_CA<4> CA3_B DQ7_B DDR_1B_DQ<2> 6 VDDQ_4 VSS1_24 W11
6,17 DDR_1A_CA<4> R11 B5 6,17 DDR_1B_CA<4> R11 U3
DDR_1A_CA<5> P11 CA4_B D5 VDDQ_7 VSS1_30 V12 DDR_1B_CA<5> P11 CA4_B AA3 VDDQ_5 VSS1_26 E12
6,17 DDR_1A_CA<5> CA5_B DDR_1A_DQ<4> VDDQ_8 VSS1_29 C12 6,17 DDR_1B_CA<5> CA5_B DDR_1B_DQ<14> VDDQ_6 VSS1_28 Y12
AA11 W5 AA11 B5
DQ8_B DDR_1A_DQ<5> DDR_1A_DQ<4> 6 VDDQ_9 VSS1_27 D11 DQ8_B DDR_1B_DQ<13> DDR_1B_DQ<14> 6 VDDQ_7 VSS1_30 V12
C PP1100_VDDQ T2 Y11 AA5 PP1100_VDDQ T2 Y11 D5 C
ODT_B DQ9_B V11 DDR_1A_DQ<6> DDR_1A_DQ<5> 6 B8 VDDQ_10 VSS1_25 A10 ODT_B DQ9_B V11 DDR_1B_DQ<12> DDR_1B_DQ<13> 6 W5 VDDQ_8 VSS1_29 C12
DDR_1A_CKE<0> DQ10_B DDR_1A_DQ<7> DDR_1A_DQ<6> 6 VDDQ_11 VSS1_23 D9 DDR_1B_CKE<0> DQ10_B DDR_1B_DQ<8> DDR_1B_DQ<12> 6 VDDQ_9 VSS1_27 D11
6,17 DDR_1A_CKE<0> P4 U11 D8 6,17 DDR_1B_CKE<0> P4 U11 AA5
DDR_1A_CKE<1> CKE0_B DQ11_B DDR_1A_DQ<3> DDR_1A_DQ<7> 6 VDDQ_12 VSS1_21 Y8 DDR_1B_CKE<1> CKE0_B DQ11_B DDR_1B_DQ<9> DDR_1B_DQ<8> 6 VDDQ_10 VSS1_25 A10
P5 U9 W8 P5 U9 B8
6,17 DDR_1A_CKE<1> CKE1_B DQ12_B DDR_1A_DQ<2> DDR_1A_DQ<3> 6 VDDQ_13 VSS1_19 E8 6,17 DDR_1B_CKE<1> CKE1_B DQ12_B DDR_1B_DQ<10> DDR_1B_DQ<9> 6 VDDQ_11 VSS1_23 D9
N8 V9 AA8 N8 V9 D8
CKE2_B DQ13_B DDR_1A_DQ<1> DDR_1A_DQ<2> 6 VDDQ_14 VSS1_17 AB5 PP1100_VDDQ CKE2_B DQ13_B DDR_1B_DQ<15> DDR_1B_DQ<10> 6 VDDQ_12 VSS1_21 Y8
Y9 B10 Y9 W8
DDR_1A_CLK_P P8 DQ14_B AA9 DDR_1A_DQ<0> DDR_1A_DQ<1> 6 F10 VDDQ_15 VSS1_15 V5 DDR_1B_CLK_P P8 DQ14_B AA9 DDR_1B_DQ<11> DDR_1B_DQ<15> 6 AA8 VDDQ_13 VSS1_19 E8
6,17 DDR_1A_CLK_P DDR_1A_CLK_N CLK_P_B DQ15_B DDR_1A_DQ<0> 6 VDDQ_16 VSS1_13 C5 6,17 DDR_1B_CLK_P DDR_1B_CLK_N CLK_P_B DQ15_B DDR_1B_DQ<11> 6 VDDQ_14 VSS1_17 AB5 PP1100_VDDQ
6,17 DDR_1A_CLK_N P9 U10 6,17 DDR_1B_CLK_N P9 B10
CLK_N_B Y3 AA10 VDDQ_17 VSS1_11 D4 CLK_N_B Y3 F10 VDDQ_15 VSS1_15 V5
DMI0_B GND VDDQ_18 VSS1_9 A3 DMI0_B GND VDDQ_16 VSS1_13 C5
Y10 D12 Y10 U10
DMI1_B W12 VDDQ_19 VSS1_7 D2 DMI1_B AA10 VDDQ_17 VSS1_11 D4
W3 DDR_1A_DQS_1_P VDDQ_20 VSS1_5 V1 R268 R269 W3 DDR_1B_DQS_0_P D12 VDDQ_18 VSS1_9 A3
DQS0_P_B DDR_1A_DQS_1_N DDR_1A_DQS_1_P 6 VSS1_3 C1 DQS0_P_B DDR_1B_DQS_0_N DDR_1B_DQS_0_P 6 VDDQ_19 VSS1_7 D2
V3 A1 GND 240_F 240_F V3 W12
DQS0_N_B DDR_1A_DQS_1_N 6 DNU_1 VSS1_1 DQS0_N_B DDR_1B_DQS_0_N 6 VDDQ_20 VSS1_5 V1 R270 R271
B1 R0201 R0201
W10 DDR_1A_DQS_0_P AA1 DNU_2 W10 DDR_1B_DQS_1_P A1 VSS1_3 C1 240_F 240_F
DQS1_P_B DDR_1A_DQS_0_P 6 DNU_3 DQS1_P_B DDR_1B_DQS_1_P 6 DNU_1 VSS1_1 GND
V10 DDR_1A_DQS_0_N AB1 A5 DDQ_1A_ZQ<0> V10 DDR_1B_DQS_1_N B1 R0201 R0201
DQS1_N_B DDR_1A_DQS_0_N 6 A2 DNU_4 ZQ0 A8 DDQ_1A_ZQ<1> DQS1_N_B DDR_1B_DQS_1_N 6 AA1 DNU_2
DDR_RST_CH1_L T11 AB2 DNU_5 ZQ1 G11 DDR_RST_CH1_L T11 AB1 DNU_3 A5 DDQ_1B_ZQ<0>
6,17 DDR_RST_CH1_L RESET_L DNU_6 ZQ2 6,17 DDR_RST_CH1_L RESET_L DNU_4 ZQ0 A8 DDQ_1B_ZQ<1>
A11 A2
AB11 DNU_7 AB2 DNU_5 ZQ1 G11
A12 DNU_8 A11 DNU_6 ZQ2
B12 DNU_9 AB11 DNU_7
AA12 DNU_10 A12 DNU_8
AB12 DNU_11 B12 DNU_9
DNU_12 AA12 DNU_10
AB12 DNU_11
DNU_12

B B

PP1100_VDDQ

PP1100_VDDQ

C221 C222 C223 C225 C227 C229 C402 C403 C231 C233
1uF/16V/X5R 1uF/16V/X5R 1uF/16V/X5R 1uF/16V/X5R 1uF/16V/X5R 1uF/16V/X5R 0.1uF/50V/X5R 0.1uF/50V/X5R 10UF/10V/X5R 10UF/10V/X5R
C208 C209 C210 C212 C214 C216 C398 C399 C218 C220 C401 C0402 C0402
C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201
1uF/16V/X5R 1uF/16V/X5R 1uF/16V/X5R 1uF/16V/X5R 1uF/16V/X5R 1uF/16V/X5R 0.1uF/50V/X5R 0.1uF/50V/X5R 10UF/10V/X5R 10UF/10V/X5R 10UF/10V/X5R 10% 10%
C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0402 C0402 C0402
ns 10% 10% 10%
ns
GND GND GND GND GND GND GND GND GND GND

GND GND GND GND GND GND GND GND GND GND GND

U21 VDD caps:1uFx6, 0.1uFx2, 10uFx2

U20 VDD caps:1uFx6, 0.1uFx2, 10uFx3

PP1800_DRAM_U PP1800_DRAM_U

C211 C213 C215 C217 C219 C400 C224 C226 C228 C230 C232
A 1uF/16V/X5R 1uF/16V/X5R 1uF/16V/X5R 1uF/16V/X5R 10UF/10V/X5R 10UF/10V/X5R 1uF/16V/X5R 1uF/16V/X5R 1uF/16V/X5R 1uF/16V/X5R 10UF/10V/X5R A
C0201 C0201 C0201 C0201 C0402 C0402 C0201 C0201 C0201 C0201 C0402
10% 10% 10%

GND GND GND GND GND GND GND GND GND GND GND Bitland Information Technology Co.,Ltd.
Page Name
MEMORY CH 10/11 LPDDR4
Size
U20 VDD caps:1uFx4, 10uFx2 C
Project Name
Phaser
Rev
U20 VDD caps:1uFx4, 10uFx1 1.3
Date: Tuesday, November 27, 2018 Sheet 17 of 43
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
5 4 3 2 1

EC_I2C_EEPROM_SCL
EC_I2C_EEPROM_SCL 19
EC_I2C_EEPROM_SDA
EC_I2C_EEPROM_SDA 19
USB_C_OC
USB_C_OC 8

PP1800_SENSOR_U PP3300_EC PP3300_PD_ANA U45A

D D
NPCX796FB0BX
bga144-nuvoton-npcx796f

M1 npcx7mnx C1 PCH_PROCHOT_ODL
R129 R130 R656 R657 9 ESPI_CLK PCI_CLK/ESPI_CLK/GPIO55 GPIO37/ADC5 PCH_RSMRST_L PCH_PROCHOT_ODL 11,37
R425 R430 R449 R454 L2 H10
9 ESPI_CS_L LFRAME_L/ESPI_CS_L/GPIO53 GPIOC2/PWM1/I2C6_SCL0 EC_PCH_PWR_BTN_ODL PCH_RSMRST_L 11,12
2.2K_F 2.2K_F 2.2K_F 2.2K_F 4.7K_J 4.7K_J 1.8K_J 1.8K_J H1 H9
9 ESPI_IO0 LAD0/ESPI_IO0/GPIO46 GPIOC1/I2C6_SDA0 EC_PCH_RTCRST EC_PCH_PWR_BTN_ODL 11,12
r0201 r0201 r0201 r0201 R0201 R0201 R0402 R0402 9 ESPI_IO1 J1 eSPI J5
K1 LAD1/ESPI_IO1/GPIO47 GPIO76/EC_SCI_L H5 EC_PCH_WAKE_ODL EC_PCH_RTCRST 11
9 ESPI_IO2 LAD2/ESPI_IO2/GPIO51 GPIO74 SYS_RST_ODL EC_PCH_WAKE_ODL 12
9 ESPI_IO3 L1 SOC B2 SYS_RST_ODL 11,12,21,22
K3 LAD3/ESPI_IO3/GPIO52 GPIO34/ADC6 F7 EC_RST_ODL
9 ESPI_RESET_L LRESET_L/ESPI_RST_L/GPIO54 GPIO02/PSL_IN4 USB_C0_HPD_1V8_ODL EC_RST_ODL 21,22
H7
EC_I2C_USB_C0_MUX_SCL GPIOC5/KBRST_L USB_C1_HPD_1V8_ODL USB_C0_HPD_1V8_ODL 7,29
29,32 EC_I2C_USB_C0_MUX_SCL K8 D10
EC_I2C_USB_C0_MUX_SDA K7 GPIO90/I2C1_SCL0 GPIOC6/SMI_L F10 PLT_RST_L USB_C1_HPD_1V8_ODL 7,39
29,32 EC_I2C_USB_C0_MUX_SDA EC_I2C_USB_C1_MUX_SCL GPIO87/I2C1_SDA0 GPIOC7 PLT_RST_L 11,12,21,23,28
39 EC_I2C_USB_C1_MUX_SCL L8
EC_I2C_USB_C1_MUX_SDA K9 GPIO92/I2C2_SCL0 E9 PMIC_EC_PWROK_OD
39 EC_I2C_USB_C1_MUX_SDA GPIO91/I2C2_SDA0 GPIOF4/I2C5_SDA1 PMIC_EC_RSMRST_ODL PMIC_EC_PWROK_OD 33
D5 A11
35 EN_PP3300_TRACKPAD_ODL USB_C_OC GPIO33/I2C5_SCL0/CTS_L GPIOE2 MECH_PWR_BTN_ODL PMIC_EC_RSMRST_ODL 33 MECH_PWR_BTN_ODL 21
D4 E6
TP71 EC_I2C_EEPROM_SCL F8 GPIO36/I2C5_SDA0/RTS_L GPIO01/PSL_IN3 J8 EN_EC_PWR TP158
TP28 EC_I2C_EEPROM_SDA GPIOD1/I2C3_SCL0 PSL_OUT/GPIO85 PP3300_PG_OD TP67
F9 I2C G6 EN_EC_PWR 34
PP3300_EC TP29 EC_I2C_BATTERY_3V3_SCL GPIOD0/I2C3_SDA0 GPIO60/PWM7 EN_PP5000_A PP3300_PG_OD 34,35
C12 G5
37 EC_I2C_BATTERY_3V3_SCL EC_I2C_BATTERY_3V3_SDA GPIOB5/I2C0_SCL0 GPIO73 EC_PCH_PWROK EN_PP5000_A 34
B12 J7
37 EC_I2C_BATTERY_3V3_SDA EC_I2C_SENSOR_U_SCL GPIOB4/I2C0_SDA0 GPIOB7/PWM5 PP5000_PG_OD EC_PCH_PWROK 11
26,27 EC_I2C_SENSOR_U_SCL J10 POWER SEQ H8
EC_I2C_SENSOR_U_SDA K10 GPIOB3/I2C7_SCL0 GPIOC0/PWM6 L5 EC_PIN_L5 PP5000_PG_OD 34 R264 0_J R0201
26,27 EC_I2C_SENSOR_U_SDA EC_I2C_CHARGER_3V3_SCL GPIOB2/I2C7_SDA0 GPIOD7 SLP_S0_L TP85
37 EC_I2C_CHARGER_3V3_SCL F5 H11
EC_I2C_CHARGER_3V3_SDA GPIOF3/I2C4_SCL1 GPIOA4 SLP_S4_L SLP_S0_L 11 LED_3_L 39
R131 R141 R158 R163 R224 R226 R227 R228 F6 K12
37 EC_I2C_CHARGER_3V3_SDA GPIOF2/I2C4_SDA1 SPIP_MOSI/GPIOA3 SLP_S3_L SLP_S4_L 11,35
10K_F 10K_F 10K_F 10K_F 10K_F 10K_F 10K_F 10K_F F11
21,22 UART_EC_TX_SERVO_RX UART_EC_TX_SERVO_RX GPIOA6 EN_PP3300_A SLP_S3_L 11,35 EN_PP3300_A 34
r0201 r0201 r0201 r0201 r0201 r0201 r0201 r0201 H4 A9
TP105 UART_SERVO_TX_EC_RX G4 GPIO65/CR_SOUT1/FLPRG# UART GPIOD4 E7 ACOK_OD TP22
ns ns ns ns ns ns ns TO ENABLE UART PROGRAMMING, H4 HAS TO BE LOW POWER UP
TP106 GPIO64/CR_SIN1 PSL_IN2/GPIO00 ACOK_OD 21,37
A10 SUSPWRDNACK EC_GPIO_03
21,22 UART_SERVO_TX_EC_RX KSI_00 GPIOD5 SUSPWRDNACK 11
A2
25 KSI_00 KSI_01_EC_SPI_FLASH_CS_L A3 KSI0/GPIO31/TRACEDATA3/GP_MOSI J3 EN_USB_A0_5V
22 KSI_01_EC_SPI_FLASH_CS_L R60 33_F R0201 KSI_02_EC_SPI_FLASH_MISO_R A4 KSI1/GPIO30/GP_CS_L GPIO67 D9 EC_GPIO_03 R184 WFCAM_VSYNC EN_USB_A0_5V 30
22 KSI_02_EC_SPI_FLASH_MISO KSI2/GPIO27/GP_MISO KSO16/GPIO03
ns 0_J R0201 WFCAM_VSYNC 26
R137
KSI_03_EC_SPI_FLASH_MOSI B3 K4 USB_C0_MUX_INT_ODL 100K_F
22 KSI_03_EC_SPI_FLASH_MOSI KSI_04_EC_SPI_FLASH_CLK KSI3/GPIO26/GP_MOSI GPIO61/PWROFF_L KB_BL_PWR_EN USB_C0_MUX_INT_ODL 29
B4 H2 R738 ns 0_J R0201 R0201
22 KSI_04_EC_SPI_FLASH_CLK KSI_05 KSI4/GPIO25/GP_SCLK GPIO62 KSO_14 TP99
C3 D6
25 KSI_05 KSI_06 C4 KSI5/GPIO24/GP_MISO KSO14/GPIO82 J4 USB_C1_PD_RST_ODL KSO_14 25
25 KSI_06 KSI_07 C5 KSI6/GPIO23 GPIO70 D11 KSO_13 USB_C1_PD_RST_ODL 29,39
C C
25 KSI_07 KSI7/GPIO22 KSO13/GPIO04 E8 USB_C1_MUX_INT_ODL KSO_13 25
KSO_00 GPIOF5/I2C5_SCL1 USB_C0_PD_RST USB_C1_MUX_INT_ODL 39 USB_C0_PD_RST 29
B5 KEYBOARD D7 GND
25 KSO_00 KSO_01 KSO00/GPIO21 KSO15/GPIO83 USB_C1_BC12_VBUS_ON TP24
B6 D8
CONNECT THE EC_AVSS TO GND AT ONE SINGLE POINT 25 KSO_01 EC_KSO_02_INV B7 KSO01/GPIO20 USB PD KSO17/GPIOB1 J2 USB_C0_BC12_VBUS_ON USB_C1_BC12_VBUS_ON 39
21 EC_KSO_02_INV KSO_03 B8 KSO02/GPIO17 GPIO63 E5 EC_VOLDN_BTN_ODL USB_C0_BC12_VBUS_ON 31
25 KSO_03 KSO_04 C7 KSO03/GPIO16 GPIO40 M12 USB_C0_BC12_CHG_DET_L EC_VOLDN_BTN_ODL 39
EC_AVSS 25 KSO_04 KSO_05 KSO04/GPIO15 SPIP_MISO/GPIO95 USB_C1_BC12_CHG_DET_L USB_C0_BC12_CHG_DET_L 31
18,24 EC_AVSS C6 L6 SPARE GPIO TO BE USED
25 KSO_05 KSO_06 KSO05/GPIO14 GPIOE4/I2C6_SCL1 USB_PD_C0_INT_ODL USB_C1_BC12_CHG_DET_L 39
C8 F4
25 KSO_06 KSO_07 B9 KSO06/GPIO13/GP_SEL1# GPIOE0 F12 USB_A0_CHARGE_EN_L TP25
25 KSO_07 KSO_08 KSO07/GPO12/JEN0_L GPIOA2 USB_A0_CHARGE_EN_L 30 USB_PD_C0_INT_ODL 32
R75 C9
PP3300_EC_VSBY 25 KSO_08 KSO_09 C10 KSO08/GPIO11/CR_SOUT1 G11 USB_A1_CHARGE_EN_L
0_J 25 KSO_09 KSO09/GPIO10/CR_SIN1 GPIOA0 USB_A1_CHARGE_EN_L 39
D1 KSO_10 B11 G3 USB_PD_C1_INT_ODL
PP3300_EC_VSBY R0603 25 KSO_10 KSO_11 KSO10/GPIO07 GPIOF1/ADC8 CHARGER_IADP USB_PD_C1_INT_ODL 39
LRB521BS-30T5G B10 E2
sod882 25 KSO_11 KSO_12 C11 KSO11/GPIO06 GPIO43/ADC2 D3 CHARGER_PMON CHARGER_IADP 37
25 KSO_12 KSO12/GPIO05 GPIO42/ADC3 CHARGER_PMON 37
U45B C517 C516 EC_RST_ODL 2 1 EC_VCC1_RST_ODL K6 M2 BASE_SIXAXIS_INT_L
VCC1_RST_L/GPO77 GPIO56/CLKRUN_L LID_ACCEL_INT_L BASE_SIXAXIS_INT_L 27
NPCX796FB0BX 0.1uF/6.3V/X5R 0.1uF/6.3V/X5R GND G10
GPIO50 CCD_MODE_EC_L LID_ACCEL_INT_L 26 EC_ENTERING_RW 21
bga144-nuvoton-npcx796f C96 M4 L7
C0201 C0201 GND 32KXIN/32KCLKIN GPIOE3/I2C6_SDA1 EC_BATT_PRES_L CCD_MODE_EC_L 31
0.1uF/10V/X5R 32KXOUT M5 CLK A12
TP107 32KXOUT GPIOE5 EC_ENTERING_RW EC_BATT_PRES_L 37
L4 C0201 F3 R257
VBAT M10 GND GND PP3300_EC EC_AP_INT_ODL M11 GPIOE1/ADC7 L12 EC_WP_ODL
VSTANDBY 12 EC_AP_INT_ODL GPIO94 SPIP_SCLK/GPIOA1 1M_F
TP_EC_GPIO97 L10 K5 GPIO80_PWM3 R18 ns 0_J R0201 KB_BL_PWM
PP3300_EC_A EC_I2S_SCLK GPIO97 GPIO80/PWM3 LED_1_L TP102 R0201
A1 FB2 240ohm/100MHz R0402 GND J11 G9
A5 VSS_1 npcx7mnx 9 EC_I2S_SCLK EC_I2S_TX_PCH_RX L11 GPIOA7/PS2_DAT3/TB2 WoV MISC GPIOC3/PWM0 G8 LED_2_L LED_1_L 27
A8 VSS_2 D1 C522 C510 9 EC_I2S_TX_PCH_RX EC_I2S_SFRM K11 GPIOB0 GPIOC4/PWM2 E10 EC_BL_EN_OD LED_2_L 27
E12 VSS_3 AVCC 4.7uF/6.3V/X5R R59 9 EC_I2S_SFRM GPIOA5/A20M GPIOD3 G7 LID_OPEN EC_BL_EN_OD 26
VSS_4 0.1uF/6.3V/X5R PSL_IN1/GPIOD2 LID_OPEN 22,26,39
G1 C0402 2.2_J F2 TEMP_SENSOR_AMB GND
VSS_5 C0201 GPIO45/ADC0 TEMP_SENSOR_CHARGER TEMP_SENSOR_AMB 24
J12 R0402 E3
M3 VSS_6 E1 EC_AVSS PP3300_EC_R H3 GPIO44/ADC1 G12 EN_USB_A1_5V TEMP_SENSOR_CHARGER 37
VSS_7 AVSS TP5 GPO32_TRIS_L GPOD6/JEN1_L GPIO96 TRACKPAD_INT_1V8_ODL EN_USB_A1_5V 39
M9 E4 E11
VSS_8 PP3300_EC_R TP2 GPO35_TEST_L K2 GPO32/TRIS_L GPIO93 D2 EC_GPIOF0_ADC9 TRACKPAD_INT_1V8_ODL 12,25
TP3 GPO66_ARM_L_X86 GPO35/TEST_L GPIOF0/ADC9 EC_GPIO41_ADC4 TP75
A7 G2 STRAPS C2 C531 C532
VCC1_1 C519 TP4 EC_GP_SEL_ODL GPO66/ARM_L/X86 GPIO41/ADC4 TP76
B1 C523 C526 C529 C76 L9 C0201 C0201
GND VCC1_2 D12 10UF/10V/X5R 22 EC_GP_SEL_ODL GPIOB6/PWM4/GP_SEL0# J6 EC_VOLUP_BTN_ODL 0.1uF/6.3V/X5R 0.1uF/6.3V/X5R
VCC1_3 0.1uF/6.3V/X5R 0.1uF/6.3V/X5R 0.1uF/6.3V/X5R 0.1uF/6.3V/X5R GPIO75/32KHZ_OUT/RXD/CR_SIN2 EC_VOLUP_BTN_ODL 39
M8 C0402 J9 TABLET_MODE_L
VCC1_4 C0201 C0201 C0201 C0201 TABLET_MODE_L 39

3
10% GPIO86/TXD/CR_SOUT2 L3 TP_EC_GPIO57
D SER_IRQ/ESPI_ALERT_L/GPIO57 TP130 EC_AVSS 18,24
Q8
B B
GND GND GND GND GND LSI1012N3T5G
H6 PMIC_EN EC_GP_SEL 1 sot883
PWRGD/GPIO72 PMIC_EN 33 21 EC_GP_SEL G S GND OF ADC FUNCTION. C531, 532 GOES TO E1 OF U45

2
PLACE R444 CLOSE TO PIN M7
GND PP3300_RTC
M7 EC_VSS_PLL R444 0_J R0201 PP1800_EC
PECI_DATA/GPIO81
ns
GND
F1 PP1800_EC_R R54 2.2_J R0402 PP3300_EC PP3300_SOC_A R153 R154 R157
VHIF H12
VSPI 499K_F 100K_F 10K_F
C521 C525 C527 R0201 R0201 r0201
10UF/10V/X5R 0.1uF/6.3V/X5R 0.1uF/6.3V/X5R
C0402 C0201 C0201 R474 R20
10% 100K_F 100K_F
LID_OPEN
R0201 R0201 EC_RST_ODL
GND GND GND
M6 VREF_PECI_VCAP_PLL R446 0_J R0201
VREF_PECI MECH_PWR_BTN_ODL
ns
USB_C1_MUX_INT_ODL EC_PCH_WAKE_ODL PPVAR_USB_C0_VBUS SUB_GPIO_ADC
A6 R429 10_F R0201 PLACE R429 CLOSE TO M6
CAP
ns
C518
1uF/10V/X5R C528 PP1800_SOC_A
C0201 0_J DIVIDES VOLTAGE
R0201 R147 R149 BY 10 FOR ADC
200K_F 200K_F
GND WHEN USE NPCX796FB EC_WP_ODL R467 100K_F R0201 EC_FLASH_WP_ODL
C528 STUFF WITH ZERO OHM R EC_FLASH_WP_ODL 19,21,22 R0201 R0201
R139 R140
R446 UNSTUFFED EC_GPIOF0_ADC9 EC_GPIO41_ADC4 1K_F 100K_F
GND R0201 R0201

C561
KSI_01 C530 R148 R150 0.01UF/25V/X7R PCH_PROCHOT_ODL
25 KSI_01 EC_KSI_02 0.01UF/25V/X7R C0402 TRACKPAD_INT_1V8_ODL
A 22K_F 22K_F A
21 EC_KSI_02 EC_KSI_03 C0402 10%
21 EC_KSI_03 KSI_04 R0201 R0201
10% ns
25 KSI_04
ns
EC_AVSS
R492 R493 R494 R499
499.0_F 499.0_F 499.0_F 499.0_F Bitland Information Technology Co.,Ltd.
GND OF ADC FUNCTION MUST GO TO E1 OF U45
r0201 r0201 r0201 r0201
Page Name
ADC CIRCUIT OR MONITORING VBUS IS OPTIONAL EC-NUVOTON
AND PARTNERS CAN CHOOSE TO USE OR NOT Size Project Name Rev
KSI_01_EC_SPI_FLASH_CS_L Custom
KSI_02_EC_SPI_FLASH_MISO Phaser 1.3
KSI_03_EC_SPI_FLASH_MOSI Date: Thursday, November 22, 2018 Sheet 18 of 43
KSI_04_EC_SPI_FLASH_CLK PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
was obtained with the expressed written consent of Bitland

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5 4 3 2 1

PCH SPI FLASH

PP1800_A
D D

R175
PP3300_A 100K_J
R0201

H1_AP_FLASH_SEL PCH_WP_OD
19,21 H1_AP_FLASH_SEL PCH_WP_OD 11
R520

3
100K_J
D Q16
R0201
PP1800_RTC LSI1012N3T5G

1
1 sot883 PP3300_RTC

G
PP1800_BIOS_SPI G

G
S
2 1 H1_AP_FLASH_SEL_3V3_ODL 3 2 2 3
19 H1_AP_FLASH_SEL_ODL

2
D
S
D

S
D40 R176
Q65 Q62

1
LRB521BS-30T5G GND 499K_F
LSI1012N3T5G LSI1012N3T5G

G
sod882 U7 R0201
2 3 PP1800_BIOS_SPI sot883 sot883 5
PP1800_A VDD

D
S
4
Y 2
Q60 A EC_FLASH_WP_ODL 18,21,22
LSI1012N3T5G C7 R91 R736 3 1
sot883 4.7uF/10V/X5R GND NC
U5 C0402
100K_J
R0201
100K_J
R0201 SN74LVC1G07DBVR 74LVC1G07
GD25LQ128DSIGT sot23-5
sop8_1d27_8 GND 1.65-5.5V
5 8
9 PCH_SPI_MOSI DIO VCC BIOS_FLASH_WP_ODL
2 3
9 PCH_SPI_MISO_R 1 DO WP# 7 SERVO_PCH_SPI_HOLD_L
9 PCH_SPI_CS0_L CS# HOLD# SERVO_PCH_SPI_HOLD_L 22
6 4
9 PCH_SPI_CLK CLK GND PP3300_EC

21,22 SERVO_PCH_SPI_MOSI R77 0_J R0201

R78 0_J R0201
21,22 SERVO_PCH_SPI_MISO R79 0_J R0201 GND R471
21,22 SERVO_PCH_SPI_CS_L
C 21,22 SERVO_PCH_SPI_CLK R80 0_J R0201 100K_J C
R0201

WINBOND: W25Q128FWPIF H1_AP_FLASH_SEL_ODL

H1_AP_FLASH_SEL_ODL 19
GIGADEVICES: 25LQ128CWIG

3
D
16MB PCH FLASH Q61
LSI1012N3T5G
H1_AP_FLASH_SEL
STANDBY CURRENT: 50 UA 19,21 H1_AP_FLASH_SEL
1
G S
sot883

MAX CURRENT: 25MA

2
GND

PP3300_EC
B
EC EEPROM SKU EEPROM B

C429 U28
R359 R360 0.01uF/10V,X5R M34E02-FDW6TP
R136 2.2K_F 2.2K_F c0201 tssop8_0d65_6d4
2.2K_F r0201 r0201
r0201 8 1
GND VCC A0 2
6 A1 3
18 EC_I2C_EEPROM_SCL SCL A2
18 EC_I2C_EEPROM_SDA 5
SDA
EEPROM_WP_OD 7 4
WP VSS
3

D Q22 WC_L : LOW = WRITE PROTECT DISABLE

LSI1012N3T5G GND
EC_FLASH_WP_ODL 1 WC_L : HI = WRITE PROTECT ENABLE
sot883
G S
2

I2C ADDRESS:0xA0
GND

A A

Bitland Information Technology Co.,Ltd.

Page Name
SPI ROM
Size Project Name Rev
C
Phaser 1.3
Date: Thursday, November 22, 2018 Sheet 19 of 43
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
5 4 3 2 1

PP1800_A LAYOUT NOTE: PLACING THE SERIAL R'S WITHIN 1 " OF THE DEBUG CONNECTOR
D PP1800_A D

C505 ns C506 ns
C0201 C0201
1uF/16V/X5R 0.1uF/16V/X5R
10% C507 ns C508 ns
C0201 C0201
J5 1uF/16V/X5R 0.1uF/16V/X5R
GND xDP DEBUG PP1800_A 10%
QSH-030-01-L-D-A-K-TR-60P-RUV
PP1800_A 61 62
G1 G2 GND
1 2 TMS
TCK 3 1 2 4 TDO TMS 12
12 TCK TDI 5 3 4 6 DBG_PMU_RSTBTN_L TDO 12
12 TDI DBG_PMU_PLTRST_L 7 5 6 8 TRSTPD DBG_PMU_RSTBTN_L 12,20
TRST_L 9 7 8 10 CX_PREQ_L
12 TRST_L CX_PRDY_L 11 9 10 12 CX_PREQ_L 12
12 CX_PRDY_L DBG_PTI_CLK0 R627 13 11 12 14 DBG_PTI_CLK2
12 DBG_PTI_CLK0
ns 0_J R0201 R602 ns 0_J R0201 R199
GP_INTD_DSI_TE2 15 13 14 16 DBG_PTI_CLK2 12
10K_F
7 GP_INTD_DSI_TE2 17 15 16 18 DBG_PTI_DATA_16
r0201
DBG_PTI_DATA_0 19 17 18 20 DBG_PTI_DATA_17 DBG_PTI_DATA_16 12
ns
12 DBG_PTI_DATA_0 DBG_PTI_DATA_1 21 19 20 22 DBG_PTI_DATA_18 DBG_PTI_DATA_17 12
12 DBG_PTI_DATA_1 DBG_PTI_DATA_2 23 21 22 24 DBG_PTI_DATA_19 DBG_PTI_DATA_18 12
12 DBG_PTI_DATA_2 DBG_PTI_DATA_3 25 23 24 26 DBG_PTI_DATA_20 DBG_PTI_DATA_19 12
12 DBG_PTI_DATA_3 DBG_PTI_DATA_4 27 25 26 28 DBG_PTI_DATA_21 DBG_PTI_DATA_20 12 GND
12 DBG_PTI_DATA_4 DBG_PTI_DATA_5 29 27 28 30 DBG_PTI_DATA_22 DBG_PTI_DATA_21 12
12 DBG_PTI_DATA_5 DBG_PTI_DATA_6 31 29 30 32 DBG_PTI_DATA_23 DBG_PTI_DATA_22 12
12 DBG_PTI_DATA_6 DBG_PTI_DATA_7 33 31 32 34 DBG_PMU_RSTBTN_L DBG_PTI_DATA_23 12
12 DBG_PTI_DATA_7 DBG_PTI_DATA_8 35 33 34 36 BOOT_HALT_L DBG_PMU_RSTBTN_L 12,20
12 DBG_PTI_DATA_8 DBG_PTI_DATA_9 37 35 36 38 DBG_PMU_PLTRST_L BOOT_HALT_L 12
12 DBG_PTI_DATA_9 DBG_PTI_DATA_10 39 37 38 40 DBG_PMU_PWRBTN_L DBG_PMU_PLTRST_L 12
12 DBG_PTI_DATA_10 DBG_PTI_DATA_11 41 39 40 42 DBG_RSMRST_L DBG_PMU_PWRBTN_L 12
12 DBG_PTI_DATA_11 DBG_PTI_DATA_12 43 41 42 44 DCI_DATA_PTITRACE3_0 DBG_RSMRST_L 12
12 DBG_PTI_DATA_12 DBG_PTI_DATA_13 45 43 44 46 DBG_PTI_DATA_TRACE3_1 DCI_DATA_PTITRACE3_0 12 C78 C93
12 DBG_PTI_DATA_13 DBG_PTI_DATA_14 47 45 46 48 DBG_PCH_I2C_SCL DBG_PTI_DATA_TRACE3_1 12 0.01uF/10V,X5R 0.01uF/10V,X5R
12 DBG_PTI_DATA_14 47 48 50 DBG_PCH_I2C_SCL 10
ns ns
DBG_PTI_DATA_15 49 DBG_PCH_I2C_SDA c0201 c0201
12 DBG_PTI_DATA_15 51 49 50 52 DBG_PTI_DATA_TRACE3_2 DBG_PCH_I2C_SDA 10
53 51 52 54 PCHTX_MIPI60RX_UART DBG_PTI_DATA_TRACE3_2 12
C C
55 53 54 56 PCHRX_MIPI60TX_UART PCHTX_MIPI60RX_UART 10 GND GND
57 55 56 58 PCHRX_MIPI60TX_UART 10
DBG_PTI_CLK1 R601 0_J R0201 59 57 58 60 R623 DCI_CLK_PTICLK3
12 DBG_PTI_CLK1
ns 59 60
ns 0_J R0201 DCI_CLK_PTICLK3 12
63 64

65
66
G3 G4

65
66
ns
GND GND

PRODUCTION NOTE: DNS J5, R627, R602, R623, R601

B B

A A

Bitland Information Technology Co.,Ltd.

Page Name
MIPI60 DEBUG HEADER
Size Project Name Rev
C
Phaser 1.3
Date: Tuesday, November 27, 2018 Sheet 20 of 43
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
5 4 3 2 1

KEEP NEAR TPM/SPI ROM TO MINIMIZE SPI STUBS

PLACE TERMINATION NEAR DIVIDE

(H1C)
D D
PP3300_RTC PP3300_VDDIOM

R782 33_J R0201 H1_SLAVE_SPI_MOSI R813 ns 0_J R0603_short

10 H1_SLAVE_SPI_MOSI_R H1_SLAVE_SPI_CLK
10 H1_SLAVE_SPI_CLK_R R792 33_J R0201
R793 33_J R0201 H1_SLAVE_SPI_CS_L
10 H1_SLAVE_SPI_CS_L_R H1_SLAVE_SPI_MISO_R
R794 33_J R0201
10 H1_SLAVE_SPI_MISO PP3300_VDDIOB
C378 C387 C388 C389
4.7uF/6.3V/X5R 0.1uF/10V/X5R 0.1uF/10V/X5R 0.1uF/10V/X5R
R450 ns 0_J R0603_short C0402 C0201 C0201 C0201
C386
0.1uF/10V/X5R
C0201 GND GND GND GND
PP1800_RTC PP1800_VDDIOA
PP3300_VDDIOM
GND
R451 ns 0_J R0603_short
ADDED TO MATCH 3MS DELAY
R857 C382 U37 PP3300_VDDIOM

H1
30.9K_F

E9

A7
B2
H1

J4
0.1uF/10V/X5R
R0201 C0201 BGA78-GOOGLE-660-00196-01-TEST
PP1800_SOC_A

VDDIOM_1
VDDIOM_2
VDDIOM_3
VDDIOA
VDDIOB
R561
C439 0.1uF/10V/X5R C0201 10% RESET_H1_ODL GND G1 C1 DIOM0 R873 0_J R0201 10K_J
GND RESETB DIOM0 SYS_RST_ODL 11,12,18,22
22 RESET_H1_ODL B1 DIOM1 R874 0_J R0201 CCD_MODE_ODL 31 r0201
DIOM1 A1 DIOM2 R875 0_J R0201
DIOM2 H1_BATT_PRES_L 37
R443 A2 DIOM3 R876 0_J R0201 PLT_RST_L 11,12,18,23,28
22 H1_BOOT_UART_TX DIOM3 A3 DIOM4 PP3300_VDDIOM
10K_J DIOM4
H1_BOOT_UART_TX B9
r0201 TP60 PCH_I2C_H1_SDA DIOA0
10 PCH_I2C_H1_SDA R334 ns 0_J R0201 DIOA1 D8
H1_SLAVE_SPI_MOSI C9 DIOA1
PCHTX_SERVORX_UART E8 DIOA2 B3 EC_RST_ODL R529
10,22 PCHTX_SERVORX_UART H1_SPI_MOSI DIOA3 DIOR0 MECH_PWR_BTN_IN_ODL EC_RST_ODL 18,22 PP1800_SOC_A
D9 A4 100K_J
DIOA4 DIOR1 MECH_PWR_BTN_IN_ODL 22,25,39
1 2 F8 B4 DIOR2
10 H1_PCH_INT_ODL H1_SLAVE_SPI_CLK DIOA5 DIOR2 EC_KSO_02_INV R0201
C F9 A5 EC_KSO_02_INV 18 C
D33 PCHRX_SERVOTX_UART G8 DIOA6 DIOR3 B5 EC_ENTERING_RW
10,22 PCHRX_SERVOTX_UART H1_SPI_CLK DIOA7 DIOR4 ACOK_OD EC_ENTERING_RW 18
LRB521BS-30T5G G9 A6 R448
PCH_I2C_H1_SCL DIOA8 DIOR5 EC_FLASH_WP_ODL ACOK_OD 18,37
sod882 R335 ns 0_J R0201 DIOA9 H8 B6 R999 1K_F R0201 100K_J
10 PCH_I2C_H1_SCL H1_SLAVE_SPI_MISO_R DIOA9 DIOR6 MECH_PWR_BTN_ODL EC_FLASH_WP_ODL 18,19,22
H9 B7
H1_SPI_MISO DIOA10 DIOR7 MECH_PWR_BTN_ODL 18 R0201
PP1800_VDDIOA R501 10K_J r0201 J9 A8 DIOR8
H1_SLAVE_SPI_CS_L J8 DIOA11 DIOR8 B8 KSO_02
22 H1_BOOT_UART_RX H1_BOOT_UART_RX DIOA12 DIOR9 EC_IN_RW_OD KSO_02 25
H7 A9 EC_IN_RW_OD 11
TP58 H1_SPI_CS_L DIOA13 DIOR10 BAT_DISABLE_ODL
R445 10K_J r0201 J7 C8
PP1800_VDDIOA DIOA14 DIOR11 BAT_DISABLE_ODL 37 PP5000_LDO

DEBUG_I2C_SCL J6 D1 H1_RDCC1 R859 ns 0_J R0201

22,36 DEBUG_I2C_SCL DEBUG_I2C_SDA DIOB0 RDCC1 H1_RDCC2 USB_C0_CC1 29,31
22,36 DEBUG_I2C_SDA H6 D2 R860 ns 0_J R0201 USB_C0_CC2 29,31
EC_GP_SEL J5 DIOB1 RDCC2
18 EC_GP_SEL H1_AP_FLASH_SEL DIOB2
H5 C577
19 H1_AP_FLASH_SEL R203 10K_J r0201 H1_BOOT_CONFIG J3 DIOB3 H2 U8
GND DIOB4 NC1 0.1uF/10V/X5R
R472 10K_J r0201 UART_SERVO_TX_EC_RX H4 H3 TLV8802DGKR
22 H1_BOOT_CONFIG 18,22 UART_SERVO_TX_EC_RX DIOB5 NC2 C0201

8
R473 10K_J r0201 UART_EC_TX_SERVO_RX J2 C3 msop8-4_9-65-ina333aidgkr
18,22 UART_EC_TX_SERVO_RX EN_PP3300_INA_H1_ODL J1 DIOB6 NC3 C4

VDD
36 EN_PP3300_INA_H1_ODL DIOB7 NC4 C5 GND
GND NC5 C7 6 OP_OUT2
DIOB4 - GND, BUT HAD INTERNAL PD - TIE MAY NOT BE NECESSARY NC6 IN2_N
D7
R855 0_J R0201 H1_USB_C0_SBU1 R304 E1 NC7 E3 OP_OUT2 7 5 USB_C0_CC2
31 USB_C0_SBU1 ns 0_J R0201 USBAN NC8
R718 10K_F r0201
OUT2 IN2_P
R720 100K_F R0201
R856 0_J R0201 H1_USB_C0_SBU2 R308 ns 0_J R0201 F1 E7
31 USB_C0_SBU2 USBAP NC9 F3
NC10 F7 R719 10K_F r0201 OP_OUT1 1 2 OP_OUT1
R310 0_J R0201 E2 NC11 G3 OUT1 IN1_N
F2 USBBN NC12 G5 3 USB_C0_CC1

VSS_10
VSS_11
R306 0_J R0201 R721 100K_F R0201

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
USBBP NC13 G6 IN1_P

VSS
NC14 G7
R204 R169 R178 R172 NC15
2M_F 2M_F 2M_F 2M_F

C2
D4
D5
D6
E4
E5
E6

4
F4
F5
F6
G2
R0201 R0201 R0201 R0201

GND
GND GND GND GND
B B
GND

FOR EC FLASH PROGRAMMING PP1800_VDDIOA

H1_SPI_CS_L R417 33_J R0201 DIOR2 R565 0_J R0201 KSI_02

H1_SPI_MISO SERVO_PCH_SPI_CS_L 19,22 KSI_02 25
R409 33_J R0201 SERVO_PCH_SPI_MISO 19,22 R412 R414 R416 R419
H1_SPI_MOSI R410 33_J R0201 R566 ns 0_J R0201 KSI_03 1M_F 1M_F 1M_F 4.7K_F
H1_SPI_CLK SERVO_PCH_SPI_MOSI 19,22 KSI_03 25
R413 33_J R0201 R0201 R0201 R0201 R0201
SERVO_PCH_SPI_CLK 19,22
ns
EC_KSI_03 R5671 0_J R0201 KSI_03 ns
18 EC_KSI_03 H1_SLAVE_SPI_CLK
DIOA1
DIOA9
H1_SLAVE_SPI_CS_L
EC_KSI_02 R567 ns 0_J R0201 KSI_02
18 EC_KSI_02
R162 R165 R166 R432
PP1800_VDDIOA 1M_F 1M_F 1M_F 1M_F
DIOR8 R568 0_J R0201 EC_KSI_02
R0201 R0201 R0201 R0201
R569 ns 0_J R0201 EC_KSI_03 ns ns
C445
U56 0.1uF/10V/X5R
C0201
ns GND GND GND GND
14
H1_AP_FLASH_SEL 1 VDD GND
H1_SPI_CS_L 2 1OE 3 SERVO_PCH_SPI_CS_L
4 1A 1Y
H1_SPI_MOSI 5 2OE 6 SERVO_PCH_SPI_MOSI
A
2A 2Y STRAPS : SPI FOR CONVERTIBLE/CLAMPSHELL A
10
H1_SPI_CLK 9 3OE 8 SERVO_PCH_SPI_CLK
13 3A 3Y
SERVO_PCH_SPI_MISO 12 4OE 11 H1_SPI_MISO
4A 4Y

GND
7 Bitland Information Technology Co.,Ltd.
Page Name
H1 SECURE MICROCONTROLLER
SN74LVC126APWR Size Project Name Rev
tssop14_0d65_6d4 GND C
ns Phaser 1.3
Date: Thursday, November 22, 2018 Sheet 21 of 43
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
5 4 3 2 1

(GOG)

P18 IS PCH UART REF VOLTAGE

D
P34 IS EC UART REF VOLTAGE D
CAN REMOVE U44, R519 IF J1 IS DNS
PCH SPI IS 1.8V
PP1800_BIOS_SPI
J1
TP125
TP124 SERVO_PCH_SPI_CLK
1 2 SERVO_PCH_SPI_CLK 19,21
SERVO_PCH_SPI_CS_L 3 GND1 S2CLK 4 SERVO_PCH_SPI_MOSI PP3300_EC
19,21 SERVO_PCH_SPI_CS_L SERVO_PCH_SPI_MISO S2CSN S2MOSI SERVO_PCH_SPI_MOSI 19,21
5 6
EC SPI IS 3.3V 19,21 SERVO_PCH_SPI_MISO SERVO_PCH_SPI_HOLD_L 7 S2MISO S2PWR 8
TP127 PP1800_A
PP3300_SERVO_EC 19 SERVO_PCH_SPI_HOLD_L KSI_04_EC_SPI_FLASH_CLK 9 S2HOLD GND8 10 KSI_01_EC_SPI_FLASH_CS_L TP128
18 KSI_04_EC_SPI_FLASH_CLK KSI_03_EC_SPI_FLASH_MOSI S1CLK S1CSN KSI_02_EC_SPI_FLASH_MISO KSI_01_EC_SPI_FLASH_CS_L 18
11 12 KSI_02_EC_SPI_FLASH_MISO 18
18 KSI_03_EC_SPI_FLASH_MOSI 13 S1MOSI S1MISO 14 EC_RST_ODL
TP126 S1PWR ECRST PCHRX_SERVOTX_UART EC_RST_ODL 18,21
15 16 PCHRX_SERVOTX_UART 10,21 R519
PCHTX_SERVORX_UART 17 GND15 UART2RX 18
10,21 PCHTX_SERVORX_UART UART2TX UART2PWR 1M_F
19 20
21 H1_BOOT_UART_RX TP95 H1_BOOT_UART_RX SD_DET GND20 MECH_PWR_BTN_IN_ODL R0201
21 22 MECH_PWR_BTN_IN_ODL 21,25,39 U44
TP6 SERVO_TP2 23 JTAG_TCK PWR_BTN# 24 5
PP1800_RTC 21 H1_BOOT_UART_TX TP7 H1_BOOT_UART_TX 25 JTAG_TMS JTAG_TDI 26
TP15 VDD 4
P29 IS PD UART REF VOLTAGE TP8 SERVO_TP4 27 JTAG_TDO JTAG_RTCK 28 SYS_RST_SERVO_ODL TP16
2 Y SYS_RST_ODL 11,12,18,21
TP9 29 JTAG_TRST_L CPU_RST_L 30 SERVO_TP30 A
R278 0_J R0201
PP3300_INA_SERVO JTAGPWR REC_MODE_L UART_SERVO_TX_EC_RX TP17
31 32 UART_SERVO_TX_EC_RX 18,21 1 3
UART_EC_TX_SERVO_RX 33 GND31 UART1RX 34 NC GND
18,21 UART_EC_TX_SERVO_RX PP3300_INA_SERVO UART1TX UART1PWR PP3300_EC
35 36 SN74LVC1G07DBVR
I2C_SERVO_SDA 37 35 GND36 38 I2C_SERVO_SCL sot23-5
SERVO_TP39 39 37 38 40 EC_FLASH_WP_ODL
TP10 EC_GP_SEL_ODL 39 40 EC_FLASH_WP_ODL 18,19,21
41 42 GND
TP56 H1_BOOT_CONFIG 43 41 42 44 LID_OPEN
18 EC_GP_SEL_ODL TP11 RESET_H1_ODL 43 44 LID_OPEN 18,26,39
45 46
TP12 45 46 TP18
47 48
TP13 49 47 48 50 TP19
TP14 49 50 TP20

AXK750147G
Cns50_0d4_v_axk750147g

C RESET_H1_ODL GND C
21 RESET_H1_ODL H1_BOOT_CONFIG GND
21 H1_BOOT_CONFIG

SERVO HEADER
CAN REMOVE U44, U26, Q77, C578, C579, R128, R47, R138 R519 IF J1 IS DNS

PP3300_EC_PROG
ns
R730 0_J R0201

PP3300_EC_VSBY PP3300_RTC
PP3300_SERVO_EC U26
TPS2559DRCR
son10-3x3-5-11p-tps2559drcr
2 7 PP3300_EC_PROG R4 ns 0_J R0201 R19 0_J R0201
3 IN_1 OUT_1 8
C578 C579 4 IN_2 OUT_2 9
4.7uF/6.3V/X5R IN_3 OUT_3 C580
0.1uF/6.3V/X5R
R728 C0402 C0201 10 4.7uF/6.3V/X5R
5 FAULT_L 1 C0402
499K_J ns EN GND_1
R0402 ns 6 11
ILIM GND_2
ns
GND GND ns
R729 GND
51.1K_F GND
3

PP5000_LDO
D R0201
Q77 ns
LBSS139LT1G
R47 ns 100K_J R0201 1 sot23-3
G S ns
GND
2

B B

R138 GND
499K_F
R0201
ns
POWER FOR FLASHING EC THROUGH SERVO
GND

CAN REMOVE Q68, Q69 IF J1 IS DNS

PP5000_LDO

PP5000_LDO
1

PP3300_INA
G

I2C_SERVO_SDA 3 2 PP3300_INA_SERVO
DEBUG_I2C_SDA 21,36
G
D

ns
S

2 3
Q68
D
S

LSI1012N3T5G C442 C443

sot883 1uF/10V/X5R Q75 4.7uF/10V/X5R
C0201 LBSS139LT1G C0402
PP5000_LDO ns sot23-3 ns
ns
GND GND
1
G

I2C_SERVO_SCL 3 2
DEBUG_I2C_SCL 21,36
D

Q69
LSI1012N3T5G
A sot883 A
ns

Bitland Information Technology Co.,Ltd.

Page Name
SERVO
Size Project Name Rev
C
Phaser 1.3
Date: Thursday, November 22, 2018 Sheet 22 of 43
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
5 4 3 2 1

32 GB EMMC STORAGE
150 UA SLEEP CURRENT

M10
M11
M12
M13
M14

N10
N11
N12
N13
N14

P11
P12
P13
P14
M1
M2
M3
M7
M8
M9

N1
N3
N6
N7
N8
N9

P1
P2
P8
P9
U13A

NC113
NC114
NC115
NC119
NC120
NC121
NC122
NC123
NC124
NC125
NC126

NC127
NC129
NC132
NC133
NC134
NC135
NC136
NC137
NC138
NC139
NC140

NC141
NC142
NC148
NC149
NC151
NC152
NC153
NC154
U13B A1 J1
PP3300_EMMC_DX A2 NC1 NC87 J2
A8 NC2 NC88 J3
D
E6 A3 EMMC_DAT0_R R205 10_F R0201 EMMC_DAT0 A9 NC8 NC89 J12 D
VCC0 DAT0 EMMC_DAT1_R EMMC_DAT1 EMMC_DAT0 9 NC9 NC92
F5 A4 R206 10_F R0201 A10 J13
VCC1 DAT1 EMMC_DAT2_R EMMC_DAT2 EMMC_DAT1 9 NC10 NC93
C147 C149 J10 A5 R207 10_F R0201 EMMC_DAT2 9 A11 J14
4.7uF/10V/X5R K9 VCC2 DAT2 B2 EMMC_DAT3_R R208 10_F R0201 EMMC_DAT3 A12 NC11 NC94
0.1uF/10V/X5R VCC3 DAT3 EMMC_DAT3 9 NC12
C0402 B3 EMMC_DAT4_R R209 10_F R0201 EMMC_DAT4 A13 K1
C0201 DAT4 EMMC_DAT5_R EMMC_DAT5 EMMC_DAT4 9 NC13 NC95
B4 R210 10_F R0201 A14 K2
DAT5 EMMC_DAT6_R EMMC_DAT6 EMMC_DAT5 9 NC14 NC96
B5 R211 10_F R0201 K3
DAT6 EMMC_DAT7_R EMMC_DAT7 EMMC_DAT6 9 NC97
B6 R212 10_F R0201 EMMC_DAT7 9 B1 K12
GND DAT7 B7 NC15 NC104 K13
A6 B8 NC21 NC105 K14
E7 VSS0 M6 EMMC_CLK_R R213 10_F R0201 EMMC_CLK B9 NC22 NC106
VSS1 CLK EMMC_CMD_R EMMC_CMD EMMC_CLK 9 NC23
G5 M5 R214 10_F R0201 B10 L1
VSS2 CMD EMMC_RCLK_R EMMC_RCLK EMMC_CMD 9 NC24 NC107
H10 H5 R215 10_F R0201 EMMC_RCLK 9 B11 L2
J5 VSS3 DS B12 NC25 NC108 L3
K8 VSS4 B13 NC26 NC109 L12
VSS5 K5 EMMC_RST_L_R B14 NC27 NC110 L13
PP1800_EMMC_DX RESET_L PP1800_EMMC_DX NC28 NC111 L14
C1 NC112
C6 A7 C3 NC29 H14
M4 VCCQ0 RFU1 E5 C5 NC31 NC86 H13
C148 C150 N4 VCCQ1 RFU2 E8 C7 NC33 NC85 H12
4.7uF/10V/X5R P3 VCCQ2 RFU3 G3 C8 NC35 NC84 H3
0.1uF/10V/X5R VCCQ3 RFU4 NC36 NC81
C0402 C0201 P5 G10 NC/RFU/VSF LEAVE FLOATING R323 C9 H2
VCCQ4 RFU5 K6 C10 NC37 NC80 H1
RFU6 100K_J NC38 NC79
K7 R0201 C11
RFU7 K10 C12 NC39
GND C4 RFU8 P7 C13 NC40
N2 VSSQ1 RFU9 P10 C14 NC41
N5 VSSQ2 RFU10 NC42
P4 VSSQ3 R427 0_J R0201
VSSQ4 EMMC_RST_ODL 9
P6 E9 ns
VSSQ5 VSF0 E10
VSF1 F10

NC43
NC44
NC45
NC46
NC47
NC48
NC49

NC50
NC51
NC52
NC60
NC61
NC62

NC63
NC64
NC65
NC68
NC69
NC70

NC71
NC72
NC76
NC77
NC78
GND EMMC_VDDI_BYP C2 VSF2 1 2
VDDI PLT_RST_L 11,12,18,21,28
D13

E12
E13
E14
D12
D13
D14
D1
D2
D3
D4

E1
E2
E3

F12
F13
F14
F1
F2
F3

G12
G13
G14
G1
G2
C146 LRB521BS-30T5G
EMMC_153P
C 1uF/6.3V/X5R sod882 EMMC_153P C
C0201 BGA153-SANDISK-SDIN7DP4-16G BGA153-SANDISK-SDIN7DP4-16G

NOT SURE HW RESET IS NEED. SW WILL RESET THE DEVICE UPON INIT
GND

PP3300_SD_DX
MICRO SD CARD
C340 C116
4.7uF/6.3V,X5R 0.1uF/10V,X5R
C0402 C0201

GND GND
R233
FB4 240ohm/100MHz R0402 U1 0_J PP3300_SD
GL3213S-OHY05 PP3300_SD
C142 R0201 PP3300_SD
C140 qfn28_0d4_4x4
0.1uF/10V,X5R 2.2uF/10V,X5R
C0201 C0402 R51
B B
13 10 100K_J C151 C152
PP1200_SD 22 V33IN SD_WP GND C559 4.7uF/6.3V,X5R
DVDD33 R0201 0.1uF/10V,X5R
GND GND 9 23 4.7uF/6.3V,X5R ns C0402 C0201
FB5 240ohm/100MHz R0402 25 AVDD33_1 PMOS C0402
AVDD33_2 J8
C431 12 5-251411002000-6
2.2uF/10V,X5R DVDD12 GND GND sd_card_5-251411002000-6
C0402 15 SD_DATA3 R217 10_F R0201 SD_DATA3_R 2
SD_D0 14 SD_CMD R218 10_F R0201 SD_CMD_R 3 CD_DAT3
3 SD_D1 20 6 CMD
GND 28 AVDD12_1 SD_D2 19 4 VSS
21 AVDD12_2 SD_D3 SD_CLK R219 10_F R0201 SD_CLK_R 5 VDD
C372 C421 C341 C430 C143 VUHSI 16 SD_DATA0 R220 10_F R0201 SD_DATA0_R 7 CLK
100pF/50V,NPO SD_CLK SD_DATA1 R221 10_F R0201 SD_DATA1_R 8 DAT0
0.1uF/10V,X5R 0.1uF/10V,X5R 1uF/10V,X5R 0.1uF/10V,X5R DAT1
C0201 18 SD_DATA2 R222 10_F R0201 SD_DATA2_R 1
C0201 C0201 C0201 C0201 SD_CMD SD_CD_3V3_OD SD_CD_3V3_OD_R DAT2
R237 0_J R0201 10
11 9 CD
GND GND GND GND GND SD_CD_L GND1
USB2_P5_SD_N 27 24 C446
8 USB2_P5_SD_N DM RST_L

GND2
GND3
GND4
USB2_P5_SD_P 26 0.1uF/10V,X5R
8 USB2_P5_SD_P DP 17 GND
USB3_P5_SD_RX_N GND C0201
8 USB3_P5_SD_RX_N C138 0.1uF/10V,X5R C0201 USB3_P5_SD_RX_C_N 1 C433 ns
USB3_P5_SD_RX_P C139 0.1uF/10V,X5R C0201 USB3_P5_SD_RX_C_P 2 TXN C314 C415 C320 C363 C380
8 USB3_P5_SD_RX_P 0.1uF/10V,X5R

11
12
13
TXP GND GND 10pF/50V/NPO 10pF/50V/NPO 10pF/50V/NPO 10pF/50V/NPO 10pF/50V/NPO C381
USB3_P5_SD_TX_N C0201
8 USB3_P5_SD_TX_N 4 C0201 ns C0201 ns C0201 ns C0201 ns C0201 ns 10pF/50V/NPO
USB3_P5_SD_TX_P 5 RXN 6 5% 5% 5% 5% 5% C0201
8 USB3_P5_SD_TX_P RXP X1
ns
7 R234 1M_F R0201 GND 5%
X2
29 8 GND GND GND GND GND
EP_GND RTERM R286 GND GND
R232 1K_J
1

1
R0201 D14 D15 D16 D17 D18 D19
GND 680.0_F AZ5725-01F.R7G AZ5725-01F.R7G AZ5725-01F.R7G AZ5725-01F.R7G AZ5725-01F.R7G AZ5725-01F.R7G
r0201 Y1 Dfn2_0d65_1d0x0d6 Dfn2_0d65_1d0x0d6 Dfn2_0d65_1d0x0d6 Dfn2_0d65_1d0x0d6 Dfn2_0d65_1d0x0d6 Dfn2_0d65_1d0x0d6
3 1 ns ns ns ns ns ns
2

2
2 4
25MHz
A y_4p_smd3225 A
GND GND GND GND GND GND GND
C153 C154
20pF/25V,NPO 20pF/25V,NPO
c0201 GND c0201

Bitland Information Technology Co.,Ltd.

GND GND
Page Name
eMMC/SD
Size Project Name Rev
C
Phaser 1.3
Date: Tuesday, November 27, 2018 Sheet 23 of 43
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

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was obtained with the expressed written consent of Bitland

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5 4 3 2 1

LEFT CHANNEL
(AMP) (AMP)
PP5000_A

U27 C11 C12

MAX98357AEWL+T
10UF/10V/X5R 0.1uF/10V/X5R
wlcsp9_0d4_1d437x1d347
C0402 C0201 CSP PACKAGE, BUT CAN BE ROUTED ON TYPE-3 PP3300_A
10%
R99 2K_F R0201 LSPK_PA_EN A1 A2 <10UA IN DEEP SLEEP
9 SPK_PA_EN I2S_SCLK_SPKR_LC_R SD_MODE VDD
9 I2S_SCLK_SPKR R43 0_J R0201 C1 GND GND
D
R44 0_J R0201 I2S_SFRM_SPKR_LC_R C3 BCLK B2 D
9 I2S_SFRM_SPKR LRCLK GAIN_SLOT
R96 0_J R0201 I2S_PCH_TX_SPKR_RX_LC_R B1 R113
9 I2S_PCH_TX_SPKR_RX DIN GND FILTER IF LEFT NOT ISOLATED 100K_F
C2 A3 SPKR_LEFT_P_R R103 0_J R0603 SPKR_LEFT_P
GND OUTP SPKR_LEFT_N_R SPKR_LEFT_N PP3300_A R0201
B3 R102 0_J R0603 ns
OUTN
HP_JACK_DET_L

GND C17 C273

PP1800_A 1uF/16V/X5R U10 1uF/16V/X5R
LEFT CHANNEL = SHORT (OR 2K FOR SAFETY) TO 1.8V C0201 DA7219-02VBA C0201
BGA32-DIALOG-DA7219 ns
GAIN_SLOT: 100K TO GND = 15 DB GAIN
GAIN_SLOT: UNCONNECTED = 9 DB GAIN GND C5
VDD HP_L
A3 HP_LEFT GND
A13 A5 HP_RIGHT
GAIN_SLOT: 0 TO VDD = 6 DB GAIN D4 VDD_MIC HP_R
GAIN_SLOT: 0 TO GND = 12 DB GAIN C14 C13 VDD_IO
GAIN_SLOT: 100K TO VDD = 3 DB GAIN 1uF/16V/X5R 1uF/16V/X5R A1 HP_CHARGE_PUMP_P
MIC_N A15 HPCSP C1 HP_CHARGE_PUMP_N
C0201 C0201 MIC_P MIC_N HPCSN HP_FLY_CAP_N
B16 C3 C20 1uF/16V/X5R
MIC_P HPCFN D2 HP_FLY_CAP_P C0402 10% C24 C25
HPCFP 1uF/16V/X5R 1uF/16V/X5R
GND C7 D16 HP_JACK_DET_L C0402 C0402
9 I2S_PCH_TX_HP_RX DATIN JKDET HP_SLEEVE
C9 A11 10% 10%
9 I2S_PCH_RX_HP_TX DATOUT SLEEVE B6 HP_SLEEVE_SENSE
PP1800_SOC_A SLEEVE_SENSE C13 HP_RING2 GND GND
D8 RING2 B4 HP_RING2_SENSE
9 I2S_SFRM_HP WCLK RING2_SENSE HP_MIC_PWR HP_MICBIAS
D6 C15 R112 2.2K_F r0201
RIGHT CHANNEL 9 I2S_SCLK_HP
9 I2S_MCLK_HP C11 BCLK
MCLK
MIC
PP5000_A R107
10K_F A9 HP_VMID
D12 VMID A7 HP_VREF
r0201 10 PCH_I2C_AUDIO_SCL SCL VREF HP_DACREF
D14 B8
10 PCH_I2C_AUDIO_SDA SDA DACREF
HP_INT_ODL D10 C19 C22 C23
U3 C269 12 HP_INT_ODL nIRQ B14 HP_MICBIAS
C271 1uF/16V/X5R 1uF/16V/X5R 1uF/16V/X5R
MAX98357AEWL+T MICBIAS
C 10UF/10V/X5R 0.1uF/10V/X5R B2 C0201 C0201 C0201 C
wlcsp9_0d4_1d437x1d347 B12 GND_CP B10
C0402 C0201 C18
10% GND_HP GND
1uF/16V/X5R
SPK_PA_EN R343 69.8K_F R0402 RSPK_PA_EN A1 A2
I2S_SCLK_SPKR I2S_SCLK_SPKR_RC_R SD_MODE VDD C0201
R344 0_J R0201 C1 GND GND GND
I2S_SFRM_SPKR R339 0_J R0201 I2S_SFRM_SPKR_RC_R C3 BCLK B2 GND
LRCLK GAIN_SLOT
I2S_PCH_TX_SPKR_RX R366 0_J R0201 I2S_PCH_TX_SPKR_RX_RC_R B1
I2C ADDRESSES:
DIN GND 0X18 GND
C2 A3 SPKR_RIGHT_P_R R374 0_J R0603 SPKR_RIGHT_P
GND OUTP B3 SPKR_RIGHT_N_R R388 0_J R0603 SPKR_RIGHT_N 0X19
OUTN
0X1A (DEFAULT)
0X1B
GND

RIGHT CHANNEL = 69.8K TO 1.8V (ADO)

GAIN_SLOT: GND = 12 DB GAIN

5K TO FILTER LEFT IF NOT ISOLATED

HP_RING2_SENSE R28 0_J R0201

J2
(ADO) MIC_N C15 1uF/16V/X5R C0402 10% HP_RING2 4
4
6
6
HP_JACK_DET_L R305 0_J R0201 HP_TERM_MAKETERM 5
5
MS
HP_LEFT R108 0_J R0201 HP_TIP 2 MS
CN4 HP_RIGHT R109 0_J R0201 HP_RING1 3 2
B
88266-04001 MIC_P C16 1uF/16V/X5R C0402 10% HP_SLEEVE 1 3 B

cns4_1d25_r_50281_GG 1
SPKR_LEFT_P 1 W-JA03406-0A00
SPKR_LEFT_N 2 1 HP_SLEEVE_SENSE R27 0_J R0201 audio_WJA03406-0A00
SPKR_RIGHT_P 3 2
SPKR_RIGHT_N 4 3 R106 R223
4 5.11K_F 5.11K_F
R0402 R0402 GND

1
C21 C145 C343 C357 6 ns ns D3 D4 D32 D5 D6
10pF/50V/COG 10pF/50V/COG 10pF/50V/COG 10pF/50V/COG 5 G2
G1 AZ5725-01F.R7G AZ5725-01F.R7G AZ5725-01F.R7G AZ5725-01F.R7G AZ5725-01F.R7G
C0201 ns C0201 ns C0201 ns C0201 ns Dfn2_0d65_1d0x0d6 Dfn2_0d65_1d0x0d6 Dfn2_0d65_1d0x0d6 Dfn2_0d65_1d0x0d6 Dfn2_0d65_1d0x0d6
5% 5% 5% 5% GND GND ns ns ns ns ns

2
GND

GND GND GND GND

GND GND GND GND GND

PP3300_A CHANGED MIC SERIES CAPS TO 1UF TO MATCH 10HZ 3DB

(THM) FREQUENCY RECOMMENDED IN THE DA7219 DATASHEET

THE TWO SENSE SIGNALS NEED TO BE CLOSE TO THE JACK CONNECTOR

ROUTE HP_RING2 AND HP_RING2_SENSE TOGETHER (TREAT AS DIFF PAIR EXCEPT NO NEED FOR IMPEDANCE CONTROL
R353 THE SAME APPLIES TO HP SLEEVE AND HP SLEEVE SENSE SIGNALS
51.1K_F ROUTE HP_RING2, HP_RING2_SENSE, HP_SLEEVE, HP_SLEEVE_SENSE BETWEEN HP_LEFT AND HP_RIGHT WHERE POSSIBLE
R0201

DO WE NEED THE AMBIENT SENSOR ? TEMP_SENSOR_AMB

TEMP_SENSOR_AMB 18
A A
1

R354
NTC_47K
R0402
Note for placement, it Bitland Information Technology Co.,Ltd.
2

EC_AVSS needs to be placed near CPU Page Name

18 EC_AVSS
requested by thermal team AUDIO
Size Project Name Rev
C
Phaser 1.3
Date: Thursday, November 22, 2018 Sheet 24 of 43
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
was obtained with the expressed written consent of Bitland

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5 4 3 2 1

TOUCHSCREEN AND PEN/STYLUS POWER TOGETHER

TOUCHSCREEN + STYLUS ( IF AVAILABLE )
PP1800_EC PP1800_A Q59 PP1800_PEN_DX
WPM2301-3/TR

2
sot23-3
3 PP1800_PEN_R R684 ns 0.1_F R0603_short PEN/STYLUS CONNECTOR (MOVE TO PAGE26)

D
R682 C344

G
100K_J 4.7uF/10V/X5R Phaser360s

1
R0201 C0402 C345
0.22uF/10V,X5R
Phaser360s
D
Phaser360s C0201
D
GND
Phaser360s

R683 200_F R0201

Phaser360s

3
D Q58
LSI1012N3T5G
1 sot883
12,35 EN_PP3300_TOUCHSCREEN G S Phaser360s

2
GND J19
Pitch=0.8mm_2pin
cns2_0d8_r_ws83021-s0171-hf
3
PEN_EJECT 1
12 PEN_EJECT
2
4
KEYBOARD
ADDED KSO13,14 FOR THE NUMPAD GND ns
CM TO CHOOSE CONNECTOR- THIS ONE WILL SUPPORT THE KEYPAD SO THE PINOUT MAY NEED TO CHANGE
GND

J9
cns30_0d8_r_51518
!!! PIN ASSIGNMENT NEED TO VERIFY WITH NEW KB !! PEN_EJECT FOR GARAGED STYLUS. IT WILL BE A WAKE SOURCE
196622-30041-3
31 30 KSO_12
29 KSO_08 KSO_12 18
KSO_09 KSO_08 18
C 28 C
27 KSO_11 KSO_09 18
KSO_10 KSO_11 18
26
KSO_10 18
25
24
23 KSO_05
22 KSO_06 KSO_05 18
KSO_06 18
21
20 KSO_03
19 KSO_02 KSO_03 18
KSI_00 KSO_02 21
18 KSI_00 18
17 KSO_01
KSO_04 KSO_01 18
16
KSI_03 KSO_04 18
15
KSI_02 KSI_03 21
14
13 KSO_00 KSI_02
KSO_00
21
18
KEYBOARD BACKLIGHT CONN
12 KSI_05
KSI_04 KSI_05 18
11 KSI_04 18
10 KSO_07
KSI_06 KSO_07 18
9
KSI_07 KSI_06 18
8 KSI_07 18
7 KSI_01
KBD_PWR_BTN_ODL KSI_01 18
6
5 KSO_13
4 KSO_13 18
3 KSO_14
2 KSO_14 18
TP40
32 1
TP46
D26 ns D54 ns
D37 ns D27 ns D28 ns D29 ns D30 ns D55 ns
D38 ns D42 ns D45 ns D48 ns D51 ns D56 ns
GND D58 ns D43 ns D46 ns D49 ns D52 ns D57 ns
D44 ns D47 ns D50 ns D53 ns
AZ5725-01F.R7G AZ5725-01F.R7G
AZ5725-01F.R7G AZ5725-01F.R7G AZ5725-01F.R7G AZ5725-01F.R7G AZ5725-01F.R7G AZ5725-01F.R7G
AZ5725-01F.R7G AZ5725-01F.R7G AZ5725-01F.R7G AZ5725-01F.R7G AZ5725-01F.R7G AZ5725-01F.R7G
AZ5725-01F.R7G AZ5725-01F.R7G AZ5725-01F.R7G AZ5725-01F.R7G AZ5725-01F.R7G AZ5725-01F.R7G
AZ5725-01F.R7G AZ5725-01F.R7G AZ5725-01F.R7G AZ5725-01F.R7G
B B

GND GND
GND GND GND GND

STUFF THESE FOR KEYBOARD LOCK BUTTON

KSO_09 KSI_03

TRACKPAD CONNECTOR
R246 R248
0_J 0_J
CM TO CHOOSE CONNECTOR
PP3300_RTC
R0201 R0201 PP3300_TRACKPAD_DX
Phaser360/360s Phaser360/360s
KBD_PWR_BTN_GND KBD_PWR_BTN_ODL

R250 C190 C192 C195

10K_J R72 R253 10UF/10V/X5R 1uF/6.3V/X5R 0.1uF/10V/X5R
R249 r0201 0_J 10K_J C0402 C0201 C0201 J12
R247 0_J R0201 R0201B 10% AFC68-S06F1A-HF
0_J PP1800_SOC_A ns cns6_0d5_r_51625
R0201
R0201 GND GND GND 6 8
Phaser 5
10 PCH_I2C_TRACKPAD_3V3_SDA

5
Phaser 4
10 PCH_I2C_TRACKPAD_3V3_SCL

G
MECH_PWR_BTN_IN_ODL 3

G
MECH_PWR_BTN_IN_ODL 21,22,39 1 6 3 4 TRACKPAD_INT_3V3_ODL 2
12,18 TRACKPAD_INT_1V8_ODL

D
TRACKPAD_BTN_L 1 7

S
Q47B TP32
GND
LBSS138DW1T1G Q47A
sot363 LBSS138DW1T1G
sot363 GND
THE PURPOSE OF THIS CIRCUIT STUFF THESE FOR KEYBOARD POWER BUTTON
IS TO ALLOW A SINGLE KEYBOARD
MATRIX FOR BOTH A CONVERTIBLE AVOIDS ANY LEAKAGE WITHOUT SOFTWARE EFFORTS
A A
AND CLAMSHELL SKU GND

Bitland Information Technology Co.,Ltd.

Page Name
KB, TPD
Size Project Name Rev
C
Phaser 1.3
Date: Tuesday, November 27, 2018 Sheet 25 of 43
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
was obtained with the expressed written consent of Bitland

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5 4 3 2 1

EDP LANE Q13B

EDP2-EDP3 DOES NOT NEED TO ROUTE TO CONNECTOR 9 DMIC_CLK1_G
DMIC_CLK1_G R320 0_J R0201
LBSS138DW1T1G ns
sot363
DMIC_CLK2 R225 0_J R0201 DMIC_CLK2_J
9,26 DMIC_CLK2
R485 ns 0_J R0402
1 6 CON_EDP_BKLTCTL_3V3

D
7 SOC_EDP_BKLTCTL_1V8
L2
EDP_TX1_N C8 0.1uF/10V/X5R C0201 ns EDP_TX1_C_N 1 2 EDP_TX1_L_N R263

G
PP1800_S PP3300_EDP_DX 7 EDP_TX1_N EDP_TX1_P EDP_TX1_C_P EDP_TX1_L_P
R117 10K_J R0201B 7 EDP_TX1_P C71 0.1uF/10V/X5R C0201 ns 4 3 200K_F

2
L4_0805 R0201
ns WCM2012F2S-900T04
R486 ns 0_J R0402 ns
R118 10K_J R0201B

5
R116 100K_J R0201 IF use FHD panel,C8,C71,R485,R486 should be stuffed GND
D D

G
R487 ns 0_J R0402
4 3 CON_EDP_BKLTEN_3V3
18 EC_BL_EN_OD

D
L21
2 1 EDP_TX0_N C117 0.1uF/10V/X5R C0201 EDP_TX0_C_N 2 1 EDP_TX0_L_N
7 SOC_EDP_BKLTEN 7 EDP_TX0_N EDP_TX0_P EDP_TX0_C_P EDP_TX0_L_P
D8 Q13A 7 EDP_TX0_P C118 0.1uF/10V/X5R C0201 4 3
LRB521BS-30T5G LBSS138DW1T1G l_4p_1012_choke
sod882 sot363 CM2-1012MCIN-900T01
R488 ns 0_J R0402
2 1
18,22,39 LID_OPEN EDP_TX3_N
D12
7 EDP_TX3_N EDP_TX3_P TP23
LRB521BS-30T5G
7 EDP_TX3_P EDP_TX2_N TP33
sod882 7 EDP_TX2_N EDP_TX2_P TP34
7 EDP_TX2_P TP35
VF=0.5V
IF LID CLOSE, DISABLE BKLT

NOTE:
1.Pin6~Pin42 map to Reference Desgin J15 Pin1~Pin40
LID ACCEL-CORAL (MOVE TO PAGE40) 2.Pin1~Pin5 is for G sensor (Reference design J24)
3.Pin43~Pin50 is for PEN (Reference design J22) PP1800_SENSOR_U

TOUCHSCREEN EDP+SENSOR+CAMERA+DMIC+PEN C3565

4.7uF/6.3V/X5R
C162
0.1uF/10V/X5R
C0402 C0201
NEED TO CHECK DMIC SPEC'S FOR 1.8V OR 3.3V SIGNAL LEVEL 10%
PP1800_SOC_A PP3300_TOUCHSCREEN_DX
J15
DMIC 1.8V POWER GND 1
LID_ACCEL_INT_L 2 51
PP1800_A 18 LID_ACCEL_INT_L EC_I2C_SENSOR_U_SDA 3
18,27 EC_I2C_SENSOR_U_SDA EC_I2C_SENSOR_U_SCL
C R123 R126 18,27 EC_I2C_SENSOR_U_SCL 4 C
10K_J 10K_J PP3300_CAMERA_S 5
r0201 r0201 6
2

Phaser360/360s Phaser360/360s 7
EDP_TX1_L_N
G

8
G

C422
1 6 3 4 TOUCHSCREEN_INT_3V3_ODL C110 C121 0.1uF/6.3V/X5R EDP_TX1_L_P 9
12 TOUCHSCREEN_INT_ODL
S

10
D

0.1uF/6.3V/X5R 1000pF/50V,X5R C0201

Q35B Q35A c0201 DMIC_DATA 11
LBSS138DW1T1G C0201 9 DMIC_DATA DMIC_CLK1
LBSS138DW1T1G R400 0_J R0402 12
sot363 9 DMIC_CLK1 DMIC_CLK2_J
sot363 GND 13
Phaser360/360s Phaser360/360s L1 14
USB2_P6_UCAM_N 1 2 USB2_P6_UCAM_CMC_N 15
PP3300_TOUCHSCREEN_DX 8 USB2_P6_UCAM_N USB2_P6_UCAM_P USB2_P6_UCAM_CMC_P
GND 8 USB2_P6_UCAM_P 4 3 16
L4_0805 17
ns WCM2012F2S-900T04 18
PP3300_CAMERA_S
R401 0_J R0402 19
R127 PP3300_EDP_DX C423 0.1uF/6.3V/X5R C0201 EDP_TX0_L_N 20
GND EDP_TX0_L_P
10K_J 21
PP3300_TOUCHSCREEN_DX 22
r0201 EDP_AUX_PANEL_C_P
C119 0.1uF/10V/X5R C0201 23
7 EDP_AUX_PANEL_P EDP_AUX_PANEL_C_N
Phaser360/360s C124 C125 7 EDP_AUX_PANEL_N C120 0.1uF/10V/X5R C0201 24
C126 4.7uF/6.3V/X5R 0.1uF/6.3V/X5R 25
4.7uF/6.3V/X5R TOUCHSCREEN_RST_3V3_ODL C0402 EDP_HPD_PANEL 26
C0201 7 EDP_HPD_PANEL CON_EDP_BKLTEN_3V3
C0402 27
3

Phaser360/360s R125 100K_J CON_EDP_BKLTCTL_3V3 28

D GND
Q9 R0201B 29
LSI1012N3T5G F2 PPVAR_BL_PWR 30
PP3300_EDP_DX
GND 12 TOUCHSCREEN_RST 1 sot883 1812L150/24MR 31
G S Phaser360/360s GND R0603 32
1 2 33
PPVAR_SYS
2

34
35
GND C122 C123 36
PP1800_A 22uF/25V/X5R 0.01UF/25V/X7R PP1800_PEN_DX 37
PP3300_TOUCHSCREEN_DX PCH_I2C_TOUCHSCREEN_3V3_SDA
C0805 C0402 38
PP3300_PEN_DX PP1800_PEN_DX 10 PCH_I2C_TOUCHSCREEN_3V3_SDA PCH_I2C_TOUCHSCREEN_3V3_SCL
10% 10% 39
PEN 7-BIT I2C ADDRESS = 0X09 Q835 ns
10 PCH_I2C_TOUCHSCREEN_3V3_SCL TOUCHSCREEN_INT_3V3_ODL 40
PEN ~ 100 MA R5159 R5148
LSI1012N3T5G TOUCHSCREEN_RST_3V3_ODL 41

1
B
sot883 R514 R515 42 B
R513 100K_J 100K_J 100K_J 100K_J 43
ns

G
100K_J 10 PCH_I2C_PEN_1V8_SDA
R0201 R0201 3 2 GND R0201B R0201B 10 PCH_I2C_PEN_1V8_SCL 44
45

D
R0201B Phaser360s Phaser360s ns ns

S
PP3300_PEN_DX
Phaser360s PP1800_PEN_DX 46
R5157 0_J R0201 PEN_PDCT_CONN_ODL PEN_PDCT_CONN_ODL 47
12 PEN_PDCT_ODL PEN_INT_CONN_ODL
Phaser360s 48 52
PEN_RESET_ODL PEN_RESET_ODL 49
PP1800_PEN_DX 50
Q837
3

LSI1012N3T5G
1

D Q83 sot883 51540-05041-002

LSI1012N3T5G ns GND GND
G

cns50_0d5_r_51540
1 sot883 3 2
12 PEN_RESET
D

G Phaser360s
S

S
2

R5158 0_J R0201 PEN_INT_CONN_ODL

12 PEN_INT_ODL
Phaser360s
GND

WFC CAMERA PP3300_CAMERA_S

C444
4.7uF/10V/X5R
C0402
Phaser360sWFC Phaser360sWFC
R458 0_J R0402
A GND J20 A
L12 1 9
1 2 USB2_P7_WCAM_CMC_N 2
8 USB2_P7_WCAM_N USB2_P7_WCAM_CMC_P
4 3 3
8 USB2_P7_WCAM_P
L4_0805 4
GND
ns WCM2012F2S-900T04 18 WFCAM_VSYNC 5
R408 0_J R0402 DMIC_CLK2 6 Bitland Information Technology Co.,Ltd.
9,26 DMIC_CLK2 DMIC_CAM2_DATA
Phaser360sWFC 9 DMIC_CAM2_DATA 7
8 10 Page Name
PREFERRED DMIC CHANNEL CONFIG GND C161 0.1uF/10V/X5R C0201 LID: eDP, CAM, TOUCH, SENSOR
Phaser360sWFC 50376-00801-001 Size Project Name Rev
R235 0_J R0402 cns8_0d6_r_50376 C
INTERFACE 1: STRAP MIC TO LEFT = CHANNEL 0 PP1800_A
Phaser360sWFC Phaser360sWFC Phaser 1.3

INTERFACE 2: STRAP MIC TO RIGHT = CHANNEL 3 Date: Tuesday, November 27, 2018 Sheet 26 of 43
GND PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
5 4 3 2 1

IMU WILL NOT BE STUFFED IF WFCAM IS STUFFED

For Phaser no need Magnetometer, remove it----0426
PP1800_SENSOR_U_IMU PP1800_SENSOR_U
Phaser360/360s
D D

R434 3.3_J R0402

U35 C511 C512

LSM6DS3TR-C 0.1uF/6.3V/X5R 1uF/6.3V/X5R R398 R404
LGA14-3X2_5-5 C0201 C0201 10K_J 10K_J
EC_I2C_SENSOR_U_SCL 13 5 Phaser360/360s Phaser360/360s r0201
18,26 EC_I2C_SENSOR_U_SCL EC_I2C_SENSOR_U_SDA SCL VDDIO r0201
14 8 Phaser360/360s
18,26 EC_I2C_SENSOR_U_SDA SDA VDD
1 12 GND GND Phaser360/360s
SDO/SA0 CS
10 3 COMPASS_I2C_SCL
11 NC1 SCX 2 COMPASS_I2C_SDA
R377 NC2 SDX
0_J
BASE_SIXAXIS_INT_L 4 6
R0201 18 BASE_SIXAXIS_INT_L BASE_SIXAXIS_INT2_L INT1 GND1
9 7
TP55 INT2 GND2
Phaser360/360s

Phaser360/360s GND
GND

IMU (6-AXIS)
MODE 2 (SLAVE TO EC, MASTER TO MAG)
I2C MODE: SET BY CS PIN TO HI
I2C ADDR: 0X6A (LSB SET BY SD0/SA0)
C C

CHARGE/BATTERY LED

Change LED color from orange/blue to red/green.

GMR SENSOR MOVED TO PAGE39 LED_1_L controls LED_RED and LED_2_L controls LED_GREEN.
This is the same as robo.

B B
PP3300_EC

LED_R LED_G
L-C191JRCT L-C191JGCT
led_0603 led_0603

C1

C2
RED LED AT ~13 MA
GREEN LED AT ~5 MA
TUNE VALUES BASED ON LEDS
R114 R115 EC CAN DRIVE 12MA
348_F 348_F
R0402 R0402

LED_2_L
LED_2_L 18

LED_1_L
LED_1_L 18

A A

Bitland Information Technology Co.,Ltd.

Page Name
SENSOR: COMPASS, GYRO (OPTION 1)
Size Project Name Rev
C
Phaser 1.3
Date: Thursday, November 22, 2018 Sheet 27 of 43
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
5 4 3 2 1

WIFI
CM TO CHOOSE CONNECTOR

(NGF)
D D
PP3300_WLAN_DX
J4
ngff_conn_as0bc5y-r06qe-7h M2_E
NGFF SlotA-SD KeyE

C73 C111
10UF/10V/X5R 1uF/6.3V/X5R
NGFF SlotA-SD PP3300_WLAN_DX
C0402 C0201
10% 10% 75
74 GND1 73
3.3Vaux3 RESERVED1 CNVI_CLK_PCH_TX_WLAN_RX_P 10
72 71
70 3.3Vaux2 RESERVED2 69 CNVI_CLK_PCH_TX_WLAN_RX_N 10
GND
68 RESERVED3 GND2 67 R34 R35
RESERVED4 Reserved6/PERn1 CNVI_D0_PCH_TX_WLAN_RX_P 10
R711 0_J R0201 66 65 100K_J 100K_J
64 RESERVED5 Reserved7/PERp1 63 CNVI_D0_PCH_TX_WLAN_RX_N 10
10 WLAN_CLKOUT_LCP NFC Reset# (MGPIO7)/RESERVED GND3 R0201 R0201
62 61
60 NFC I2C IRQ (MGPIO5)/ALERT Reserved8/PETn1 59 CNVI_D1_PCH_TX_WLAN_RX_P 10
NFC I2C SM CLK/I2C CLK Reserved9/PETp1 CNVI_D1_PCH_TX_WLAN_RX_N 10
58 57
WIFI_DISABLE_3V3_L 56 NFC I2C SM DATA/I2C DATA GND4 55
TP92 BT_DISABLE_3V3_L W_DISABLE#1(WIFI) PEWake0# WLAN_PCIE_WAKE_3V3_ODL 8
54 53
TP93 WLAN_PLT_RST_ODL_L Reserved/W_DISABLE#2(BT) CLKRQ0# WLAN_PCIE_CLKREQ_3V3_ODL 8
52 51
WLAN_SUSCLK 50 PERST0# GND5 49
PP1800_SOC_A SUSCLK REFCLKN0 PCIE_WLAN_CLK_N 8
12 CNVI_MFUART2_RXD R705 0_J R0201 48 47
COEX1 REFCLKP0 PCIE_WLAN_CLK_P 8
R707 0_J R0201 46 45
12 CNVI_MFUART2_TXD COEX2 GND6
R709 0_J R0201 44 43
12 CNVI_GNSS_PA_BLANKING COEX3 PERn0 PCIE_PCH_RX_WLAN_TX_N 8
42 41 PCIE_PCH_RX_WLAN_TX_P 8
R290 40 CLINK_CLK/RESERVED PERp0 39
38 CLINK_DATA/RESERVED GND7 37 PCIE_PCH_TX_WLAN_RX_N C113 0.1uF/10V/X5R C0201
20K_F CLINK_RST/RESERVED PETn0 PCIE_PCH_TX_WLAN_RX_C_N 8
CNVI_BRI_DT 36 35 PCIE_PCH_TX_WLAN_RX_P C114 0.1uF/10V/X5R C0201
r0201 10 CNVI_BRI_DT UART RTS PETp0 PCIE_PCH_TX_WLAN_RX_C_P 8
ns 10 CNVI_RGI_RSP R30 33_J R0201 CNVI_RGI_RSP_R 34 33
CNVI_RGI_DT 32 UART CTS GND8
10 CNVI_RGI_DT UART Tx
CNVI_BRI_DT
KEY E
C 23 CNVI_CLK_PCH_RX_WLAN_TX_P 10 C
R31 33_J R0201 CNVI_BRI_RSP_R 22 SDIO_RST 21
10 CNVI_BRI_RSP UART Rx SDIOWAKE CNVI_CLK_PCH_RX_WLAN_TX_N 10
20 19
18 UART Wake SDIODAT3 17
GND GND9 SDIODAT2 CNVI_D0_PCH_RX_WLAN_TX_P 10
16 15
LED#2 SDIODAT1 CNVI_D0_PCH_RX_WLAN_TX_N 10
10 WLAN_CLKREQ0 14 13
12 PCM_OUT SDIODAT0 11
PCM_IN SDIOCMD CNVI_D1_PCH_RX_WLAN_TX_P 10
10 CNVI_RF_RESET_L 10 9 CNVI_D1_PCH_RX_WLAN_TX_N 10
R15 8 PCM_SYNC SDIOCLK 7
PP3300_WLAN_DX 6 PCM_CLK GND10 5
10K_J LED#1 USB_D-
4 3 USB2_P2_BT_N 8
r0201 3.3Vaux1 USB_D+ USB2_P2_BT_P 8
2 1
3.3Vaux0 GND11

GND12

GND13
C75 C112
10UF/10V/X5R 1uF/6.3V/X5R
GND C0402 C0201
10% 10%

76

77
GND
GND

PLACE THE PULL-UP R CLOSE TO M.2. ( FOR DEBUG ) GND

PP3300_WLAN_DX
PP3300_WLAN_DX

PP3300_WLAN_DX R144
PP1800_SOC_A 100K_J
R38 R0201
B D9 B
100K_J ns
LRB521BS-30T5G U46
R0201
R714 sod882 ns 5
VDD 4 WLAN_PLT_RST_ODL_L
4.7K_J Y
2 1 WLAN_PLT_RST_ODL 2
R0201 11,12,18,21,23 PLT_RST_L
2

3
G

1 3
G

ns R1402
WIFI_DISABLE_L 1 6 3 4 WIFI_DISABLE_3V3_L D Q45 NC GND
8 WIFI_DISABLE_L 100K_J
S

LSI1012N3T5G SN74LVC1G07DBVR R0201

Q72B 1 sot883 ns sot23-5
Q72A 9 WLAN_PE_RST
LBSS138DW1T1G G S ns GND ns
sot363 LBSS138DW1T1G

2
sot363 R536 0_J R0201
ns GND

GND

PP3300_WLAN_DX PP3300_WLAN_DX

R39
R715 10K_J
4.7K_J r0201
R0201
2 1 WLAN_SUSCLK
BT_DISABLE_L BT_DISABLE_3V3_L 11 PCH_SUSCLK
11 BT_DISABLE_L R1400 0_J R0201
D10
LRB521BS-30T5G
sod882
ns
A A

Bitland Information Technology Co.,Ltd.

Page Name
WIFI/BT CONNECTOR
Size Project Name Rev
C
Phaser 1.3
Date: Tuesday, November 27, 2018 Sheet 28 of 43
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
was obtained with the expressed written consent of Bitland

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 RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
5 4 3 2 1

D D

FOR USB-C PORT 0

PP3300_PD_A->>>R581->>>PP3300_ANX(analog power rail )
->>>FB3->>>PP3300_PD_ANA(digital power rail)

PP3300_PD_ANA
PP3300_PD_A PP3300_ANX

0.1_F R581 R878 ns 0_J R0201

ns R0603_short

U16 FB3 240ohm/100MHz R0402

ANX3447QN-AC-R
qfn48-6x6-4-49p-anx7447qn C159 C158 C576 C157
0.1uF/10V/X5R 0.1uF/10V/X5R 1uF/16V/X5R 0.1uF/10V/X5R
13 C0201 C0201 C0402 C0201
DDI0_TX0_P 1 AVDD33_1 24
7 DDI0_TX0_P DDI0_TX0_N DP_LN_0P AVDD33_2 10%
2 39
7 DDI0_TX0_N DP_LN_0N DVDD_IO
DDI0_TX1_P 7 25 USB_C0_TX1_C_P C566 0.1uF/10V/X5R C0201 USB_C0_TX1_P
7 DDI0_TX1_P DDI0_TX1_N DP_LN_1P SSTXP1 USB_C0_TX1_C_N USB_C0_TX1_N USB_C0_TX1_P 31
8 26 C568 0.1uF/10V/X5R C0201

PP1800_SOC_A
AP 7 DDI0_TX1_N
DDI0_TX2_P 9
DP_LN_1N SSTXN1
31 USB_C0_RX1_P
USB_C0_TX1_N 31

7 DDI0_TX2_P DDI0_TX2_N DP_LN_2P SSRXP1 USB_C0_RX1_N USB_C0_RX1_P 31

10 32
7 DDI0_TX2_N DP_LN_2N SSRXN1 USB_C0_RX1_N 31 TO MLB CONNECTOR
50K INTERNAL PU PD DDI0_TX3_P 3 30 USB_C0_TX2_C_P C569 0.1uF/10V/X5R C0201 USB_C0_TX2_P
7 DDI0_TX3_P DDI0_TX3_N DP_LN_3P SSTXP2 USB_C0_TX2_C_N USB_C0_TX2_N USB_C0_TX2_P 31
4 29 C570 0.1uF/10V/X5R C0201
7 DDI0_TX3_N DP_LN_3N SSTXN2 USB_C0_TX2_N 31
R301 leave USB_C0_DISCHARGE/EN_USB_C0_5V_3A_ILIM
C 100K_J DDI0_AUX_P 16 34 USB_C0_RX2_P C
7 DDI0_AUX_P DDI0_AUX_N AUXP SSRXP2 USB_C0_RX2_N USB_C0_RX2_P 31 NC and keep components being stuffed for
17 33
R0201 7 DDI0_AUX_N AUXN SSRXN2 USB_C0_RX2_N 31
debug purpose
USB3_P0_C0_TX_P 12 22 USB_C0_CC1
USB_C0_HPD_1V8_ODL 8 USB3_P0_C0_TX_P USB3_P0_C0_TX_N 11 SSTX_P CC1 21 USB_C0_CC2 USB_C0_CC1 21,31
7,18 USB_C0_HPD_1V8_ODL 8 USB3_P0_C0_TX_N SSTX_N CC2 USB_C0_SBU1_ANX USB_C0_CC2 21,31
19
USB_C0_SBU1_ANX 31
3

USB3_P0_C0_RX_P 6 SBU1 18 USB_C0_SBU2_ANX PPVAR_USB_C0_VBUS

D 8 USB3_P0_C0_RX_P USB3_P0_C0_RX_N SSRX_P SBU2 USB_C0_SBU2_ANX 31
Q18 8 USB3_P0_C0_RX_N 5
LSI1012N3T5G SSRX_N 44 R563 0_J R0201 EN_USB_C0_5V_OUT
USB_C0_HPD_3V3 SOURCE_CTRL USB_C0_DISCHARGE EN_USB_C0_5V_OUT 32
sot883 1 36 35 R564 0_J R0201 R315 R319
G HPD DISCH_CTRL 43 R651 0_J R0201 USB_C0_CHARGE_ON R330
S SINK_CTRL USB_C0_CHARGE_ON 32 2M_F 2M_F
PP3300_ANX R303 4.7K_F R0201 USB_C0_DRP_EN 28
R0201 R0201 348K_F
2

R200 ROLE_SEL 41 EN_USB_C0_5V_3A_ILIM TP98

FF0
ns ns R0402
100K_J USB_C0_PD_RST 46 42 TP100
TP45 TP_TEST_EN 45 TEST_R FF1
R0201 TP84 TEST_EN VBUS_DIV
15
PP3300_PD_ANA EC_I2C_USB_C0_MUX_SCL 38 VBUS_SENSE 20 VBUS_OCP_CURRENT_SENSE TP104
18,32 EC_I2C_USB_C0_MUX_SCL EC_I2C_USB_C0_MUX_SDA CFG_SCL VBUS_OCP
18,32 EC_I2C_USB_C0_MUX_SDA 37
CFG_SDA 23 R333
USB_I2C_ADR0_C0 VCONN_PWR PP5000_A
48 49.9K_F
47 I2C_ADR_0 14
I2C_ADR1 NC[1] R0201
27 C267
R428 R562 40 NC[2] 4.7uF/10V/X5R
INPT_OUT 49 C0402
100K_J 4.7K_F EP_GND
R0201 R0201
ns
USB_I2C_ADR1_C0
USB_C0_MUX_INT_ODL
18 USB_C0_MUX_INT_ODL WITH THE NX20P3483, THE VBUS DISCHARGE CAN BE SW CONTROL

DEFAULT I2C ADDRESS: 0X58

IF ADR1 IS PULLED UP: 0X7C
B B

PP3300_PD_A

2 3 USB_C0_PD_RST
S

USB_C0_PD_RST 18
Q32
WPM2301-3/TR
G

sot23-3
1

R435 ns
100K_J
R0201
ns
USB_C1_PD_RST_ODL
18,39 USB_C1_PD_RST_ODL

A A
USB_C0_PD_RST IS ACTIVE HIGH WITH 100K INTERNAL PD

Bitland Information Technology Co.,Ltd.

Page Name
USB C TCPC/MUX (OPTION 2)
Size Project Name Rev
C
Phaser 1.3
Date: Thursday, November 22, 2018 Sheet 29 of 43
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
was obtained with the expressed written consent of Bitland

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 RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
5 4 3 2 1

BC 1.2 FOR THE TYPE-A PORT A0

D Deviation D

Change L5(PCMF3USB3S) to discrete EMI filter and ESD----0315

R484 4.7_F R0402
PP5000_A PP5000_A_BC12_A0
CHK2
USB3_P1_A0_RX_P 1 2 USB3_A0_RX_L_P
PP5000_USB_A0_VBUS 8 USB3_P1_A0_RX_P USB3_P1_A0_RX_N USB3_A0_RX_L_N
R677 ns 0.1_F R0603_short 4 3
8 USB3_P1_A0_RX_N
U18 ns WCM2012F2S-900T04
C196 1 12 L4_0805
C0603 R256 R258 R260 R262 IN OUT
22uF/10V/X5R 100K_J 100K_J 100K_J 100K_J 8 USB2_P1_A0_N USB2_P1_A0_N 2 11 USB2_A0_S_N R457 4.7_F R0402
USB2_P1_A0_P 3 DM_OUT DM_IN 10 USB2_A0_S_P
R0201 R0201 R0201 R0201 8 USB2_P1_A0_P DP_OUT DP_IN R418 4.7_F R0402

6 9 USB_A0_STATUS_L CHK3
CTL1 STATUS USB_A0_STATUS_L 39 USB3_P1_A0_TX_P USB3_A0_TX_L_P
7 8 USB3_P1_A0_TX_P 1 2
8 CTL2 13 USB_A0_OC_ODL USB3_P1_A0_TX_N 4 3 USB3_A0_TX_L_N
CTL3 FAULT USB_A0_OC_ODL 8 8 USB3_P1_A0_TX_N
ns WCM2012F2S-900T04
EN_USB_A0_5V 5 L4_0805
18 EN_USB_A0_5V EN
R254 0_J R0201 USB_A0_ILIM_SEL 4 17 R453 4.7_F R0402
39 USB_A1_STATUS_L ILM_SEL GND_PAD 14
15 GND
3 16 ILM_LO R442 0_J R0402
D Q21 ILM_HI
D34
LSI1012N3T5G SN1702001 CHK4
USB_A0_CHARGE_EN_L 1 sot883 qfn16_0d5_3x3 USB2_A0_S_N 4 3 USB2_A0_L_N USB2_A0_L_P 4 3 USB2_A0_L_N
18 USB_A0_CHARGE_EN_L USB2_A0_S_P USB2_A0_L_P 4 3
G S 1 2 5 2 GND
R679 R265 R267 6 5 2 1
ns WCM2012F2S-900T04
2

30.9K_F L4_0805 6 1
100K_J 51.1K_F
R0201 R0201 R0201 R462 0_J R0402 AZC199-04S
SOT23_6

C U36 C
AZ1045-04F.R7G_0.5pF
DFN10_0D5_2D5X1D0
USB3_A0_RX_L_N 1 10 USB3_A0_RX_L_N
USB3_A0_RX_L_P 2 Line-1 NC4 9 USB3_A0_RX_L_P
3 NC1 Line-2
USB3_A0_TX_L_N GND 4 GND 7 USB3_A0_TX_L_N
USB3_A0_TX_L_P 5 Line-3 NC3 6 USB3_A0_TX_L_P
NC2 Line-4

CM TO CHOOSE CONNECTOR

B PP5000_USB_A0_VBUS B

1
C202 C315
T + 100uF/6.3V C0603
TC3528 22uF/6.3V/X5R
10%

2
ns
CN1
GND GND WUSF0809-0A00
usb_wusf0809-0a00
1
USB2_A0_L_N 2 Vbus
USB2_A0_L_P 3 D-
4 D+ 10
USB3_A0_RX_L_P 6 PGND GND1 11
USB3_A0_RX_L_N 5 RX+ GND2 12
7 RX- GND3 13
USB3_A0_TX_L_P 9 GND GND4
USB3_A0_TX_L_N 8 TX+
TX-

GND GND

A A

Bitland Information Technology Co.,Ltd.

Page Name
USB A CONNECTIONS (MLB)
Size Project Name Rev
C
Phaser 1.3
Date: Tuesday, November 27, 2018 Sheet 30 of 43
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
5 4 3 2 1

PP3300_EC
Q66
Deviation:
TYPE-C PORT 0 BC1.2 WPM2301-3/TR PP5000_A
Change L7(PCMF2USB3S) to discrete EMI filter and ESD----0315
sot23-3
R692
VBUS_C0_BC12 3 2

S
100K_J

D
R0201 R452 0_J R0402

G
C182 R694 CHK8

1
1uF/10V/X5R 100K_J USB_C0_RX2_N 1 2 USB_C0_RX2_L_N
USB_C0_BC12_CHG_DET_L 18 29 USB_C0_RX2_N USB_C0_RX2_P USB_C0_RX2_L_P
4 3
C0201 R0201 29 USB_C0_RX2_P
3 ns WCM2012F2S-900T04
Q63 D L4_0805
LSI1012N3T5G GND R440 0_J R0402
sot883 1 Q71

3
D D
S G U54 LSI1012N3T5G R441 0_J R0402
MAX14637CVB+T D
sot883
2

qfn10_0d5_1d6x2d1 CHK9
USB_C0_BC12_CHG_DET 10 1 USB_C0_TX2_N 4 3 USB_C0_TX2_L_N
CHG_DET USB_C0_BC12_VBUS_ON 18 29 USB_C0_TX2_N USB_C0_TX2_P USB_C0_TX2_L_P
GND 9 S G
29 USB_C0_TX2_P 1 2
USB2_P0_C0_P 3 VBUS WCM2012F2S-900T04
8 USB2_P0_C0_P

2
USB2_P0_C0_N 2 DP_HOST R196
8 USB2_P0_C0_N DM_HOST
ns L4_0805
7 100K_J R447 0_J R0402
DP_CON 8 GND
DM_CON R0201
1
4 SW_OPEN U33
TP122 VBUS_C0_BC12 5 CHG_AL_N 6 AZ1045-04F.R7G_0.5pF
GOOD_BAT GND DFN10_0D5_2D5X1D0
GND USB_C0_RX2_L_N 1 10 USB_C0_RX2_L_N
USB_C0_RX2_L_P 2 Line-1 NC4 9 USB_C0_RX2_L_P
GND 3 NC1 Line-2
USB_C0_TX2_L_P GND 4 GND 7 USB_C0_TX2_L_P
USB_C0_TX2_L_N 5 Line-3 NC3 6 USB_C0_TX2_L_N
NC2 Line-4
ns
USB2_0_C0_P D22
R182 ns 0_J R0201
R183 ns 0_J R0201 USB2_0_C0_N USB_C0_CC2 4 3 USB_C0_CC1
21,29 USB_C0_CC2 5 4 3 2 USB_C0_CC1 21,29
5 2 GND
6 1
R886 R893 6 1

1
C18003 AZC199-04S C18002
BY-PASS RESISTORS ON USB2.0 IF U54 NOT USED 1M_F 1M_F
330pF/50V,X7R SOT23_6 330pF/50V,X7R
R0201 R0201
C0402 ns C0402

2
ns ns
GND GND
GND GND

C
Deviation: C

Change L6(PCMF3USB3S) to discrete EMI filter and ESD----0315

R164 0_J R0402
Note, for proto, stuffing
CHK10
USB_C0_RX1_P 1 2 USB_C0_RX1_L_P maxim to TI land pattern
29 USB_C0_RX1_P
29 USB_C0_RX1_N
USB_C0_RX1_N 4 3 USB_C0_RX1_L_N
should be ok, but for EVT, it TYPE-C PORT 0 (MLB)
ns L4_0805
WCM2012F2S-900T04 is required to update
R177 0_J R0402 particular footprint created
R252 0_J R0402
for maxim's use
J13
CHK11 NBR2D-AK1327
USB_C0_TX1_P 1 2 USB_C0_TX1_L_P usb_typec_nbr2d-ak1326-1
29 USB_C0_TX1_P USB_C0_TX1_N USB_C0_TX1_L_N
29 USB_C0_TX1_N 4 3
ns WCM2012F2S-900T04
L4_0805 GND GND
Type - C
R236 0_J R0402
G6
G5 GND6
R423 0_J R0402 GND5
A1 B12
CHK12 GND_A1 GND_B12
USB2_0_C0_P 1 2 USB2_0_C0_L_P USB_C0_TX1_L_P A2 B11 USB_C0_RX1_L_P
USB2_0_C0_N 4 3 USB2_0_C0_L_N SSTXp1 SSRXp1
ns WCM2012F2S-900T04 USB_C0_TX1_L_N A3 B10 USB_C0_RX1_L_N
L4_0805 SSTXn1 SSRXn1
R406 0_J R0402 A4 B9
PPVAR_USB_C0_VBUS VBUS_A1 VBUS_B1 PPVAR_USB_C0_VBUS
USB_C0_CC1 A5 B8 USB_C0_SBU2
CC1 SBU2
B USB2_0_C0_L_P USB2_0_C0_L_N B
A6 B7
Dp1_A Dn1_B
U42 USB2_0_C0_L_N A7 B6 USB2_0_C0_L_P
AZ1045-04F.R7G_0.5pF Dn1_A Dp1_B
DFN10_0D5_2D5X1D0 USB_C0_SBU1 A8 B5 USB_C0_CC2
USB_C0_RX1_L_N 1 10 USB_C0_RX1_L_N SBU1 CC2
USB_C0_RX1_L_P 2 Line-1 NC4 9 USB_C0_RX1_L_P A9 B4
NC1 Line-2 PPVAR_USB_C0_VBUS VBUS_A2 VBUS_B2 PPVAR_USB_C0_VBUS
GND 3
USB_C0_TX1_L_N 4 GND 7 USB_C0_TX1_L_N USB_C0_RX2_L_N A10 B3 USB_C0_TX2_L_N
USB_C0_TX1_L_P 5 Line-3 NC3 6 USB_C0_TX1_L_P SSRXn2 SSTXn2
NC2 Line-4 USB_C0_RX2_L_P A11 B2 USB_C0_TX2_L_P
SSRXp2 SSTXp2
ns
A12 B1
GND_A12 GND_B1
D36
G3 G1
USB2_0_C0_L_N 4 3 USB2_0_C0_L_P G4 GND3 GND1 G2
5 4 3 2 GND4 GND2
USB_C0_SBU2 5 2 USB_C0_SBU1 GND
6 1
21 USB_C0_SBU2 6 1 USB_C0_SBU1 21
AZC199-04S
C86 SOT23_6 C181 GND GND
1000pF/25V,X5R ns 1000pF/25V,X5R
c0201 c0201

GND GND

D23 R437 ns 0_J R0201

LRB521BS-30T5G
sod882
R3109 0_J R0201 1 2 Q25
PP3300_VDDIOM PP3300_EC PP5000_A LSI1012N3T5G
sot883
R3111 ns 0_J R0201 R291 2 3 USB_C0_SBU1
S

PP5000_LDO 29 USB_C0_SBU1_ANX
22K_F
G

A R0201 A
R41 R89
1

100K_J 100K_J CAREFULLY PLACE THE FETS, AVOID LONG STUB

CCD_DISENGAGE_SBU
R0201 R0201
2

5
G

C3112
1

CCD_MODE_ODL 1 6 3 4 0.01uF/16V,X5R Bitland Information Technology Co.,Ltd.

CCD_MODE_EC_L 18
S

G
D

c0201
Q300B 2 3 USB_C0_SBU2 Page Name
USB C CONNECTOR ( MLB )
3

Q300A 29 USB_C0_SBU2_ANX
D
S

LBSS138DW1T1G
sot363 LBSS138DW1T1G D GND Q28 Size
sot363 Project Name Rev
LSI1012N3T5G C
PP3300_VDDIOM 1 Q3108 sot883 Phaser 1.3
G S LSI1012N3T5G Date: Tuesday, November 27, 2018 Sheet 31 of 43
sot883 R439 ns 0_J PROPERTY NOTE: this document contains information confidential and property to
2

R0201 Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
21 CCD_MODE_ODL documents or disclosed to others or used for any purpose other than that for which it

RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
5 4 3 2 1

PORT 0
PROVIDES ESD PROTECTION, PLACE CLOSE TO CONNECTOR

D PPVAR_VBUS_IN D

TYPE-C CONN PPVAR_USB_C0_VBUS

U2
NX20P3483UK
bga42-nxp-nx20p3483uk-0_5s C285
C2 C6 10uF/35V/X5R
C3 VBUS0
VBUS1
VCHG0
VCHG1
D6 c0603 TO-CHARGER
C65 C4 E6
4.7uF/35V,X5R C5 VBUS2 VCHG2 F6 PP5000_A
c0603 D4 VBUS3 VCHG3 G6 GND
PP3300_PD_A D5 VBUS4 VCHG4
E4 VBUS5 D2 PP5000_POWER_MUX_C0 R674
VBUS6 V5V_0
ns 0_J R0603_short
GND E5 D3
F4 VBUS7 V5V_1 E2 C77 C325 C362
C59 C63 F5 VBUS8 V5V_2 F2 C0603 C0603 10UF/10V/X5R
4.7uF/6.3V/X5R G4 VBUS9 V5V_3 G2 22uF/10V/X5R 22uF/10V/X5R
0.1uF/10V/X5R VBUS10 V5V_4 C0402
C0402 G5 E3 10%
C0201 VBUS11 V5V_5 F3
A1 V5V_6 G3 GND GND GND PP3300_VBUS_LDO
GND GND VDD V5V_7
USB_PD_C0_EN_L A2 A5
TP26 EN_L VLDO
29 USB_C0_CHARGE_ON F1 C1 R201 0_J R0201 C81
G1 EN_SNK SDA B1 EC_I2C_USB_C0_MUX_SDA 18,29
29 EN_USB_C0_5V_OUT R202 0_J R0201 4.7uF/6.3V/X5R
EN_SRC SCL EC_I2C_USB_C0_MUX_SCL 18,29
C0402
USB_C_FRS_EN B6 E1
TP73 FRS_EN ADDR
R346 R355
100K_J 100K_J A3 D1 USB_PD_C0_INT_ODL GND
A6 CAP1 INT_L R216 PP3300_PD_A
R0201 R0201 CAP2
R288 A4 0_J
GND0 B3
100K_J GND1 R0201
C66 C74 B4
R0201 GND2
1000pF/16V,X5R 0.01UF/50V/X7R B5 R324
GND GND c0201 C0402 GND3 B2
GND4 47K_J
10% r0201
GND
GND
C PPVAR_VBUS_IN GND GND C
USB_PD_C0_INT_ODL 18
PPVAR_VBUS_IN

B B

A A

Bitland Information Technology Co.,Ltd.

Page Name
USB C VBUS CONTROL
Size Project Name Rev
C
Phaser 1.3
Date: Thursday, November 22, 2018 Sheet 32 of 43
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

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was obtained with the expressed written consent of Bitland

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5 4 3 2 1

PPVAR_VCCGI

L3
INDUCTOR SAT I IS 25A PEAK CURRENT:25A
1 2 PPVAR_VCCGI

1
C351
0.22uh l_2p_6d6x7d3 C134 C137 C186 C189 C194 C265 C276 C283 C286 C328 T + 330uF/2V
0.1uF/10V/X5R 0.1uF/10V/X5R 0.1uF/10V/X5R 0.1uF/10V/X5R 0.1uF/10V/X5R C0603 C0603 C0603 C0603 C0603
TC7343
C0201 C0201 C0201 C0201 C0201 22uF/6.3V/X5R 22uF/6.3V/X5R 22uF/6.3V/X5R 22uF/6.3V/X5R 22uF/6.3V/X5R
ns ns ns ns ns ns ns

2
PPVAR_VCCGI

D D
PPVAR_VCCGI
TOO MANY CAPS ?!

1
C352
C135 C184 C187 C191 C260 C266 C279 C284 C287 C347 T + 330uF/2V
0.1uF/10V/X5R 0.1uF/10V/X5R 0.1uF/10V/X5R 0.1uF/10V/X5R 0.1uF/10V/X5R C0603 C0603 C0603 C0603 C0603
TC7343
C0201 C0201 C0201 C0201 C0201 22uF/6.3V/X5R 22uF/6.3V/X5R 22uF/6.3V/X5R 22uF/6.3V/X5R 22uF/6.3V/X5R
ns ns ns ns ns ns

2
ns

R696 2.94K_F C128 0.1uF/10V/X5R

R0402 C0201

2
R52 C593
392.0_F R697 R53 1uF/16V/X5R
NTC_10K 536_F PP5000_A PPVAR_SYS
R0402 C0201 PPVAR_SYS
R0402 R0402

1
R69 0_J R0201 PMIC_ISENSE2_N

R68 0_J R0201 PMIC_ISENSE2_P R146

R145 2.2_F
2.2_F R0805
PPVAR_SYS PP5000_A PP1800_A R0805 R151
PP1800_A
100K_F
PPVAR_SYS
C292 R0201
R87 2.2uF/10V,X5R C377
C41 C48 C50
C0402 C367
10uF/25V/X5R 10uF/25V/X5R 10uF/25V/X5R 2.2_F
0.1uF/16V/X5R
1uF/16V/X5R PEAK CURRENT:4A
C0603 C0603 C0603 R0402 PP1800_DRAM_U C0201 PPVAR_VNN
C0402
5

ns U12 U24
RT9610CGQW RT5077AGQW R152 C454
D

DFN8_0D5_2x2 QFN52_0D4_6X6 127K_F 0.1uF/16V/X5R PPVAR_VNN

Q5H 4 DRV2_UGATE R82 0_J DRV2_UGATE_R C262 R0402 C0402

1
EMB09N03HR ns R0603_short C504 C469 C473 C477 C481 C485
G

1uF/16V/X5R
dfn8_1d27_5x6 3 8 10UF/16V/X5R 52 7 PP1100_VDDQ_S 22uF/6.3V/X5R 22uF/6.3V/X5R 22uF/6.3V/X5R 22uF/6.3V/X5R 22uF/6.3V/X5R
S

UGATE VCC C0201 VIN_CT VCC

C C0402 11 C0603 C0603 C0603 C0603 C0603 C
1
2
3

2
C132 0.1uF/10V/X5R R85 0_J 4 VSYS
BOOT
ns ns
C0402 ns R0603_short 1 20
PPVAR_VCCGI_SW DRV2_PHASE 2 EN GATE_VIN 4 PP1100_VDDQ_S
PHASE 5 VTT_IN PPVAR_VNN
PW M
5

1
7
LGATE
R168 ns 0.1_F PP1800_DRAM_U_R 19 GATE_VOUT
C464
R42 6 R0603_short 3 TP_VTT_SRC 10UF/16V/X5R C487 C489 C491 C492
D

GND VTT TP_VTT_SRC

10.0_F 9 2 C0402 22uF/6.3V/X5R 22uF/6.3V/X5R 22uF/6.3V/X5R 22uF/6.3V/X5R

2
EP_GND VTT_SNS

1
4 DRV2_LGATE R83 0_J DRV2_LGATE_R R124 28.7K_F R0201 9 C463 C0603 C0603 C0603 C0603
R0402 OCSET2
R0603_short 10UF/16V/X5R
G

ns ns PP5000_A ns
Q5L C0402
S

2
1

1
EMB04N03HR PMIC_DRV_EN2 44 47 C55 C453 C460
1
2
3

DRV_EN2 VIN1_1
2

C127 dfn8_1d27_5x6 PMIC_PWM2 42 48 0.1uF/16V/X5R 10UF/16V/X5R 10UF/16V/X5R

DRV2_PHASE R119 ns 0_J DRV2_PHASE_R 43 PW M2 VIN1_2 C0402 C0402
1000pF/50V,X7R C0201 PEAK CURRENT: 4.5A

2
R0603_short PHASE2
C0402 ns ns
1

14 PPVAR_VCCGI_SENSE_P 45 R724
ns LX1_1
R95 9.1K_F PPVAR_VCCGI_SENSE_P 35 46 L14 1 2 0.47uh PPVAR_VNN_R PP1050_S
R0402 VOUT2 LX1_2 1 PPVAR_VNN_SENSE_P l2520 0.005_F ns R0805_short
VOUT1 PPVAR_VNN_SENSE_P 14
R94 1K_J C316 1 2 c0402
R88 R0201 2200PF/50V,X7R 33 PP1050_S
34 COMP2
10K_F
PPVAR_SYS FB2 40 C466 C470 C474 C478 C482
r0201 VIN3_1 PP5000_A
C268 41 22uF/6.3V/X5R 22uF/6.3V/X5R 22uF/6.3V/X5R 22uF/6.3V/X5R 22uF/6.3V/X5R
VIN3_2

1
PPVAR_SYS C0201 PMIC_ISENSE2_P 32 C53 C435 C457 C0603 C0603 C0603 C0603 C0603
PP5000_A PMIC_ISENSE2_N 31 ISENSEP2 10UF/16V/X5R 10UF/16V/X5R PP1050_S_R
10pF/50V/COG 0.1uF/16V/X5R
C36 C45 C49 C263 ISENSEN2 C0402 C0402
C0201

2
10uF/25V/X5R 10uF/25V/X5R 10uF/25V/X5R 1000pF/50V,X5R 37 ns ns R725
C0603 C0603 C0603 c0201 PPVAR_VCCGI_SENSE_N 8 LX3_1 38 L9 1 2 0.47uh PP1050_S
14 PPVAR_VCCGI_SENSE_N VSSSENSE2 LX3_2
ns R86 24 PP1050_VCCRAM_S l2520 0.005_F ns R0805_short
VOUT3 PP1050_VCCRAM_S
2.2_F C486 C488 C490
R0402 R111 10.7K_F r0201 10 PP5000_A 22uF/6.3V/X5R 22uF/6.3V/X5R 22uF/6.3V/X5R
OCSET6 C0603 C0603 C0603
5

1
Q4H 25 C58 C436 C458 ns ns ns
D EMB12N03V U9 PMIC_DRV_EN6 51 VIN4 10UF/16V/X5R 10UF/6.3V/X5R PP1800_A_R
0.1uF/16V/X5R
dfn8_0d65_3x3 RT9610CGQW PMIC_PWM6 49 DRV_EN6 C0402 C0402
C0201 PEAK CURRENT: 1.5A

2
DFN8_0D5_2x2 DRV6_PHASE R120 DRV6_PHASE_R 50 PW M6 28
ns 0_J PHASE6 LX4_1 ns ns
G 4 DRV6_UGATE R70 0_J DRV6_UGATE_R C261 R0603_short 29 L8 1 2 1.0UH_3.5A l2520 R170 ns 0.02_F R0603_short
S R0603_short LX4_2 26
B
ns 1uF/16V/X5R
VOUT4 B
3 8 PP1100_VDDQ 5 PP1800_A
C0201 PP1100_VDDQ PP5000_A
3
2
1

UGATE VCC VOUT6

1
C131 0.1uF/10V/X5R R84 0_J 4 C54 C449 C459
C0402 BOOT 1 PMIC_PCH_INT_ODL 39 22 10UF/16V/X5R 10UF/16V/X5R PP1800_A
ns R0603_short EN 12 PMIC_PCH_INT_ODL IRQ_N VIN5
0.1uF/16V/X5R
DRV6_PHASE 2 C0402 C0402
C0201

2
PHASE 18 PMIC_EC_RSMRST_ODL
5

Q4L 5 ns ns PP1200_A_R C467 C471 C475 C479 C483

D EMB06N03V 7 PW M R411 10K_F r0201 PMIC_EC_RSMRST_ODL 36 21 22uF/6.3V/X5R 22uF/6.3V/X5R 22uF/6.3V/X5R 22uF/6.3V/X5R 22uF/6.3V/X5R
dfn8_0d65_3x3 LGATE 6 THERMTRIP_L 17 RSMRST_N LX5 18 L10 1 2 1.0UH_3.5A l2520 R171
GND 11 THERMTRIP_L THERMTRIP_N VOUT5 ns 0.02_F R0603_short C0603 C0603 C0603 C0603 C0603
9 PMIC_EN 30 ns ns ns
DRV6_LGATE EP_GND 18 PMIC_EN PMIC_EN
G 4 R81 0_J DRV6_LGATE_R
S ns R0603_short PP1800_SOC_A
R698 ns 100K_J R0201 PMIC_DDR_SEL 23 13
3
2
1

DDR_SEL I2C_SDA 12
I2C_SCL R547 R552 PEAK CURRENT: 2A
PP3300_A R646 10K_F r0201 PMIC_EC_PWROK_OD 27 4.7K_J 4.7K_J
PP3300_A PCH_PW ROK PP1200_A
18 PMIC_EC_PWROK_OD R0201 R0201
6
14 AGND 53
9,11 PCH_SLP_S0_L SLP_S0_N EP_GND PP1200_A
15
PP1100_VDDQ_SW

11 PCH_SLP_S3_L SLP_S3_N
11 PCH_SLP_S4_L 16
SLP_S4_N PCH_PMIC_I2C_SDA 11
C468 C472 C476 C480 C484
22uF/6.3V/X5R 22uF/6.3V/X5R 22uF/6.3V/X5R 22uF/6.3V/X5R 22uF/6.3V/X5R
PCH_PMIC_I2C_SCL 11
R1181 R699 C0603 C0603 C0603 C0603 C0603
100K_J 100K_J ns ns ns
I2C ADDR:0X5E
R0201 R0201

PP1100_VDDQ_S_R PP1100_VDDQ_S PP1100_VDDQ

PEAK CURRENT:4.0A
L4 R723
1 2 PP1100_VDDQ_S W2 ns 0_J R0603_short
0.47uh l2520 0.005_F ns R0805_short

1
C133 C136 C185 C188 C193 C264 C270 C282 C308 C87 C160 C198 C274 C275
R195 0.1uF/10V/X5R 0.1uF/10V/X5R 0.1uF/10V/X5R C0603 C0603 C0603 C0603 C0603 T + 330uF/2V C0603 C0603 C0603 C0603 C0603
10.0_F C0201 C0201 C0201 22uF/6.3V/X5R 22uF/6.3V/X5R 22uF/6.3V/X5R 22uF/6.3V/X5R 22uF/6.3V/X5R TC7343 22uF/6.3V/X5R 22uF/6.3V/X5R 22uF/6.3V/X5R 22uF/6.3V/X5R 22uF/6.3V/X5R
A R0402 ns ns ns ns A

2
ns
2

C44
1000pF/50V,X7R
C0402 Bitland Information Technology Co.,Ltd.
1

ns Page Name
PMIC
Size Project Name Rev
Custom
Phaser 1.3
Date: Tuesday, November 27, 2018 Sheet 33 of 43
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1

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 RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
5 4 3 2 1

PP3300_A
UVLO 4.5V- IF VBAT IS 2S, THEN WATCH OUT.
PPVAR_SYS

C564 C358
22uF/25V/X5R 22uF/25V/X5R U34
C0805 C0805 RT6258BGQUF
10% 10% QFN12_0D45_3X3-3
D D
5 10
VIN VOUT
EN_EC_PWR 2 1 C354
1uF/16V/X5R
D256 9 12 R194 1K_J R0201 C574 10pF/50V/COG C0201
C0201 VCC FF PP3300_A
LRB521BS-30T5G
sod882 PP3300_A_R

R192 1K_J R0201 6 2 PP3300_SW L11 1 2 R92 0.002_F R1206_short

18 EN_PP3300_A EN SW1 1.0uH ns
3 l_2p_6d6x7d3
R685 C758 SW2 C586 C589 C590 C591
100K_J 0.1uF/10V/X5R 0.1uF/10V/X5R 0.1uF/10V/X5R 47uF/10V,X5R 47uF/10V,X5R
R0201 C0201 C0402 C0201 C0805 C0805
PP3300_LDO_OUT 11 1 R64 10.0_J R0603
LDO BOOT PP3300_EC

1
C364
C0402
4.7uF/6.3V/X5R 4 7 PP3300_PG_OD R142 100K_J R0201

2
PGND PG
10%
PP3300_PG_OD
8
AGND
PP3300_PG_OD 18,35 +V3P3A
R133
ns 0.1_F Imax = 5A
R0603_short
LDO AUTO SWITCH AFTER PG Fsw = 500kHz
LDO 150MA MAX, AUTO SWITCH WHEN PG IS GOOD
R292 0_J R0402

U39
RT9742CNGJ5
SOT23-5
5 1 PP3300_RTC
IN VOUT
4 R687 ns 0.1_F R0603_short
EN PP3300_LDO
C C
2 3
GND FLG U31
ns RT9742CGJ5 PP3300_EC_WAKE
SOT23-5
U25 CAN NOT HAVE DISCHARGE. USE RT9742CNGJ5 5 1 R415 ns 0.1_F R0603_short PP3300_EC
IN VOUT
EN_EC_PWR 4 R495 ns 0.1_F R0603_short
18,34 EN_EC_PWR EN PP3300_PD_SW_A
2 3
R134 GND FLG
499K_F
R0201

PPVAR_SYS
PP5000_A
UVLO 5.4V - IF VBAT IS 2S, THEN WATCH OUT FOR VOLTAGE LOCK OUT FOR 1.8V

C356 C3561
22uF/25V/X5R 22uF/25V/X5R U40
C0805 C0805 RT6258CGQUF
10% 10% QFN12_0D45_3X3-3

5 10
VIN VOUT
C306
1uF/10V/X5R
C0201 11 9 R193 1K_J R0201 C587 10pF/50V/COG C0201
B VCC FF PP5000_A B
20%
PP5000_A_R

R188 1K_J R0201 6 2 PP5000_SW L15 1 2 R421 ns 0.002_F R1206_short

18 EN_PP5000_A EN SW1 1.0uH
3 C588 l_2p_6d6x7d3
SW2

1
R686 C757 0.1uF/10V/X5R C592 C394 C379
100K_J 0.1uF/10V/X5R C0402 0.1uF/10V/X5R 47uF/10V,X5R 47uF/10V,X5R
12 1 R66 10.0_J R0603 c0201 C0805 C0805
R0201 C0201 PP5000_LDO PP3300_EC

2
LDO BOOT
1

C330
C0402
4.7uF/10V/X5R 4 7 R431 499K_F R0201
2

PGND PG
10%
8 PP5000_PG_OD
AGND PP5000_PG_OD 18

+V5P0A
Imax = 5A
Fsw = 500kHz
LDO 150MA MAX, AUTO SWITCH WHEN PG IS GOOD

PP1800_RTC

PP3300_LDO U14
RT9078N-08GJ5
PP1800_RTC
SOT23-5 R97 U38
1 5 PP1800_EC
PP5000_LDO R181 0.51_F R0603 20K_F C567 TPS22929
VIN VOUT 1uF/10V/X5R SOT23-6
ns r0201
C565 C0201 6 1
1uF/10V/X5R 20% 4 VIN1 VOUT 2
C0201 4 EN_EC_PWR 3 VIN2 GND1 5
BP 18,34 EN_EC_PWR ON GND2
20% C72
A 1uF/10V/X5R A
R3484 0_J R0201 3 R98 C0201
EN 2 VOUT = (R1 + R2 )/ R2 * VSNS (0.8V) 20%
GND 16K_F
R0402
C3485
0.1uF/10V/X5R
C0201 Bitland Information Technology Co.,Ltd.
ns Page Name
POWER:1.8V(EC) 3.3V AND 5V
Size Project Name Rev
C
PP1800_EC MUST BE UP WITHIN 5MS AFTER PP3300_EC Phaser 1.3
Date: Thursday, November 22, 2018 Sheet 34 of 43
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
was obtained with the expressed written consent of Bitland

5 4 3 2 1
 RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
A B C D E

Q33 PP3300_S
PP3300_S WPM2301-3/TR
sot23-3 0_J
2 3 PP3300_S_R R364 ns 0.02_F R390 0.02_F R0603_short

D
PP3300_A
R0603_short R1Q ns
PP3300_CAMERA_S
R0603_short PP3300_SD_DX PP3300_A
ns
PP3300_SD_DX

1
C311 C317

G
4.7uF/6.3V/X5R 0.22uF/10V,X5R

1
C0402 C0201

2
R347 100K_J SLP_S3_L_R1
PP3300_EC
R0201

R356
200_F
R0201

SLP_S3_L_Q1
PP3300_PD_A PP3300_SOC_A_R
D D

3
R70Q 0_J R0201 EN_PP3300_CAMERA_R
11,18 SLP_S3_L D Q27 PP3300_A R2Q 0_J R0603_short R383 0.02_F R0603_short PP3300_SOC_A
LNTK3043NT5G ns ns
R71Q 0_J R0201 1 PP3300_PD_SW_A
12 EN_PP3300_CAMERA sot723
ns G S
3 2 R384 0.1_F R0603_short

S
D
PP3300_PD_A

2
Q73 ns
WPM2301-3/TR

1
sot23-3 C434

1
R491 100K_J R0201 4.7uF/6.3V/X5R
C0402

2
3
Q34 R167 0.1_F PP3300_PEN_DX
WPM2301-3/TR ns R0603_short D Q74
sot23-3 LSI1012N3T5G
Phaser360/360s 1 sot883
PP3300_TOUCHSCREEN_DX_R 18,34 PP3300_PG_OD
2 3 R369 0.1_F G
S

PP3300_A PP3300_TOUCHSCREEN_DX S
ns R0603_short

2
1

C312
G

4.7uF/6.3V/X5R C318 TOUCHSCREEN+STYLUS(IF AVAILABLE)

1

C0402 0.22uF/10V,X5R
2

Phaser360/360s C0201
R348 100K_J EN_PP3300_TOUCHSCREEN_R
PP3300_EC Phaser360/360s
R0201
Phaser360/360s
R357
200_F
R0201
Phaser360/360s
3

D Q29
LSI1012N3T5G
1 sot883
12,25 EN_PP3300_TOUCHSCREEN
C
G S Phaser360/360s C

PP3300_TOUCHSCREEN_DX PP1800_SENSOR_S
2

Q39 PP1800_S
WPM2301-3/TR
PP1800_A sot23-3

2 3 R387 0.1_F

D
PP3300_EMMC_DX ns R0603_short
PP1800_SENSOR_U

1
C321

G
4.7uF/6.3V/X5R

1
PP3300_A R370 0.02_F R0603_short PP3300_EMMC_DX C0402 C326

2
ns 0.22uF/10V,X5R ALS, GYRO, COMPASS, AUDIO
C0201

R372 100K_J R0201 SLP_S4_L_R2

PP3300_EC

R375
200_F
R0201
Q31
PP3300_TRACKPAD_DX WPM2301-3/TR
SLP_S4_L_Q2
sot23-3
2 3 P3300_TRACKPAD_DX_R R368 0.1_F
S

PP3300_A PP3300_TRACKPAD_DX

3
ns R0603_short
1

C309 D Q37
G

4.7uF/6.3V/X5R C329 LNTK3043NT5G

1

C0402 0.22uF/10V,X5R 11,18 SLP_S4_L 1 sot723

2

C0201 G S
PP3300_EC R345 100K_J

2
R0201

18 EN_PP3300_TRACKPAD_ODL R351 2K_F

R0201

B B

PP3300_WLAN_DX FOR CNVI MODULE, DNS U15 AND BYPASS WITH RESISTOR. PP1800_EMMC_DX
PP3300_A PP3300_WLAN_DX_R
PP1800_A R386 0.02_F R0603_short PP1800_EMMC_DX
EMMC
R186 0_J R0603 ns 180MA

C324 U15
10UF/6.3V/X5R RT9742DGJ5
R321 C0402 SOT23-5
100K_F 10% 5 1 R389 0.02_F R0603_short PP3300_WLAN_DX
R0201 IN VOUT
ns
1

ns 4 C26 C32
EN 0.1uF/10V/X5R 4.7uF/6.3V/X5R
10 EN_PP3300_WLAN_L
2 3 C0201 C0402
2

GND FLG
ns PP1800_SOC_A
PP1800_A R381 0.02_F R0603_short PP1800_SOC_A
ns

PP3300_A
PP3300_EDP_DX
C310 U60 PP3300_EDP_DX_R
10UF/6.3V/X5R RT9742CGJ5
C0402 SOT23-5
10% 5 1 R367 0.02_F R0603_short PP3300_EDP_DX
IN VOUT
A ns A
1

R726 0_J R0201B 4 C35

7 EN_PP3300_EDP_DX EN 4.7uF/6.3V/X5R
C27
C3564 2 3 0.1uF/10V/X5R C0402
2

4.7uF/6.3V/X5R GND FLG

C0201
C0402
10% Bitland Information Technology Co.,Ltd.
ns
Page Name
POWER-LOAD SWITCH
Size Project Name Rev
C
Phaser 1.3
Date: Thursday, November 22, 2018 Sheet 35 of 43
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

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5 4 3 2 1

PP3300_INA

INA3221AIRGVT INA3221AIRGVT
R741 R742 C673 U77 QFN16-4X4-65-17P-MAX4063 U79 QFN16-4X4-65-17P-MAX4063
4.7K_J 4.7K_J 0.1uF/10V/X5R
R0201 R0201 C0201
ns ns ns 16 12 16 12
VPU IN+1 PP3300_EDP_DX_R PP3300_INA VPU IN+1 PP1200_A_R
4 11 4 11
VS IN-1 PP3300_EDP_DX VS IN-1 PP1200_A
GND
DEBUG_I2C_SCL 6 DEBUG_I2C_SCL 6
21,22,36 DEBUG_I2C_SCL DEBUG_I2C_SDA SCL 21,22,36 DEBUG_I2C_SCL DEBUG_I2C_SDA SCL
7 7
21,22,36 DEBUG_I2C_SDA SDA 21,22,36 DEBUG_I2C_SDA SDA
15 15
IN+2 PP5000_A_R IN+2 PP1100_VDDQ_S_R
5 14 PP5000_A C675 5 14 PP1100_VDDQ_S
AO IN-2 0.1uF/10V/X5R AO IN-2
C0201
D D
10 ns 10
GND 8 PV 8 PV
9 WARNING 2 9 WARNING 2
CRITICAL IN+3 PP1800_A_R CRITICAL IN+3 PP1050_S_R

TPAD

TPAD
13 1 GND 13 1

GND

GND
TC IN-3 PP1800_A TC IN-3 PP1050_S

ROUTE TO SENSE RESISTOR DIFFERENTIALLY ns

17

17
3

3
ns

GND GND

I2C ADDR: 0X40 I2C ADDR: 0X41

U78 U80
INA3221AIRGVT INA_CUSTOM IS FOR JUMPER WIRE INA3221AIRGVT
QFN16-4X4-65-17P-MAX4063 QFN16-4X4-65-17P-MAX4063

16 12 INA_CUSTOM_P 16 12
PP3300_INA VPU IN+1 TP38 PP3300_INA VPU IN+1 PP3300_WLAN_DX_R
4 11 INA_CUSTOM_N 4 11
VS IN-1 TP39 VS IN-1 PP3300_WLAN_DX

DEBUG_I2C_SCL 6 DEBUG_I2C_SCL 6
21,22,36 DEBUG_I2C_SCL DEBUG_I2C_SDA SCL 21,22,36 DEBUG_I2C_SCL DEBUG_I2C_SDA SCL
7 7
21,22,36 DEBUG_I2C_SDA SDA 21,22,36 DEBUG_I2C_SDA SDA
15 PP3300_EC_WAKE 15 PP3300_A_R
C674 5 IN+2 14 C676 5 IN+2 14
AO IN-2 PP3300_EC AO IN-2 PP3300_A
0.1uF/10V/X5R 0.1uF/10V/X5R
C0201 C0201
ns 10 ns 10
8 PV 8 PV
C C
9 WARNING 2 9 WARNING 2
CRITICAL IN+3 PP3300_SOC_A_R CRITICAL IN+3 PP3300_PD_SW_A
TPAD

TPAD
13 GND 1 13 1

GND
TC IN-3 PP3300_SOC_A TC IN-3 PP3300_PD_A
GND GND

ns ns
17

17
3

3
GND GND

I2C ADDR: 0X42

I2C ADDR: 0X43

H2 H3 H4 H5 H6 H7
HOLE HOLE HOLE HOLE HOLE HOLE
hole2d5_t7d0x4d2_b7d0 hole2d5_7d0 hole2d5_7d0 HOLE2D5_7D0 hole2d5_7D0 hole2d5_7d0

B B
1

1
ns ns ns ns ns ns
Q17
WPM2301-3/TR
sot23-3 GND GND GND GND GND GND
2 3 PP3300_INA H8 H11 H10 H9 H12
S

PP3300_RTC PP3300_INA
HOLE HOLE HOLE HOLE HOLE
HOLE2D5_7D0 HOLE2D5_7D0 hole3d0_t7d0_b9d0 hole3d0_t7d0_b9d0 HOLE3D0_T8D0X5D0_B12D0X3D0
G

C280 ns
1

4.7uF/6.3V/X5R R159 C281

C0402 100K_J 0.22uF/10V,X5R
ns R0201 C0201
ns ns
1

1
GND
ns ns ns ns ns

EN_PP3300_INA_H1_ODL R161 200_F R0201 GND GND GND GND

21 EN_PP3300_INA_H1_ODL
ns GND
H16 H19
CPU_boss CPU_boss
boss2d5_7d0 boss2d5_7d0
1

MK1 MK2 MK3 MK4 MK5 MK6 MK7 MK8

ns ns 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
A GND GND FMARKS FMARKS FMARKS FMARKS FMARKS FMARKS FMARKS FMARKS A
fmarks ns fmarks ns fmarks ns fmarks ns fmarks ns fmarks ns fmarks ns fmarks ns

Bitland Information Technology Co.,Ltd.

Page Name
INAs
Size Project Name Rev
C
Phaser 1.3
Date: Thursday, November 22, 2018 Sheet 36 of 43
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

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 RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
5 4 3 2 1

RECOMMENDED VALUE
INCREASE OR ADD POSCAPS IF AUDIBLE NOISE IS HEARD
PPVAR_VBUS_IN FROME DATASHEET PPVAR_PWR_IN_BB
PPVAR_SYS Q6 PPVAR_BAT
QM3003M3
PPVAR_VBUS_IN R522 0.02_F R1206 dfn8_0d65_3x3
1 PPVAR_BAT
PPVAR_SYS R542 R1206 PPVAR_BAT_G 2
RC SNUBBER C538 C539 C542 C543 C545 0.01_F 3
10uF/50V/X5R 10uF/50V/X5R 10uF/50V/X5R 10uF/50V/X5R 0.1uF/50V/X5R C550 C552 C554 C555 C3563 C560 5
REQUIRED? S
C0603 C0603 C0603 C0603 C0402 0.1uF/50V/X5R 22uF/25V/X5R 22uF/25V/X5R 22uF/25V/X5R 22uF/25V/X5R 22uF/25V/X5R D
ns C0402 C0805 C0805 C0805 C0805 C0805 G

5
10% 10% 10% 10% 10%

4
D D R541 R543
R505 R526 dfn8_0d65_3x3 1_J 1_J
1_J 1_J Q23H R0402 R0402
D HDRIVE_1 4 G SM3326NHQAC-TRG SM3326NHQAC-TRG 4 HDRIVE_2 D
R0402 R0402 G
S Q12H dfn8_0d65_3x3 S
L16

1
2
3

3
2
1
C536 BB_SWITCH_1 1 2 BB_SWITCH_2
2 1 MHCC10028-2R2M-R7

5
l_2p_10d1x11 C557
4.7uF/10V/X5R D D
C0402 1UF/35V,X5R

BATTERY_GATE_L
C0402
LDRIVE_1 4 G G 4 LDRIVE_2 10%
S C548 C549 S C141
C534 C537 Q12L 0.22uF/25V/X5R 0.22uF/25V/X5R Q23L ns 4700pF/25V/X5R

1
2
3

3
2
1
1UF/35V,X5R 1UF/35V,X5R SM3326NHQAC-TRG C0402 C0402 SM3326NHQAC-TRG C0402
C0402 C0402 dfn8_0d65_3x3 dfn8_0d65_3x3 C556 C558 ns

BB_BOOT1_R

BB_BOOT2_R
10% 10% 1UF/35V,X5R 1UF/35V,X5R
C0402 C0402
R479 R475 R480 R481 10% 10%
0_J 0_J BUCK LEG BOOST LEG 0_J 0_J ns
PPVAR_VBUS_IN PPVAR_SYS
R0402 R0402 R0402 R0402
R533 R534
0_J 0_J
R0402 R0402
2

D11
0.35V_0.2A_LBAT54CLT1G BB_LDRIVE_1 BB_LDRIVE_2

BB_BOOT1

BB_BOOT2
sot23-3 BB_HDRIVE_1 BB_HDRIVE_2
3

C535 1UF/35V,X5RC0402 10%

11

10

12
U6

5
R506 1_F R0805 PPVAR_BB_IN

UGATE1

PHASE1

LAGTE1

LGATE2

PHASE2

UGATE2
BOOT1

BOOT2
C C
C540 2 1 4.7uF/10V/X5R 17
C0402 DCIN
VDD_BB_GATE_DRIVE 8
PPVAR_VBUS_IN VDDP
3 BB_PPVAR_SYS R539 0_J
PP5000_BB_LDO_OUT VSYS PPVAR_SYS
R528 4.7_F R0402 18 R0201
VDD C551
C544 2 1 4.7uF/10V/X5R 1UF/35V,X5R
C0402 C0402
R503 BB_CSN 14 10%
392K_F CSIN
ns
R0402 BB_CSP 15
ADAPTER VOLTAGE CSIP
VALID IF > 3.4V
BB_ACIN 19 2 BATTERY_SRP_BB
ACIN CSOP
PULL-UP FROM EC OR H1? BB_ASGATE 13
R504 TP109 ASGATE BATTERY_SRN_BB
C533 1
120K_F 0.1uF/50V/X5R PPVAR_VBUS_IN 16 CSON
R0201 PPVAR_VBUS_IN ADP
C0402 ISL9238
EC_I2C_CHARGER_3V3_SDA 21 31 BB_PPVAR_BAT R540 100_F
18 EC_I2C_CHARGER_3V3_SDA SDA VBAT PPVAR_BAT
R0201
EC_I2C_CHARGER_3V3_SCL 22 C553
18 EC_I2C_CHARGER_3V3_SCL SCL 1UF/35V,X5R
C0402
ACOK_OD 24 10%
18,21 ACOK_OD ACOK
ns
PCH_PROCHOT_ODL R527 100_F R0201 BB_CHARGER_PROCHOT_ODL 23
11,18 PCH_PROCHOT_ODL PROCHOT#
CHARGER_PMON 30 32 BATTERY_GATE_L
PSYS BGATE

CHARGER_IADP R530 0_J R0201 29

18 CHARGER_IADP AMON/BMON

R521 0_J R0201 BB_CMIN 20 25 R538 0_J R0201 CHARGER_BAT_PRES_L

B PP3300_EC OTGEN/CMIN BATGONE B
ns ns
BB_CMOUT 26
TP110 OTGPG/CMOUT
1

R525 C541 BB_COMP 28 R537

0.01UF/16V/X7R COMP
100K_F 100K_J
R0201 C0402 R0201 CV: 12.6V
2

PROG
GND

R532 PP3300_VDDIOM 3S1P Battery

698_F
2

C546 R0402 ISL9238HRTZ-T

33

27

470pF/25V,X5R QFN32_0D4_4X4 J10

R544 PPVAR_BAT
C541 GND PIN SHOULD GOES TO PIN E1 AVSS OF U45 C0402 BATGONE LOW
1

499K_F
INDICATES
2

ns C547 R0201 R436 100K_J 9

0.022uF/25V/X5R R405 BATTERY PRESENT R0201 1 GND1 10
ns 1 GND2
C0402 105K_F 2
EC_I2C_BATTERY_3V3_SCL 3 2
I2C ADDR: 0X09 R0201 H1_BATT_PRES_L 18 EC_I2C_BATTERY_3V3_SCL EC_I2C_BATTERY_3V3_SDA 3
0_J R424 18 EC_I2C_BATTERY_3V3_SDA 4
21 H1_BATT_PRES_L R0201 BATT_TEMP 5 4
1

BATT_DISABLE_OD 6 5
PP3300_A 7 6
EC_BATT_PRES_L 100K_J R426 8 7 11
18 EC_BATT_PRES_L R0201 8 GND3 12
GND4
PP3300_RTC
FOR 0.476A ADAPTER CURRENT LIMIT
R702 GND
13.7K_F
AND 733KHZ SWITCHING FREQUENCY:
R0402 18 CHARGER_PMON
CHARGER_PMON 2 CELL: 93.1K WWAA1208-0A00

3
3 CELL: 105K D D
GND cns8_1d25_r_ws33081-s0201-hf
Q10
3 CELL: 162K (AUTONOMOUS CHARGING) LSI1012N3T5G
TEMP_SENSOR_CHARGER 1 sot883 1 BAT_DISABLE_ODL
TEMP_SENSOR_CHARGER 18
1

C594 R174 G S ns S G Q87

0.01UF/25V/X7R 6.04K_F 2N7002K

2
1

C0402 SETS GAIN R420 SOT23-3

R0201
2

2
R703 100K_F ns

3
NTC_47K R0201
A R0402 D Q55 A
LSI1012N3T5G
2

BAT_DISABLE_ODL 1 sot883
21 BAT_DISABLE_ODL G S

2
C299
PLACE NEAR HOTSPOT
OF THE CHARGER 1UF/6.3V/X5R Bitland Information Technology Co.,Ltd.
C0201
10% Page Name
BATTERY CHARGER
BAT_DISABLE_OD C299 Q55 Q10 Size Project Name Rev
C
Phaser 1.3
FLOAT* STUFF STUFF DNS Date: Tuesday, November 27, 2018 Sheet 37 of 43
ACTIVE LOW DNS DNS STUFF PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
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 RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
5 4 3 2 1

GPIO for LTE

Coral sub board
-LTE_SAR_ODL has pullup to PP1800_DX_LTE
-LTE_OFF_OFL has pullup to PP1800_DX_LTE STEST
-LTE_WAKE_L has pullup to PP1800_SOC_A, R773 still needs
to be stuffed if sub board is not attached
D D

LTE has been removed-0426

LEVERAGING CORAL BOARD!

C C

STEST has been removed-0426

P-SENSOR

B B

P-SENSOR has been removed-0426

A A

Bitland Information Technology Co.,Ltd.

Page Name
LTE, STEST
Size Project Name Rev
C
Phaser 1.3
Date: Thursday, November 22, 2018 Sheet 38 of 43
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
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EC_GPIO_1, 2 CAN BE USED FOR CONNECTING THE GMR SENSOR ON THE SUB-BOARD
OR IT CAN BE USED TO CONNECT TO AN SPARE EC GPIO PINS FOR ADDITIONAL CONTROL FROM EC

LID_OPEN R132 0_J R0201

ns
LED_3_L R255 0_J R0201 EC_GPIO_1
18 LED_3_L

R197
100K_J
R0201
D D

GND
J17
1
DDI1_AUX_P 2 51
7 DDI1_AUX_P DDI1_AUX_N
7 DDI1_AUX_N 3 J18
4 AFC68-S30F1A-HF
EC_GPIO_1 5 cns30_0d5_r_51540
PP3300_RTC 6
PP3300_RTC PP3300_PD_A 7 1 32
PP3300_PD_A 8 USB3_P3_A1_RX_P
8 8 USB3_P3_A1_RX_N 2
USB_PD_C1_INT_ODL 9 3
PP3300_PD_A 10 8 USB3_P3_A1_TX_P 4
C424 C425 EC_I2C_USB_C1_MUX_SCL 11 5
EC_I2C_USB_C1_MUX_SDA 8 USB3_P3_A1_TX_N
0.1uF/16V/X5R 0.1uF/16V/X5R 12 6
C0201 C0201 13 7 DDI1_TX0_P 7
R48 R49 R259 USB_C1_HPD_3V3 14 8
USB_C1_PD_RST_ODL 7 DDI1_TX0_N
1.8K_J 1.8K_J 100K_J 15 9
R0402 R0402 16 10
R0201 18 EC_VOLUP_BTN_ODL 7 DDI1_TX1_P
GND GND 17 11
18 EC_VOLDN_BTN_ODL USB_A0_STATUS_L 7 DDI1_TX1_N
30 USB_A0_STATUS_L 18 12
19 13
USB_C1_CC1_MB 7 DDI1_TX2_P
20 7 DDI1_TX2_N 14
18 USB_PD_C1_INT_ODL TP79 USB_C1_CC2_MB 21 15
18 EC_I2C_USB_C1_MUX_SCL TP80 22 16
18 EC_I2C_USB_C1_MUX_SDA 7 DDI1_TX3_P
18 USB_C1_BC12_CHG_DET_L 23 7 DDI1_TX3_N 17
24 18
18 USB_C1_BC12_VBUS_ON
18 USB_C1_MUX_INT_ODL 25 8 USB2_P4_C1_N 19
26 20
18,29 USB_C1_PD_RST_ODL USB_A1_CHARGE_EN_L 8 USB2_P4_C1_P
27 21
18 USB_A1_CHARGE_EN_L EN_USB_A1_5V
18 EN_USB_A1_5V 28 8 USB3_P4_C1_RX_N 22
USB_A1_OC_ODL 29 23
8 USB_A1_OC_ODL USB_A1_STATUS_L 8 USB3_P4_C1_RX_P
C3562 30 USB_A1_STATUS_L 30 24
1uF/6.3V/X5R 31 25
21,22,25 MECH_PWR_BTN_IN_ODL 8 USB2_P3_A1_P
32 26
C0201 8 USB2_P3_A1_N
C ns 33 27 C
34 28
8 USB3_P4_C1_TX_N
35 8 USB3_P4_C1_TX_P 29
GND 36 30 31
PPVAR_VBUS_IN
37
38
C62 C68 39
PP3300_EC 10uF/50V/X5R 0.1uF/50V/X5R 40
C0603 C0402 41 GND GND
42
43
GND 44
PP5000_A
R229 R185 R693 45
100K_J 100K_J 100K_J C426 46
0.1uF/16V/X5R 47
R0201 R0201 R0201
C0201 48 52
49
50
GND
USB_C1_BC12_CHG_DET_L GND
51540-05041-002
EC_VOLDN_BTN_ODL cns50_0d5_r_51540 SELECT PER SEL SI TEAM
SUB_GPIO_ADC R135 0_J R0201
EC_VOLUP_BTN_ODL SUB_GPIO_ADC

SELECT PER SEL SI TEAM

GND CM TO ADJUST PINOUT/PIN COUNT
SUB_GPIO_ADC GOES TO AN ADC PIN OF EC
WITH STUFFING OPTIONS, THE PIN CAN BE USED FOR VBUS DETECT
OR FOR BOARD ID DETECT. OR USE AS A GENERAL GPIO FROM EC
U30
HGDEDM013A
sensor4_0d5_0d9x1d3 PP1800_SOC_A
3 4
VDD OUT1
B B
2 1
GND OUT2
R240
U19 100K_J
x2dfn4_0d5_1d4x1d0 R0201
AH1389-HK4-7
1 3 LID_OPEN_GMR R293 1K_J R0201 LID_OPEN
PP3300_RTC VDD OUTPUT2 LID_OPEN 18,22,26
PAD

2 4 TABLET_MODE_GMR R294 0_J R0201 USB_C1_HPD_1V8_ODL

GND OUTPUT1 TABLET_MODE_L 18 7,18 USB_C1_HPD_1V8_ODL
C70
0.1uF/10V/X5R
5

3
C0201 ns
10% Q19 D
LNTK3043NT5G
1 USB_C1_HPD_3V3
sot723
S G
GND GND

2
R1401
499K_F
R0201
GND

GND

A A

Bitland Information Technology Co.,Ltd.

MOTHER BOARD INTERFACE Page Name

Size
C
Project Name
CONNECTORS TO SUB BOARD
Rev
Phaser 1.3
Date: Thursday, November 22, 2018 Sheet 39 of 43
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

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was obtained with the expressed written consent of Bitland

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SUB_PP1800_SENSOR_U

D D

R261
100K_F
R0201
SUB_PP1800_SENSOR_U ns
LID ACCEL-CORAL SUB_LID_ACCEL_INT_L
(SUB BOARD) TP_KX022_1_INT2
TP21
U11
R121 R403 R122 LIS2DE12TR

12

11
4.7K_J 0_J 4.7K_J lga12_0d5_2x2
SUB_PP1800_SENSOR_U

INT1

INT2
R0201 R0201 R0201
ns ns
Phaser360/360s
EC_I2C_SENSOR_SCL 1 10
SCL/SPC VDD_IO
2 9 C108 C109
SUB_PP1800_SENSOR_U CS VDD 4.7uF/6.3V/X5R 0.1uF/10V/X5R
3 8 C0402 C0201
SDO/SA0 GND2 Phaser360/360s
EC_I2C_SENSOR_SDA Phaser360/360s
4 7
SDA/SDI/SDO GND1

GND
RES
GND_GDB

6
Phaser360/360s

GND_GDB

C C

I2C MODE: ( SET BY NCS TIE TO VDDIO )

I2C ADDRESS: 0X1E (SDO_ADDR = GND), 0X1F (SDO_ADDR = VDDIO)
I2C MAX SPEED = 3.4MHZ

CON73
50376-00601-001
cns6_0d6_r_50376
EC_I2C_SENSOR_SDA 1 7
EC_I2C_SENSOR_SCL 2
SUB_LID_ACCEL_INT_L 3
4
5
SUB_PP1800_SENSOR_U
6 8

Phaser360/360s

GND_GDB
GND_GDB

B B

A A

Bitland Information Technology Co.,Ltd.

Page Name
SUB:G sensor DB
Size Project Name Rev
C
Phaser 1.3
Date: Thursday, November 22, 2018 Sheet 40 of 43
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

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was obtained with the expressed written consent of Bitland

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1.8V for WoV option

Layout note:
Place the 10nF,0.1uF and 1uF capacitors close to the EC

VSPI EC AP
DMIC0 GPIO97
0ohm
CAP
1uF
10ohm
ns
D
0ohm ns D

DMIC_OUT GPIO97/DMIC_IN
0ohm VREF_PECI
VREF_PECI-VCAP_PLL 0.1uF for VREF_PECI
1uF-4.7uF,0402,for VCAP_PLL

0ohm ns
0ohm 0ohm PECI_DATA/GPIO81
GPIO94 PECI_DATA/GPIO81-VSS_PLL
0ohm ns
DMIC_CLK GPIO94/DMIC_CLK 10nF 1uF-4.7uF
0201 0402
ns ns
0ohm GPIOD7
GPIO72(NPCX796F)-
VCC_PLL
10ohm
ns

VCC1
0.1uF
C C

GPIOB0/I2S_SDAT GPIOA7/PS2_DAT3/ GPIOA5/A20M/I2S_SYNC

TB2/I2S_SCLK
0ohm ns
I2S_SYNC
0ohm

0ohm

0ohm
Place close to the EC

DMIC1 33ohm for WoV option

GPIOA5/A20M

0ohm ns
I2S_SCLK
DMIC_OUT

0ohm

0ohm
0ohm

0ohm

GPIOA7/PS2_DAT3/TB2

0ohm ns
DMIC1_EN I2S_SDAT
0ohm

0ohm
DMIC_CLK
B B
200k

GPIOB0

I2S_SYNC
DSP
I2S_SCLK

I2S_SDAT

DMIC_CLK

A A

DMIC_IN
Bitland Information Technology Co.,Ltd.
Page Name
WOV DIAGRAM
Size Project Name Rev
C
Phaser 1.3
Date: Thursday, November 22, 2018 Sheet 41 of 43
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

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D D

C C

B B

A A

Bitland Information Technology Co.,Ltd.

Page Name
POWER SEQUENCE
Size Project Name Rev
C
Phaser 1.3
Date: Thursday, November 22, 2018 Sheet 42 of 43
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

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Bootstrap Default Bootstrap Bootstrap

GPIO # Bump Name Voltage Termination Termination Purpose Usage Bootstrap Octopus Signal Name

GPIO 27 GPIO 27 1.8V 20K PU 1K PD Allow eMMC as a boot source 1=enable(default) eMMC Boot DBG_PTI_DATA_16
0=disable

GPIO 28 GPIO 28 1.8V 20K PU 20K PU Allow SPI as a boot source 1=enable(default) SPI Boot DBG_PTI_DATA_17
0=disable

GPIO 42 MDSI_A_TE 1.8V 20K PD 20K PD Flash Descriptor override 1=Override Flash Descriptor TP_WIFI_RST_N,TP135
0=No Override(default)
D D

GPIO 43 MDSI_C_TE 1.8V 20K PU 20K PU RSVD 1=Disable(default) RSVD GP_INTD_DSI_TE2

0=Do Not Use

GPIO 44 USB2_OC0_N 1.8V 20K PD 20K PD RSVD 1=Do Not Use RSVD USB_A_OC_ODL
0=Disable(default)

GPIO 45 USB2_OC1_N 1.8V 20K PD 20K PD Top swap override 1=enable Top Swap USB_C_OC_ODL
0=disable(default)

GPIO 61 SIO_UART0_TXD 1.8V 20K PD 20K PD Enable TXE ROM Bypass 1=enable bypass TXE ROM Bypass PCHTX_MIPI60RX_UART
0=disable bypass(default)

GPIO 62 1.8V 20K PD 20K PD RSVD 1=Do Not Use RSVD STEST_INT_L
SIO_UART0_RTS_N 0=Disable(default)

GPIO 65 1.8V 20K PD 20K PD Force DNX FW Load 1=Force DnX DnX FW Load PCHTX_UART2
SIO_UART2_TXD 0=Do not force(default)

GPIO 66 1.8V 20K PD 20K PD LPC boot BIOS strap 1=boot from LPC LPC Boot TP172
SIO_UART2_RTS_N 0=do not boot from LPC(default)
1=Do Not Use
GPIO 79 SIO_SPI_0_CLK 1.8V 20K PD 1M PD RSVD 0=Normal Operation RSVD H1_SLAVE_SPI_CLK_R
1=Do Not Use
GPIO 80 SIO_SPI_0_FS0 1.8V 20K PD 1M PD RSVD 0=No halt(default) RSVD H1_SLAVE_SPI_CS_L_R

SIO_SPI_0_FS1 1.8V 20K PU 20K PU RSVD 1=Disable(default)

C
GPIO 81 0=Do Not Use RSVD
GPIO_81_DEBUG
C

20K PU [Pre-ES and

GPIO 83 SIO_SPI_0_TXD 1.8V ES]
20K PD [ES21 and
4.7K PU LPC 1.8V/3.3V mode select 1=1.8V mode LPC Voltage select H1_SLAVE_SPI_MOSI_R
QS] 0=3.3V mode(default)

SIO_SPI_2_CLK 1.8V 20K PU 3.3K PD Allow SPI as a boot source 1=don't boot from SPI(default) SPI Boot Source
GPIO 84 0=boot from SPI(debug) STEST_SPI1_CLK_R

SIO_SPI_2_FS0 1.8V 20K PD 20K PD RSVD 1=Do Not Use

GPIO 85 0=Disable(default) RSVD STEST_SPI_CS_L_R

SIO_SPI_2_FS1 1.8V 20K PD 20K PD RSVD 1=Do Not Use

GPIO 86 0=enable(default)
RSVD STEST_CNTRL

SIO_SPI_2_FS2 1.8V 20K PD 20K PD RSVD 1=Do Not Use RSVD

GPIO 87 0=default TP_PCH_GPIO_87_PD DURING RSMRST
1=Do Not Use
GPIO 89 SIO_SPI_2_TXD 1.8V 20K PD 20K PD RSVD 0=default RSVD STEST_SPI1_MOSI_R

AVS_I2S0_SDI 1.8V 20K PD 20K PD RSVD 1=Do Not Use

GPIO 159 0=default
RSVD I2S0_PCH_RX
AVS_I2S1_WS 20K PU [Pre-ES and 20K PU [Pre-ES and
1.8V ES] ES] SMBus 1.8V/3.3V mode select 1=1.8V mode Buffers 1.8V/3.3V
GPIO 163 _SYNC 20K PD [ES21 and 20K PD [ES21 and 0=3.3V mode(default) I2S_SFRM_SPKR
QS] QS]

AVS_I2S1_SDI 1.8V 20K PD 20K PD RSVD 1=Do Not Use

GPIO 164 0=default RSVD WLAN_PE_RST
B B
20K PU [Pre-ES and 20K PU [Pre-ES and
AVS_HDA_SDI 1.8V ES] ES] PMU 1.8V/3.3V mode select 1=1.8V mode
GPIO 168 20K PD [ES21 and 20K PD [ES21 and 0=3.3V mode(default)
PMU 1.8V/3.3V I2S2_PCH_RX
QS] QS]

1=Enable
GPIO 172 AVS_M_CLK_B1 1.8V 20K PD 20K PD SMBus No Reboot 0=Disable (default) SMBus Reboot DMIC_CLK2_R

AVS_M_CLK_AB2 1.8V 20K PD 20K PD VDD2 1.24V vs 1.2V select 1=VDD2 is 1.24V VDD2 Voltage
GPIO 174 0=VDD2 is 1.20V(default) TP_GPIO_174

AVS_M_DATA_2 1.8V 20K PD 4.7K PU eSPI vs LPC 1=eSPI mode eSPI/LPC mode
GPIO 175 0=LPC mode(default) DMIC_CAM2_DATA
1=Do Not Use
GPIO 177 SMB_CLK 3.3V(Default) 20K PD 20K PD RSVD 0=default RSVD TP_PCH_SMB_CLK,TP160
/1.8V

CNV_BRI_DT 1.8V 20K PD 20K PD eSPI Flash Sharing Mode 1=slave attached
GPIO 191 0=master attached(default) Flash Sharing CNVI_BRI_DT_R

CNV_BRI_RSP 1.8V 20K PD 20K PD RSVD 1=Do Not Use

GPIO 192 0=Normal Operation RSVD CNVI_BRI_RSP

CNV_RGI_DT 1.8V 20K PU 20K PU RSVD 1=Do Not Use RSVD

GPIO 193 0=Normal Operation CNVI_RGI_DT_R

CNV_RGI_RSP 1.8V 20K PD 20K PD RSVD 1=Do Not Use RSVD

GPIO 194 0=Normal Operation CNVI_RGI_RSP
A A
CNV_RF_RESET_N 1.8V 20K PD 20K PD RSVD 1=Do Not Use RSVD
GPIO 195 0=Normal Operation CNVI_RF_RESET_L

GPIO 196 XTAL_CLKREQ 1.8V 20K PD 10K PD RSVD 1=Do Not Use RSVD WLAN_CLKREQ0
0=Normal Operation Bitland Information Technology Co.,Ltd.
Page Name
SOC STRAPPING
Size Project Name Rev
C
Phaser 1.3
Date: Thursday, November 22, 2018 Sheet 43 of 43
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

RELEASED BY WWW.LAPTOP-SCHEMATICS.COM
was obtained with the expressed written consent of Bitland

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