Digital Logic & Design
IT-622 (2+3)
B.S Information Technology
Class/Sec: IT2B
Lab Lecture 13
Mr. Amjad Ali Khawaja
(Course Supervisor)
Government College University Hyderabad BS - Information Technology
Student’s ID: Student’s Name:
Laboratory Exercise No: 13
Objective: To verify Karnaugh Map Validation Using SOP.
Goal: In this experiment students will reduce a logic expression using K-map and will verify
their simplification practically.
Required Tools/Equipment: -
1) Analog & Digital Training System (M21-7000).
2) Connecting Wires (Jumpers).
3) Basic Logic Gates ICs (NOT =74HC04, AND =74HC08, OR = 74HC32).
Theory: -
A Karnaugh map provides a systematic method for simplifying Boolean expressions, if
properly used, will produce the simplest SOP or POS expression possible, known as the
minimum expression. [1]
A Karnaugh map is similar to a truth table because it represents all of the possible
values of input variables and the resulting output of each value. Instead of being organized into
columns and rows like a truth table, the Karnaugh map is an array of cells, in which each cell
represents a binary value of the input variables. [2]
Procedure:
Consider a SOP expression:
𝐴𝐵𝐶 + 𝐴𝐵𝐶 + 𝐴𝐵𝐶 +
𝐴𝐵𝐶 = X This expression yield following truth table:
This Truth Table will produce K map as shown:
Government College University Hyderabad Information Technology
Carefully following K-Map rules, expression will be reduced as shown:
Reduced equation will be: X = 𝐶
1. Construct digital circuit of above mentioned SOP expression as:
2. Apply input to this circuit according to table below and completely fill it.
C 𝐴 𝐵 𝐶 𝐴𝐵 𝐴𝐵 𝐴𝐵 𝐴𝐵 𝐴𝐵𝐶 + 𝐴𝐵𝐶 + 𝐵𝐶
𝐶 𝐶 𝐶 + = 𝑋
A B �
�
0 0 0 1 1 1
0 0 1 1 1 0
0 1 0 1 0 1
0 1 1 1 0 0
1 0 0 0 1 1
1 0 1 0 1 0
1 1 0 0 0 1
1 1 1 0 0 0
3. If X = 𝐶, for same set of inputs then it is proved that K-Map simplification is done
successfully.
