R-19 Syllabus for ECE - JNTUK w. e. f.

2019 – 20

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY: KAKINADA

KAKINADA – 533 003, Andhra Pradesh, India
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

III Year - II Semester L T P C

3 0 0 3

INTERNET OF THINGS

Course Objectives:
x To learn and understand elements of IoTsystem.
x Acquire knowledge about various protocols ofIoT.
x To learn and understand design principles and capabilities ofIoT.

UNIT I: Introduction to IoT

Introduction to IoT, Architectural Overview, Design principles and needed capabilities, Basics of
Networking, M2M and IoT Technology Fundamentals- Devices andgateways, Data
management, Business processes in IoT, Everything as a Service (XaaS), Role ofCloud in IoT,
Security aspects inIoT.

UNIT II: Elements of IoT

Hardware Components- Computing- Arduino, Raspberry Pi, ARM Cortex-A class processor,
Embedded Devices – ARM Cortex-M class processor, Arm Cortex-M0 Processor Architecture,
Block Diagram, Cortex-M0 Processor Instruction Set, ARM and Thumb Instruction Set.

UNIT III: IoT Application Development

Communication, IoT Applications, Sensing, Actuation, I/O interfaces.
Software Components- Programming API’s (using Python/Node.js/Arduino) for
CommunicationProtocols-MQTT, ZigBee, CoAP, UDP, TCP, Bluetooth.
Bluetooth Smart Connectivity
Bluetooth overview, Bluetooth Key Versions, Bluetooth Low Energy (BLE) Protocol, Bluetooth,
Low Energy Architecture, PSoC4 BLE architecture and Component Overview.

UNIT IV: Solution framework for IoT applications

Implementation of Device integration, Data acquisitionand integration, Device data storage-
Unstructured data storage on cloud/local server,Authentication, authorization of devices.

UNIT V: IoT Case Studies

IoT case studies and mini projects based on Industrial automation, Transportation,
Agriculture,Healthcare, HomeAutomation.

Text Books:
1. Raj Kamal, “Internet of Things: Architecture and Design Principles”, 1 st Edition,
McGraw Hill Education,2017.
2. The Definitive Guide to the ARM Cortex-M0 by JosephYiu,2011
3. Vijay Madisetti, ArshdeepBahga, Internet of Things, “A Hands on Approach”,
UniversityPress,2015.
 R-19 Syllabus for ECE - JNTUK w. e. f. 2019 – 20

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY: KAKINADA

KAKINADA – 533 003, Andhra Pradesh, India
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

References:
1. Cypress Semiconductor/PSoC4 BLE (Bluetooth Low Energy) Product TrainingModules.
2. Pethuru Raj and Anupama C. Raman, “The Internet of Things: EnablingTechnologies,
Platforms, and Use Cases”, CRC Press,2017.

Course Outcomes:
The student will be able to:
x Understand internet of Things and its hardware and softwarecomponents.
x Interface I/O devices, sensors &communicationmodules.
x Remotely monitor data and controldevices.
x Design real time IoT basedapplications
 IOT

UNIT-1

INTERNET OF THINGS: Internet of Things (IoT) is a concept which enables communication

between internetworking devices and applications, whereby physical objects or ‘things’ communicate
through the Internet.

The concept of IoT beganwith things classified as identity communication devices. Radio Frequency
Identification Device (RFID) is an example of an identity communication device. Things are tagged to
these devices for their identification in future and can be tracked, controlled and monitored using
remote computers connected through the Internet.

The concept of IoT enables, for example, GPS-based tracking, controlling and monitoring of devices;
machine-to-machine (M2M) communication; connected cars; communication between wearable and
personal devices and Industry 4.0.

1 IoT Definition The Internet is a vast global network of connected servers, computers, tablets and
mobiles that is governed by standard protocols for connected systems. It enables sending, receiving, or
communication of information, connectivity with remote servers, cloud and analytics platforms.

Thing in English has number of uses and meanings. In a dictionary, thing is a word used to refer to a
physical object, an action or idea, a situation or activity, in case when one does not wish to be precise.
Example of reference to an object is—an umbrella is a useful thing in rainy days. Streetlight is also
referred to as a thing. Example of reference to an action is— such a thing was not expected from him.
Example of reference to a situation is—such things were in plenty in that regime. Thus, combining both
the terms, the definition of IoT can be explained as follows:

Internet of Things means a network of physical things (objects) sending, receiving, or

communicating information using the Internet or other communication technologies and network just
as the computers, tablets and mobiles do, and thus enabling the monitoring, coordinating or controlling
process across the Internet or another data network.

Another source, defines the term IoT as follows:

Internet of Things is the network of physical objects or ‘things’ embedded with electronics, software,
sensors and connectivity to enable it to achieve greater value and service by exchanging data with the
manufacturer, operator and/or other connected devices. Each thing is uniquely identifiable through its
embedded computing system but is able to interoperate within the existing Internet infrastructure.

IoT Vision Internet of Things is a vision where things (wearable watches, alarm clocks, home devices,
surrounding objects) become ‘smart’ and function like living entities by sensing, computing and
communicating through embedded devices which interact with remote objects (servers, clouds,
applications, services and processes) or persons through the Internet or Near-Field Communication
(NFC) etc. The vision of IoT can be understood through Examples 1.1 and 1.2.

Example 1.1:

Through computing, an umbrella can be made to function like a living entity. By installing a tiny
embedded device, which interacts with a web based weather service and the devices owner through the
Internet the following communication can take place. The umbrella, embedded with a circuit for the
purpose of computing and communication connects to the Internet. A website regularly publishes the
weather report. The umbrella receives these reports each morning, analyses the data and issues
reminders to the owner at intermittent intervals around his/her office-going time. The reminders can be
distinguished using differently coloured LED flashes such as red LED flashes for hot and sunny days,
yellow flashes for rainy days.

A reminder can be sent to the owner’s mobile at a pre-set time before leaving for office using NFC,
Bluetooth or SMS technologies. The message can be—(i) Protect yourself from rain. It is going to rain.
Don’t forget to carry the umbrella; (ii) Protect yourself from the sun. It is going to be hot and sunny.
Don’t forget to carry the umbrella. The owner can decide to carry or not to carry the umbrella using the
Internet connected umbrella.

Example 1.2:

Streetlights in a city can be made to function like living entities through sensing and computing
using tiny embedded devices that communicate and interact with a central control-and-command
station through the Internet. Assume that each light in a group of 32 streetlights comprises a sensing,
computing and communication circuit. Each group connects to a group-controller (or coordinator)
through Bluetooth or ZigBee. Each controller further connects to the central command-and-control
station through the Internet.

The station receives information about each streetlight in each group in the city at periodic
intervals. The information received is related to the functioning of the 32 lights, the faulty lights, about
the presence or absence of traffic in group vicinity, and about the ambient conditions, whether cloudy,
dark or normal daylight.

The station remotely programs the group controllers, which automatically take an appropriate
action as per the conditions of traffic and light levels. It also directs remedial actions in case a fault
develops in a light at a specific location. Thus, each group in the city is controlled by the ‘Internet of
streetlights’. Figure 1.1 shows the use of the IoT concept for streetlights in a city

IoT CONCEPTUAL FRAMEWORK Example 1.1 showed a single object (umbrella) communicating with a
central server for acquiring data. The following equation describes a simple conceptual framework of
IoT2 :
Physical Object + Controller, Sensor and Actuators + Internet = Internet of Things … 1.1

Equation 1.1 conceptually describes the Internet of umbrellas as consisting of an umbrella, a controller,
sensor and actuators, and the Internet for connectivity to a web service and a mobile service provider.

Generally, IoT consists of an internetwork of devices and physical objects wherein a number of
objects can gather the data at remote locations and communicate to units managing, acquiring,
organising and analysing the data in the processes and services. Example 1.2 showed the number of
streetlights communicating data to the group controller which connects to the central server using the
Internet. A general framework consists of the number of devices communicating data to a data centre or
an enterprise or a cloud server. The IoT framework of IoT used in number of applications as well as in
enterprise and business processes is therefore, in general, more complex than the one represented by
Equation 1.1. The equation below conceptually represents the actions and communication of data at
successive levels in IoT consisting of internetworked devices and objects.

Gather + Enrich + Stream + Manage + Acquire + Organise and Analyse … 1.2

Equation 1.2 is an IoT conceptual framework for the enterprise processes and services, based on a
suggested IoT architecture given by Oracle (Figure 1.5 in Section 1.3). The steps are as as follows:

1. At level 1 data of the devices (things) using sensors or the things gather the pre data from the
internet.

2. A sensor connected to a gateway, functions as a smart sensor (smart sensor refers to a sensor with
computing and communication capacity). The data then enriches at level 2, for example, by transcoding
at the gateway. Transcoding means coding or decoding before data transfer between two entities.

3. A communication management subsystem sends or receives data streams at level 3.

4. Device management, identity management and access management subsystems receive the device’s
data at level 4.
5. A data store or database acquires the data at level 5.

6. Data routed from the devices and things organises and analyses at level 6. For example, data is
analysed for collecting business intelligence in business processes.

The equation below is an alternative conceptual representation for a complex system. It is based on IBM
IoT conceptual framework. The equation shows the actions and communication of data at successive
levels in IoT. The framework manages the IoT services using data from internetwork of the devices and
objects, internet and cloud services, and represents the flow of data from the IoT devices for managing
the IoT services using the cloud server. Gather + Consolidate + Connect + Collect + Assemble + Manage
and Analyse … 1.3 Equation 1.3 represents a complex conceptual framework for IoT using cloud-
platformbased processes and services.

The steps are as follows: 1. Levels 1 and 2 consist of a sensor network to gather and consolidate the
data. First level gathers the data of the things (devices) using sensors circuits. The sensor connects to a
gateway. Data then consolidates at the second level, for example, transformation at the gateway at level
2.

2. The gateway at level 2 communicates the data streams between levels 2 and 3. The system uses a
communication-management subsystem at level 3.

3. An information service consists of connect, collect, assemble and manage subsystems at levels 3 and
4. The services render from level 4.

4. Real time series analysis, data analytics and intelligence subsystems are also at levels 4 and 5. A cloud
infrastructure, a data store or database acquires the data at level 5. Figure 1.3 shows blocks and
subsystems for IoT in the IBM conceptual framework. New terms in the figure will be explained in the
subsequent chapters. Various conceptual frameworks of IoT find number of applications including the
ones in M2M communication networks, wearable devices, city lighting, security and surveillance and
home automation. Smart systems use the things (nodes) which consist of smart devices, smart objects
and smart services. Smart systems use the user interfaces (UIs), application programming interfaces
(APIs), identification data, sensor data and communication ports.
IoT ARCHITECTURAL VIEW:
An IoT system has multiple levels (Equations 1.1 to 1.3). These levels are also known as tiers. A model
enables conceptualisation of a framework. A reference model can be used to depict building blocks,
successive interactions and integration. An example is CISCO’s presentation of a reference model
comprising seven levels (Figure 1.4). New terms in the figure will be explained in the subsequent
chapters.
A reference model could be identified to specify reference architecture. Several reference architectures
are expected to co-exist in the IoT domain. Figure 1.5 shows an Oracle suggested IoT architecture. New
terms in the figure will be explained in the subsequent chapters.

An architecture has the following features:

● The architecture serves as a reference in applications of IoT in services and business processes.

● A set of sensors which are smart, capture the data, perform necessary data element analysis and
transformation as per device application framework and connect directly to a communication manager.

● A set of sensor circuits is connected to a gateway possessing separate data capturing, gathering,
computing and communication capabilities. The gateway receives the data in one form at one end and
sends it in another form to the other end.

● The communication-management subsystem consists of protocol handlers, message routers and

message cache.

● This management subsystem has functionalities for device identity database, device identity
management and access management.

● Data routes from the gateway through the Internet and data centre to the application server or
enterprise server which acquires that data.

● Organisation and analysis subsystems enable the services, business processes, enterprise integration
and complex processes (These terms are explained in Chapter 5).
 A number of models (CISCO, Purdue and other models) have been proposed at SWG (Sub
Working Group) Teleconference of December 2014. Standards for an architectural framework for the
IoT have been developed under IEEE project P2413. IEEE working group is working on a set of guidelines
for the standard IEEE suggested P24133 standard for architecture of IoT. It is a reference architecture
which builds upon the reference model(s). The reference architecture covers the definition of basic
architectural building blocks and their integration capability into multi-tiered systems

P2413 architectural framework4 is a reference model that defines relationships among various IoT
verticals, for example, transportation and healthcare. P2413 provides for the following:

Follows top-down approach (consider top layer design first and then move to the lowest)

● Does not define new architecture but reinvent existing architectures congruent with it

● Gives a blueprint for data abstraction

● Specifies abstract IoT domain for various IoT domains

● Recommends quality ‘quadruple’ trust that includes protection, security, privacy and safety

● Addresses how to document

● Strives for mitigating architecture divergence(s) Scope of IEEE P2413 standard defines an architectural
framework for the IoT. It includes descriptions of various IoT domains, definitions of IoT domain
abstractions and identification of commonalities between different IoT domains. Smart manufacturing,
smart grid, smart buildings, intelligent transport, smart cities and e-health are different IoT domains.
P2413 leverages existing applicable standards. It identifies planned or ongoing projects with a similar or
overlapping scope.5

TECHNOLOGY BEHIND IoT : The following entities provide a diverse technologyenvironment and
are examples of technologies, which are involved in IoT.

● Hardware (Arduino Raspberry Pi, Intel Galileo, Intel Edison, ARM mBed, Bosch XDK110, Beagle Bone
Black and Wireless SoC)

● Integrated Development Environment (IDE) for developing device software, firmware and APIs

● Protocols [RPL, CoAP, RESTful HTTP, MQTT, XMPP (Extensible Messaging and Presence Protocol)]

● Communication (Powerline Ethernet, RFID, NFC, 6LowPAN, UWB, ZigBee, Bluetooth, WiFi, WiMax,
2G/3G/4G)

● Network backbone (IPv4, IPv6, UDP and 6LowPAN) ● Software (RIOT OS, Contiki OS, Thingsquare Mist
firmware, Eclipse IoT)

● Internetwork Cloud Platforms/Data Centre (Sense, ThingWorx, Nimbits, Xively, openHAB, AWS IoT,
IBM BlueMix, CISCO IoT, IOx and Fog, EvryThng, Azure, TCS CUP)
● Machine learning algorithms and software. An example of machine-learning software is GROK from
Numenta Inc. that uses machine intelligence to analyse the streaming data from clouds and uncover
anomalies, has the ability to learn continuously from data and ability to drive action from the output of
GROK’s data models and perform high level of automation for analysing streaming data.

The following five entities can be considered for the five levels behind an IoT system (Figure 1.3): 1.
Device platform consisting of device hardware and software using a microcontroller (or SoC or custom
chip), and software for the device APIs and web applications 2. Connecting and networking (connectivity
protocols and circuits) enabling internetworking of devices and physical objects called things and
enabling the internet connectivity to remote servers 3. Server and web programming enabling web
applications and web services 4. Cloud platform enabling storage, computing prototype and product
development platforms 5. Online transactions processing, online analytics processing, data analytics,
predictive analytics and knowledge discovery enabling wider applications of an IoT system

Server-end Technology :IoT servers are application servers, enterprise servers, cloud servers,
data centres and databases. Servers offer the following software components: ● Online platforms ●
Devices identification, identity management and their access management ● Data accruing, aggregation,
integration, organising and analysing ● Use of web applications, services and business processes

Major Components of IoT System

Major components of IoT devices are:

1. Physical object with embedded software into a hardware.

2. consisting of a microcontroller, firmware, sensors, control unit, actuators and communication

module.

3. Communication module: Software consisting of device APIs and device interface for communication
over the network and communication circuit/port(s), and middleware for creating communication stacks
using 6LowPAN, CoAP, LWM2M, IPv4, IPv6 and other protocols.

4. for actions on messages, information and commands which the devices receive and then output to
the actuators, which enable actions such as glowing LEDs, robotic hand movement etc.

Sensors and Control Units Sensors Sensors are electronic devices that sense the physical environments.
An industrial automation system or robotic system has multiple smart sensors embedded in it. Sensor-
actuator pairs are used in control systems. A smart sensor includes computing and communication
circuits.

Recall Example 1.2 of Internet of streetlights. Each light has sensors for measuring surrounding light-
intensity and surrounding traffic-proximity for sensing and transmitting the data after aggregation over
a period. Sensors are used for measuring temperature, pressure, humidity, light intensity, traffic
proximity, acceleration in an accelerometer, signals in a GPS, proximity sensor, magnetic fields in a
compass, and magnetic intensity in a magnetometer.

Sensors are of two types. The first type gives analog inputs to the control unit. Examples are thermistor,
photoconductor, pressure gauge and Hall sensor. The second type gives digital inputs to the control unit.
Examples are touch sensor, proximity sensor, metal sensor, traffic presence sensor, rotator encoder for
measuring angles and linear encoders for measuring linear displacements. Sensors and circuits are
explained in detail in Chapter 7.

Control Units Most commonly used control unit in IoT consists of a Microcontroller Unit (MCU) or a
custom chip. A microcontroller is an integrated chip or core in a VLSI or SoC. Popular microcontrollers
are ATmega 328, ATMega 32u4, ARM Cortex and ARM LPC. An MCU comprises a processor, memory and
several other hardware units which are interfaced together. It also has firmware, timers, interrupt
controllers and functional IO units.

Additionally, an MCU has application-specific functional circuits designed as per the specific version of a
given microcontroller family. For example, it may possess Analog to Digital Converters (ADC) and Pulse
Width Modulators (PWM). Figure 1.6 shows various functional units in an MCU that are embedded in an
IoT device or a physical object. New terms in the figure will be discussed in detail in Chapter 8. Sensor
types—analog and digital output sensors Internet of Things: An Overview 15 Microcontroller

Communication Module

A communication module consists of protocol handlers, message queue and message cache. A device
message-queue inserts the messages in the queue and deletes the messages from the queue in a first-in
first-out manner. A device message-cache stores the received messages.

Representational State Transfer (REST) architectural style can be used for HTTP access by GET, POST,
PUT and DELETE methods for resources and building web services. Communication protocols and REST
style are explained in detail Chapter 3 and 4.

Software IoT software consists of two components—software at the IoT device and software at the
IoT server. Figure 1.7 shows the software components for the IoT device hardware and server.
Embedded software and the components are explained in Chapter 8. Software APIs, online component
APIs and web APIs are explained in Section 9.4.

Middleware OpenIoT is an open source middleware. It enables communication with sensor clouds
as well as cloud-based ‘sensing as a service’. IoTSyS is a middleware which enables provisioning of
communication stack for smart devices using IPv6, oBIX, 6LoWPAN, CoAP and multiple standards and
protocols. The oBIX is standard XML and web services protocol oBIX (Open Building Information
Xchange).

Operating Systems (OS) Examples of OSs are RIOT, Raspbian, AllJoyn, Spark and Contiki.
RIOT is an operating system for IoT devices. RIOT supports both developer and multiple architectures,
including ARM7, Cortex-M0, Cortex-M3, Cortex-M4, standard x86 PCs and TI MSP430.

Raspbian is a popular Raspberry Pi operating system that is based on the Debian distribution of Linux

AllJoyn is an open-source OS created by Qualcomm. It is a cross platform OS with APIs available for
Android, iOS, OS X, Linux and Windows OSs. It includes a framework and a set of services. It enables the
manufacturers to create compatible devices.

Spark is a distributed, cloud-based IoT operating system and web-based IDE. It includes a command-line
interface, support for multiple languages and libraries for working with several different IoT devices

Contiki OS7 is an open-source multitasking OS. It includes 6LowPAN, RPL, UDP, DTLS and TCP/IP
protocols which are required in low-power wireless IoT devices. Example of applications are street
lighting in smart cities, which requires just 30 kB ROM and 10 kB RAM.
 IV Unit – M2M and IoT Technology Fundamentals

UNIT IV: M2M and IoT Technology Fundamentals

Devices and gateways, Local and wide area networking, Data management, Business processes
in IoT, Everything as a Service(XaaS), M2M and IoT Analytics, Knowledge Management.
4.1 Devices and gateways

4.1.1 Introduction

 There is a growing market for small-scale embedded processing such as 8-, 16-, and 32-
bit microcontrollers with on-chip RAM and flash memory, I/O capabilities, and
networking interfaces such as IEEE 802.15.4 that are integrated on tiny System-on-a-
Chip (SoC) solutions.
 Such devices enable very constrained devices with a small footprint of a few mm2 and
with a very low power consumption in the milli- to micro-Watt range, but which are
capable of hosting an entire Transmission Control Protocol/Internet Protocol (TCP/IP)
stack, including a small web server.
 A device is a hardware unit that can sense aspects of it’s environment and/or actuate, i.e.
perform tasks in its environment.
 A device can be characterized as having several properties, including:

• Microcontroller: 8-, 16-, or 32-bit working memory and storage.

• Power Source: Fixed, battery, energy harvesting, or hybrid.

• Sensors and Actuators: Onboard sensors and actuators, or circuitry that allows them
to be connected, sampled, conditioned, and controlled.

• Communication: Cellular, wireless, or wired for LAN and WAN communication.

• Operating System (OS): Main-loop, event-based, real-time, or full featured OS.

• Applications: Simple sensor sampling or more advanced applications.

• User Interface: Display, buttons, or other functions for user interaction.

• Device Management (DM): Provisioning, firmware, bootstrapping, and monitoring.

• Execution Environment (EE): Application lifecycle management and Application

Programming Interface (API).

4.1.1.1 Device types

 Group devices into two categories

• Basic Devices: Devices that only provide the basic services of sensor readings and/or
actuation tasks, and in some cases limited support for user interaction. LAN

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 IV Unit – M2M and IoT Technology Fundamentals

communication is supported via wired or wireless technology, thus a gateway is

needed to provide the WAN connection.

• Advanced Devices: In this case the devices also host the application logic and a
WAN connection. They may also feature device management and an execution
environment for hosting multiple applications. Gateway devices are most likely to fall
into this category.

4.1.1.2 Deployment scenarios for devices

 Example deployment scenarios for basic devices include:

• Home Alarms: Such devices typically include motion detectors, magnetic

sensors, and smoke detectors. A central unit takes care of the application logic that
calls security and sounds an alarm if a sensor is activated when the alarm is armed.
The central unit also handles the WAN connection towards the alarm central. These
systems are currently often based on proprietary radio protocols.

• Smart Meters: The meters are installed in the households and measure
consumption of, for example, electricity and gas. A concentrator gateway collects data
from the meters, performs aggregation, and periodically transmits the aggregated data
to an application server over a cellular connection. By using a capillary network
technology it’s possible to extend the range of the concentrator gateway by allowing
meters in the periphery to use other meters as extenders, and interface with handheld
devices on the Home Area Network side.

• Building Automation Systems (BASs): Such devices include

thermostats, fans, motion detectors, and boilers, which are controlled by local
facilities, but can also be remotely operated.

• Standalone Smart Thermostats: These use Wi-Fi to communicate with web

services. Examples for advanced devices, meanwhile, include:

• Onboard units in cars that perform remote monitoring and configuration over a
cellular connection.

• Robots and autonomous vehicles such as unmanned aerial vehicles that can
work both autonomously or by remote control using a cellular connection.

• Video cameras for remote monitoring over 3G and LTE.

• Oil well monitoring and collection of data points from remote devices.

• Connected printers that can be upgraded and serviced remotely.

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 IV Unit – M2M and IoT Technology Fundamentals

4.1.2 Basic devices

 These devices are often intended for a single purpose, such as measuring air pressure or
closing a valve. I
 In some cases several functions are deployed on the same device, such as monitoring
humidity, temperature, and light level.
 The main focus is on keeping the bill of materials (BOM) as low as possible by using
inexpensive microcontrollers with built-in memory and storage, often on an SoC-
integrated circuit with all main components on one single chip (Figure 5.1).
 Another common goal is to enable battery as a power source, with a lifespan of a year
and upwards by using ultra-low energy microcontrollers.

 The microcontroller typically hosts a number of ports that allow integration with sensors
and actuators, such as General Purpose I/O (GPIO) and an analog-to-digital converter
(ADC) for supporting analog input.
 For certain actuators, such as motors, pulse-width modulation (PWM) can be used.
 As low-power operation is paramount to battery-powered devices, the microcontroller
hosts functions that facilitate sleeping, such as interrupts that can wake up the device on
external and internal events.

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 IV Unit – M2M and IoT Technology Fundamentals

 Some devices even go as far as harvesting energy from their environment, e.g. in the
form of solar, thermal, and physical energy.
 To interact with peripherals such as storage or display, it’s common to use a serial
interface such as SPI, I2C, or UART.
 These interfaces can also be used to communicate with another microcontroller on the
device.
 This is common when the there is a need for offloading certain tasks, or when in some
cases the entire application logic is put on a separate host processor.
 It’s not unusual for the micro controller to also contain a security processor,e.g. to
accelerate Advanced Encryption Standard (AES).
 This is necessary to allow encrypted communication over the radio link without the need
for a host processor.
 The gateway together with the connected devices form a capillary network.
 The microcontroller contains most of the radio functions needed for communicating with
the gateway and other devices in the same capillary network.
 An external antenna is, however, necessary, and preferably a filter that removes
unwanted frequencies, e.g. a surface acoustic wave (SAW) filter.
 Due to limited computational resources, these devices commonly do not use a typical OS.
 It may be something as simple as a single-threaded main-loop or a low-end OS such as
FreeRTOS, Atomthreads, AVIX-RT, ChibiOS/RT, ERIKA Enterprise, TinyOS, or
Thingsquare Mist/Contiki.
 These OSes offer basic functionality, e.g. memory and concurrency model management,
(sensor and radio) drivers, threading, TCP/IP, and higher level protocol stacks.
 The actual application logic is located on top of the OS or in the mainloop.
 A typical task for the application logic is to read values from the sensors and to provide
these over the LAN interface in a semantically correct manner with the correct units.

4.1.3 Gateways

 A gateway serves as a translator between different protocols, e.g. between IEEE 802.15.4
or IEEE 802.11, to Ethernet or cellular.
 There are many different types of gateways, which can work on different levels in the
protocol layers.
 A gateway refers to a device that performs translation of the physical and link layer, but
application layer gateways (ALGs) are also common.
 The latter is preferably avoided because it adds complexity and is a common source of
error in deployments.
 Some examples of ALGs include the ZigBee Gateway Device which translates from
ZigBee to SOAP and IP, or gateways that translate from Constrained Application
Protocol (CoAP) to HyperText Transfer Protocol/Representational State Transfer
(HTTP/REST).

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 IV Unit – M2M and IoT Technology Fundamentals

 Tthe gateway device is also used for many other tasks, such as data management, device
management, and local applications.

4.1.3.1 Data management

 Typical functions for data management include performing sensor readings and caching
this data, as well as filtering, concentrating, and aggregating the data before transmitting
it to back-end servers.

4.1.3.2 Local applications

 Examples of local applications that can be hosted on a gateway include closed loops,
home alarm logic, and ventilation control, or the data management function above
 The benefit of hosting this logic on the gateway instead of in the network is to avoid
downtime in case of WAN connection failure, minimize usage of costly cellular data,
and reduce latency.
 To facilitate efficient management of applications on the gateway, it’s necessary to
include an execution environment.
 The execution environment is responsible for the lifecycle management of the
applications, including installation, pausing, stopping, configuration, and uninstallation of
the applications.
 A common example of an execution environment for embedded environments is OSGi,
which is based on Java: applications are built as one or more Bundles, which are
packaged as Java JAR files and installed using a so-called Management Agent.
 The Management Agent can be controlled from, for example, a terminal shell or via a
protocol such as CPE WAN Management Protocol (CWMP).
 Bundle packages can be retrieved from the local file system or over HTTP, for example.
OSGi also provides security and versioning for Bundles, which means that
communication between Bundles is controlled, and several versions of them can exist.
 The benefit of versioning and the lifecycle management functions is that the OSGi
environment never needs to be shut down when upgrading, thus avoiding downtime in
the system.
 Also, Linux can be used as an execution environment.

4.1.3.3 Device management

 Device management (DM) is an essential part of the IoT and provides efficient means to
perform many of the management tasks for devices:
• Provisioning: Initialization (or activation) of devices in regards to configuration and
features to be enabled.
• Device Configuration: Management of device settings and parameters.
• Software Upgrades: Installation of firmware, system software, and applications on the
device.

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• Fault Management: Enables error reporting and access to device status.

 Examples of device management standards include TR-069 and OMA-DM.
 In the simplest deployment, the devices communicate directly with the DM server.
 This is, however, not always optimal or even possible due to network or protocol
constraints, e.g. due to a firewall or mismatching protocols.
 In these cases, the gateway functions as mediator between the server and the devices, and
can operate in three different ways:
• If the devices are visible to the DM server, the gateway can simply forward the
messages between the device and the server and is not a visible participant in the
session.
• In case the devices are not visible but understand the DM protocol in use, the
gateway can act as a proxy, essentially acting as a DM server towards the device
and a DM client towards the server.
• For deployments where the devices use a different DM protocol from the server,
the gateway can represent the devices and translate between the different
protocols (e.g. TR-069, OMA-DM, or CoAP).
 The devices can be represented either as virtual devices or as part of the gateway

4.1.4 Advanced devices

 An advanced device are the following:

• A powerful CPU or microcontroller with enough memory and storage to host
advanced applications, such as a printer offering functions for copying, faxing,
printing, and remote management.
• A more advanced user interface with, for example, display and advanced user
input in the form of a keypad or touch screen.
• Video or other high bandwidth functions.

4.1.5 Summary and vision

 The most important of these is security, both in terms of physical security as well as
software and network security.
 External factors that can affect the operation of the devices, such as rain, wind,
chemicals, and electromagnetic influences.
 One of the major effects that the IoT will have on devices is to disrupt the current value
chains, where one actor controls everything from device to service.
 This will happen due to standardization and consolidation of technologies, such as
protocols, OSes, software and programming languages (e.g. Java for embedded devices),
and the business
 New types of actors will be able to enter the market, e.g. specialized device vendors,
cloud solution providers, and service providers.

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 Standardization will improve interoperability between devices, as well as between

devices and services, resulting in commoditization of both.
 Another expected outcome of improved interoperability is the possibility to reuse the
same device for multiple services;
 for example, a motion detector can be used both for security purposes as well as for
reducing energy consumption by detecting when no one is in the room.
 Thanks to developments in hardware and network technologies, entirely new device
classes and features are expected, such as:
• Battery-powered devices with ultra-low power cellular connections.
• Devices that harvest energy from their environment.
• Smart bandwidth management and protocol switching, i.e. using adaptive RF
mechanisms to swap between, for example, Bluetooth LE and IEEE 802.15.4.

• Multi-radio/multi-rate to switch between bands or bit rates

• Microcontrollers with multicore processors.

• Novel software architectures for better handling of concurrency.

• The possibility to automate the design of integrated circuits based on
business-level logic and use case.

4.2 Local and wide area networking

4.2.1 The need for networking

 A network is created when two or more computing devices exchange data or information.
 The ability to exchange pieces of information using telecommunications technologies has
changed the world
 Devices are known as “nodes” of the network, and they communicate over “links.”
 In modern computing, nodes range from personal computers, servers, and dedicated
packet switching hardware, to smart phones, games consoles, television sets and,
increasingly, heterogeneous devices that are generally characterized by limited resources
and functionalities.
 Limitations typically include computation, energy, memory, communication (range,
bandwidth, reliability, etc.) and application specificity (e.g. specific sensors, actuators,
tasks), etc. Such devices are typically dedicated to specific tasks, such as sensing,
monitoring, and control.
 Network links rely upon a physical medium, such as electrical wires, air, and optical
fibers, over which data can be sent from one network node to the next.
 A selected physical medium determines a number of technical and economic
considerations.

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 Nodes of the network must have an awareness of all nodes in the network with which
they can indirectly communicate. This can be a direct connection over one link (edge, the
transition or communication between two nodes over a link), or knowledge of a route to
the desired (destination) node by communicating through cooperating nodes, over
multiple edges.

 In Figure 5.2 is the simplest form of network that requires knowledge of a route to
communicate between nodes that do not have direct physical links.
 if node A wishes to transfer data to node C, it must do so through node B.
 Thus, node B must be capable of the following:
 Communicating with both node A and node C,
 advertising to node A and node C that it can act as an intermediary.
 Basic networking requirements have become explicit.
 It is essential to uniquely identify each node in the network, and it is necessary to have
cooperating nodes capable of linking nodes between which physical links do not exist.
 In modern computing, this equates to IP addresses and routing tables.
 Consider the differences between streaming video from a surveillance camera, for
example, and an intrusion-detection system based on a passive sensor.
 Streaming video requires high bandwidth, whereas transmitting a small amount of
information about the detection of an intruder requires a tiny amount of bandwidth, but a
higher degree of reliability with respect to both the communications link and the accuracy
of the detection.
 Node A is a device that can only communicate over a particular wireless channel of
limited range
 Node B is cap able of communicating with node A, but also with an application server
with service capabilities (node C, with which it can connect using wired Ethernet, e.g.
over a complex link using a standardized protocol and/or web service such as REST at
the application layer) over the Internet.
 Node B may be connected to a sub-network (of child nodes, similar to node A) of up to
thousands of similarly constrained devices (A1. . .An).
 These thousands of devices may be equipped with sensors, deployed specifically to
monitor some physical phenomenon.
 They can only communicate with one another and node B, and may communicate with
each other over single or multiple hops.

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 Consider that the owner of the WSN wishes to obtain the data from each of the (A1. .
.An) devices in the WSN.
 However, the preferred way to read the data is through a web browser, or application on a
smartphone/tablet, via node C.
 Therefore, a networking solution is required to transfer all of the WSN data from nodes
A1. . .An to node C, through node B.
 This concept maps directly to the M2M Functional Architecture, where nodes A1. . .An
are an M2M Area Network, node B is an M2M Gateway, and node C is representative of
M2M Service Capabilities and Applications.
 A Local Area Network (LAN) was traditionally distinguishable from a Wide Area
Network (WAN) based on the geographic coverage requirements of the network, and the
need for third party, or leased, communication infrastructure.
 In the case of the LAN, a smaller geographic region is covered, such as a commercial
building, an office block, or a home, and does not require any leased communications
infrastructure.
 WANs provide communication links that cover longer distances, such as across
metropolitan, regional, or by textbook definition, global geographic areas.
 In practice, WANs are often used to link LANs and Metropolitan Area Networks (MAN)
 LANs tended to cover distances of tens to hundreds of meters, whereas WAN links
spanned tens to hundreds of kilometers.
 The most popular wired LAN technology is Ethernet. Wi-Fi is the most prevalent
wireless LAN (WLAN) technology.
 Wireless WAN (WWAN), as a descriptor, covers cellular mobile telecommunication
networks, a significant departure from WLAN in terms of technology, coverage, network
infrastructure, and architecture.
 Difference between LAN and WAN

S.NO LAN WAN

LAN stands for Local Area Whereas WAN stands for Wide Area

1. Network. Network.

LAN’s ownership is But WAN’s ownership can be private

2. private. or public.

3. The speed of LAN is While the speed of WAN is slower

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 IV Unit – M2M and IoT Technology Fundamentals

S.NO LAN WAN

high(more than WAN). than LAN.

The propagation delay is Whereas the propagation delay in

4. short in LAN. WAN is long(longer than LAN).

There is less congestion in While there is more congestion in

5. LAN(local area network). WAN(Wide Area Network).

There is more fault While there is less fault tolerance in

6. tolerance in LAN. WAN.

LAN’s design and While it’s design and maintenance is

7. maintenance is easy. difficult than LAN.

 The current generation of WWAN technology includes LTE (or 4G) and WiMAX.
 Acting as a link between LANs and Wireless Personal Area Networks (WPANs), M2M
Gateway Devices typically include cellular transceivers, and allow seamless IP-
connectivity over heterogeneous physical media.
 In the home, the “wireless router” typically behaves as a link between the Wi-Fi (WLAN,
and thus connected laptops, tablets, smartphones, etc. commonly found in the home) and
Digital Subscriber Line (DSL) broadband connectivity, traditionally arriving over
telephone lines. “DSL” refers to Internet access carried over legacy (wired) telephone
networks, and encompasses numerous standards and variants.
 “Broadband” indicates the ability to carry multiple signals over a number of frequencies,
with a typical minimum bandwidth of 256 kbps.
 In the office, the Wi-Fi wireless access points are typically connected to the wired
corporate (Ethernet) LAN, which is subsequently connected to a wider area network and
Internet backbone, typically provided by an Internet Service Provider (ISP).
 The need exists to interconnect devices (generally integrated microsystems) with central
data processing and decision support systems, in addition to one another.
 In WLAN technologies, a geographic region can be covered by a network of devices that
connect to the Internet via a gateway device, which may use a leased network connection.
 For example, a gateway device can access the IP backbone over a WWAN (e.g.
GPRS/UMTS/LTE/WiMAX) link, or over a WLAN link.
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 WPANs is the for newer standards that govern low-power, low-rate networks suitable for
M2M and IoT applications.
 “IEEE 802.15.4 _ Wireless Medium Access Control (MAC) and Physical Layer (PHY)
Specifications for Low-Rate Wireless Personal Area Networks (LR-WPANs).
 This is similar to the evolution of Wi-Fi WLAN technology (e.g. IEEE 802.11, a, b, g, n,
etc.).
 Communication ranges for IEEE 802.15.4 technology may range from tens of meters to
kilometers.
 Devices in an M2M Area Network connect to the IP backbone, or Network Domain, via
an M2M Gateway device.
 Gateway device is equipped with a cellular transceiver that is physically compatible with
UMTS or LTE-Advanced, for example, WWAN.
 The same device will also be equipped with the necessary transceiver to communicate on
the same physical medium as the M2M Area Network(s) in the M2M Device Domain.
 M2M Area Networks may include a plethora of wired or wireless technologies,
including: Bluetooth LE/Smart, IEEE 802.15.4 (LR-WPAN; e.g. ZigBee, IETF
6LoWPAN, RPL, CoAP, ISA100.11a, WirelessHART, etc.),
 The “Internet of Things,” as a term, originated from Radio Frequency Identification
(RFID) research, wherein the original IoT concept was that any RFID-tagged “thing”
could have a virtual presence on the “Internet.”
 RFID ,bar codes and QR codes use different technological means to achieve the same
result.
 M2M applications become more synonymous with IoT, it is necessary to understand the
technologies, limitations, and implications of the networking infrastructure.

4.2.2 Wide area networking

 WANs are typically required to bridge the M2M Device Domain to the backhaul
network, thus providing a proxy that allows information (data, commands etc) to traverse
heterogeneous networks.
 It is used to provide communications services between the M2M service enablement and
the physical deployments of devices in the field.
 WAN is capable of providing the bi-directional communications links between services
and devices which is achieved by means of physical and logical proxy.
 The proxy is achieved using an M2M Gateway Device.
 M2M Gateway Device is typically an integrated microsystem with multiple
communications interfaces and computational capabilities.
 It is a critical component in the functional architecture, as it must be capable of handling
all of the necessary interfacing to the M2M Service Capabilities and Management
Functions.

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 Example: consider a device that incorporates both an IEEE 802.15.4-compliant

transceiver, capable of communicating with a capillary network of similarly equipped
devices, and a cellular transceiver that connects to the Internet using the UMTS network.
 Transceivers (sometimes referred to as modems) are typically available as hardware
modules with which the central intelligence of the device (gateway or cell phone)
interacts by means of standardized AT Commands.
 This device is now capable of acting as a physical proxy between the LR-WPAN, or
M2M Device Domain, and the M2M Network Domain.
 The latest ETSI M2M Functional Architecture is illustrated in Figure 5.3.

 The Access and Core Network in the ETSI M2M Functional Architecture are foreseen to
be operated by a Mobile Network Operator (MNO), and can be thought of simply as the
“WAN” for the purposes of interconnecting devices and backhaul networks (Internet),
thus, M2M Applications, Service Capabilities, Management Functions, and Network
Management Functions.
 The WAN covers larger geographic regions using wireless as well as wire-based access.
 WAN technologies include cellular networks (using several generations of technologies),
DSL, WiMAX, Wi-Fi, Ethernet, Satellite, and so forth.
 The WAN delivers a packet-based service using IP as default. Circuit-based services can
also be used in certain situations.
 important functions of the WAN include:
• The main function of the WAN is to establish connectivity between capillary

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networks, hosting sensors, and actuators, and the M2M service enablement.
• The default connectivity mode is packet-based using the IP family of
technologies.
• Many different types of messages can be sent and received. for example, a
message sent from a sensor in an M2M Area Network and resulting in an SMS
received from the M2M Gateway or Application
• Use of identity management techniques (primarily of M2M devices) in cellular
and non-cellular domains to grant right-of-use of the WAN resource.
• The following techniques are used for these purposes:
 MCIM (Machine Communications Identity Module) for remote
provisioning of SIM targeting M2M devices.
 xSIM (x-Subscription Identity Module), like SIM, USIM, ISIM.
 Interface identifiers, an example of which is the MAC address of
the device, typically stored in hardware.
 Authentication/registration type of functions (device focused).
 Authentication, Authorization, and Accounting (AAA), such as
RADIUS services.
 Dynamic Host Configuration Protocol (DHCP), e.g. employing
deployment-specific configuration parameters specified by device,
user, or application-specific parameters residing in a directory.
 Subscription services (device-focused).
 Directory services, e.g. containing user profiles and various device
(s) parameter(s), setting(s), and combinations thereof.
• M2M-specific considerations include, in particular:
 MCIM (cf. 3GPP SA3 work).
 User Data Management (e.g. subscription management).
 Network optimizations (cf. 3GPP SA2 work).

4.2.2.1 3rd generation partnership project technologies and machine type communications

 Machine Type Communications (MTC) is heavily referred to in the ETSI documentation.

 MTC refers to small amounts of data that are communicated between machines (devices
to back-end services and vice versa) without the need for any human intervention. In the
3rd Generation Partnership Project (3GPP), MTC is used to refer to all M2M
communication.

4.2.3 Local area networking

 Capillary networks are typically autonomous, self-contained systems of M2M devices

that may be connected to the cloud via an appropriate Gateway.

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 They are often deployed in controlled environments such as vehicles, buildings,

apartments, factories, bodies, etc. (Figure 5.4) in order to collect sensor measurements,
generate events should sensing thresholds be breached, and sometimes control specific
features of interest (e.g. heart rate of a patient, environmental data on a factory floor, car
speed, air conditioning appliances, etc.).
 There will exist numerous capillary networks that will employ short-range wired and
wireless communication and networking technologies.
 For certain application areas, there is a need for autonomous local operation of the
capillary network.
 In the event that application-level logic is enforceable via the cloud, some will still need
to be managed locally.
 The complexity of the local application logic varies by application.
 For example, a building automation network may need local control loop functionality
for autonomous operation, but can rely on external communication for configuration of
control schemas and parameters.
 The M2M devices in a capillary network are typically thought to be low-capability nodes
(e.g. battery operated, with limited security capabilities) for cost reasons, and should
operate autonomously.
 For this reason, a GW/application server will naturally also be part of the architected
solution for capillary networks.
 More and more (currently closed) capillary networks will open up for integration with the
enterprise back end systems.
 For capillary networks that expose devices to the cloud/Internet, IP is envisioned to be
the common waist.

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 IPv6 will be the protocol of choice for M2M devices that operate a 6LoWPAN-based
stack.
 IPv4 will still be used for capillary networks operating in non-6LoWPAN IP stacks (e.g.
Wi-Fi capillary networks).
 In terms of short-range communication technology convergence, an IPv6 stack with
6LoWPAN running above the physical medium is expected.
 The development of the IEEE 802.15.4g standard, a physical layer amendment to support
Smart Utility Networks (SUN) _ smart grid in particular _ designed to operate over much
larger geographic distances (wireless links spanning tens of kilometers), and specifically
designed for minimal infrastructure, low power, many-device networks.

4.2.3.1 Deployment considerations

 There are increasing numbers of innovative IoT applications (hardware and software)
marketed as consumer products.
 These range from intelligent thermostats for effectively managing comfort and energy
use in the home, to precision gardening tools (sampling weather conditions, soil moisture,
etc.).
 Scaling up for industrial applications and moving from laboratories into the real world
creates significant challenges that are not yet fully understood.
 Low-rate, low-power communications technologies are known to be “lossy.” The reasons
can relate to environmental factors, which impact upon radio performance, technical
factors such as performance trade-offs based on the characteristics of medium access
control and routing protocols, and physical limitations of devices (including software
architectures, runtime and execution environments, computational capabilities, energy
availability, local storage, etc), and practical factors such as maintenance opportunities
(scheduled, remote, accessibility, etc.).
 Numerous deployment environments (factories, buildings, roads, vehicles) are expected
in addition to wildly varying application scenarios and operational and functional
requirements of the systems.
 ETSI describes a set of use cases, namely eHealth, Connected Consumer, Automotive,
Smart Grid, and Smart Meter, that only capture some of the breadth of potential
deployment scenarios and environments that are possible.
 Assuming that IP connectivity can be the fundamental mechanism to bridge
heterogeneous physical and link layer technologies, it stands to reason that fragmentation
can continue such that appropriate technologies are available for the breadth of potential
application scenarios.

4.2.3.2 Key technologies

 Power Line Communication (PLC) refers to communicating over power (or phone, coax,
etc.) lines.

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 IV Unit – M2M and IoT Technology Fundamentals

 This amounts to pulsing, with various degrees of power and frequency, the electrical lines
used for power distribution.
 PLC comes in numerous flavors. At low frequencies (tens to hundreds of Hertz) it is
possible to communicate over kilometers with low bit rates (hundreds of bits per second).
Typically, this type of communication was used for remote metering, and was seen as
potentially useful for the smart grid.
 Enhancements to allow higher bit rates have led to the possibility of delivering broadband
connectivity over power lines.
 There have been a number of attempts to standardize PLC in recent years. NIST recently
included IEEE 1901 and ITU-T G.hn as standards for further review for potential use in
the smart grid in the United States.
 LAN (and WLAN) continues to be important technology for M2M and IoT applications.
 This is due to the high bandwidth, reliability, and legacy of the technologies. Where
power is not a limiting factor, and high bandwidth is required, devices may connect
seamlessly to the Internet via Ethernet (IEEE 802.3) or Wi-Fi (IEEE 802.11).
 The IEEE 802.11 (Wi-Fi) standards continue to evolve in various directions to improve
certain operational characteristics depending on usage scenario.
 A widely adopted recent release was IEEE 802.11n, which was specifically designed to
enhance throughput (typically useful for streaming multimedia).
 Ongoing work such as IEEE 802.11ac is developing an even higher throughput version to
replace this, focusing efforts in the 5 GHz band.
 IEEE 802.11ah is allow a number of networked devices to cooperate in the ,1 GHz (ISM)
band.
 The idea is to exploit collaboration (relaying, or networking in other words) to extend
range, and improve energy efficiency (by cycling the active periods of the radio
transceiver).
 Bluetooth Low Energy (BLE; “Bluetooth Smart”) is designed for short-range (,50 m)
applications in healthcare, fitness, security, etc., where high data rates (millions of bits
per second) are required to enable application functionality.
 It is deliberately low cost and energy efficient by design, and has been integrated into the
majority of recent smart phones.
 Low-Rate, Low-Power Networks are another key technology that form the basis of the
IoT.
 For example, the IEEE 802.15.4 family of standards was one of the first used in practical
research and experimentation in the field of WSNs.
 Low-Rate Wireless Personal Area Networks (LR-WPAN)- It covered the Physical and
Medium Access Control layers, specifying use in the ISM bands at frequencies around
433 MHz, 868/915 MHz, and 2.4 GHz. This supported data rates of between 20 kbps up
to 256 kbps, depending on selected band, over distances ranging from tens of meters to
kilometers.

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 Radio duty cycling refers to managing the active periods of the Radio Frequency
Integrated Circuit (RFIC) during transmission, and listening to the medium.
 IEEE 802.15.4 defines the PHY layer, and in some instances the MAC layer, upon which
a number of low-energy communications specifications have been built. Namely, ZigBee.
 Recent developments, such as the PHY Amendment for Smart Utility Networks (SUN),
IEEE 802.15.4g, seek to extend the operational coverage of these networks up to tens of
kilometers in order to provide extremely wide geographic coverage with minimal
infrastructure.
 6LoWPAN (IPv6 Over Low Power Wireless Personal Area Networks) was developed
initially by the 6LoWPAN Working Group (WG) of the IETF as a mechanism to
transport IPv6 over IEEE 802.15.4-2003 networks.
 Specifically, methods to handle fragmentation, reassembly, and header compression were
the primary objectives.
 The WG also developed methods to handle address autoconfiguration, the hooks for
mesh networking, and network management.
 RPL (IPv6 Routing Protocol for Low Power and Lossy Networks) was developed by the
IETF Routing over Low Power and Lossy Networks (RoLL) WG.
 They defined Low Power Lossy Networks as those typically characterized by high data
loss rates, low data rates, and general instability.
 No specific physical or medium access control technologies were specified, but typical
links considered include PLC, IEEE 802.15.4, and low-power Wi-Fi.
 Typical use cases involve the collection of data from many (for example) sensing points,
nodes towards a sink, or alternatively, flooding information from a sink to many nodes in
the network.
 Thus, the well-known concept of a Directed Acyclic Graph (DAG) structure was
concentrated to a Destination Oriented DAG (DODAG) for the purposes of initial
development.
 The group defined a new ICMPv6 message, with three possible types, specific for RPL
networks.
 These include a DAG Information Object (DIO), that allows a node to discover an RPL
instance, configuration parameters and parents, a DAG Information Solicitation (DIS) to
allow requests for DIOs from RPL nodes, and Destination Advertisement Object (DAO),
used to propagate destination information upwards (i.e. towards the root) along the
DODAG (specific RPL details are available in RFC 6550 and related RFCs).
 The Trickle Algorithm is an important enabler of RPL message exchange.
 CoAP (Constrained Application Protocol) is being developed by the IETF Constrained
RESTful Environments (CoRE) WG as a specialized web transfer protocol for use with
severe computational and communication constraints typically characteristic of M2M and
IoT applications.

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4.3 Data management

4.3.1 Introduction

 In the era of M2M, where billions of devices interact and generate data at exponential
growth rates, data management is of critical importance as it sets the basis upon which
any other processes can rely and operate
 Some of the key characteristics of M2M data include:

• Big Data: Huge amounts of data are generated, capturing detailed aspects of the
processes where devices are involved.

• Heterogeneous Data: The data is produced by a huge variety of devices and is

itself highly heterogeneous, differing on sampling rate, quality of captured values,
etc.

• Real-World Data: The overwhelming majority of the M2M data relates to real-
world processes and is dependent on the environment they interact with.

• Real-Time Data: M2M data is generated in real-time and overwhelmingly can

be communicated also in a very timely manner.

• Temporal Data: The overwhelming majority of M2M data is of temporal

nature, measuring the environment over time.

• Spatial Data: Increasingly, the data generated by M2M interactions are not only
captured by mobile devices, but also coupled to interactions in specific locations,
and their assessment may dynamically vary depending on the location.

• Polymorphic Data: The data acquired and used by M2M processes may be
complex and involve various data, which can also obtain different meanings
depending on the semantics applied and the process they participate in.

• Proprietary Data: Up to now, due to monolithic application development, a

significant amount of M2M data is stored and captured in proprietary formats.
However, increasingly due to the interactions with heterogeneous devices and
stakeholders, open approaches for data storage and exchange are used.

• Security and Privacy Data Aspects: Due to the detailed capturing of

interactions by M2M, analysis of the obtained data has a high risk of leaking
private information and usage patterns, as well as compromising security.\

4.3.2 Managing M2M data

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 IV Unit – M2M and IoT Technology Fundamentals

 The data flow from the moment it is sensed (e.g. by a wireless sensor node) up to the
moment it reaches the backend system has been processed manifold (and often
redundantly), either to adjust its representation in order to be easily integrated by the
diverse applications, or to compute on it in order to extract and associate it with
respective business intelligence (e.g. business process affected, etc.).

 In Figure 5.5, we see a number of data processing network points between the machine
and the enterprise that act on the datastream (or simply forwarding it) based on their end-
application needs and existing context.
 Dealing with M2M data may be decomposed into several stages.
 Additionally, the degree of focus in each stage heavily depends on the actual usage
requirements put upon the data as well as the infrastructure.

4.3.2.1 Data generation

 Data generation is the first stage within which data is generated actively or passively
from the device, system, or as a result of its interactions.
 The sampling of data generation depends on the device and its capabilities as well as
potentially the application needs.
 Usually default behaviors for data generation exist, which are usually further
configurable to strike a good benefit between involved costs, e.g. frequency of data
collection vs. energy used in the case of WSNs, etc.

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4.3.2.2 Data acquisition

 Data acquisition deals with the collection of data (actively or passively) from the device,
system, or as a result of its interactions.
 The data acquisition systems usually communicate with distributed devices over wired or
wireless links to acquire the needed data, and need to respect security, protocol, and
application requirements.
 The nature of acquisition varies, e.g. it could be continuous monitoring, interval-poll,
event-based, etc.
 The frequency of data acquisition overwhelmingly depends on, or is customized by, the
application requirements (or their common denominator).
 The data acquired at this stage (for non-closed local control loops) may also differ from
the data actually generated.
 In simple scenarios, due to customized filters deployed at the device, a fraction of the
generated data may be communicated.
 Data aggregation and even on-device computation of the data may result in
communication of key performance indicators of interest to the application.

4.3.2.3 Data validation

 Data acquired must be checked for correctness and meaningfulness within the specific
operating context.
 This is usually done based on rules, semantic annotations, or other logic.
 The acquired data may not conform to expectations and data may be intentionally or
unintentionally corrupted during transmission, altered, or not make sense in the business
context.
 As real-world processes depend on valid data to draw business-relevant decisions
 Several known methods are deployed for consistency and data type checking;
 for example, imposed range limits on the values acquired, logic checks, uniqueness,
correct time-stamping, etc.
 In addition, semantics may play an increasing role here, as the same data may have
different meanings in various operating contexts, and via semantics one can benefit while
attempting to validate them.
 Another part of the validation may deal with fallback actions such as requesting the data
again if checks fail, or attempts to “repair” partially failed data.
 Failure to validate may result in security breaches.
 Tampered-with data fed to an application is a well known security risk as its effects may
lead to attacks on other services, privilege escalation, denial of service, database
corruption, etc.

20
 IV Unit – M2M and IoT Technology Fundamentals

4.3.2.4 Data storage

 The data generated by M2M interactions is what is commonly referred to as “Big Data.”
 Machines generate an incredible amount of information that is captured and needs to be
stored for further processing.
 As this is proving challenging due to the size of information, a balance between its
business usage vs. storage needs to be considered; that is, only the fraction of the data
relevant to a business need may be stored for future reference.
 However, one has to carefully consider what the value of such data is to business not only
in current processes, but also potentially other directions that may be followed in the
future by the company as different assessments of the same data may provide other,
hidden competitive advantages in the future.
 Due to the massive amounts of M2M data, as well as their envisioned processing (e.g.
searching), specialized technologies such as massively parallel processing DBs,
distributed file systems, cloud computing platforms, etc. are needed.

4.3.2.5 Data processing

 Data processing enables working with the data that is either at rest (already stored) or is
in-motion (e.g. stream data).
 The scope of this processing is to operate on the data at a low level and “enhance” them
for future needs.
 Typical examples include data adjustment during which it might be necessary to
normalize data, introduce an estimate for a value that is missing, re-order incoming data
by adjusting timestamps, etc.
 Similarly, aggregation of data or general calculation functions may be operated on two or
more data streams and mathematical functions applied on their composition.
 Another example is the transformation of incoming data; for example, a stream can be
converted on the fly (e.g. temperature values are converted from _F to _C), or repackaged
in another data model, etc. Missing or invalid data that is needed for the specific time-slot
may be forecasted and used until, in a future interaction, the actual data comes into the
system.

4.3.2.6 Data remanence

 Even if the data is erased or removed, residues may still remain in electronic media, and
may be easily recovered by third parties _ often referred to as data remanence.
 Several techniques have been developed to deal with this, such as overwriting,
degaussing, encryption, and physical destruction.
 For M2M, not only the DBs where the M2M data is collected, but also the points of
action, which generate the data, or the individual nodes in between, which may cache it.

21
 IV Unit – M2M and IoT Technology Fundamentals

 At the current technology pace, those buffers (e.g. on device) are expected to be less at
risk since their limited size means that after a specific time has elapsed, new data will
occupy that space; hence, the window of opportunity is rather small.
 In addition, for large-scale infrastructures the cost of potentially acquiring “deleted” data
may be large; hence, their hubs or collection end-points, such as the DBs who have such
low cost, may be more at risk.

4.3.2.7 Data analysis

 Data available in the repositories can be subjected to analysis with the aim to obtain the
information they encapsulate and use it for supporting decision-making processes.
 The analysis of data at this stage heavily depends on the domain and the context of the
data.
 For instance, business intelligence tools process the data with a focus on the aggregation
and key performance indicator assessment.
 Data mining focuses on discovering knowledge, usually in conjunction with predictive
goals.
 Statistics can also be used on the data to assess them quantitatively (descriptive statistics),
find their main characteristics (exploratory data analysis), confirm a specific hypothesis
(confirmatory data analysis), discover knowledge (data mining), and for machine
learning, etc.
 This stage is the basis for any sophisticated applications that take advantage of the
information hidden directly or indirectly on the data.

4.3.3 Considerations for M2M data

 The M2M infrastructure in place heavily depends on real-world processes, implying also
that a big percentage of data will be generated by machines that interact with the real-
world environment, while the rest will be purely virtual data.
 Many of the machines generating this data, which can then be communicated to others
(e.g. analytics specialists).
 The end-beneficiaries might acquire information, but do not necessarily need to have
access or to process the data by themselves.
 There is a rise of specialists in the various stages of M2M data management that will
cooperate with application providers, users, etc. for the common benefit.
 Sharing of data and usage in multiple applications, security and trust are of key
importance.
 Security is mandatory for enabling confidentiality, integrity, availability, authenticity,
and nonrepudiation of data from the moment of generation to consumption.
 Due to the large-scale IoT infrastructure, heterogeneous devices, and stakeholders
involved, this will be challenging.

22
 IV Unit – M2M and IoT Technology Fundamentals

 In addition, trust will be another major issue, as even if data is securely communicated or
verified, the level of trust based on them will impact the decision-making process and
risk analysis.
 Managing security and trust in the highly federated M2M-envisioned infrastructures
poses a significant challenge, especially for mission critical applications that also exercise
control.
 Privacy is also expected to be a significant issue in IoT infrastructures.
 Currently, a lot of emphasis is put on acquiring the data, and no real solutions exist for
large-scale systems to share data in a controlled way.
 Once data is shared, the originator has no more control over its lifetime.
 A typical example here constitutes the usage of private citizen data, which could be
controllably shared as wished; it should also be possible to (partially) revoke that right at
will.
 Data Science in the IoT era is a cross-discipline approach building on mathematics,
statistics, high-performance computing, modeling, machine learning, engineering, etc.
that will play a key role in understanding the data, assessing their information at large
scale, and hopefully enabling the better studying of complex systems of systems and their
emergent characteristics.

4.3.4 Conclusions

 Data and its management hold the key to unveiling the true power of M2M and IoT.
 To do so, however, we have to think and develop approaches that go beyond simple data
collection, and enable the management of their whole lifecycle at very large scale, while
in parallel considering the special needs and the usage requirements posed by specific
domains or applications.

4.4 Business processes in IoT

4.4.1 Introduction

 A business process refers to a series of activities, often a collection of interrelated processes

in a logical sequence, within an enterprise, leading to a specific result.
 There are several types of business processes such as management, operational, and
supporting, all of which aim at achieving a specific mission objective.
 As business processes usually span several systems and may get very complex, several
methods and techniques have been developed for their modeling, such as the Business
Process Model and Notation (BPMN), which graphically represents business processes in a
business process model.

23
 IV Unit – M2M and IoT Technology Fundamentals

 Several key business processes in modern enterprise systems heavily rely on interaction with
real-world processes, largely for monitoring, but also for some control (management), in
order to take business-critical decisions and optimize actions across the enterprise.

 In Figure 5.6, the dramatic reduction of the data acquisition from the real world
 Initially all these interactions were human-based (e.g. via a keyboard) or human-assisted
(e.g. via a barcode scanner); however, with the prevalence of RFID, WSNs, and advanced
networked embedded devices, all information exchange between the real-world and
enterprise systems can be done automatically without any human intervention and at
blazing speeds.
 In the M2M era, connected devices can be clearly identified, and with the help of
services, this integration leads to active participation of the devices to the business
processes.
 Existing modeling tools are hardly designed to specify aspects of the real world in
modeling environments and capture their full characteristics. To this direction, the
existence of SOA-ready devices

24
 IV Unit – M2M and IoT Technology Fundamentals

 (i.e. devices that offer their functionalities as a web service) simplifies the integration and
interaction as they can be considered as a traditional web service that runs on a specific
device.
 A layered approach for developing, deploying, and managing WSN applications that
natively interact with enterprise information systems such as a business process engine
and the processes running therein is proposed and assessed.
 M2M and IoT empower business processes to acquire very detailed data about the
operations, and be informed about the conditions in the real world in a very timely
manner.

4.4.2 IoT integration with enterprise systems

 M2M communication and the vision of the IoT pose a new era where billions of devices
will need to interact with each other and exchange information in order to fulfill their
purpose.

25
 IV Unit – M2M and IoT Technology Fundamentals

 In Figure 5.7, cross-layer interaction and cooperation can be pursued:

• at the M2M level, where the machines cooperate with each other
(machine-focused interactions)

• at the machine-to-business (M2B) layer, where machines cooperate also

with network-based services, business systems (business service focus),
and applications.

 Several devices in the lowest layer. These can communicate with each other over short-
range protocols (e.g. over ZigBee, Bluetooth), or even longer distances (e.g. over Wi-Fi,
etc.).
 Some of them may host services (e.g. REST services), and even have dynamic discovery
capabilities based on the communication protocol or other capabilities (e.g. WS-Eventing
in DPWS).
 Some of them may be very resource constrained, which means that auxiliary gateways
could provide additional support such as mediation of communication, protocol
translation, etc.
 Independent of whether the devices are able to discover and interact with other devices
and systems directly or via the support of the infrastructure, the M2M interactions enable
them to empower several applications and interact with each other in order to fulfill their
goals.
 Promising real-world integration is done using a service-oriented approach by interacting
directly with the respective physical elements, for example, via web services running on
devices (if supported) or via more lightweight approaches such as REST.
 Many of the services that will interact with the devices are expected to be network
services available, for example, in the cloud.
 The main motivation for enterprise services is to take advantage of the cloud
characteristics such as virtualization, scalability, multi-tenancy, performance, lifecycle
 management, etc.
 A key motivator is the minimization of communication overhead with multiple endpoints
by, for example, transmission of data to a single or limited number of points in the
network, and letting the cloud do the load balancing and further mediation of
communication.
 Content Delivery Network (CDN) can be used in order to get access to the generated data
from locations that are far away from the M2M infrastructure (geographically, network-
wise, etc.).
 To this end, the data acquired by the device can be offered without overconsumption
 of the device’s resources, while in parallel, better control and management can be
applied.

4.4.3 Distributed business processes in IoT

26
 IV Unit – M2M and IoT Technology Fundamentals

 In Figure 5.9, the integration of devices in business processes merely implies the
acquisition of data from the device layer, its transportation to the backend systems, its
assessment, and once a decision is made, potentially the control (management) of the
device, which adjusts its behavior.
 In future, due to the large scale of IoT, as well as the huge data that it will generate, such
approaches are not viable.
 Enterprise systems trying to process such a high rate of non- or minor-relevancy data will
be overloaded.

 The first step is to minimize communication with enterprise systems to only what is
relevant for business. With the increase
 in resources (e.g. computational capabilities) in the network, and especially on the
devices themselves (more memory, multi-core CPUs, etc.), it makes sense not to host the
intelligence and the computation required for it only on the enterprise side, but actually
distribute it on the network, and even on the edge nodes (i.e. the devices themselves), as
depicted on the right side of Figure 5.9.

27
 IV Unit – M2M and IoT Technology Fundamentals

 Partially outsourcing functionality traditionally residing in backend systems to the

network itself and the edge nodes means we can realize distributed business processes
whose sub-processes may execute outside the enterprise system.
 As devices are capable of computing, they can either realize the task of processing and
evaluating business relevant information they generate by themselves or in clusters.
 Business processes can bind during execution of dynamic resources that they discover
locally, and integrate them to better achieve their goals.

4.4.4 Considerations

 Existing tools and approaches need to be extended to the make the business processes IoT
aware.
 Distributed execution of processes exists (e.g. in BPMN), additional work is needed to be
able to select the devices in which such processes execute and consider their
characteristics or dynamic resources, etc.
 The dynamic aspect is of key importance in the IoT, as this is mobile and availability is
not guaranteed, which means that availability in modeling time does not guarantee
availability at runtime and vice-versa.
 Scalability is an aspect that needs to be considered in the business process modeling and
execution.
 In addition, event-based interactions among the processes play a key role in IoT, as a
business process flow may be influenced by an event, or as its result, trigger a new event.

4.4.5 Conclusions

 Modern enterprises operate on a global scale and depend on complex business processes.
 Efficient information acquisition, evaluation, and interaction with the real world are of
key importance.
 The infrastructure envisioned is a heterogeneous one, where millions of devices are
interconnected, ready to receive instructions and create event notifications, and where the
most advanced ones depict self-behavior (e.g. self-management, self-healing,
selfoptimization, etc.) and collaborate.
 Business logic can now be intelligently distributed to several layers such as the network,
or even the device layer, creating new opportunities, but also challenges that need to be
assessed.
 Future Enterprise systems will be in position to better integrate state and events of the
physical world in a timely manner, and hence to lead to more diverse, highly dynamic,
and efficient business applications.

28
 IV Unit – M2M and IoT Technology Fundamentals

4.5 Everything as a service (XaaS)

 Cloud computing is a model for enabling ubiquitous, on-demand network access to a

shared pool of configurable computing resources (e.g. networks, servers, storage,
applications, and services) that can be provisioned, configured, and made available with
minimal management effort or service provider interaction.
 All applications need access to three things: compute, storage, and data processing
capacities.
 With cloud computing, a fourth element is added _ distribution services _ i.e. the manner
in which the data and computational capacity are linked together and coordinated.

Characteristics of cloud computing

 On-Demand Self-Service.
A consumer can unilaterally provision computing capabilities, such as server time
and network storage, as needed, or automatically, without requiring human
interaction with each service provider.
 Broad Network Access.
Capabilities are available over the network and accessed through standard
mechanisms that promote use by heterogeneous thin or thick client platforms (e.g.
mobile phones, tablets, laptops, and workstations).
 Resource Pooling.
The provider’s computing resources are pooled to serve multiple consumers using
a multi-tenant model, with different physical and virtual resources dynamically

29
 IV Unit – M2M and IoT Technology Fundamentals

assigned and reassigned according to consumer demand. Examples of resources

include storage, processing, memory, and network bandwidth.
 Rapid Elasticity.
Capabilities can be elastically provisioned and released, in some cases
automatically, to scale rapidly outward and inward commensurate with demand.
 Measured Service.
 Cloud systems automatically control and optimize resource use by leveraging a
metering capability, at some level of abstraction, appropriate to the type of
service (e.g. storage, processing, bandwidth, and active user accounts).
 Resource usage can be monitored, controlled, and reported, providing
transparency for both the provider and consumer of the utilized service.

For M2M and IoT, these infrastructures provide the following:

1. Storage of the massive amounts of data that sensors, tags, and other “things” will produce.

2. Computational capacity in order to analyze data rapidly and cheaply.

3. Over time, cloud infrastructure will allow enterprises and developers to share datasets,
allowing for rapid creation of information value chains.

30
 Devices
178
lOT Physical
&Endpoins
7.1 What is an loT Device
Internet of Things (lo'lT)can
be any objecttha h
As descriled carlier, a
"Thing" in
send/receive data (including user data) over a network (e
identifier and which can
connected to the
lol devices are connecter sman
refrigerator, car, etc. ).
phone. simart TV,
computer.
about their surroundings (e.g. information terne
and send information about themselves
or

other devices or servers/storage.

nsel
the connected sensors) over a network (to
by
entities/environment around them remotely. Some exa
actuation upon the physical nples of
loT devices are listed below
A home automation device that allows remotely monitoring the status of applian
liance
andcontrolling the appliances.
An industrial machine which sends information abouts its operation and healit

monitoring data t0 a server.

A car which sends information about its location to a cloud-based service.
A wireless-enabled wearable device that measures data about a person such as the
number of steps walked and sends the data to a cloud-based service.

7.1.1 Basic building blocks of an loT Device

An loT device can consist of a number of modules based on functional attributes, suchas
Sensing: Sensors can be either on-board the loT device or attached to the device. lt
device can collect various types of information from the on-board or attached sensors
such as temperature, humidity, light intensity, etc. The sensed information can *

communicated either to other devices or cloud-based servers/storage.

.Actuation: loT devices can have various types of actuators attached that allow takin
actions upon the physical entities in the vicinity of the device. For example. a
lof device can turn an appliance on/off based on the
switch
connected
sent to the device.
to an
comman
Communication: Communication modules are responsible for sending
collecc
to other devices or cloud-based
servers/storage and receiving data from other ue
and commands from remote
applications
Analysis & Processing: Analysis and processing modules are responsible ior makin
sense of the collected data.
The representative loT device used for the
examples in this book is the wi
single-board mini computer called Raspberry Pi (explained in later sections).
Raspberry Pi is intentional since
and

these devices are

available from muluple vendors. Furthermore, extensive widely accessible, inexpn the
information is availaoh
programming and use both on the Internet and in other textbooks. The principles
2015

Bahga & Madisetti,

 7.2
Exemplary
Device: Raspberry Pi 179

ok
just as
are just as applicabl
applicableto other (including proprietary) loT endpoints, in addition to
Pi. Before we look at the specifics of Raspherry Pi, let us first look at the building
Rsphery

blocks of a generic síngle-bOard computer (SBC) based lo'T device.

Figure
Figur 7.1 shows a generie block diagram of a single-board computer (SBC) base
that includes CPU, GPU, RAM, storage and various types of interfaces and
device that inclu
loT
peripherals.

Connectivity Processor Graphics Audio/Video

USB Host HDMI
CPU GPU

RJ45/Ethernet 3.5mm audio

RCA video

nterconnect

Memory Interfaces
Interfaces Storage lntertaces
UART SD NAND/NOR

SPI MMC DDR1/DDR2/DDR3

AR2883

2C SDIO

CAN

Figure 7.1: Block diagram of an IoT Device

2 Exemplary Device: Raspberry Pi

with the physical size of a credit card.
aspberry Pi [104] is a low-cost mini-computer almost all tasks that a normal
Linux and can perform
ETy Pi runs various flavors of Pi also allows interfacing sensors
top computer can do. In addition to this, Raspbery
Since Raspberry Pi runs Linux operating
CTuators through the general purpose /O pins.
stem, it supports Python "out of the box".
ernet of Things - A Hands-On Approach
 loT Plysical Dovices &ndpeiv

7.3 About the Board

shows the Riasptery P'i b n d witlh the vilfious ¢o110ents/periphera. L .

Figun beled
.Processor & RAM: Raspbcry P'i is bAScdon an ARM proCessor. The lalest erin

Raspbeny Pi (Model B, Revision 2) cones with 700 Power

MHz Low Power ARMIU.
ARMI17617.
pawessor and S12 NMB SDRAM.
.iSB Ports: Raspherry Pi comes with two USB 2.0 ports. The USB ports onRasphe
Pi can provide a cunTent upto l00mA. For connecting devices that draw current
bey
than 100mA. an external USB powered hub is required.
Ethernet Ports: Raspberry Piconmes with a standard RJ45 Ethernet port. Youca
connect an Ethernet cable or a USB Wifi adapter to provide Internet connectivity
HDMI Output : The HDMI port on Raspberry Pi provides both video andaudio
output. You can connect the Raspberry Pi to a monitor using an HDMI ca
monitors that have a DVI port but no HDMI port, you can use an HDMI to DVI
adapter/cable.
.Composite Video Output : Raspberry Pi comes with a composite videooutput with
an RCA jack that supports both PAL and NTSC video output. The RCA jack can be
used to connect old televisions that have an RCA input only.
Audio Output: Raspberry Pi has a 3.5mm audio output jack. This audio jack is u
for providing audio output to old televisions along with the RCA jack for video.
audio quality from this jack is inferior to the HDMI output
GPIO Pins: Raspberry Pi comes with a number of general purpose input/ouput pins
Figure 7.3 shows the Raspberry Pi GPlO headers. There are four types of pins on
ad
Raspberry Pi- true GPIO pins, 12C interface pins, SPI interface pins and serial Rx
Tx pins.
The DSI interface be used to connect an LD
Display Serial Interface (DSI) : can

panel to Raspberry Pi.

Camera Serial Interface (CS): The CSI interface can be used to connect a came

module to Raspberry Pi.

.Status LEDs: Raspberry Pi has five status LEDs. Table 7.1 lists Raspberry Pi stau
LEDs and their functions
SD Card Slot: Raspberry Pi does not have a built in operating system and stors
You can plug-in an SD card loaded with a Linux image to the SD card slot. Appendik
provides instructions on setting up New Out-of-the-Box Software (NOOB5
Raspberry Pi. You will require atleast an 8GB SD card for setting up NOOBS.
Power Input: Raspberry Pi has a micro-USB connector for powerinput.

5
Bahga & Madisetti, 20
74 Linux on Raspberry Pi

181
Status LED Function
ACT SD card access
PWR .3V Power is
present
FDX Full duplex LAN
connected
LNK Link/Network activity
100 100 Mbit LAN
connected
Table 7.1:
Raspberry Pi Status LEDs
RCA Video

GPIO Headers Audio Jack

Status LEDs

DSI Connector
Display

SD Card USB 2.0

Slot

Micro USB
Ethernet
Power

CSI Connector
HDMI
Camera

Figure 7.2: Raspberry Pi board

7.4 Linux on Raspberry Pl

spberry Pi supports various flavors of Linux including:
Raspbian Raspbian Linux is a Debian Wheezy port optimized for Raspberry Pi. This
1S the recommended Linux for Raspberry Pi. Appendix-I provides instructions on

Setting up Raspbian on Raspberry P.

Arch: Arch is an Arch Linux port for AMD devices.
Pidora: Pidora Linux is a Fedora Linux optimized for Raspberry Pi.
aspBMC : RaspBMC is an XBMC media-center distribution for Raspberry Pi.
DenELEC: OpenELEC is a fast and user-friendly XBMC media-center distribution.
R : RISC OS is a very fast and compact operating system.

Internet of Things A Hands-On Approach

182
OT Physical Devices
&Eni
3V3

GPIO 2 (12c 5DA)

GPiO3(12C sDL)
GROUND
GPIO 4O GPIO 14
GROUND
(UART TO)
GPIO 15
GPIO 17 (UART RxD)
GPIO18
GPIO 27
GROUND
GPIO 22
GPIO 23
3V3
GPIO 24
GPIO 10( SPIO
MOSI)
Ground
GPIO 9(SPIO MISO)
GPIO 25

O GPIO 11 (5PIO
SCLK) GPIO 8 (SPIO CEO
N)

VU GROUND O GPIO 7
(SPIO CEI N)

Figure 7.3: Raspberry Pi GPIO headers

OCR

Figure 7.4: Rasbian Linux desktop

C)_"
Bahga & Madiset.
 44 Linux on
Raspberry Pi

183

Figure 7.5: File explorer on Raspberry Pi

;31

g:1/wm a i e t . r g

Console on
Raspberry Pi
Figure 7.6:

riternet of Things -AHands-On Approac

 hysicala Devices
Devices &Etn
dkfpa

e tet Dewnia ad By Codec

Forum FAG

Downioads

New Out Of Box

Software
(Recommended)
w*
acommend tha firct t*n Si
start bry
ytars
Ne Cat e Rov 5otrarn {*3AS} onte serat te arrg and gt aling
a RGR for
y:bnt. ths erese yms t b hoe n
ts a
iarger) t ) card. or
ncheng ranpea Prdora and turo favours ofoyorating syst erns 1o iret ,
net niind XpAC oree you hære
operatng tyct em. yoiu ean retun to tha
n ding dram sht d.rmg boot. thrt alowt
NOO rterface
by
yots to sut ch to a
Heatino system, t trereite a ferent
toerus1t ed card wth a fresh
ert instal if te

ay detah COBS wl output over

HOM at your
dsplay is connected. displays preferred
resohson, even f no MEMI
oxtpt on your f you do not
HO dspiay or are usrg the s4e any
2.3 o 4 n
your keyboard to select corngposte
HOM preterred mode,output, press 1
HOMI Sate

Figure 7.7: Browser on

Raspberry Pi

Rasp
Set up Option

ange User PassWord

Erab ie Boot to De
sktop/I5cratch nanga
nternationalisation
passuord for the default
Choose whetherto
Tebi arnera opt ions Set up boot into a da
P.dd to Rastrac. language arnd regional sett
Enabie this
Verc iock hdd Pi to workwith Ehe R
th
is Pi to the online
8
Advnced 9pt 1on Contigure Ranpber
9 Pbout Conf igure overclock ing for you
raspicon f ig intormat ion
adyennced BeEting
about Ehia conEigurat
S1ct>
<Einiah

Figure 7.8: Raspberry Pi

configuration tool
Figure 7,4 shows the
the default file Raspbian Linux desktop on 75
s

explorer on Raspbian.
Figure
Raspberry P1.
nRs
Figure 7.7 shows the default
tool is used which
7.6 shows the default
browser on Raspbian. To cohe rasp
launched from commandconfigure
Aspi t h eraspi-

can be
Figure 7.8. Using the
Raspberry 1s sho
a ss h o w

line as
configuration tool you can expand root(Sraspl-co
keyboard layout, change SD
I SDcar
partition
password, set locale and timezone, change split.e
Split
me
74 Linux on Raspberry Pi

isable SSH server and

change boot behavior. 185
l Stemthat you can use the
so It is
gh Raspbemy Pi comes with space on the SDrecommended
entire
NC an HDMI card.
to
expand the root
evie uith a VN
e connection or SSH. This doesoutput. it is more
e m Fi and
you can use away with the needconvenient to access the
ndi-A provides mstrucuons Raspberry Pi from fora
your desktop or separate display
ri ans to connect to on
setting up VNC server on laptop computer
instrutio

ommands on Raspberry Pi.

RaspberTy Pi with
SSH. Table 7.2 Raspberry Pi and the
lists the
frequently used
Command Function
cd Change directory Example
ed /homelpi
cat Show file contents
cat file.txNt
Is List files and folders
Is home/pi
locate Search for a file locate tile.txt
Isusb List USB devices Isusb
Print name of present working
pwd pwd
Dw
directory
mkdir Make directory mkdir /home/pi/new
mv Move (rename) file mv sourceFile.txt destinationFile.txt
Tm Remove file m file.txt
reboot Reboot device sudo reboot
sudo shutdown -h now
shutdownShutdowndevice
grep Print lines matching a patterm grep -r "pi" /home/
Report file system disk space df-Th
df
usage
ifconfig
ifconfig Configure a network interface
connections, netstat-intp
netstat Print network
statistics
routing tables, interface tar -xzf foo.tar.gz
tar Extract/create archive
network wget http://example.com/tile.targz

Non-interactive
wget
downloader
commands
Pi frequently used
Table 7.2: Raspberry

or Things A Hands-On Approach

 186
lOT Physical evices& Endo
ndpoirns
Interfaces
7.5 Raspberry Pi
shown in Fion
Raspberry Pi has
serial, SPI and 12C
intertaces for data transter as
Figure 7.3,
7.5.1 Serial

The serial interface on

with serial peripherals.
Raspberry Pi has receive
ommunicatn
(Rx) and transmit (Tx) pins for comm.

7.5.2 SPI
Serial Peripheral Interface (SPI) is a synchronous serial data protocol used for communicatino
ating
with one or more peripheral devices. In an SPI connection, there is onemaster devicea
one or more peripheral devices. There are five pins on Raspberry Pi for SPI interface:
.MISO (Master In Slave Out) Master line for sending data to the peripherals.
MOSI (Master Out Slave In): Slave line for sending data to the master.
SCK (Serial Clock): Clock generated by masterto synchronize data transmission
.CEO (Chip Enable 0): To enable or disable devices.
.CEO (Chip Enable 1): To enable or disable devices.

7.5.3 12C
The 12C interface pins on Raspberry Pi allow you to connect hardware modules. 12C intetace
allows synchronous data transfer with just two pins SDA (data line) and SCL (clockline
-

7.6 Programming Raspberry Pi with Python

In this section you will learn how to
get started with developing Python prograis
Raspberry Pi. Raspberry Pi runs Linux and supports Python out of the box. Therefore.
yo
can run any Python program that runs on a
normal computer. However, it is the genet
purpose input/output capability provided by the GPIO
useful device for Internet of Things. You can
pins on Raspberry Pi that make>
interface a wide variety of sensor and
with Raspberry Pi using the GPIO actu
pins and the SPI, 12C and serial interfaces. Input from the
sensors connected to
Raspberry Pi can be processed and various actions can be for

instance, sending data to a server,

sending
taket
an email, triggering a relay switch.
7.6.1 Controlling LED with Raspberry Pi
Let us start with a basic
example of controlling
the schenmalic diagram of connecting an LED an LED from Pi. Box 7.1Pi.shows howshow
to Raspberry
Raspberry Figure 7. turn

2 0 1 5

Bahga & Madisetti,

 ramming Haspberry Pi with ython
7 6Program

187
om
command line. In
his example the
EDon/ofl LED is
connected to CPIO 18.
L E Do n / o f r

the LED to any other GPIO pin as

c o n n e c t

well.
for blinking an 1LED pin
shows a Python program
m can

Box
7.2
program
es the RPi. GPIO module
usesth connected
to control to Raspherry Pi every
the CGPIO on
nd. The 18 18. direction to and output Raspherry Pi. In
program
weset pin then write
TruelFalse alternatively after
thrs s e c o n d ,
a
one
ot
lay

3V3 SV
DSI DISPLAY A6ND

22GND

no31GND

GNDc
GP10

OK
PUR
FDX
NK

10n1

with RaspberryPi
Figure 7.9: Controlling LED

Pi console
Box 7.1: Switch
c h i n g LED
on/off from
Raspberry

sys/class/gpio/export

ys/class/gpio/gpiol
Ser pin 18 direct ion to Out
0t direct10n

arn LED on
echo1 value

teno of
Thing -

A Hands-On Approach
 &ta
Turn LED Off
$echo >value

Box 7.2: Python program for blinking LED

import RPi.CPIO as GP IO
import time

GPIO.setmode (GPIO.BCM)
GP10.setup (18, GPIO.OUT)
while True:
GPIO.output (18, True)
time.s leep (1
GPIO.output (18, False)
time.sleep (1)

7.6.2 Interfacing an LED and Switch with

Now let us look at more detailed
Raspberry Pi
control the LED.
a
example
involving an LED and a switch that is used e
Figure 7.10 shows the schematic diagram of
Pi. Box 7.3 shows a connecting
Python program controlling an LED with a
for
an LED and switch to
Rasphen
the LED is connected to GPIO switch. In this examp
pin 18 and switch is connected to
loop the value of pin 25 is checked and the state of pin 25. In the infinite W
This example shows how to get LED is toggled if the switch is presSsed
input from GPIO pins and
process the input and take s
ome

action. The action in this example is

toggling
example. in which the action iS an email
the state of an
LED. Let us look at an
other

alert. Box 7.4

anemail on switch press. Note that the structure shows a Python program for se ding
of this
Box 7.3. This program uses the program is similar to the prog
Python SMTP library for
connected to Raspberry Pi is pressed. sending an email when the

Box 7.3: Python program for

controlling an LED with a switch
from time import
leep
import RPi.GP IO as GPIO

GPIO.setmode (GPI0.BCM)

Bahga& Madisetti.
:6Programming Raspberry Pi with Python

Sviteh Pin

GP TO. IN)
189
(,
.setuP

S D Pin
F io.oUT
PE.setup (i8,

statef a i s e

e tolelEDipin):
state net state

.output (pin, state)

GPIC.input (25) == True) :

goleteD (pin)
sieep
Except ybeardInterrupt:
exit

SPA

n
Raspbetry
switch with
C.0: Interfacing LED and

\iternet of Things
hings- A Hands-On Approachn
 es & ENdpointe
190

an email on switch press

Box 7.4: Python prograiu for sending

i i 3i}

y OEt Xit

124 nt à31 r ceipient-email>'

ist

sub ject 'iello'

Switch pressed on Raspberry P i '
essye
5eriame Gmail-username>'

passwOrd <pasSWord>
Server = smtp.gmail.com:587'

GPIO.set mode (GP IO .BCM)

GPI0.setup (25, GPIO. IN)

to_addr1ist, cc_addr_Llist,
def sendemai l (from_addr,
Subject, message,
1ogin, pass word,
smtpserver)

header = 'From: sn' fr om_addr

header += To: S n'% , ' . join (to_addr_list)
header t ' Cc: %sn' ','.join (cc_addr_list)
header += 'Subject: %s \n n ' subject
fheader+ meSsage
mes sage

Ser ver Smtplib, SMTP (smtpserver)

Server. startt 1s ()
SErver, 10gin (1ogin, password)
to_addrlist, message
probiems server.sendmail (from_addr,
s Ver.quit )

whiie True:
try:
if (GP10, input (25) True);
sendenail (fromena i l , r eceipient s i s t ,
CCIist, u b ject, ne s sage,
u8eriänG, pässword, serve)
1eep(.01)

2015

Bahga & Madisetti, ©

26 Progra
Win Python

ot Keyboarainterrupt:
exce
exit ()
191

Interfacing a Light Sensor

63 (LDR) with
Sofaryou
have learnedhow to interface LED and
switch
Raspberry
Pi
example of interfacing Light with
Dependent Raspberry Pi. Now let
a
ok at an
LED on/off based on the light-level Resistor (LDR) with us
rut
an
turning
shows the schema diagram of
7.11 sensed.Raspberry Pi and
connecting an LDR to Raspberry Pi.
ure

f LDR to 3.3V and other side to a

neS
An LLED is connected to
An
1uF capacitor and also to a Connect
this example). pin which is
18 GPIO pin (pin 18 in
controlled based on the
S7sed.

Ra7.5 shows the Python program for the

light-level
LDR example. The
COunt which is proportional to the
light level. In this functionreadLDR() function
ms

attnut and low and then to input. At this the LDR pin is set
point
a
the capacitor starts
esistor (and a counter
started) until the input pin reads
is charging through the
high (this happens when capacitor
oltage becomes greater than 1.4V). The counter is
stopped when the input reads high. The
final count is proportional
to the level light as greater the amount of light, smaller is the LDR
resistance and greater is the time taken to charge the capacitor.

Box 7.5: Python program for switching LED/Light based on reading LDR reading
mport RPi.GPIO as GPIO
miport time

GPI0.setmode (GPIO. BCM

dr_threshold = 1000
LDR_PIN = 18
LIGHT_PIN = 25
0ef
readLDR (P IN):
reading=0
PIO.setup (LIGHT_PIN, IO.OUT)
GPIO.out put (PIN, False)
time.sleep(0.1)
10.setup (PIN, GPIO. IN)
while
(GPIO. input (PIN) ==False):
reading=readingtl
Teturn reading

nternet of
Things- AHands-On Approach

MUOC
192

adin eadi.D: (LU_IN)

dr_teading 1dr_threshoid:
SwitchonLigit (1.IGHT_PI!N)

tiight (L1GHTPIN)

tme,sieep(1)

3VESV
ET 1ISPLAY

GN

Figure 7.11: Interfacing LDR with Raspberry Pi

A M a d i s e t t i .
 Transport Layer
message
transter capability independent
end-to-end
The transport layer protocols provide can be set up on connections.
The message transfer capability
of the underlying network. handshakes/acknowledgements (as in UDP).
without
either using handshakes (as in TCP)
or

such as error control, segmentation,

flow control and
The layer provides functions
transport
congestion control.
TCP: Transmission Control Protocol (TCP) is the most widely used transport layer
protocol, that is used by web browsers (along with HTTP, HTTPS application layer
protocols), email programs (SMTP application layer protocol) and file transfer (FTP).
TCP is a connection oriented and stateful protocol. While IP
protocol deals with
sending packets, TCP ensures reliable transmission of packets in-order. TCP also
provides error detection capability so that duplicate packets can be discarded and
lost packets are retransmitted. The
flow control capability of TCP
ensures that

Bahga &Madisetti, ©2015

 which the sender sends the data is not
to0o high for the receiver to
process.
The congestion control capability of 'TCP helps in avoiding network
congestion and
angestion collapse which can lead to degradation of network performance. TCP is
described in RFC 793 191.
IPUnlike TCP, which requires carrying out an initial
setup procedure, UDP is
tionless protocol. UDP is useful for time-sensitive
applications that have very
a

emall data units to exchange and do not want the overhead of connection setup. UDP
is a transaction
oriented and stateless protocol. UDP does not
provide guaranteed
delivery, ordering of messages and duplicate climination. Higher levels of protocols
can ensure reliable delivery or cnsuring connections created are reliable. UDP is
described in RFC 768 [10].

Application Layer
Anplication layer protocols define how the applications interface with the lower layer
nrotocols to send the data over the network. The application data, typically in files, is
encoded by the application layer protocol and encapsulated in the transport layer protocol
transaction oriented communication the network. Port
over
which provides connection or
numbers are application addressing
used for (for example port 80 for HTTP, port 22 for SSH,
connections using ports.
etc.). Application layer protocols enable process-to-process
the application layer protocol that
HTTP : Hypertext Transfer Protocol (HTTP) is
forms the foundation of the World Wide
Web (Www). HTTP includes commands
OPTIONS, etc. The protocol
such as GET, PUT, POST, DELETE, HEAD, TRACE,
the
follows request-response
a
model where a client sends requests to a server using
and each HTTP request is independent
HTTP commands. HTTP is a stateless protocol
client can be a browser or an application running
of the other requests. An HTTP
on an IoT device, a mobile application
or
on the client (e.g., an application running
Universal Resource Identifiers (URIs) identify
to
other software). HTTP protocol uses
RFC 2616 [11].
HTTP resources. HTTP is described in for
Protocol (CoAP) is an application layer protocol
CoAP: Constrained Application environments with
for constrained
meant
machine-to-machine (M2M) applications, CoAP is a web transfer
constrained networks. Like HTTP,
Constrained devices and of UDP instead of
however it runs on top
model,
uses a request-response with servers
ProtDcol and communicate
architecture where clients
TCP.CoAP uses a
client-server
interface with HTTP
designed to easily
connectionless
datagrams, CoAP is and DELETE.
CoAP
PUT, POST,
methods such as GET, Working
HITP, CoAP supports environments (CoRE)
KC available on IEFT Constrained
Specifications are
Group website [12].

rnet of Things- A Hands-On Approacn

 communication single
over a
.WebSocket: WebSocket prvtocol allows full-duplex
between client and server. WebSocket is
socket connection for sending essages
of messages to be sent back and forth between
the
based TCP and allows streanms
on
the TCPconncction open. The client can be a browser.
client and server while keeping
or an loT device. WebSocket is described in
RFC 6455 [13].
a mobile application
is a light-weight messaging
MQTT: Message Queue Telemetry Transport (MQTT)
client-server architecture
prowol based on the publish-subscribe model. MQTTuses a
where the client (such as an loT device) connects to the server (also called MQTT
Broker) and publishes messages to topies on the server. The broker forwards the

messages the clients subseribed to topies. MQTT is well suited for constrained
to
environments where the devices have limited processing and memory resources
and the network bandwidth is low. MQTT specifications are available on IBM
developerWorks [14].
XMPP: Extensible Messaging and Presence Protocol (XMPP) is a protocol for
real-time communication and streaming XML data between network entities. XMPP
powers wide range of applications including messaging, presence, data syndication,
gaming, multi-party chat and voice/video calls. XMPP allows sending small chunks
of XML data from one network entity to another in near real-time. XMPP s a
decentralized protocol and uses a client-server architecture. XMPP supports both
client-to-server and server-to-server communication paths. In the context of loT,
XMPP allows real-time communication between IoT devices. XMPP is
described in
RFC 6120 [15].
DDS: Data Distribution Service (DDS) is a
data-centric middleware standard for
device-to-device or machine-to-machine communication. DDS uses a
model where publishers (e.g. devices that publish-subscribe
generate data) create topics to which
subscribers (e.g., devices that want to consume
data) can subscribe. Publisher is an
object responsible for data distribution and the subscriber is
published data. DDS provides quality-of-service responsible for receiving
reliability. DDS is described in (QoS) control and configurable
Object Management Group (OMG) DDS
AMQP: Advanced Message Queuing Protocol (AMQP) is an specification [16].
layer protocol for business
messaging. AMQP supports both open application
publisher/subscriber models, routing and queuing. AMQP brokerspoint-to-point and
from publishers
(e.g., devices or receive messages
connections to consumers
applications that generate data) and route them over
messages (applications that process data). Publishers
to
exchanges which then distribute
either delivered publish the
message copies to queues.
by the broker to the consumers
or the which have subscribed Messages are
consumers can pull the to the queues
messages from the queues.
AMQP specification is

Bahga & Madisetti, © 2015

CoAP: Constrained Application Protocol (CoAP) is an application layer
protocol for
machine-to-machine (M2M) applications, meant for constrained environments with
constrained devices and constrained networks. Like HTTP, CoAP is a web transfer
protocol and uses a request-response model, however it runs on top of UDP instead of
TCP. CoAP uses a client-server architecture where clients
communicate with servers
using connectionless datagrams. CoAP is designed to easily interface
with HTTP
Like HTTP, CoAP supports methods such as GET, PUT, POST, and DELETE. CoAP
draft specifications are available on IEFT Constrained environments
(CoRE) Working
Group website [12].
a lllOU UUIN

MQTT: Message Queue Telemetry Transport (MQTT) is a light-weight messaging

protocol based on the publish-subscribe model. MQTT uses a client-server architecture
where the client (such as an loT device) connects to the server (also called MOTT
Broker) and publishes messages to topics on the server. The broker forwards the
messages to the clients subscribed to topics. MQTT is well suited for constrained
environments where the devices have limited processing and memory resources
and the network bandwidth is low. MQTT
specifications are available on IBM
developerWorks [14].
 CHAPTER1
Introduction
1.1 Welcome the World of
to
Embedded Processors
1.1.1 Where Are the Processors Used?
If you are new to
microcontrollers or ARM processors, first I would like to give you a
very wanm welcome.

Processors are used in majority of electronic products. For example, your mobile phones,
televisions, washing machines, cars, bank card (smartcards), and even
the remote control for simple devices like
your radio can have processors inside. In most cases, these
processors are placed inside in chips called microcontrollers. In modern microcontrollers,
the chip also contains the essential elements like memory systems and interface hardware
(often called peripherals). There are many diferent types of microcontrollers; they can be
available with different processors, memory sizes, and peripherals inside, and can be
available in different packages (Figure 1.1).
Large numbers of microcontrollers are designed for general purpose, which means they
can be used in wide range of
applications. Sometimes processors are used in chips that are

NXP LPC1114
Freescale Kinetis KL03
(Cortex-M0)
(Cortex-MO0+)
Driving o New t
h e Next Word
Knats k cho

NXP LPC1343
(Cortex-M3)

LPCXpresso LPC1343 REVVe

021ROHS/NO-PB 0C

R38
R
UT Uesigned b
C3
Ombedaad Ani
Figure 1.1
Microcontrollers are available in wide range of physical packages.
The DebinitiveGaide toARM Cortex -Mo and Cortex-Mo+ Prucessors, ttp:/dxadovi.ory/10.101 MRY78:-0-12-80327-0,o001-
Copyright 2015 ElsevierIne. All rightis reserved.
 6 Chapter 1

Gortex-A72
High-end
Application
ARM Cortex
Performance processor
Cortex As7 processors
functhenality
Cortex-A17
Cortex-A15 Cortex-A12

Cortex-A9
Cortex A53
Cortex-A8 Gortex-
Cortex-A5
Cortex-R7
High performance
Real-time system

ARM11 Cortex-R5

series

ARMOE
Cortex-R4
Cortex-M
Cortex-M4
series
Cortex-M3 Microcontroller

ARM7TDMI Cortex-Mo0 applications

Cortex-Mo
Cortex-M1

2003 2005 2009 2012 Future

Figure 1.3
Overview of the ARM processor family.

In around 2003, ARM realized that it needs to diversify the processor products to address
different technical requirements in different markets. As a result, three product profiles are
defined, and the Cortex processor brand name is created for the naming of these new

processors:
LCortex-A processors-These are Application processors, which are designed to provide
high performance and include features to support advanced operation systems (eg.
Android. Linux, Windows, i0S). These processors typically have longer processor pipeline
and can run at relatively high clock frequency (e.g. over 1 GHz). In terms of features,
these processors have Memory Management Unit (MMU) to support virtual memory
addressing required by advanced OS, optional enhanced Java support, and a secure
program execution environment called TrustZone".3

The Cortex-A processors are typically used in mobile phone, mobile computing devices
(eg, tablets), television, and some of the energy efficient servers.

While the Cortex-A processors have high performance, the processor is not designed to
provide rapid response time to hardware events (i.e., real-time requirements). As a result, a
 Introduction 7

of high-performance processors is needed, and they are the Cortex-R

different profile
processors.
Cortex-R processors-These are Real-Time, high performance processors that are very
good at data erunching. can run at fairly high clock speed (e.g., 500 MHz to 1 GHz range),
and at the same time can be very responsive to hardware events. They have cache
memories as well as Tightly Coupled Memories, which enable deterministic behavior for

interrupt handling. The Cortex-R processors are also designed with additional features
to

enable much higher system reliability such as Error Corection Code (ECC) support for
memory systems and dual-core lock-step feature (i.e., redundant core logic for error
detection).]
LThe Cortex-R processors can be found in hard disk drive controllers, wireless baseband
controllers/modem, specialized microcontrollers such as automotive and industrial
controllers.
While the Cortex-R processors can be very good at high-performance microcontroller
applications, they are quite complex designs and can consume fair amount of power.)
Therefore, another group of processors are need for the very low-power embedded
products, and they are the Cortex-M processors.

[Cortex-M Processors-The Cortex-M Processors are designed for main stream

microcontroller market where the processing requirement is less critical, but need to be
very low power. Most of the Cortex-M Processors are designed with a fairly short pipeline,
for example, two stage in the Cortex-M0+ processor and three stages in Cortex-MO,
Cortex-M3, and the Cortex-M4 Processors. The Cortex-M7 processor has a longer
pipeline (six stages) due to higher performance requirement, but still the pipeline is a lot
shorter than the designs of high-end application processors As a result of the shorter
pipeline and low power optimizations in the design, the maximum clock frequencies for
these processors are slower than Cortex-R and Cortex-A processors, but this is rarely a
problem because even a 100 MHz Cortex-M-based microcontroller can do a lot of work.

The Cortex-M processors are designed to provide very quick and deterministic interrupt
responses. To achieve this, the processor's execution control part is closely coupled with a
built-in interrupt controller called Nested Vectored Interrupt Controller (NVIC). The NVIC
provides powerful and yet easy-to-use interrupt's management. In general, the Cortex-M
processors are very easy to use, with almost everything can be programmed in C.

Due to their low power, fairly high performance, and ease of use benetits, the Cortex-M
processors are selected bymost major microcontroller vendors in their flagship
microcontroller productsThe Cortex-M processors are also used in some of the sensors,
wireless communication chipsets, mixed signal ASICs/ASSPs, and even used as controller
in some of the subsystems in complex application processors/SoC products.
8 Chapter 1
designed
the Cortex processor families, ARM also has processors specially
In addition to
features. These
which included temper-resistance
for security-sensitive products,
of the SecurCore is
are the series. For example. the SCO00. one
SecurCore
processors
basedthe Cortex- MO processor (same instruction set, and uses NVIC for
designed on
can be found in SIM cards, banking/
interrupt management). The SecurCore products
payment systems, and even some electronic 1D cards.

1.2.3 Bhurring the Boundaries

In some ways, the tenn microcontroller can be a bit vague. Some of the microcontrollers
are based on application processors such as ARM926EJ-S. one of the processor in the
ARM9E processor family. In last few years, some of the microcontroller vendors starting
to prduce microcontroller products based on the ARM Cortex-A processors
(eg..Freescale Vybrid. Atmel SAMASD3). and ARM Cortex-R processors (e.g.. Texas
Instruments TMS570. Spansion Traveo
Family).
At the same time. the Cortex-M
processors are also being used in many complex SoC
devices as
power management controller, I/O subsystem controller, etc.
In the next
generation of Cortex-R processor based on the ARMv8-R architecture. the
architecture definition also allows the
used with a full feature OS like
processor to incorporate a MMU so that it can be
Linux or Android, and at the same time handle
tasks based real-time
on a virtualization mechanism.
1.2.4 ARM Cortex-M
Processor Series
There are
a number of processors in the Cortex-M
If
processor family, as shown in Table 1.1.
we look at the instruction set in a bit more details
Cortex-MO, Cortex-MO+, and
(Figure 14), we can see that the
Cortex-M1 processors only
(56 instructions). Most of these support a small instruction set
instructions are 16 bit, thus
density-which means it need a smaller program provide a very good code
compared to many architecture. memory require for the same task
The instruction of the
set
Cortex-M0 and
an
application task involves complex data Cortex-MO+ processors are fairly simple. But if
instructions is needed to processing, then potentially a long
accomplish
because of the simple instruction
the
operations in the sequence of
set. In those Cortex-MO/MO+ processor
Cortex-M3 processor because the cases, it might be better
to use the
instructions (mostly 32 bit) that Cortex-M3 processor supports a number of
supports the following: extra
More memory addressing modes
Larger immediate data in the 32-bit
instructions
 Introduction 9

Table 1.1: The Cortex"-M Processor family

Processor Descriptions
Cortex-M0 The smallest ARM processor-only approximately 12000* logic gates at minimum
configuration. It is very low power and energy efficient.
Cortex-M0+ The most energy efficient ARM processorit has a similar size as the Cortex-M0
processor, but with additional system level and debug features (all optional), and have
higher energy efficiency than the Cortex-M0 processor design. It supports the same
instruction set as the Cortex-MO processor.
Cortex-M1
smali
It is a processor design optimized for field programmable Gate Array (FPGA)
applications. It has the same instruction set and architecture as in the Cortex-M0
processor, but has FPGA specific memory system features.
Cortex-M3 When compared to the Cortex-M0 and Cortex M0+ processors, the Cortex-M3 has a
much more powerful instruction set, and its memory system is designed to provide
higher processing throughput (e.g, use of Harvard bus architecture). lt also has more
system level and debug features, but at a cost of larger silicon area (minimum gate
count is about 40000 gates) and slightly lower energy efficiency. In general, the energy
effciency of the Cortex-M3 processor is still a lot better than may traditional 8-bit
and 16-bit microcontroller devices because the performance is substantially higher.

Cortex-M4
The Cortex-M3 processor is very popular in the 32-bit microcontroller market.
The Cortex-M4 processor contains all the features of the Cortex-M3 processor, but
with additional instructions to support DSP applications and have an option to
include a floating point unit (FPU). It has the same system level and debug features as
the Cortex-M3 processor.
Cortex-M7 lt is a high performance processor designed to cover application spaces where the
existing Cortex-M3 and Cortex-M4 processors cannot reach. Its instruction set is a
superset of the Cortex-M4 processor, for example, supporting both single and double
precision floating point calculations. It also has many advanced features, which are
usually find in high-end processors such as caches and branch predictions.
The exact gate count of a processor depends on many factors such as the serniconductor process library used, the chip
design tool used, the design optimization options, signal routing constraints, etc.

Longer branch and conditional branch ranges

Additional branch instructions
Hardware divide instructions
Multiply accumulate (MAC) instructions
Bit field processing instructions
Saturation adjustment instructions
As a result, the Cortex-M3 processor can handle complicate data processing quicker.
The code size might be similar to Cortex-M0 or Cortex-M0+ processor because although
fewer number of instructions are required to perform the same operations, and these

powerful instructions are mostly 32 bit instead of 16 bit. These 32-bit instructions also
enable the Cortex-M3 processor to utilize the registers in the register bank better.

In some applications, however, you might need to perform some DSP operations such as
filtering, signal transformations (e.g., Fast Fourier Transform), etc. In these applications,
10 Chapter 1
Cortex-M7 FPU
AANNA VMIMA single and double
precision floating point)
Cortex M4 FPU
VwNR IETN
(sirnigle preclsion

HY floating point)
MH
veV VFNMA
V NMIA VMALS
M
A TMS VFNMS
VSTA VSUe
M

UADD UMADI u1HADD

SADD1
$ADDe UAODI

SHADD16 HABO" SHBUR1

ASR SE SMSYA
AN PKH
CREX CM CMO SMULTT MUTa
AOD1

cDP

ORB 1ORD
DRH SMULST SMULa9
FOR
LORS uADO
OAT DRHT tORAT LDRSH SMLATT SMAT
uQsUB
LDREX LOREX LOREM 5 SMLART SMLARS
LOREET LDRSHT
SMMUL
MCA MRC MCRR MRRC ) PLD SMLALTT 5MLALTB

MVN MLS MA SMLALST L SMLALBs

ULWT

MOV MOVW MOVT MUL

SMULW
ORN PLDW RBIT USADAS USA0s
RR
USH POP
SMLAD
REVSH GASX
ADO ADR BRPT BLX BC REV J LREV16 QSAK

UOASX SMLSO
JLRRX sec Ev
UQSAX
A*D ASR BX CPSCMN ISB

UBFX sBFX
SASX LALD
MRS MSR SUB STC UASX

DSE DMB ISB JLSTRD

UOIV J SDIV
USAX 5AX SMLSLD

UMULL SMULL
SHASX SMUAD
STRB STRH UHASX
CMP EOR LOR LDRH LDRB LDM
SMLAL SHSAX SMUSO
STMDB UHSAX
UMLAT

SL
LSB MOV NOP STMIA

REV EY6 VS MUL MVN ORR

STREX | STREX8 UXTB SXB UXTAB SXTAS SMLAWT

USAT SSAT SXTAH SMLAW3

POP ROX RSB SEVSVC STREXH STRT UXTAH
PUSM

SXTH SxTAB165 SMMLA

SBC STR STRH STRB STM sUB
STRHT STRBT UXTH
uXTAB16
WFE SXTB16 SMMS
BH WFI UXTB16
SXTBUKTBSXTH UXTH TST NELD TBB

Cortex-MO/M0+/M1 EQ YIELD T USAT16 sSAT16 UMAAL

WFE WR
S T

(ARMv6-M) 32-bit instructions Cortex-M3 (ARMV7-M) Cortex-M4 (ARMv7E-M)

16-bit instructions

Figure 1.4

Instruction set of the Cortex-M processor family.

because the Cortex-M4 processor added

want to use the Cortex-M4 processor
you might applications-these included Single
another group of instructions targeted for these instructions. The
and saturated arithmetic
Instruction Multiple Data (SIMD) operations MAAC
is also redesigned to enable single cycle
internal data path of the processor

operations
unit that support IEEE-754
also has an optional floating point
The Cortex-M4 processor cannot perform
calculations. It does not mean that you
single precision floating point without the
in the Cortex-M0, Cortex-M0+, or other processors
floating point processing for floating point operations,
the
unit. If you are using these processors
floating point
 Introduction 11
compiler will insert runtime library functions to handle
software, which can take much longer to do and need floating point calculation using
the
additional code size overhead.
For applications that demand very high data-processing requirements, or if double
precision floating point calculation is needed, then the Cortex-M7
best choice. It is processor might be the
designed to provide very high data-processing
same
programmer's model and a superset of the instruction set asperformance,
Cortex-M4
but use the

To decide which processor.

processor to use in a project, you need to understand the
requirements of the application. Some general guideline is shown in Table processing
1.2.
Please note that you
might also need to consider the differences of
the system-level
features and performance when
selecting the right Cortex-M processor. An overview of the
comparison is shown in Table 1.3 and a
Table 14. Please note that the comparison of the performance is shown in
Cortex-M processors are very
features can be customized configurable and the exact
by the chip designers and vary among different devices.
In general, the ARM
Cortex-MO and Cortex-MO+
ultra-low power applications, and because processors are both very suitable for
the instruction set and
relatively simple, and the architecture is very programmer's model are
C-friendly,
beginners. For example, there is no need to learn a lot of they are also very suitable for
data types to
get the application to work on a Cortex-M
tool chain-specific keywords or
or 16-bit architectures. microcontroller, unlike many 8-bit

Table 1.2: The

applications for various Cortex-M Processors
Processor
Applications
Cortex-M0, Cortex-M0+ General data processing and 1/O control
processors tasks.
Ultra low power
applications.
Upgrade/replacement for 8-bit/16-bit microcontrollers.
Low-cost ASICs, ASSPs
Cortex-M1 Field Programmable Gate
medium data processing
Array(FPGA) applications with small to
complexity. (For high-complexity data
processing there are FPGAs with built-in Cortex-A processors such
Xilinx Zynq-7000 and some of the Altera as
Arria V SoCs and
Cyclone V
SoCs).
Cortex-M3
Feature-rich/high-performance/low-power microcontrollers.
Light-weight DSP applications.
Cortex-M4
Feature-rich/high-performance/low-power
DSP applications.
microcontrollers.
Applications with frequent single precision floating point operations.
Cortex-M7
Feature-rich/very high pertormance power microcontrollers.
DSP applications.
Applications with frequent single or double precision floating point
operations.
 12 Chapter 1

Table 1.3: An overview of the system level and

debug features
for various Cortex"-M Processors
Features Cortex-M0 Cortex-M0+ Cortex-M1 Cortex-M3 Cortex-M4 Cortex-M7
Number of 1-32 1-32 1, 8, 16, 32 1-240 1-240
interrupts 1-240

Interrupt 4
8-256
priority levels 8-256 8-256

FPU
Optional Optional (single
(single precision/single +
OS support
precision) double precision)
Optional
Memory Optional
Protection Optional Optional Optional
unit

Cache
Optional
Debug Optional Optional Optional Optional Optional Yes
instruction
Optional Optional Optional Optional ETM
trace MTB ETM ETM
Other trace
Optional Optional Optional
Table 1.4: Performance
of various Cortex"-M Processors with commonly used benchmarks
Features Cortex-MO Cortex-MO+ Cortex-M13 Cortex-M4 Cortex-M7
Dhrystone 2.1 (per MHz) 0.9 0.95 1.25 1.25 2.14
CoreMark 1.0 (per MHz) 2.33 .46 3.34 3.40 5.01

1.2.5 Quick Glance on the ARM Cortex-MO and Cortex-M0+ Processor

The Cortex-M0 and Cortex-M0+ Processors:

Are 32-bit Reduced Instruction Set

Computin (RISC) processor, based on an architec-
ture specification called ARMv6-M Architecture. The bus interface and internal data
paths are 32-bit width.
Have 16 32-bit registers in the register bank (r0 to rl15). However, some of these
regis-
ters have special purposes (e.g., R15 is the Program Counter, R14 is a register called
Link Register, and R13 is the Stack Pointer).
The instruction set is a subset of the Thumb Instruction Set Architecture. Most of the
instructions are 16 bit to provide very high code density.
Support up to 4 GB of address space. The address space is architecturally divided into a
number of regions.
Based on Von Neumann bus architecture (although arguably the Cortex-M0+ processor
have a hybrid bus architecture because of an optional separate bus interface for fast
peripheral register accesses, see section 4.3.2 Single Cycle IVO Interface in Chapter 4).
 Introduction 13

Designed for low-power applications, including architectural support for sleep modes
and have various low power features at the design/implementation level.
Includes an interrupt controller called NVIC. The NVIC provides very flexible and
powerful interrupt management.
The system bus interface is pipelined, based on a bus protocol called Advanced High-
performance Bus (AHB") Lite. The bus interface supports transfers of 8-bit, 16-bit, and
32-bit data, and also allows wait states to be inserted. The Cortex-MO+ procesor also
have an optional bus interface (Single Cycle I/0 interface, see section 4.3.2) for high-
speed peripheral registers, which is separated from the main system bus.
Support various features for the OS (Operating System) implementation such as a
system tick timer, shadowed stack pointer, and dedicated exceptions for OS operations.
Includes various debug features to enable software developers to create applications
efficiently.
Designed to be very easy to use. Almost everything can be programmed in C and in
most cases no need for special C language extension for data types or interrupt handling

support
Provide good performance in most general data processing and 1/0 control applications.

The Cortex-MO and Cortex-M0+ processors do not include any memory and have only
got one built-in timer which is primarily for OS operations. Therefore a chip designer
needs to add additional components in the chip design themselves.

1.2.6 From Cortex-Mo Processor to Cortex-M0+ Processor

The ARM Cortex-M0 processor was released in 2009. It was a ground-breaking product
because it is the first product that demonstrated it is possible to cramp a 32-bit processor
into the silicon footprint similar to an 8-bit or 16-bit processors, while still able to make
the design usable and provide excellent energy efficiency and a decent performance for a
32-bit processor.
Although the Cortex-M0 processor is a lot smaller than the Cortex-M3 processor (which
was released in 2005), it maintains a number of key advantages as in Cortex-M3
processor:

Flexible interrupt management using a built-in interrupt controller called NVIC

OS support features including a timer hardware called SysTick (System Tick timer) and
exception types dedicated to OS operations
High code density
Low power support such as sleep modes
Integrated debug support
Easy to use (almost everything programmable in plain C language)
 ne
Cortex-M0 processor has been very successful product, and was the fastest licensed
a
ARM processor in
2009.
After the Cortex-MO processor is released, the designers in
ARM have received additional feedback from
customers, microcontroller users and chip
designers, and ARM decided that there is an opportunity for an enhanced version for the
Cortex-MO processor, which was subsequently called the Cortex-MO+ processor.
The Cortex-M0+ processor supports all the features available in the Cortex-MO processor,
but additional features
were added to make it more powerful (these are all configurable
by
the chip designers):

Unprivileged execution level and Memory Protection Unit (MPU)-this feature is

available in other ARM processors such as the Cortex-M3 processor. It allows an OS to
execute some of the application tasks with an unprivileged level so that the OS can
mpose memory access restrictions. For example, the unprivileged software cannot
access critical system registers in the processors like NVIC registers, and memory
access permissions can be managed by the MPU. In this way, a system can be made
more robust because a misbehaving unprivileged task cannot corrupt critical data used
by the OS kernel and other tasks.
Vector Table relocation-again, this is a feature already existing in the Cortex-M3
processor. By default, the vector table is defined as the start of the memory (address
Ox0O000000). The Vector Table Offset Register allows the vector table to be defined in
other memory locations such as a different program memory location or in SRAM. This
is very useful for microcontroller devices, which might have separated vector table for
boot process and user applications.
Single Cycle I/O interface-this is a separate bus interface specifically added to allow
frequently accessed I/O registers to be read/write in a single cycle. Without this feature,
a load/store operation needs to go through the pipelined system bus, which needs two
clock cycles per access. This feature enables microcontrollers or embedded system to
have higher VO performance, as well as higher energy eficiency in I/O intensive
operations.
Internally to the processor design, there are also some significant changes. Instead of using
a three-stage pipeline as in the Cortex-MO and Cortex-M3 processors, the Cortex-M0+
This reduces the number of flip-flops in
processor is designed with a tw0-stage pipeline.
the processor, and hence reduces the dynamic power, and provides slightly higher
one clock cycle.
performance at the same time because the branch penalty is reduced by

In the Cortex-M0+ processor pipeline, as shown in Figure 1.5, a small part of the
soon as the instruction enters the
instruction decoding operations is carried out as

ARM Processor (http:l/www.arnm.com/about/newsroom/26419.php).

Cortex-MO Processor-Fastest Licensing
 Introduction 15
Pipellne
stage Cortex-MO+
Processor
Pipeline Maln
stage
Address Program Memor instruction
(e flastm0 decode
Instruction Buffer

Control
Pre decode Pipeline
Registers Execution
logic
Address
generation

Clock

Instruction #N
Fetch
Degode Execute
Instruction #N+1
Fetch
Decbde Execute
Pre-decode
Main decode
Two-stage Pipeline Figure 1.s
in the ARM"
processor bus interface. The Cortex-MO+ Processor.
execution stage. rest of the instruction decoding is combined with the
Adding decode logic to the
the design. instruction fetch stage do have
However, the balance between some
impact to the timing of
carefully to minimize the predecode and main decode
most of the impact the achievable
to logic was selected
low-power maximum clock
themaximum processormicrocontrollers run at fairly low clock frequency. In addition
designs. speed. Therefore this is not a frequency in
comparison to
problem to most of the silicon
In some
cases, the
power consumption of the
comparing between Cortex-M0 processor is reduced by 30%
when
system level, processor the and
be much smallerCortex-M0+ Processor. However, at
the difference would
consumed by the because most of the the
memory system. power could be
In order to
reduce
system-level power,
program memory accesses: additional
reduce the
optimizations have been
First, by implemented to
shortening the
processor is reduced. In processor
to a
two-stage pipeline design,
a
pipeline processor, when a
the branch
branch instruction is shadow of the
executed, the
16 Chapter 1

Branch taken Maximum branch shadow is 2

instructions (1 word) and minimum
Label is 0 instructlon

ADD CMP BGE Label

(branch)
Branch shadow

Program flow Instructions fetched but not

executed due to branch

Figure 1.6
Power wastage reduction by reducing branch shadow. Image courtesy of ARM".

instructions following the branch instruction would have been fetched by the processor.
These instructions fetched are called branch shadow (Figure 1.6), and they are discarded
by the processor and hence a long branch-shadow means wasting more energy.

Secondly, when a branch operation takes place and if the branch target instruction
occupies only the second half of a 32-bit memory space (as shown in Figure 1.7), the
instruction fetch is carried out as a 16-bit transfer. In this way, the program memory can
switch off half of the byte lanes to reduce power.

The amount of power reduction by these techniques depends on how often branch
operations are carried out in the application code.
Finally, in linear code execution, the program fetches are handled as 32-bit accesses. Since
most of the instructions are 16-bit, each instruction fetch can provide up to two
instructions. This means that the processor bus can be in idle state half of the time if there

Branch taken
Label

Ox00001006 Ox00001008 Ox0000100A 0x0000100C ox0000100D

Word boundry

Program flow

Figure 1.7
with minimum transfer size.
Power wastage reduction by fetching branch target
Image courtesy of ARM
 Introduction 17

HTRANSHED KE
AH
HAODR

HRDATA

Fetrch
(xecute pipere

Figure 1.8
Program fetch power reduction by fetching up to two instructions at a time.
Image courtesy of ARM"

is no data access instruction executed (Figure 1.8). Chip designers can utilize this
characteristic to reduce the power consumption in the program memory (e.g., flash
memory).
Another important enhancement in the Cortex-M0+ processor is the adding of a feature
called Micro Trace Buffer (MTB). This unit enables low-cost instruction trace, which is
very useful during software development, for example, helping to investigate the reason
for a software failure. The details of the MTB are covered in Chapter 13 and appendix E.

The Cortex-M0+ processor have additional enhancements when compared to the

Cortex-M0 processor in terms of chip design aspects (most of these are invisible to
microcontroller users). For example, a hardware interface was added to allow the startup
sequence of the processor to be delayed, which is useful for many SoC designs with
multiple processors.
Today, many microcontroller vendors already started offering microcontroller products
based on the Cortex-MO+ processors.

1.2.7 Applications of the Cortex-M0 and Cortex-M0+ Processor

The Cortex-M0 and Cortex-M0+ processors are used in a wide range of products.

Microcontrollers
The most common usage is microcontrollers. Many Cortex-M0 and Cortex-MO+
microcontrollers are low-cost devices and are designed for low-power applications. They
can be used in applications including computer peripherals and accessories, toys, white
goods, industrial and HVAC (heating, ventilating, and air conditioning) controls, home
automation, etc.

When comparing the microcontrollers based on the Cortex-MO and Cortex-M0+

processors to traditional 8-bit and 16-bit microcontroller products, the Cortex-M
 18 Chapter 1

microcontrollers allow embedded products to be built with more features, more

sophisticated user interface, due to support of larger address space, powerful interrupt
control, and higher performance.
The better performance and small size also bring the benefit of higher energy efficiency.
For example, for the same processing task, you can finish the processing quicker and allow
the system to stay in sleep modes longer
Another advantage of using ARM Cortex-M processors for microcontroller applications is
that they are very easy to use. Therefore it is very appealing to many microcontrolier
vendors as product support and educating the users can be challenging for some other
processor architectures.
ASICs and ASSPs

Another important group of

applications for the Cortex-M0 and Cortex-M0+ processors
are ASICs and ASSPs. For
example, there are a number of touch screen controllers,
sensors, wireless controllers, Power
Management ICs (PMIC), and smart battery
controllers designed based on the Cortex-MO or
Cortex-M0+ processors.
In these
applications, the low gate count
advantage of the Cortex-M0 and Cortex-M0+
processors allow high performance processing capability to be included in
that
traditionally only allow 8-bit or simple 16-bit processors to be used. chip designs
System on Chips
For complexSoC, the designs are often divided into a
main application
and number of subsystems for: /O
a processor system
controls, communication protocol
system management. In some cases, the Cortex-MO and processing, and
used in part of the Cortex-M0+ processor can be
subsystems to off-load some activities from the main
processor, and to allow small amount of application
processing be carried out while the main
processor is in standby mode (e.g., in battery
powered
System Control Processor (SCP) for boot sequence products). andmight also be used as
It a

management power management.

1.3 What Is Insidea Microcontroller
1.3.1 Typical Elements Inside a Microcontroller
There can be many components inside basic
a
microcontroller. For example, a simplified
block diagram is shown in Figure 1.9:
In the diagram there lot of acronyms.
are a
They are
explained in Table 1.5.
As shown in Figure 1.9, there can be a lot of components in a microcontroller
mention other (not to
complex interfaces like Ethernet, USB, etc.). In some
microcontrollers you
 CHAPTER 2
Technical Overview
2.1 What are the Cortex"-MO and Cortex-MO+ Processors?
The ARM Cortex-MO
Their internal
processor and Cortex-M0 + processors are both 32-bit
registers the register banks, data paths, and the bus
in processors.
bit. Both of them have interfaces are all 32
a
single main system bus interface, therefore
Von Neumann bus architecture. they are considered as

The Cortex-M0+
processor has an
optional single cycle /O interface that is
faster peripheral /O primarily for
register accesses. Therefore, it is possible to say the Cortex-MO+
processor has limited Harvard bus architecture
register accesses could be carried out at the capability as instruction access and I/O
that same time, but it is
although there can be two bus important to understand
therefore interfaces, the memory
interface does not bring additional space shared (unified) and
the extra bus is

The
addressable memory space.
key characteristics of the Cortex-MO and Cortex-M0+ processors are as follows:
Processor pipeline
The Cortex-M0
processor has a three-stage pipeline (fetch, decode, and
The Cortex-M0+ processor execute)
has a
two-stage pipeline (fetch +
execute) predecode, decode +
Instruction set
The instruction set is based on
Thumb" Instruction Set
subset of the Thumb ISA is
used (56 of them). Most of
Architecture (ISA). Only a
size, only a few of them are 32 bit. the instructions are 16 bit
in
In general, the
Cortex-M processors are classified
as Reduced
Computing although they have instructions of different Instruction Set
Support optional single cycle 32 bit x 32 bit sizes.
plier for designs that need small silicon area. multiply, or a smaller multicycle multi-
Memory addressing
32-bit addressing
supporting
The system bus interface is
up to 4 GB of
memory space
based
supporting an on-chip bus protocol called
8-bit, 16-bit, and 32-bit data transfers
on
AHB-Lite.
The AHB-Lite protocol is
pipelined, support high operation
Peripherals can be connected to a simpler bus based on APB
frequency for the system.
Peripheral Bus) via an AHB to APB bus protocol (Advanced
bridge.
The
Defiitive Guide w ARM" Cortex-MU and
Cupyright 2015 Elsevier Cortex-MU+ Prucessurs.
lnc. All ights reserved httyp://ds.
29
dui.org/10.101b/B78-44-12-803277-8,t00u2-3
30 Chapter 2

Interrupt Handling Nested Vectored Interrupt

controller called the
The processors include a built-in interrupt functions. It
Controller (NVIC). This unit handles interrupt
prioritization and masking
from various peripherals (chip
design dependent), an
Supports up to 32 interrupt requests number of system
and also support a
additional Non-Maskable Înterrupt (NMI) input,
exceptions. priority levels. NMI
be set to of the four programmable
Each of the interrupts can one

has a fixed priority level.

Operating Systems (OS) support to support OS operations.
and PendSV) are included
Two system exception types (SVCall also included
An optional 24-bit hardware timer called SysTick
(System Tick Timer) is
for periodic OS time keeping. level
and unprivileged execution
The Cortex-M0+ processor support privileged
tasks with
designers). This allows OS to run some of the application
(optional chip
to
to these tasks.
restrictions
unprivileged execution level and impose memory access allow
Unit (MPU) to
The Cortex-M0+ processor has anoptional Memory Protection
run time.
OS to define memory access permission for application tasks during
Low Power support
normal sleep and deep sleep. The exact
Architecturally twosleep modes are defined as
on which chip you are
behaviors in these sleep modes are device specific (depends
device specific power saving mode control registers
using). Chip designers can also add for each part
to expand the number of sleep
modes or to allow the sleep mode behavior
of the chip to be defined.
WFI (Wait for Interrupt) or WFE (Wait for Event)
Sleep mode can be entered using
to allow the processor to enter sleep
instructions, or using a feature called Sleep-on-Exit
automatically.
Additional hardware level supports to enable chip designers to create better power
reductions based on the sleep mode features, for example, the Wake-up Interrupt
Controller (WIC).
Debug
ARM CoreSight Debug Architecture. It is a
"
scalable
The debug system is based on the multi-
processor designs to complex
debug architecture that can support simple-single
processor designs.
be based on JTAG protocol (4 or five pins), or
Serial
A debug interface that can either
interface allows software developers to access
Wire Debug protocol (2 pins). The debug
debug features of the processors.
two data watchpoints, and unlimited software
Support up to four hardware breakpoints,
instruction.
breakpoint using BKPT (breakpoint)
a feature called Program Counter (PC)
Support basic program execution profiling using
Sampling via the debug connection.
 Technical Overview 31
seiveatuyieiicoa

The Cortex-MO+ Processor has an optional feature called Micro Trace Buffer (MTB),.
this provide instuction trace.
The Cortex-M Processors are configurable designs. They are delivered to chip designers in
form of Verilog source cote files with a number of parameters that chip designers can
select. In this way, chip designers can omit some of the features that are unnecessary for
their projects to save power and reduce silicon area. As a result, you can find
with different number
mierocontrollers based on the Cortex-MO and Cortex-MO+ processor
with and without the optional MPU.
Of supported interupts, and Cortex MO0+ processor
During the design process (lipure 2.). the processor is integrated with the rest of the

of logic gates and then transistors layout using

sy'stem and converted to a design composed are defined at
like maximum clock frequency
chip design tools. The timing characteristics
sclccted for the project and various
thesc stages based on the semiconductor process the
exact maximum speed and power
consumption of
design constraints. In addition, the
different products can also be different from
Cortex-MO or Cortex-MO+ processor on
cach other.

module mux(
input wire A,
input wire B,
input wire Sel,
output wire Y

assign Y= (Sel) ? B: A
endmodule Transistor layout
Logic gate netlist
Verilog code
Figure 2.1
flow.
Simplified chip design

2.2 Block Diagrams 2.2.

Cortex"-MO processor
is shown in Figure
A simplified
block diagram of the logic. It is a
data path, and control
ALU,
contains the register banks, execution stage. The
decode stage, and
core
The processor fetch stage, bank have
design with in the register
three-stage pipeline A few of the registers
sixteen 32-bit
registers.
bank has data processing.
register are
available for general
The rest
(e.g.. PC). contains the
special usages NMI input. It
request signals and a
to 32 interrupt requests and
current

NVIC accepts up between interrupt

The
for comparing
priority If an interrupt is
handled automatically.
functionality required c a n be
the execute

nested interrupts
can

s o that
the p r o c e s s o r
level s o that with the prOcessor
priority communicates

the NVIC
accepted,
correct interrupt handler.
32 Chapter 2

Power management interface

Wakeup JTAG
Interrupt Serlal-Wire Connection
Controller to debugger
Debug
(WIC) Interface

*******

Nested
Interrupt Vector
requests and Processor Debug
NMI Interrupt Core Subsystem
Controller
(NVIC)

Internal Bus System

Processor AHB LITE

bus interface
System unit
(Integration Cortex-M0
layer) Processor Bus Interface

Memory and
Peripherals
Figure 2.2
of the Cortex-MO Processor.
A simplified block diagram

microcontroller can enter

the
unit. In low-power applications,
The WIC is an optional down. Under this situation,
the
most parts of the processor powered
standby state with while the NVIC and the processor
the function of interrupt masking
WIC can perform the WIC informs the power
When an interrupt request is detected, then
inactive. the processor core can
core are
so that the NVIC and
management to power
up the system
the interrupt processing
handle the rest of
handle debug control, program
functional blocks to
contains various the processor
The debug subsystem When a debug
event occurs, it can put
data watchpoints. the status of the processor
breakpoints, and can examine
embedded developers
so that
core in a halted state

at that point. bus interface

and the AHB-Lite
in the processor core,
data path
The internal bus system, in many ARM processors.
is an on-chip
bus protocol used
AHB-Lite Architecture)
wide. M i c r o c o n t r o l l e r Bus
are all 32-bit (Advanced
AMBA°
is part of the used in the IC
This bus protocol ARM and widely
architecture developed by
which is a bus
specification,
design industry.
 Technical Overview 33

The JTAG Serial Wire interface units provide access to the bus
or
system and debugging
functionalities. The JTAG protocol is a popular 4-pin (5-pin if
including a reset signal)
communication protocol commonly used for IC and PCB testing. The Serial Wire
iS a newer communication
protocol
protocol that only requires two wires, but it can handle the same
debug functionalities as JTAG. As illustrated in the block diagrams (Figures 2.2 and 2.3),
the debug interface module is separated from the processor design. This is required in the
CoreSight Debug Architecture where multiple processors can share the same debug
connections. There are a number of additional signals for multiprocessor debug support not
shown in the diagrams.
The Cortex-M0+ processor is very similar (as shown in Figure 2.3) to Cortex-M0
processor. The only addition is the adding of the optional MPU, single cycle VO interface
bus and the interface for the MTB. The processor core internal design is also changed to a
two-stage pipeline arrangement

Power
management Single Cydie
intertace VO intertace AHB SRAM

Wakeup Micro Trace JTAG

interrupt Butfler (MTB) Serial-Wire Connection
Controliler Debug to debugger
(WIC) interface
Trace
intertace
Interrupt tiested
requests and Vector
inderrup Processor core Debug
NMI
Controler subsystemn
(NVIC)
MPU

internal Bus Systerm

Processo AHB LITE Single Cycle

System bus interface VO interface
(integration Contex-MO0
layer) Processor Bus Interface

Memory and Fast peripherals

Peripherais
Figure 2.
A simplifed block diagram of the
Cortex-MO processor.
34 Chapter 2
The MPU is a programmable device used to dlefine access permission of the memory map.
tasks can be executed with
In some of the applications where an OS is used, application
which is
an unprivileged execution level with
restrict memory access defined by the MPU,
programmed by the OS.
compared to
provides another bus interface with
faster access
The single cycle 1/O interface
The MTB is used to provide instruction trace.
the AHB-Lite system bus (pipelined operation).
the
In both Cortex-MO and Cortex-MO+ processors, a number of components in
WIC are all
processoN are optional. For example, the debug support, MPU and the
optional. Some other components like the NVIC
areconfigurable: allowing chip designers
the number of interrupt requests (IRQ).
to define the features available., for example,

2.3 Typical Systems

Cortex-M0+ processors do
As you ean see from the block diagrams, the Cortex-MO and to the
need to add these components
not contain memories and peripherals. Chip designers
microcontrollers can have
designs. As a result, different Cortex-M processor-based
different memory sizes, address map, peripherals, interrupt
assignment, etc.
design would
based Cortex-M processor, the
In a simple microcontroller design on a

consist of the following:

component,
a Read-Only-Memory (ROM)
A memory for program code storage, usually
or reprogrammable memory
technologies such as flash memory.
usually based on Static
data (including variables, stack, etc.),
A read-write memory for
Random Access Memory (SRAM).
Various types of peripherals.
processor to all
the memories and
Bus infrastructure components for joining the
peripherals.
device with boot code to
boot up the
separate ROM
also be a
In s o m e cases, there
can called
This is typically
in the user flash is
executed.
microcontroller before the program

boot ROM or boot loader.

the shown
design could look like
one
the
with Cortex-M0 processor,
For a simple design
in Figure 2.4.
the bus system into
the Cortex-M0 processor might partition
based on
A typical design
are as
follows:
two parts, which u s e r program
ROM, flash imnemory (for
the inemories including
System bus connected to and a bus bridge to the peripheral
a few
number of peripherals,
SRAM,
storage), the
bus system.
 Technical Overview 35

Interrupts
IRQS NM Processo
Digital logic
System bus (AHB Lite) Memories

Boot ROM Flash

SRAM
HighSpeed Bus Digital Peripherals
Memory Peripherals Bridge
(egGPIO) Analogue / Mixed
Signal Peripherals
IRQS
Peripheral bus (AP8)

UART SP Timers DAC ADC Other

peripherals

VOpads
Figure 2.4
A simple system with the Cortex-MO Processor.

The peripherals are connected to the peripheral bus, which might have a different oper
ating frequency compared to the system bus.
It is quite common for some of the
bus, which is linked peripherals to be connected to
separated peripheral
a
to the main system bus via a bus
peripheral bridge. This bus protocol for the
bus is typically based on APB, which is a bus
protocol defined in the AMBA".
The of
uses a
separated APB peripheral bus are as follows:
Allows lower hardware cost because the
APB protocol (non-pipelined operations)
simpler than AHB-Lite (pipelined operations) is
Allows the peripheral bus to run at a
different clock frequency than the main
Avoids large combinational system bus
logic the bus infrastructure for the main
in
which could become the bottle neck in
terms of getting to
system bus,
Many peripherals might present in a microcontroller get high operating frequeney.
ripherals can become designs and the bus fabric for
quite large. pe-
Another group important connections are the
of
generate interrupt requests, including the Generalinterrupts-A number of peripherals can

In most Purpose
microcontroller designs, external devices connectedInpuuOutput (GPiO) modules.
to certain GPIO
generate interrupt request to the processor via some pins can
additional conditioning and
synchronization logic.
 36 Chapter 2

Singie Cvele 1/0

intertace bus
High Speed
Pernpherals
eeG0)
nterrupts Processer Trace
IRQs, NM) interface Digital logic

System bus (AHB Lite) Memories

MTB Bus Digital Peripherals

Boot ROM Flash
Memory Bridge
Analogue / Mixed
SRAM Signal Peripherals
IRQS Peripheralbus (APB)

UART Timers DAC ADC Other

peripherals

VO pads
Figure 2.5
A simple system with the Cortex-M0+ Processor.

For a system based on the Cortex-MO+ processor, the system design can be very similar
like the one shown in Figure 2.5.

In this design, the high-speed peripherals are moved to the single cycle /O interface bus
for faster VO performance, and the MTB is added between the AHB-Lite system bus and
the SRAM for support instruction trace capture.

that can generate

Potentially the processor might not be the only component in the system
there is also a component called Direct
bus transactions. In many microcontroller products,
the DMA controller can carry out
Memory Access (DMA) controller. Once programmed,
from peripherals without processor intervention (Figure
2.6)
memory accesses on requests
between memory and peripherals, or
The DMA controller can perform data transfers
This is commonly needed for
befween memories (e.g, to accelerate memory copy).
or USB.
communication interface like Ethernet
microcontrollers with high bandwidth
However, it can also benefit some low-power
applications, for example, by avoiding
of data from
mode to collect small amount
waking up the processor from sleep
peripherals.
4.2.2 Registers and Special Registers

In order to perform data processing and controls, a number of registers are required inside
the processor core. If data from memory is to be processed, it has to be loaded from the
written
memory to a register bank, processed inside the processor, and then
register in the
another operation. This is
back to the memory if needed, or kept in the register bank for
a sufficient number of registers in
commonly called "load-store architecture." By having
and is C-friendly. It is easy for C
theregister bank, this mechanism is easy to use,
machine code with good performance.
compilers to compile a C program into
bank of 16 32-bit registers
The Cortex-MO and Cortex-M0+ processor provides a register
and a number of special
(most are general purposed, R13-RI5 has special purposes),
registers (Figure 4.3).
 Architecture 91

Register bank

RO General Purpose Register

General Purpose Register Special Registers
2 General Purpose Register
General Purpose Register xPSR Program Status Registers
Low Registers
R General Purpose Register
R5 General Purpose Register
APSR EPSR PSR
R6 General Purpose Register Application Execution Intermupt
R7 General Purpose Register PSR PSR PSR
R8 General Purpose Register
R9 General Purpose Register PRIMASK Interrupt Mask Register
R10 General Purpose Register High Registers
R11 General Purpose Register CONTROL Stack definition
R12 General Purpose Register
R13 (banked) Stack Pointer (SP)
R14 Link Register (LR)
R15 Program Counter (PC)

MSP Main Stack Pointer

PSP Processs Stack Pointer

Figure 4.3
Registers in the Cortex"-M0 and Cortex-MO+ processors.
The detailed descriptions for these registers are as follows:
RO-R12

Registers RO-R12 are for general uses. Due to the limited space in the 16-bit
instructions, many of the Thumb instructions can only access Thumb
called the low registers. While some R0-R7, which are also
instructions, like MOV (move), can be used on all
registers. When using these registers with ARM"
assembler, you can use either upper
development tools such as the ARM
case (e.g., RO) or lower (e.g., r0)
register to be used. The initial values of
R0-R12 at reset are
case to specify the
undefined.
R13, Stack Pointer
R13 is the Stack Pointer. It is used
for accessing the stack
via PUSH and POP
operations. There are
physically two different stack pointersmemory
in Cortex-M0 and Cortex-
M0+ Processors.
The Main Stack Pointer
(MSP, or SP_main in ARM
Pointer after reset, and is used when documentation) is the default Stack
The Process Stack Pointer running exception handlers.
(PSP, or SP_process in ARM
used in Thread mode
(when not documentation) can only be
handling exceptions).
The stack pointer selection is determined by the
registers which will be introduced later CONTROL register, of the
one
special
(CONTROL-Special Register).
92 Chapter 4

stack pointer using either "R13"

When usingARM development tools, you can access the
"r13" or "sp") can be used. Only one of
the
case and lower case (e.g.,
or "SP" Both upper
time. However, you can access to the MSP or
PSP
stack pointers is visible at a given
MSR. In such cases,
directly when using special
the register access instructions MRS and
"PSP" should be used.
the register names "MSP" or
zero and writes to these 2 bits are ignored.
The lowest 2 bits of the stack pointers are always
32-bit accesses because the registers are
In ARM processors, PUSH and POP are always
be aligned to a 32-bit word boundary. The
32-bit, and the transfers in stack operations must
word of the vector table from the program
initial value of MSP is loaded from the first 32-bit
the sequence. The initial
value of PSP is undefined.
memory during start-up
the system can completely rely on
It is not necessary to use the PSP. In many applications,
the MSP. The PSP is normally used in designs
with an OS, where the stack memory for
must be separated.
OS Kermel and the thread-level application codes

R14, Link Register

the return address of a subroutine
R14 is the Link Register (LR). The LR is used for storing
BLX is executed, the return address is stored
in LR. At the end
or function call. When BL or
stored in LR is loaded into the program
of the subroutine or function, the return address
can be resumed. In the case
where
counter (PC) so that the execution of the calling program
a special code value which is used by
the
an exception occurs, the LR also provides
ARM development tools, you can access to
the
exception return mechanism. When using be used.
and lower case (e.g., "T14" or "r) can
LR using either "R14" or "LR." Both upper
address
Cortex-MO/M0+- processor is always an even
Although the return address in the
instruction 16-bit and must be half-word aligned), bit
bit[0] is zero because smallest
are

ARMv6-M architecture, some instructions

zero of LR is readable and writeable. In the
set to 1 to indicate Thumb state.
require bit zero of a function address
R15, Program Counter
returns the current instruction address
RI5 is the PC. It is readable and writeable. A read
nature of the design). Writing to R15
will cause a
plus four (this is caused by the pipeline
branch to take place (but unlike a function call, the LR does not get updated).

either "RI5" or "PC," in either upper

In the ARM assembler, you can access the PC using
or lower case (e.g., "r15" or "pc").
Instruction addresses in the Cortex-M0/M0+ processor

must be aligned to half-word address, which means

the actual bit zero of the PC should be
zero all the time. However, when attempting
to carry out a branch using the branch
This is to indicate that
instructions (BX or BLX), the LSB of the PC should be set tol.

is used to modity the PC.

Not required when a move (MOV) or add (ADD) instruction
 Architecture 93
the branch target is a Thumb
program region. Otherwise, it can imply an attempt to switch
the processor to ARM state
(depending on the instruction used), which is not supported
and will cause a fault exception.

xPSR, Combined Program Status Register

The combined Program Status Register (PSR)
provides information about program
execution and the AlLU Mags. It consists of the
following three PSRs (Figure 4.4):
Application PSR (APSR).
Interupt PSR (IPSR), and
Exccution PSR (EPSR)

Dit
31 28 24
16| 8 0
APSR NZcV Reserved

31
24 16 8 5

IPSR Reserved ISR Number

31 24 6|
EPSR Reserved Reserved

Figure 4.4
Application PSR (APSR), Interrupt PSR (IPSR), and Execution PSR (EPSR)

The APSR contains the ALU flags: N (negative flag), Z (zero flag), C (carry or borrow
flag), and V (overflow flag). These bits are at the top 4 bits of the APSR. The common use
of these flags is to control conditional branches.

The IPSR contains the current executing ISR (Interrupt Service Routine) number. Each
exception on the Cortex-MO/MO+ processor has a unique associated ISR number (exception
type). This is useful for identifying the current interupt type during debugging and allows an
exception handler that is shared by several exceptions to know which exception it is serving.

The EPSR on the Cortex-MO/M0+ processor contains the T bit which indicates that
processor is in the Thumb state. On the Cortex-MO/MO+ processor, this bit is normally set
to I because the Cortex-M processors only support Thumb state. If this bit is cleared, a
HardFault exception will be generated in the next instruction execution.

These three registers can be accessed as one register called xPSR. For example, when :
interrupt takes place, the xPSR is one of the registers that is stored on to the stack memory
automatically and restored automatically after returning from an exception. During the
stack store and restore, the xPSR is treated as one register (Figure 4.5).
94 Chapter 4
bit

28 24 16
31
Reservod ISR Number
xPSR N Z CVReserved T

Figure 4.5
xPSR.

instructions.
only possible through special register
access
Direct access to the PSRs is
and the carry flag in the
APSR can affect conditional branches
However, the value of the
instructions.
APSR can also be used in some data processing

PRIMASK-Interrupt Mask Special Register

it blocks all
The PRIMASK register is a interrupt mask register. When set,
1-bit wide
(NMI) and the HardFault exception.
interrupts apart from the Non-Maskable nterrupt which is the highest value for a
it raises the current interrupt priority level to 0
Effectively
programmable exception (Figure 4.6).
oit
31
Reserved
PRIMASK

PRIMASK

Figure 4.6
PRIMASK.

access instructions (MSR,

The PRIMASK register can be accessed using special register
CPS. This is commonly used for handling
MRS) as well as using an instruction called
time critical routines.

CONTROL-Special Register
in the Cortex-M0 and Cortex-M0+
As mentioned earlier, there are two stack pointers
as the
selection is determined by the processor mode as well
processors. The stack pointer
The Thread mode of the
configuration of the CONTROL register (bit 1-SPSEL).
and this is also controlled
Cortex-M0+ processor can either be privileged or unprivileged,
by CONTROL (bit 0--nPRIV) (Figure 4.7).
oit
0
31

CONTROL Reserved

SPSEL (Stack definition)

nPRIV (not Privileged) /Reserved
Figure 4.7
CONTROL
 Architecture 95

PSP in Thread mode (when not

but can be switched to the
After reset, the MSP is used,
the CONTROL register. During running
exception handler) by setting bit[|] in
running an
the MSP is used,
the processor is in handler mode), only
of an exception handler (when
reads as zero. The bit[I] of CONTROL
register can only be
and the CONTROL register
return mechanism
the exception entrance and
changed in Thread node, or via
(igure 4.8).
Thumb State

Handler Mode Exception

Exception Executing exception handler roturn
request
CONTROL[1]= 0
MSP selected

Thread Mode
Executing normal code

CONTROL[1] = 0 CONTROL[1] = 1

Start
MSP selected PSP selected

Figure 4.8
Stack pointer selection.

between Privileged and Unprivileged

Bit[0] of the CONTROL register is for selecting
Cortex-M0+ devices and all Cortex-MO
states during Thread mode. Some of the

processor-based devices do not unprivileged state and therefore this bit is always
support
zero (Figure 4.9).

Thumb State

Exception Handler Mode Exception

request Executing exception handler return

Always Privileged

Thread Mode
Executing normal code

cONTROL[O] = 0 CONTROL[O]=1
Start
Privileged Unprivileged

Figure 4.9
Privileged state selection.
96 Chapter 4

Access of Registers and Special Registers

In C/C++ programming or any other high level languages, the registers in the register
In most cases, you do not
bank (R0-RI2) can be utilized by the compiler automatically.
are interfacing assembly code
need to worry about which registers being used. unless you
will be cover in Chapter 21).
and C/C++ code (such mixed language development
instructions (MRS and
The other special registers need to be accessed using some special
such usages. However. please note
MSR). The CMSIS-CORE provides a number of APls for
cannot be accessed or changed by
software (Table 4.1).
that some
ofthese special registers
Table 4.1: Access limitations to special registers

Unprivileged
Privileged
R/W
APSR R/W No access (T bit read as zero)
No access (T bit read as zero)
EPSR
Read only
Read only
IPSR
Read only
PRIMASK R/W
R/W
Read only
CONTROL

4.2.3 Behaviors of the APSR

registers
destination as well as the APSR which is
Dataprocessing instructions can affect is
in other processor architectures. The APSR
commonly known as ALU status flags the C
essential for conditional branches. In addition, one of the APSR flags,
controlling
used in add and subtract operations.
(Carry) bit, can also be
in the Cortex-MO ad Cortex-M0+ processors (Table 4.2).
There are four APSR fiags
Table 4.2: ALU flags on the Cortex-M0 and Cortex-M0+ processors

Flag Descriptions result has

executed instruction. When it is "1," the
a

N (bit 31) Set bit[31] of the result ofthe

to
When it is "0," the result has a
a s a signed integer).
negative value (when interpreted
positive value or equal zero. be set to "1" after a
executed instruction is zero. It can also
z (bit 30) Set to "1" if the result of the
are the
instruction is executed if the two values
same.
compare "1" if an unsigned
c (bit 29) Carry flag of the result. unsigned addition, this bit is set to
For
this bit is the inverse of the borrow
overflow occurred. For unsigned subtract operations,
output status.
addition subtraction, this bit is set to "1" if a signed
V(bit 28) Overflow of the result. For signed or

overflow occurred.

results are as given in Table 4.3.

A few examples of the ALU fAag
 Architecture 97

examples
Table 4.3: ALU flags operation
Results, lag
Operation Result0xE0000000, N1, Z-0, C 0, V 1
Ox70000000+ 0x70000000
Result-0x20000000, N 0, Z = 0, C 1, V= 1
1
Ox90000000 Ox90000000
Result-0x00000000, N 0, Z 1, C 1, V
Ox80000000+ 0x80000000
Result0x00000234, N 0, Z-0, C 1,
V-0
Ox00001234 Ox00001000
Z = 0, C 0, V 0
-

ResultOxFFFFFFFF, N 1 ,

0, Z - 0, C =1, V=
Ox00000004 0x00000005
N= 0
Result-Ox00000003,
OxfFFFEFFF OxFFFFFFFC
Result-0x00000001, N- 0, Z=0,
C 1, V - 0

Result 0x80000000, N1,Z0, C 0, V=

Ox80000005 0x80000004 1 =

0, Z - 1, C= 1, V=0
0 x70000000 OxFO000000
Result-Ox00000000, N
-

OxAO000000 0xA0O00000

instructions
almost all of the data processing
In the Cortex-MO and Cortex-M0+ processors,
the C flag.
some of these instructions
do not update the V flag or
modify the APSR; however,
instruction only changes the N flag
and the Z flag.
For example, the MULS (multiply)
32-bits. For example, we
The ALU flags can be used forhandling data that is larger than
two 32-bit additions. The
can perform a 64-bit addition by splitting the operation into
be written as follows:
pseudo fom of the operation can
64-bit
// Calculating Z X + Y, where X, Y and Z a r e al1
-

Calculate 1ower word addition,

Z[31:0] X[31:0] + Y[31:0]: //
1 carry flag get updated
Calculate upper word addition.
Z[63:32] X[63:32] + Y[63:32] + Carry: //
-
be found in
example of carry out such 64-bit add operation assembly
in code can
An
Chapter 6 (Section 6.5.1).
More on this will be covered
The other common usage of APSR flag is to control branching.
in Chapter 5 (Section 5.4.8), where the details of the
condition branch instruction will be
covered.

4.3 Memory System

4.3.1 Overview
All ARM Cortex-M processors have a 4 GB of memory address space. The memory

space is architecturally defined into a number of regions, with each region having a

recommended usage to help software porting between different devices (Figure 4.10)
The Cortex-MO and Cortex-M0+ processors contain a number of built-in components like
the NVIC (the interrupt controller) and a number of debug components. These are located in
fixed memory locations within the system region of the memory map. As a result, all the
devices based on the Cotex-M processors have the same programming model for interrupt
control and debug. This makes it convenient for software porting as well as helping debug
98 Chapter 4

OxE0OFFFFF OxE0OOEFFF

OxFFFFFFFF
Private peripherals including Private System Control
built-in interrupt controler
System Peripheral Bus Space (SCs)
(NVIC) and debug (PPB)
components Private Peripheral Bus
OxE 0000000
OxE0000000 OxEO0OE000
OxDFFFFFFF

Mainly used for external External Device 1GB

penpherals.
OxA0000000
Ox9FFFFFFF

Mainly used for external External RAM 1GB

memory.
Ox60000000
Ox5FFFFFFF
Mainly used for peripherals Peripherals 0.5GB
Ox40000000
Ox3FFFFFFF
Mainly used for data memory SRAM 0.5GB
(e.g. static RAM.) Ox20000000
Mainly used for program 0x1FFFFFFF
CODE 0.5GB
code. Also used for default
Ox00000000
exception vector tabde
Figure 4.10

Memory map.

Cortex-MO-based microcontroller or System-

develop debug solutions for the
tool vendors to
on-Chip (SoC) products.
instruction memory, data memory, peripherals
The memory space is shared between
the interrupt controller), and processor's debug
processor's built-in peripherals (e.g., software running on
are not visible to the
components. However, the debug components
this is implementation defined, and existing
the processor (from architecture point of view to be
Cortex-MO and Cortex-M0+ processors
are designed to make the debug components
Cortex-M7
is different from Cortex-M3, Cortex-M4, and
visible only from debugger). This
codes can access the debug components.
processors, where privileged
are 32-bits, but it is also
connected to the Cortex-M processors
In most cases, the memories with suitable
connect memory of different
data widths toa Cortex-M processor
possible to
Cortex-M processors supports memory
hardware. The memory system in
memory interface The
such as byte (8-bit), half
word (16-bit), and word (32-bit).
transfers of different sizes
either little
can be configured to support
Cortex-MO and Cortex-M0+ processor designs another in an
but cannot switch from one to
endian or big endian memory systems,
implemented design.
Cortex-M0+
connected to the Cortex-M0 or
Since the memory system and peripherals
SoC different memory
designers,
vendors or
developed by
microcontroller
processors are Cortex-M0/MO+-based products.
be found in different
sizes and memory types can
 Architecture 99

4.3.2 Single Cycle /O Interface

feature, which allows chip designer to add a
The Cortex-M0+ Processor has an optional
the main system bus), which allows certain
separated bus interface (in addition to
in a single clock cycle. This enables the
microcontroller
peripheral registers to be accessed well as improve energy
provide better performance in I/O operations, as
product to
efficiency in 1/0 intensive applications.
the single cycle 1/O
When this feature is implemented, the address space connect to
so from software point of view the
interface appears as a part of the main memory space,
bus works in the same way as registers on the
peripheral registers in the single cycle /O and does
only be used for data accesses
AHB-Lite system bus. However, this interface can

not support instruction accesses (lFigure 4.1 1).

Address Single Cycle 1/O interface

decoder to define
fast /O memory Data Transfers in memory
space. space allocated for fast VO
are handled on this bus.

Fast
Processor
Peripherals
System Bus

Data Transfers not belong System bus

to fast l/O space and (Pipelined operation,
instruction fetches. AHB Lite protocol)

AHB interconnect

ROM RAM Peripherals

Figure 4.11
Interface the Cortex-M0+ Processor.
Optional single Cycle 1/O on

The single cycle VO interface is intended for connecting small number of peripherals, which
need faster access speed (e.g., GPI0). Peripherals like UART and timerS are normally
connected via the AHB-Lite system bus because the associated operations typically do not
have short-latency requirement and do not occur frequently.

4.3.3 Memory Protection Unit

Another optional feature in the Cortex-M0+ processor is the MPU (MPU). This is a

programmable unit and is to be used with the privileged-unprivileged states of the

100 Chapter 4

and each region be

processor. The MPU provides up to eight programmable regions,
can

defined with different starting addresses, sizes, and memory access permissions.

tasks in unprivileged state

In a multitasking system, an OS can run some of the application
between tasks, so each of
and the OS can program the optional MPU each time it switches
the unprivileged application tasks run in their own permitted memory space and can only
access to memory locations allocated to them.

The configuration registers of the MPU is privileged access only so that an unprivileged
task cannot change the access permission to bypass the MPU.

More information about the MPU is covered in Chapter 12.

4.4 Stack Memory Operations

the system memory to be used as
Stack memory is memory usage mechanism that allows
a
buffer. One of the essential elements
temporary data storage that behaves as a first-in-last-out
indicates
of stack memory operation is a register called the Stack Pointer. The stack pointer
each time a stack
where the current stack memory location is, and is adjusted automatically
operation is carried out.
bank.
In the Cortex"-M processors, the Stack Pointer is register R13 in the register
but only one of them
Physically there are two stack pointers in the Cortex-M processors,
and the state
is used at a time, depending on the current value of the CONTROL register
of the processor (see Figure 4.8).
In common terms, storing data to the stack is called pushing (using the PUSH instruction)

and restoring data rom the stack is called popping (using the POP instruction). Depending
on processor architecture, some processors perform storing of new data to stack memory
decrement address indexing. In the
using incremental address indexing and some use
stack model.
Cortex-M processors, the stack operation is based on a "full-descending"
data in the stack memory, and
This means the stack pointer always points to the last filled
the stack pointer predecrements for each new data store (PUSH) (Figure 4.12).
the end of a function or
PUSH and POP are commonly used at the beginning and at
used by the
subroutine. At the beginning of a function, the current contents of the registers
PUSH operations, and at the end of
calling program are stored onto the stack memory using
the function, the data on the stack memory is restored to the registers using POP operations.
Typically, each register PUSH operation should have a corresponding register POP operation;
their original values. This
otherwise the stack pointer will not be able to restore registers to
can result in unpredictable behaviors, for example,
function return to incorrect addresses.

is one word
The minimum data size to be transferred for each push and pop operations
one instruction. The stack
(32-bit) and multiple registers can be pushed or popped in
Bluetooth Classic: Version 1.0- 3.0
someone to distinguish the different Bluetooth
We have 3 factors that enable
and data speed. Data packets
versions. They are power consumption, range,
determinates of these factors.
used and modulation schemes are the primary
the way for the emergence of
The first Bluetooth version's release paved
wireless items such as speakers, headphones, Bluetooth beacons, and game
controllers used today.

Bluetooth Low Energy: Versions 4.0- 5.0:

Bluetooth 4.0 was announced to the marketplace forming a new grouping
named Bluetooth Low Energy (BLE). It was geared towards installing
applications that require low power consumption and a GFSK modulation
Even
scheme that would enable it to return insufficient data output of 1Mbps.
though its maximum data output is 1Mbps, BLE is still unsuitable for products
that need continuous data streaming

Specifications and Features from Bluetooth 1.0 to

Bluetooth 5.0
a) Bluetooth 1.0

It invented in 1998 was a significant groundbreaking discovery. As the

was

technology was somehow immature, challenges such as no anonymity

were

encountered, but the technology is now outmoded with today's standards.

Some of the minor challenges were fixed by Bluetooth version 1.1, but the
most significant problems were fixed after Bluetooth version 1.2. Significant
improvements included sustenance for adaptive frequency-hopping spread
transmissions of
spectrum (AFH) that minimized interference, quicker speed
close to 721kbit/s, Host Controller Interface (HCI), improved discovery,
and
Extended Synchronous Connections (ESCO).

b) Bluetooth 2.0

This version 2.0 wasreleased in 2004. GFSK and phase-shift keying

features in this version. The
modulation (PSK) are some of the main improved
transfer by supporting the
role of GFSK is to improve the speed of data
Enhanced Data Rate (EDR).
 The technology improved further after the launch of Bluetooth version 2.1 by
supporting a new feature dabbed "simple. secure pairing" (SSP). It enhanced
the pairing experience. security. and extended inquiry response (EIR), thus
allowing improved devices' filtering before establishing a connection.

c) Bluetooth 3.0

This Bluetooth version was announced into the market in 2009. Over a
collocated 802.11 link, the Bluetooth 3.0 through the High Speed (HS) mode
enables the transfer of data with speeds of up to 24 Mbps. The Bluetooth
version 3.0 comeswith other new specifications such as Uitra-wideband,
Enhanced Power Control, L2CAP Enhanced modes, Unicast Connectionless
Data, and Aiternate MAC/PHY. Its high rate of power consumption has
significant drawbacks.

d) Bluetooth 4.0

Bluetooth version 4.0 was released in 2010. Back in those days, the version
was marketed as Bluetooth Smart and Wibree, although it still supported all
the previous versions' features. BLE devices are powered by coin-cell
batteries making power consumption its significant change.
e) Bluetooth version 4.1

Bluetooth version 4.1 was released in 2013, hence improving the users'
experience further. This version enabled easy transfers of bulk data. It also
allowed multiple simultaneous roles and co-existed with LTE.

Other new features supported by this version include:

11n PAL
Minor duty cycle directed publicizing
Partial time of discovery
L2CAP Connection
Dual-mode and topology
LE link-layer topology
Comprehensive interlaced scanning
A fast interval of data advertising
Mobile wireless coexistence signaling services
Wideband speech from audio architecture updates

f) Bluetooth version 4.2

 After the release of Bluetooth version 4.2 in 2014, it made it possible for the
release of the Internet of Things (loT). MOKOBlue and other manufacturers
are the first to enter the Bluetooth Internet of things industry, and also make a
total contribution to the development of Bluetooth.. Its main area of
improvements includes
Link-layer privacy that extended the policies for scanner filters
Low energy secure connection that extended the
length of Data packets
Version G of the Internet Protocol Support Profile (IPSP)
g) Bluetooth 5.0

The version was presented by Bluetooth SIG in 2016, although it was Sony in
their product Xperia XZ Premium who first
implemented this technology. Both
Bluetooth 5 vs. 4.2 primarily focused on refining connectivity and
of the internet of Things (loT),
experience
thereby offering a unified flow of data. Between
Bluetooth 5.0 vs 5.1, the Bluetooth 5.1 range is a bit higher. Its main areas of
improvements include
Slot Availability Mask (SAM)
Extensions of LE Advertising
2 Mbit/s PHY for LE
LE Channel Selection Algorithm # 2
Long-range LE Long
Non-Connectable advertising high duty cycle

h) Bluetooth version 5.1

Bluetooth 5.1 was unconfined in 2019. When Bluetooth 5.0 vs. 5.1 are
compared, version 5.1 was the first to support the Mesh-based model
hierarchy. Its main improvements areas are;

The angle of Departure (AoD) and Angle of Arrival (A0A)

GATT Caching
Periodic Advertising Sync Transfer
Advertising Channel Index

i) Bluetooth Version 5.2

The latest Bluetooth version 5.2 was introduced by the Bluetooth SIG during
the CES 2020 which was held in January 2020. This version was introduced
into the market alongside the next generation of Bluetooth LE Audio. The
most significant change made between Bluetooth 5.1 vs. 5.2 was that version
5.2 has lsochronous Channels (1SOC). Isochronous Channels supports BLE
devices with Bluetooth 5.2 or later where it acts as the base during the
implemerntation of LE Audio. The other 3 features that come with Bluetooth
version 5.2 are;

Isochronous Channels (ISOC)

Enhanced Attribute Protocol (EATT)
LE Power Control (LEPC)
Bluetooth devices Ranges by class

Bluetooth devices have 3 classes that compromise 3

standard anticipated ranges. Class 1 devices have a range of 328 feet or 100
meters, transmitting at 100 mW. Class 2 devices have a range of 33 feet or 10
meters, transmitting at 2.5 mW, whereas the range of Class 3 devices is less
than 10 meters transmitting at 1 mW.

These are the anticipated ranges, where they can radically decrease due to
an obstacle between the two devices, for instance, walls that weaken signals.
Therefore, the transmitter's strength, the device's proximity obstruction, and
the receiver's sensitivity are the most common factors influencing the range of
Bluetooth devicesS.

Bluetooth mesh version Range in ft Speed in (Mbit/s)

Class 1 100mW 100 meters

Class 2 2.5mW 10 meters

Class 2 1mW Less than 10 meters

When New Bluetooth versions are used with compatible peripherals, they
come with improvements. Before the invention of Bluetooth 4.2 back in 2014,
the other major version ofthe standard, Bluetooth 4.0, was in 2011. On the
other hand, Bluetooth 5.0 is configured with far better improvements than
previous standards (Bluetooth 4.0 & 4.2). The specifications of Bluetooth
4.2
features are ratified. Hence it can be supported by everything ranging trom
moble phones to beacons. The table below
will highlight the typical basic
features that difterentiate Bluetooth 50 and
Bluetooth 42 versions

Features or
Specifications Bluetooth 4.2 Bluotooth 5.0

Bluetooth 4.2 speed is Higher speed supporting about 2

Speed lower, only supporting Mbps, twice the speed of the
about 1 Mbps Bluetooth 4.2 version

Bluetooth 5.0 range is high,

Bluetooth 4.2 rangeis supporting 40 meters in indoor
low, only supporting 10
Range meters indoors and 50
areas and 20 meters in outdoor
locations in Line Of Sight (LOS).
meters Outdoors four times than Bluetooth 4.2
version

Power Requirement High power requirement Low power requirement

Small message capacity

of about 31 bytes. Its Large message capacity of about
Message Capacity actual data payload gives 255 bytes
17 20 bytes

Robustness to
Its robustness to operate
operate in a lts robustness to work in
in congested environs is
congested congested areas is more
less
environment

Battery Lfe Short battery life Longer battery life

Less secure than

Security Control More secure than Bluetooth 4.2
Bluetooth 5.0

It has a theoretical output of 2

Theoretical Data It has a theoretical output
Mbps and an overhead of about
Throughput of 1 Mbps
1.6 Mbps

Reliability Less reliable Highly reliable

 Foatures or
Specifications Bluetooth 4.2
Bluotooth 5.0

Digitat tite Less good digital life than

Better digital life than
Buetooth 4.0 vs. 5.0 4.2
Bluetooth

Support for loT Bluetooth 4.2 do not

davicess support loT devices It supports loT devices

Due to its lower

speed
and range, Beacons weree
Bhuetooth Beacon less popular. Their
With increased speed and range
inBluetooth 5.0 version,
message capacity is low, Beacons become more popular
at about 31
bytes

Can Bluetooth 4.0 connect to

multiple devices?
The Bluetooth version 4.0
specification has two modes of devices; dual-mode
devices and single-mode devices. All Bluetooth 4.0
passive devices can
implement both or either of the ways. The classic model (BR/EDR) and Low
energy mode are the two Bluetooth version 4.0 modes.

To the question, A single-mode low-energy-only device cannot connect to

classic mode devices. A dual-mode Bluetooth version 4.0 device can connect
with several Bluetooth Low Energy (BLE) devices.

Difference Analysis on Bluetooth 4.0 vs. Bluetooth 4.1

vs. Bluetooth 4.2
New standards that add new features or more Hardware resources required
for running more complicated protocols and algorithms are issued by the SIG
each year. Hence, without the latest software, it becomes tough to eliminate
old natural hardware. The main differences between the 3 versions are;

Bluetooth 4.0 vs. Bluetooth 4.1

1. Increased rate of data transfer

The Bluetooth version 4.1 has a single packet data of 20 bytes, while
the
Bluetooth 4.1 has a maximum transter maximum of 23 bytes. This raises
 rate of data transfer by 15%. Modifying the transmission rate of 23 bytes when
the chip is supporting Bluetooth version 4.0 is irrelevant as it drops the
packet
or complies with an error.

2 Master-slave coexistence

The Bluetooth version 4.2 has an updated link-layer topology that allows
concurrent master-slave coexistence and topology with master-to-multiple
slave connection

B. Supports the 32-Bit UUID

The broadcast packet carries a 32-Bit UUID. This UUID is not about the
attribute list that has the 16-bit and 128-bit. To obtain the full 128-bit UUID on
Bluetooth version 4.1, you only need to broadcast the 32-Bit UUID mapping
as it increases the active broadcast data length in a broadcast packet.

Bluetooth 4.1 vs. Bluetooth 4.2

1. LE connection security
links
The AES-CCM encryption bases the specifications of pairing encryption
stocks the identical
of Biuetooth versions 4.0 and 4.1; because Bluetooth 4.1
cracked. The Diffie-Hellman
key, some dangers, and vulnerabilities might be
link of Bluetooth version 4.2.
Key Exchange algorithm encrypts the pairing and a public key. The
Every Bluetooth 4.2 device has two keys; private key
a
the encrypted file,
users' private key and the other party's public key encrypts
while the receiver decrypts both the transmitting party's
private and public
from key event cracking
keys. This effectively prevents the intermediary

2 Privacy protection
broadcasts a Bluetooth device
address with a unique
Bluetooth continuously for
address. The address is essential to some applications,
Bluetooth Mac as stated by
which fixes logistics equipment
instance, logistics tracking app
Bluetooth device address.

transmission rate
3 Improved data
Bluetooth version 4.1
transmission of single packet data,
When it comes to 4.2 provides up to
255
bytes, whereas Bluetooth version
supports up to 23
the rate of data transmission
bytes, thereby improving
 is Bluetooth 4.0 the same as BLE?
Bluetooth version 4.0 rebranding by the
group controlling technology helped
individuals differentiate Bluetooth Smart and Bluetooth
Low Energy. The
Bluetooth SIG stated that version 4.0 devices would be
called Bluetooth Smart
Ready and Bluetooth Smart to distinguish the products
technology. featuring
this

Bluetooth Smart will characterize a new class of Bluetooth 4.0

features sensor-type devices such as peripherals. It
pedometers and heart-rate monitors
specially made to collect
unique data. Meanwhile, devices using dual-mode
radios referred to as Bluetooth Smart
Ready can handle both the Bluetooth
4.2 BLE technology and classic Bluetooth
capabilities, for instance,
connecting to a hands-free device or transferring files.

Why you should Update your Bluetooth to 5.2

Since the introduction of Bluetooth 5.0 in December
2016, the technology has
become more user-friendly and advanced. The Bluetooth SIG introduced into
the market a radical Bluetooth version 5.2
receiver known as Bluetooth LE
Audio on 7 January 2020. The version is modified with an LE Audio that
enables multiple devices to share data. However, it has a limit of two devices
where files can be transferred from a phone, tablet, or computer. Also, the LE
Audio gives a better audio experience to individuals with hearing problems
Some of the technical specifications of the latest Bluetooth Version 5.1 vs.
5.2 are;

1. Enhanced Attribute Protocol (EATT)

combination of enhancements to the Generic Attribute profile and an
upgraded version of Attribute Protocol (ATT) lead to the birth of Enhanced
Attribute Protocol (EATT). This new protocol enables end-users to reduce
end-to-end latency with development in the sensitivity of applications.

2. Low Energy Power Control

Bluetooth 5.2 devices have an LE Power control that exercises an essential

part in improving transmission power when two devices are connected. They
can also enthusiastically demand transmission power changes to lower power
usage and trade-off the signal's quality.
 Some benefits of LE Power control are;

I. Less power consumption.

ii. It enhances the receiver signal dependability.

ii. Growth of existing and upcoming wireless devices

3. Low Energy Isochronous Channels

Improved quality of sound hearing aids has been made promising by the
introduction of Lovw Energy Isochronous Channels. The lsochronous Channels
have made broadcasting and connection of sound to multiple devices
possible. Also, multi-language audio systems have been developed due to
this technology.

(a) Low Energy Audio

LE Audio transmits sound data on low-energy spectrum devices. A new
compression algorithm is used to maintain the Bluetooth's quality.

(b) LC3- Low Complexity Communication Codec

LC3.
LE Audio encompasses the new low robust and high-quality audio codec
With better audio high-quality and less power consumption, inventors
now
merchandise
have a colossal elasticity as they can design new wireless
easily.
(c) Hearing Aid improvements
technology, where wireless
Many individuals have benefited from Bluetooth
has made driving safer. Productivity has increased as people can take
calling
calls while driving to the office or home.
 BLE (Bluetooth Low Energy)
Introduction:

BLE (Bluetooth Low Energy) is wireless PAN technology designed and

maintained by Bluetooth Special Interest Group (SIG). There are various
versions of bluetooth. The version 4.2 and above is referred as BLE. The latest in
the series are v5.0 and v5.1. BLE specifications
intended to reduce power
are

consumption and cost of devices while maintaining coverage range. BLE is

known as "Bluetooth Smart" where as previous version is known as "bluetooth
classic"
BLE is not backward
compatible with BR/EDR protocols.
BLE 2.4 GHz ISM
uses
frequency band either in dual mode or single mode.
Dual mode supports both bluetooth classic and low
energy peripherals.
All BLE devices use the GATT profile (Generic Attribute Profile). The GATT
protocol provides series of commands for the client to discover information about
BLE server.
The BLE protocol stack architecture consists of two parts viz. controller and
host. Both are interfaced using HCI (Host to Controller
Interface).
Any profiles and applications run on top of GAP& GATT protocol layers.
BLE Protocol Stack | BLE
Architecture
System
 Ap on Layer (App)

Generlc Access Profile (GAP) Generic Attribute Protocol

(GATT)
Security Manager (SMP) Atribute Protocol (ATT HOST
Logical Link Control &Adaptation Protocol
L2CAP
HCI

LinkLayer (LL
Contro
Physical Layer (PHY \ler
BLE (Bluetooth Low Energy) Protocol Stack
The figure-2 depicts BLE system architecture. Let us understand functions of
different layers of this BLE protocol stack.
Physical Layer
The transmitter uses GFSK modulation and operates at unlicensed 2.4 GHz
frequency band.
Using this PHY layer, BLE offers data rates of 1
Mbps (Bluetooth v4.2)/2 Mbps
(Bluetooth v5.0).
It uses frequency hopping transceiver.
Two modulation schemes are specified to deliver 1 Msym/s and 2 Msym/s.
Two PHY layer variants are specified viz. uncoded and coded.
A Time Division Duplex (TDD) topology is employed in both of the PHY modes.

Link Layer: This layer sits above the

Physical layer. It is responsible for
advertising, scanning, and creating/maintaining connections. The role of BLE
devices changes in peer to peer
(i.e. Unicast) or broadcast modes. The common
roles are Advertiser/Scanner (Initiator), Slave/Master or
Broadcaster/Observer
Link layer states are defined in the figure below.

Scanning

SynchronMzation

Advertrseg Standby Intiadng

Connection
BLE Link Layer
States

The figure-1 depicts BLE device states >>. The device wil be in any one of these

states which include Standby state, Advertising state, Scanning state, Initiating
state, Connection State and Synchronization state.

HCI: It provides communication between controller and host through standard

interface types. This HCI layer can be implemented either using APl or by
interfaces such as UART/SPI/USB. Standard HCI commands and events are
defined in the bluetooth specifications.

L2CAP :This layer offers data encapsulation services to upper layers. This
allows logical end to end data communication.

SMP :This security Manager layer provides methods for device pairing and key

distributions. It offers services to other protocol stack layers in order to securely

connect and exchange data between BLE devices.
 .GAP: This layer directly interfaces with application layer and/or profiles on it. t
handles device discovery and connection related services for BLE
device. It also
takes care of initiation of security features.

GATT: This layer service framework which

is
specifies sub-procedures to use
ATT. Data communications between two BLE devices
are handled
through these
sub-procedures.The applications and/or profiles will use GATT directly.

ATT This layer allows BLE device to expose certain pieces of data or
attributes.

Application Layer :
The BLE protocol stack layers interact with applications and profiles as desired.
Application interoperability in the Bluetooth system is accomplished by Bluetooth
profiles.
The profile defines the vertical interactions between the layers as well as the
peer-to-peer interactions of specific layers between devices.
A profile composed of one or more services to address particular use case. A
service consists of characteristics or references to other services.
Any profiles/applications run on top of GAP/GATT layers of BLE protocol stack.
It handles device discovery and connection related services for the BLE device.
IOSS GPIO (5x ports)

4x TCPWM

CapSense

2x SCB-12CISPUUART

LCD

2x LP Comparator

24MHzXO
32kHz XO
LDO
1. Introduction
2CYPRESS EMBEDDED IH TOMORROW*

svstem controller with an ARM

Cortex"-MO CPU. It combines programmable ana-
lo s a programmable
Ogrammable embedded
interconnect, user-oroarammable diaital logic, and commonly used fixed-function peripherals with a high-
architecUre which supports
Cortex-M0 subsystem, The PSoC 4xxx-BL family is based on the PsoC 4
Bl "ARM
Bluetooth. This is upward-compatible with larger members ot o *
PSOC 4 devices have these characteristics:
High-performance, 32-bit single-cycle Cortex-MO CPU core
BLE radio
and subsystem
o On-chip BLE transceiver
o Link layer controller
compliant with Bluetooth 4.2
Fixed-unction and configurable digital blocks
Programmable digital logic
High-performance analog system
Flexible and programmable interconnect
Capacitive touch sensing (CapSense")
Low-power operating modes- Sleep, Deep-Sleep, Hibernate, and Stop modes
Direct memory access (DMA)
This document describes each functional block of the PSoC device in detail. This information will help designers to create
system-level designs.

1.1 Top Level Architecture

Figure 1-1 shows the major components of the PSoC 41x7-BL4xx architecture and Figure 1-2 shows the major components
of the PSoC 42x7-BLA architecture. Figure 1-3 shows the major components of the PSoC 41x8-BL4xx architecture and
Figure 14 shows the major components of the PSoC 42x8-BL4xx architecture. Figure 1-5 shows the major components of
the PSoC 41x8-BL5xx architecture and Figure 1-6 shows the same for PSoC 42x8-BL5xx architecture.

PSoC 41Xx BLEJ42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No. 001-92738 Rev. 'D
19
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MBGOPE0 IN YOMORROW

Introduction

Flgure 1-1. PSoC 41x7-BL4xx Famlly Block Diagram

CPU& Momory
PSOC 41x7-BL
Corlex
32-Ujt
MO
FLASH SRAM ROM
128kB 16 kB 8 kB
AHDite 24MHz
NYAEMU ReadAccoloralor 9FAM Conilroler ROM Controller
NVIRgMA
Synteny Rexources
Rowet
Sponto
ROR IVA
SystemInterconnoot (SingleLayer AHB)
Pertpherals
AWRSYS
NVLnHe NLPCLK Porlpheral Intorconnect (MMIO)

look
Cock Control Programmmablo Bluetooth Low
IMOT ILO Analog
EnergySubsystem
Rosot
BLE Basoband
Resel ontro SAR ADG eral
XNES (12-bit) KB SRAM
GFSK Modem
DF Loglc 2.4 GH
DFY AM GFSK
SMX CTBm x1 Radio
HH 2xOpAmp Port Interfaco &Digital System Intorconnect (DSI)

10 AntonnaPawer/Cryla
Actvo Sloep HIgHSpO0C 1/OIMar
e p SJo0p
RHIbOnate.i) S6GX GPIOS
IO Sübsysterm

PSOC 41Xx BLE/42XX_BLE Family PSoC 4 BLE Archteoture TRM, Document No. 001-92738 Rev. 'D
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Introduction

Figure 1-3. PSoC 41x8-BL4xx Family Block Diagram

CPU &Memory
PSoC 41xB-BL
SWONO SPCE
Cortex ROM
32-0It
MO FLASH SRAM
256kB 32 KB 8 KB
24 MHz
AHB-LIO ASTMUL ROMControler
NVIG ROMX Read Accelerator SRAMConlroller
System Resources

Sleen eontrol| System interconnect (Single Layer AHB)

PORT VI
REE O
Peripherals 1
NVLalehas
NVLatcies.u.
PCLK J Peripheral Interconnect (MMI0)

Clock
Programmable Bluetooth Low
Clock Control
WDT Analog Energy Subsystem
IMO |ILO
BLE Baseband
Peripheral
Reset SAR ADC KB SRAM
Reset Control 2-bit GFSK Modem
RES
24 GHz i
Test GFSK
DFTLogic Radio
DFT Analog CTBm x1
2xOpAmP Port Interface &Digital System Interconnect (s

OAntennalPowericrystal
ighSpeeda/oMatrix
AGVEISleap
eep Sleep
Hibenate 36x GEIOS

1O Subsystema

PSoC 41XX BLE/42XXBLE Family PsoC4 BLE Architecture TRM, Document No. 001-92738 Rey 'n
22
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ENBBDORO TOMORnow
Introduction

Figure 1-2. PSoC

PSOC 42x7-BL CPU &Memory 42x7-BL4xx Family Block Diagram
SWOATC
32-bit Cortex SPCIE
MO FLASH SRAM ROM
AHB 48 MHz 128 kB 16kB 8 KB
System Resources O5HASIIMUL
NVCHIRCMX
Read Accaorator SRAM Controller ROM Controller
Rower
Sleep Control
POR T VD System Interconnect (Single Layer AHB)
REF BOD Peripherals
PWRSYSC ALN
NVLatches PCLK Peripheral Interconnect (MMIO)
ock
Clock Control rogrammable
IMO LO Analog Programmable
Digital Bluetooth Low
Energy Subsystem
UDB
Reset Control
UDB BLE Baseband
SAR ADC
(12-bit) Peripheral
L1KB SRAM
GFSK Modem
DETLoglc
DFT Analog 2.4 GHz
SMX CTBm x 2 GFSK
2x OpAMP Radio
Port Intertace & Digital System Interconnect (DSI)

ACIvelsioep High speed VO Matrix 10Antenna/PowerCrystal

Sleep
Hibernate.
36x GPIOs
1O Subsystem

PSOC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No. 001-92738 Rev. 'D
21
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Iritroduction

EMBEDSES IN TOMGRRDH

Figure 1-4. PSoC 42x-BLAxx Faily Bhosk Disgram

PSoC 42x8-BL CPU&Memory

Cortex
MO FLASH SRAM ROM
256 KB 32 K KE
AHB-Lite 48 MHz
EAST 7UL HOM AARD
Resd hctelerator SHAM Contade
System Resourcess
OWer
System Interconnect (Singls Laysr AHE)
PORLVD Peripherals
REFBOO
PWRSYS
VLatbies POK Peripheral nterconned (GMAIO)

Clock Control Progranimabe TOgrasmTFable

WDT Analog Digital Energy/sern

MO L
UDB UDE
Reset Control SARADC
12
2AGH
DF LOgc
DFTAnalog CTBm
2x Ophmp Pot Interfas Digaad ystenn nerned ( )

AciversSeep
HDenaie
10Subsyystem

PSOC 41Xx_BLE/42XX._BLE Family PSoC 4 BLE ArChtecture IRM, Document No. 001-92738 Rev. "D
23
 CYPRESS
Introduction
EMBEDDED 1H 1E#OR#OW"

Figure 1-5. PSoC

CPU Subsysterm 41x8-BL5xx Family Block
PsOC 41x8-BL5x Dlagram
SWVAC SPGIE
32-bit
AHB-Lite ASMUL
NVIC, RQMUX Road
System Resources AccelerelotSRAM Controler ROM Controller atos/MMIO
Power
See

POR
System Interconnect (Multi Layer AHB)
RE
PWRSYS
NVLatci
LPCLK
Peripheral Interconnect (MMIO)
rock
Cock Control Programmable
Analog BluetoothLow
IMO iLO SARAADC Energy Subsystem
(12-bit)
Ese BLE Baseband
Resetcontrol
AKES
Peripheral
X1 AKE SRAM
Test GFSK Modem
Digital DF
LAnaloa O
SARMUX CBm 24 GHz
2xOpAmp x GFSK
Port Intertace & Digital System Interconnect (DSI) Radio

O Antenna/Powerlcryslal
Power Modes
AcWESEEgi
DeepSleep
Hibemate O Subsystem

psaC 41Xx BLE/42XX_BLE Family PSoC4 BLE AICIIeCiure IRM, Document No. 001-92738 ev. *n

24
 Introduction

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ENBEDOEO IN TOMORROW

PSoC 42x8-BL5xx Family Block Diagramn

Figure 1-6.

CPU Subsystem
PSOC 42x8-BL5xx
SWOS

32-bIt
Inilloto/MMIO
ROMControllor
AHB-Lite
Ux Rond Accolerator SRAMControllar
1
System Resources Interconnect (Multi Layer AHB)
ower
System
Sleegrontrol
POR VO Peripheral Interconnect (MMIO)
PCLKJ
NKkehes. Bluetooth Low
Programmable Programimable Energy Subsystem
Clock Dlgltal
Clock Control Analog BLE Baseband
SAR ADC
IMO O 12-bt) UDB UDB
Perlpheral

L TKE SRAM
GFSK Modem
Roso
Raset control
ARES x1
2,4 GHz
GFSK
ET Radio
Digital
Analog
DE
DET SARMUX CTEM PortInterface &Digital System Interconnect
(DS)
HHA 2x OpAmp
UO: AntennaPower/Crystal
L NNR www

Powor Modes
Active/sleep
Deepsleep
Hbernate O SUoSyStem

Segment LCD direct drive

1.2 Features Low-power operating modes: Sleep, Deep-Sleep, Hiber-
nate, and Stop
The PSoC 4xx-BL family has these major components: wire
BLE radio and subsystem Programming and debugging system through serial
deliver- debug (SwD)
32-bit Cortex-M0 CPU with single-cycle multiply,
IDE tool
ing up to 43 DMIPS at 48 MHz Fully supported by PSoC CreatorT
Up to 256 KB flash and 32 KB SRAM
Direct memory access (DMA) 1.3 CPU System
Four independent center-aligned pulse-width
modula-
dead-band program
tors (PWMs) with complementary, 1.3.1 Processor
mable outputs
sampling rate of 1 Msps in The heart of the PSoC 4 is a 32-bit Cortex-M0 CPU core
Twelve-bit SAR ADC (with a
in PSOC 41xx-BL) with running up to 48 MHz for PSoC 42x-BL and 24 MHz for
PSoC 42xx-BL and 806 ksps
channels PSoC 41xx-BL. It is optimized for low-power operation with
hardware sequencing for multiple
extensive çlock gating. It uses 16-bit instructions and exe-
be used for analog signal
Up to four opamps that can cutes a subset of the Thumb-2 instruction set. This instruc-
a comparator
conditioning and as tion set enables fully compatible binary upward migrationhof
Two low-power comparators the code to higher performance processors such as Cortex
blocks (SCB) that can work M3 and M4.
Two serial communication
as SPI, UART, FC,
and local interconnect network (LIN)
The CPU has a hardware multiplier that provides a 32-bit
communication channels
slave serial result in one cycle.
blocks, known as univer-
Up to four programmable logic
saldigital blocks (UDBs)
CapSense

PSoC 41XX BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No. 001-92738 Rey. 'D
25
 CYPRESS EMBEOOEO W TOMORROW

Introduction

MHz can
ranging from 0
MHz to 48
1.3.2 Interrupt Controller external clock source
functional
clock derivatives for the
be used to generate the
The CPU subsystem includes a nested vectored interrupt blocks instead of the
IMO.
controller (NVIC) with 32 interrupt inputs and a wakeup a highly accurate 24-MHz
interrupt controller (WIC), which can wake the processor The ECO is used to generate
components. It is primaily used
from Deep-Sleep mode. The Cortex-MO CPU of PSoC 4 clock without any external
which contains the Link Layer
implements a non-maskable interrupt (NMI) input, which can to clock the BLE subsystem,
and the RF transceiver. The
be tied to digital routing for
general-purpose use. engine, the digital PHY modem, also be used as a clock
cock can
high-accuracy ECO
source for the PSoC
4 device.
1.3.3 Direct Memory Access WCO is used to
source for LFCLK.
The WCO is used as a events
The DMA engine is capable of independent data interval of advertising
transfers
anywhere within the memory map (peripheral-to-perpheral
accurately maintain the
time
Sleep mode. Similar to
and connection events during Deep Hiber-
and peripheral-to/from-memory) with a available in all modes, except
programmable the ILO, WcO is also
descriptor chain. nate and Stop modes.

Note: DMA is available only in PSoC 41x8-BL5xx and PSoC

42x8-BL5xx families. 1.5.2 Power System
external supply in the
The PSoC 4 operates with a single
1.4 Memory range 1.71 V to 5.5 V.
The PSoC 4 memory subsystem consists of flash and PSOC 4 has four low-power modes Sleep, Deep-Sleep,
SRAM. A supervisory ROM, containing boot and configura- Active mode.
Hibernate, and Stop in addition to the default
-

tion routines, is also present. In Active mode, the CPU runs with all the logic powered. In
Sleep mode, the CPU is powered off with all other peripher
als functional. In Deep-Sleep mode, the CPU, SRAM,
and
1.4.1 Flash
is
high-speed logic are in retention; the main system clock
The PSoC 4 has a flash module, with a flash accelerator OFF while the low-frequencyclock is N and the low-fre-
tightly coupled to the CPU, to.improve average access times In Hibernate mode,
quency peripherals are in operation.
from the flash block. The lash accelerator delivers even the low-frequency clock is OFF and low-frequency
85 percent of single-cycle SRAM access performance on an
peripherals stop operating.
average.
Multiple internal regulators are available in the system to

SRAM support power supply schemes in different power modes.

1.4.2
The PSoC 4 provides SRAM, which is retained during Hiber- 1.5.3 GPIO
nate mode.
Every GPIO in PSoC 4 has the following characteristics:

1.5 System-Wide Resources Eight drive strength modes

Individual control ofinput and oútput disables
1.5.1 Clocking System Hold mode for latching previous state
device consists of the Selectable slew rates
The clocking system for the PSoC 4
internal main oscillator (IMO) and internal low-speed oscilla- Interrupt generation edge triggered
locks and has provision for an external CapSense and LCD drive'support
tor (ILO) as internal
watch crystal
clock, external crystal oscillator (ECO), and
oscillator (Wco). PSOC 4 also has two over-voltage tolerant ports, which
enable 12C Fast Mode power down specification compliance
is the primary
The IMO with an accuracy of t2 percent and have the ability to cónnect to higher voltage buses while
source of internal clocking
in the device. Multiple clock deriv- operating at lower Vpp.
clock frequency to meet
atives are generated from the main
various application needs. The pins are organized in a port that is 8-bit wide. A high-
speed l/O matrixiS used to multiplex between various sig-
accurate oscillator and is used
The ILO is a low-power, less nals that may connect to an I/O pin. Pin locations for fixed
to generate clocks for peripheral
as a source for LFCLK, function peripierals are also fixed.
in Deep-Sleep mode. Its clock frequency is 32 kHz
operation
with +60 percent accuracy.

PSoC 41XX_BLE42XX_BLE Family PSoC 4 E Architecture TRM, Document No. 001-92738 Rev. D
26
 CYPRESS
ENBEDOE0 IN TOMORADW
Introduction

1.6 Bluetooth Low-Energy of these counters can be synchronized. Each block has a

Subsystem capture register, period register, and compare register. The

block supports complermentary, dead-band programmable
PSoC 4xxx Bluetooth
Low-Energy (BLE) subsystem inte-
grates the RF transceiver,
outputs. It also has a kill input to force outputs to a predeter-
mined state. Other features of the block include center
digital PHY modem, and link
controller layer aligned PWM, clock prescaling, pseudo randorm PWM, and
quadrature decoding.
1.6.1 RF Transceiver
The RF transceiver 1.8.2 Serial Communication Blocks
contains an
integrated balun, which pro-
vides a
via
single-ended
RF port pin to drive
50-ohm antenna a
The device has two SCBs. Each SCB can implement a
matching/filtering
a
block converts
network. In the recelve
direction, this
serial communication interface as FC, UART, local intercon
neot network (LIN) slave, or SPI.
the RF signal from the
intermediate frequency and antenia to a 1-MHz
bit digital signal. In the digitizes the analog signal to 10- The features of each SCB include:
transmit direction, this block takes 1 Standard PC multi-master and slave function
Mbps GFSK modulated from digital
radio frequency, and transmit it to air PHY, up-converts it to Standard SPI master and slave function with Motorola,
through antenna. Texas Instruments, and National (MicroWire) mode
1.6.2 Digital PHY Modem Standard UART transmitter and receiver function with
SmartCard reader (ISO7816), IrDA protocol, and LIN
In the transmit direction, this
sub-block takes the 1-Mbps Standard LIN slave with LIN v1.3 and LIN v2.1/2.2 spec
serial data from the link
layer controller, generates GFSK ification compliance
direct modulated data, and sends it to the BLE
analog
tion. On the receive side, it takes the 1-MHz IF ADC sec EZ function mode support for SPI and PC with 32-byte
data buffer
from the BLE analog section and uses digital demodulator to
generate the 1-Mbps serial data.
1.9 Analog System
1.6.3 Link Layer Controller
1.9.1 SAR ADC
The link layer controller implements all timing critical func-
tions specified in the Bluetooth Low-Energy Link Layer PSOC 42xx-BL has a configurable 12-bit 1-Msps SAR ADC
and PSoC 41xx-BL has a similar 12-bit SAR ADC with
specifications (packet framing/de-framing, CRC generation/
806 ksps. The ADC provides three internal voltage refer
checking, encryption/decryption, state machines, and
ences (VDDA VDDA2, and VrEF) and an external reference
packet transmission); it also provides interface to the digital
through a GPIO pin. The SAR hardware sequencer is avail-
PHY. The communication between link layer hardware and
able, which scans multiple channels without CPU interven-
firmware is done through interrupt, FIFO, and registers.
tion.

1.7 Programmable Digital 1.9.2 Continuous Time Block mini

The PSoC 42xx-BL has up to four UDBs. Each UDB con- The Continuous Time Block mini (CTBm) provides continu-
tains structured data-path logic and uncommitted PLD logic
ous time functionality at the entry and exit points of the ana-
with fiexible interconnect. The UDB array provides a log subsystem. The CTBm has two highly configurable and
switched routing fabric called the digital signal interconnect high-performance opamps with a switch routing matrix. The
(DSI). The DSI allows routing of signals from peripherals opamps can also work in comparator mode. PSoC 42xx-BL
and ports to and within the UDBs. has two such CTBm blocks, while PSoC 41xx-BL has one
enable custom logic or CTBm block.
The UDB arays in PSoC 42xx-BL
communication interfaces such
additional timers/PWMs and The block allows open-loop opamp, linear bufter, and
as PC, SPi, 125, and UART. com
parator functions to be performed without external compo-
have UDBs. nents. PGAs, voltage buffers, filters, and trans-impedance
Note PSoC 41xx-BL does not
amplifiers can be realized with external components.CTBm
block can work in Active, Sleep, and Deep-Sleep modes.
1.8 Fixed-Function Digital
1.9.3 Low-Power Comparators
Timer/Counter/PWM Block
1.8.1 The PSoC 4xxx-BL has a pair of low-power
comparators,
block consists of four 16-bit
coun-
whlch can operate in all device power modes. This function-
The Timer/Counter/PWM

ters with User-programmable

period length. The functionality alty allows the CPU and other system blocks to be disabled

PSoC4 BLE ArChitecture TRM, Document No. 001-92738 Re

41XX BLEJ42XX_BLE Family
n
PSoC 27
 Introduction
CYPRESS
ENBEODEO IN TOMORROW

while retaining the

during low-power ability toIwomonitor external voltage levels
mOdes.
from pins, or one from input voltages can both
an internal buttons and sliders. CapSense functionality is supported on
come
BUS. signal through the AMUX- all GPIO
pins in PSoC 4 through a CapSense Sigma-Delta
(CSD) block. The CSD also provides waterproofing capabil
1.10 ity.
Special Function
1.10.1 LCD
Peripherals 1.10.2.1 IDACs
DAC and Comparator

The PSoC 4 has

Segment Drive The CapSense block has two
a 12-V
lIDACs and a comparator with
an LCD reference, which can be used for general
controller, which
four commons and every GPIO can drive up to CapSense is not used. purposes, i
Common or can be
configured to drive
segment. It uses full digital methods
relation and PWM) to drive (digital cor 1.11
the LCD
require generation of internal LCD segments, and does not Program and Debug
voltages. PSOC 4 devices support
tures of the device via the programming
and debugging fea
1.10.2
CapSense Creator IDE provides
on-chip SWD interface. The PSoC
fully integrated
debugging support. The SWD interface is programming
and
PSOC 4 devices have the also fully compati
CapSense feature, which ble with industry standard
you to use the capacitive properties of your fingers to allows
toggle
third-party tools.

1.12 Device Feature Summary

Table 1-1 shows the PSoC
41xx-BLI42xx-BL device summary.
Table 1-1. PSoC 41xx-BL/42Xx-BL Device
Summary
Feature PSoC41xx-BL PSoC 42xx-BL
Maximum CPU Frequency
|24 MHz 48 MHz
Flash PSOC 41x7-BL: 128 KB PSoC 42X7-BL: 128 KB
PSOC 41x8-BL: 256 KB PSoC 42x-BL: 256 KB
SRAM PSOC 41x7-BL: 16 KB PSOC 42x7-BL: 16 KB
PSoC 41x8-BL: 32 KB3 PSOC 42x8-BL: 32 KB
GPIOs (maximum) 38 38
CapSense Available Available
LCD Driver Available Available
Timer, Counter, PWM (TCPWM)
wwwwww

Serial Communication Block (SCB)

wwww.w

Universal Digital Block(UDB) Not Available

IDAC(part ofCapSense)
Opamp
Comparator 2 2

ADC |12-bit SAR,806 ksps 12-bit SAR, 1Msps

Bluetooth Available Available

psaC 41XX BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No. 001-92738 Rev. "D

28
4 Cortex-M0 CPU
CYPRESS EMBEDDEO IN TOMORROw

The PSoC4 ARM Cortex-MO core is a 32-bit CPU optimized for low-power operation. It has an efficlentthree-stage pipeline
a single-cycle 32-
enory map, and supports the ARMv6-M Thumb instruction set. The Cortex-MO also features
the CPU include a nested
instruction and low-latency interrupt handiing. Other subsystems tightly linked to core
E y
vectored interrupt controller (NVIC), a SYSTICK timer, and
debug
section gives an overview of the Cortex-MO processor. For more details, see the ARM Cortex-M0 user guide or technical
his
reference manual, both available at www.arm.com.

4.1 Featuress
The PSoC4 Cortex-M0 has the following features:
Easy to use, program, and debug, ensuring easier migration from 8- and 16-bit processors
Operates at up to 0.9 DMIPS/MHz; this helps to increase execution speed or reduce power
Maximum CPU cdock frequency of 24 MHz in PSOC41xx_BL and 48 MHz in PSoC42xx_BL
Supports the Thumb instruction set for improved code density, ensuring efficient use of memory
NVIC unit to support interrupts and exceptions for rapid and deterministic interrupt response
Extensive debug support including:
o sWD port
o Breakpoints
o Watchpoints

Document No. 001-92738 Rev n 37

PSoC 4 BLE ArChitecture TRM,
PSoC 41XX BLE/42XX_BLE Family
 EM8EODED IN 19MORROW
Cortex-MO CPU

4.2 Block Diagram

Figure 4-1. PSoC 4 CPU
Subsystem Block Diagram

CPU Subsysterm
nterup
MUX

ARM Cortex-Mo CPU

DAP+
te
Contra

system Interconnect

FInsh
Flash SRAM SROM
Programming
Interfece Accelerator Controlle Controlle

CPU & Memory

Flash SRAM SROM
Subsystem

AHB Brldge

4.3 How It Works

and a 32-bit memory interface. It supports most
The Cortex-M0 is a 32-bit processor with a 32-bit data path, 32-bit registers,
16-bit instructions in the Thumb instruction set and some 32-bit instructions in the Thumb-2 instruction set

operating modes (see "Operating Modes" on page 40). It has a single-cycle 32-bit multiplication
The processor supports two
instruction.

4.4 Address Map

fixed address map allowing access to memory and peripherals using simple memory
access

The ARM Cortex-M0 has a in Table 4-1. Note that code can be executed
address space is divided into the regions shown
instructions. The 32-bit (4 GB)
from the code and SRAM
regions.

Table 4-1. Cortex-MO

Address Map
Use
Address
Range Name also place data here. Includes the exception vector table,
Program code region. You can
Code
Ox00000000-Ox1FFFFFFF which starts at address 0.
code from this region,
Ox20000000 0x3FFFFFFF SRAM | Data region. You can also execute
All peripheral registers. You cannot execute code from this region.
Ox40000000-Ox5FFFFFFF
Peripheral
Not used.
the CPU
Ox60000000-0xDFFFFFFF
within core.
PPB Peripheral registers
rew
PSOC 4 implementation-specific
OxEOO00000-OxE0OFFFFF

OxE0100000 OxFFFFFFFF Device

PSoc 4 BLE ArChitecture TRM, Document No. 001-92738 Rev. 'D

aSeC 41Xx BLE/42XX_BLE Family
38
CYPRESS ENPEDDED IN TOMORAOW"
Cortex-MO CPU

4.5
The
Registers
Cortex-MO has 16 32-bit
registers, as Table 4-2
O ato R12-General-purpose registers. RO to R7 shows
can be accessed by all instructions; the
by subset of the instructions. other registers can De ao
a c k pointer (SP). There are two stack pointers. with only one available at a time. In thread mode, the CONTROL
egister indicates the stack
pointer to use, Main Stack Pointer (MSP) or Process Stack Pointer (PSF).
R14-ink register. Stores the return
R15-Program counter. This register can be counterto during
function
program cails
written
control 1oW. program
Table 4-2. Cortex-M0
Registers
Name
Type Reset Value Description
RO-R12 RW L Undefined RO-R12 are 32-bit general-purpose registers for data operauons.
The stack pointer (SP) is register R13. In thread mode, bitl1] ofthe CONTROL register
indicates which stack pointerto use:
MSP (R13) RW
PSP (R13) [Ox0000000o 0 Main stack pointer (MSP). This is the reset value.
1
pointer (PSP).
Process stack
On reset, the processorloadsthe MSP with the valuefrom address Ox00000000.
LR(R14) RW Undefined The link register (LR) is register R14. It stores the return information for subroutines,
function calls, and exceptions.
The program counter (PC) is register R15. It contains the current program address. On
PC (R15) RW [OxO0O00004] reset, the processor loads the PC with the value from address 0x00000004. Bit0] ofthe
value is loadedinto the EPSR T-bit at reset and mustbe 1.
The program status register (PSR) combines:
PSR Application Program Status Register (APSR).
RW Undefined
Execution Program Status Register (EPSR).

Interrupt ProgramStatus Register (PSR).

APSR RW Undefined The APSR contains the current state ofthe condition flags from previous instruction
executions.
EPSR RO
[Ox000000041.0 On reset, EPSRisloadedwiththevalue bit0] of the register[0x00000004].
IPSR RO The IPSRcontains the exception number ofthe currentISR.
PRIMASK RW The PRIMASKregister prevents activation ofall exceptions with configurable priority.
CONTROL RW |The CONTROLregister controlsthe stack used when the processor is in thread mode.
a. Describes access type during program execution in thread mode and handier mode. Debug access can differ.

Table 4-3 shows how the PSR bits are assigned.

Table 4-3. Cortex-M0 PSR Bit Assignments

Bit PSR Register Name Usage

31 APSR Negative flag
30 APSR Zero flag
29 APSR Carry or borrow flag
APSR Overflow Tlag

4 BLE Architecture TRM, Document No. 001-92738 Rev. "D

PSOC 41XX BLE/42XX_BLE Family PSoC 39
 Cortex-M0 CPU
CYPREss EMBEOOED IN TGMORROW

Table 4-3. Cortex-MO PSR Bit

Bit
PSR Register Assignments
Name
27 255

24 Usage
EPSR Reserved
Th
23-6 numd state bit. Must
results in a HardFault always
be 1. Altempting to execute
instructions wnen ue

exception.
Reserved
Exception number of current ISR:
0 = thread mode
1 reserved
2= NMI
3 HardFault
5-0 IPSR 4-10 reserved
N/A 11 SVCall
12, 13 reserved
14 PendSV
15 SysTick
16 IRQO
47 IRQ31
Use the MSR or CPS
instruction to set or clear bit 0 of the
IS 1, all
exceptions with PRIMASK register. If the bit is 0,
configurable priority, that is, all exceptions except exceptions are enabled. if the Dit
Interrupts chapter on page 57 for a list of HardFault, NMI, and Reset, are disabled. See tne
exceptions.
4.6 Operating Modes
The Cortex-M0
processor supports two operating modes:
Thread Mode used by all normal
applications. In this mode, the MSP
-

determines which stack pointer is used: or PSP can be used. The CONTROL
register bit 1
o 0 MSP is the current stack
pointer
1 PSP is the
O
current stack pointer
Handler Mode used to execute
exception handlers. The MSP is always used.
In thread mode, the MSR instruction to set the stack
use
pointer bit in the CONTROL
pointer, use an ISB instruction immediately after the MSR instruction. This ensures that register. When changing the stack
using the new stack pointer. instructions after the IB execute

In handler mode, explicit writes to the CONTROL

register are ignored, because the MSP is always used. The
and return mechanisms automatically update the CONTROL
register.
exception entry

4.7 Instruction Set

The Cortex-M0 implements a version of the Thumb instruction set, Table 4-4 shows. For
Generic User Guide.
as
details, see the Cortex-MO
An instruction operand
can be an ARM register, a constant, or another
instruction-specific parameter. Instructions act on the
operands and often store the result in a destination register. Many instructions are unable
to use, or have restrictions
using, the PC or SP for the operands or destination register. on

40
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 CYPRESS
EMBEDGED IN TOMORROW"
Cortex-Mo CPU

Table 4-4. Thumb Table 4-4. Thumb Instruction Set

Instruction Set
Mnemonic Brief Description
Mnemonic Brief Description
SEV Send event
ADCS Add with carry
STM Store multiple registers,increment aftsr
ADDIS) Add
STR Store registerasword
ADR PC-relative address to register STRB | Store register as byte
|ANDS Bit wise AND Store register as half-word
ASRS
IRH

Arithmetic shift right SUB(S)° Subtract

BKoc Branch (conditionally) SVC Supervisor call
BICS Bit clear Sign extend byte
SXTB
BKPT Breakpoint Sign extend half-word
SXTH
BL Branch with link TST Logical AND-based test
BLX Branch indirect with link
|UXTB Zero extend a byte
BX Branch indirect UXTH Zero extend a half-word
CMN Compare negative WFE Wait for event
CMP
Compare WFI Wait for interrupt
update
CPSID Change processorstate, disable interupts a.
The 'S qualifier causes
APSR condition flags.
the ADD, SUB, or MOV instrucions to

CPSIE
Change processor state, enableînterrupts
DMB |Data memory barrier 4.7.1 Address Alignment
DSB Data synchronizatiorn barrier An aligned access is an operation where a word-aligned
EORS Exclusive OR address is used for a word or multiple word access,
or

ISB Instruction synchronization barrier where a half-word-aligned address is used for a half-word

LDM Load multipleregisters,increment after access. Byte accesses are always aligned.
Load register from PC-relative address
LDR No support is provided for unaligned accesses
on the Cor

tex-M0 processor. Any attempt to perfom an unaligned

DRB |Load register with word
operation results in a HardFault exception.
LDRH Load.register with half-word memory access

LDRSB Load registerwith signed byte Memory Endianness

4.7.2
LDRSH Load register with signed half-word where
|Logical shiftleft The PSoC4 Cortex-MO uses the little-endian format,
LSLS the least-significant byte of a word is stored at
the lowest
|Logical shiftright address and the most significant byte is stored at the high-
LSRS
Move est address.
MOVIS)
Move to general registerfrom special
register
MRS |Move to special registerfrom general
register 4.8 Systick Timer
MSR
Multiply, 32-bit result The Systick timer is integrated with the NVIC and generates
MULS
Bit wise NOT be used for task
MVNS the SYSTICK interrupt. This interrupt can
The timer has a reload
No operation management in a real-time system.
OP a countdown value
|Logical OR register with 24 bits available to use as
internal clock as a
ORRS The Systick timer uses the Cortex-MO
Pop registers from stack
POP onto stack
source.

PUSH | Push registers

Byte-reverseword
REV Byte-reverse packed half-words
4.9 Debug
REV16 Byte-reverse signed half-word
PSoC 4 contains a debug interface based
on SWD; it fea-

REVSH and two watch-

tures four breakpoint (address) comparators
Rotate right point (data) comparators.
RORS Reverse subtract

SBS
Subtract with carry

SBCS
41
Archtecture TRM, Document No. 001-92738 Rev. "D
PSoC 4 BLE
41Xxx
BLE/42XX_BLE Family
nSac
 IOT UINIT-4

DATA ACQUIRING AND STORAGE:

Following subsections describe devices data, and steps in acquiring and storing data for
an application, service or business process.

Data Generation:
 Data generates at devices that later on, transfers to the Internet through a gateway.
Data generates as follows:

 ● Passive devices data: Data generate at the device or system, following the result of
interactions. A passive device does not have its own power source. An external source
helps such a device to generate and send data. Examples are an RFID (Example 2.2) or
an ATM debit card (Example 2.3). The device may or may not have an associated
microcontroller, memory and transceiver. A contactless card is an example of the
former and a label or barcode is the example of the latter.

 Active devices data: Data generates at the device or system or following the result of
interactions. An active device has its own power source. Examples are active RFID,
streetlight sensor (Example 1.2) or wireless sensor node. An active device also has an
associated microcontroller, memory and transceiver.

 Event data: A device can generate data on an event only once. For example, on
detection of the traffic or on dark ambient conditions, which signals the event. The
event on darkness communicates a need for lighting up a group of streetlights (Example
1.2). A system consisting of security cameras can generate data on an event of security
breach or on detection of an intrusion. A waste container with associate circuit can
generate data in the event of getting it filled up 90% or above. The components and
devices in an automobile generate data of their performance and functioning. For
example, on wearing out of a brake lining, a play in steering wheel and reduced air-
conditioning is felt. The data communicates to the Internet. The communication takes
place as and when the automobile reaches near a Wi-Fi access point.

 Device real-time data: An ATM generates data and communicates it to the server
instantaneously through the Internet. This initiates and enables Online Transactions
Processing (OLTP) in real time.
  Event-driven device data: A device data can generate on an event only once. Examples
are: (i) a device receives command from Controller or Monitor, and then performs
action(s) using an actuator. When the action completes, then the device sends an
acknowledgement; (ii) When an application seeks the status of a device, then the device
communicates the status.

Data Acquisition:
Data acquisition means acquiring data from IoT or M2M devices. The data communicates after the
interactions with a data acquisition system (application). The application interacts and communicates
with a number of devices for acquiring the needed data. The devices send data on demand or at
programmed intervals. Data of devices communicate using the network, transport and security layers
(Figure 2.1). An application can configure the devices for the data when devices have configuration
capability. For example, the system can configure devices to send data at defined periodic intervals.
Each device configuration controls the frequency of data generation. For example, system can configure
an umbrella device to acquire weather data from the Internet weather service, once each working day in
a week (Example 1.1). An ACVM can be configured to communicate the sales data of machine and other
information, every hour. The ACVM system can be configured to communicate instantaneously in event
of fault or in case requirement of a specific chocolate flavour needs the Fill service

 Application can configure sending of data after filtering or enriching at the gateway at the data-
adaptation layer. The gateway in-between application and the devices can provision for one or
more of the following functions—transcoding, data management and device management. Data
management may be provisioning of the privacy and security, and data integration, compaction
and fusion (Section 2.3).

 Device-management software provisions for device ID or address, activation, configuring

(managing device parameters and settings), registering, deregistering, attaching, and detaching
(Section 2.3.2). Example 5.2 gives the process of acquiring data from the embedded component
devices in the automobiles for Automotive Components and Predictive Automotive
Maintenance System (ACPAMS) application.

 Data Validation:
 Data acquired from the devices does not mean that data are correct, meaningful or consistent.
Data consistency means within expected range data or as per pattern or data not corrupted
during transmission. Therefore, data needs validation checks. Data validation software do the
validation checks on the acquired data. Validation software applies logic, rules and semantic
annotations. The applications or services depend on valid data. Then only the analytics,
predictions, prescriptions, diagnosis and decisions can be acceptable

 Large magnitude of data is acquired from a large number of devices, especially, from machines
in industrial plants or embedded components data from large number of automobiles or health
 devices in ICUs or wireless sensor networks, and so on. Validation software, therefore,
consumes significant resources. An appropriate strategy needs to be adopted. For example, the
adopted strategy may be filtering out the invalid data at the gateway or at device itself or
controlling the frequency of acquiring or cyclically scheduling the set of devices in industrial
systems. Data enriches, aggregates, fuses or compacts at the adaptation layer.

 Data Categorisation for Storage:

 Data from large number of devices and sources categorises into a fourth category called
Big data. Data is stored in databases at a server or in a data warehouse or on a Cloud as
Big data.

 Assembly Software for the Events A device can generate events. For example, a sensor
can generate an event when temperature reaches a preset value or falls below a
threshold. A pressure sensor in a boiler generates an event when pressure exceeds a
critical value which warrants attention.

 Each event can be assigned an ID. A logic value sets or resets for an event state. Logic 1
refers to an event generated but not yet acted upon. Logic 0 refers to an event generated
and acted upon or not yet generated. A software component in applications can assemble
the events (logic value, event ID and device ID) and can also add Date time stamp. Events
from IoTs and logic-flows assemble using software.

 Data Store:
 A data store is a data repository of a set of objects which integrate into the store. Features
of data store are: ● Objects in a data-store are modeled using Classes which are defined by
the database schemas. ● A data store is a general concept. It includes data repositories such
as database, relational database, flat file, spreadsheet, mail server, web server, directory
services and VMware ● A data store may be distributed over multiple nodes. Apache
Cassandra is an example of distributed data store.

 A data store may consist of multiple schemas or may consist of data in only one scheme.
Example of only one scheme data store is a relational database. Repository in English means
a group, which can be related upon to look for required things, for special information or
knowledge

 For example, a repository of paintings of artists. A database is a repository of data which

can be relied upon for reporting, analytics, process, knowledge discovery and intelligence.
 A flat file is another repository. Flat file means a file in which the records have no structural
interrelationship (Section 5.3). Section 5.5.1 explains the spreadsheet concept. VMware
uses data store to refer to a file that stores a virtual machine

 Data Centre Management:

 A data centre is a facility which has multiple banks of computers, servers, large memory
systems, high speed network and Internet connectivity. The centre provides data security
and protection using advanced tools, full data backups along with data recovery, redundant
data communication connections and full system power as well as electricity supply
backups.

 Large industrial units, banks, railways, airlines and units for whom data are the critical
components use the services of data centres. Data centres also possess a dust free, heating,
ventilation and air conditioning (HVAC), cooling, humidification and dehumidification
equipment, pressurisation system with a physically highly secure environment.

 The manager of data centre is responsible for all technical and IT issues, operations of
computers and servers, data entries, data security, data quality control, network quality
control and the management of the services and applications used for data processing

 Server Management:
 Server management means managing services, setup and maintenance of systems of all
types associated with the server.

 A server needs to serve around the clock. Server management includes managing the
following:

 ● Short reaction times when the system or network is down

 ● High security standards by routinely performing system maintenance and updation

 ● Periodic system updates for state-of-the art setups ● Optimised performance

 ● Monitoring of all critical services, with SMS and email notifications

 ● Security of systems and protection

 ● Maintaining confidentiality and privacy of data

 ● High degree of security and integrity and effective protection of data, files and
databases at the organisation

 ● Protection of customer data or enterprise internal documents by attackers which

includes spam mails, unauthorised use of the access to the server, viruses, malwares and
worms

 ● Strict documentation and audit of all activities

 Spatial Storage:
 Consider goods with RFID tags. When goods move from one place to another, the IDs of
goods as well as locations are needed in tracking or inventory control applications. Spatial
storage is storage as spatial database which is optimised to store and later on receives
queries from the applications. Suppose a digital map is required for parking slots in a city.
Spatial data refers to data which represents objects defined in a geometric space. Points,
lines and polygons are common geometric objects which can be represented in spatial
databases. Spatial database can also represent database for 3D objects, topological
coverage, linear networks, triangular irregular networks and other complex structures.
Additional functionality in spatial databases enables efficient processing

 Internet communication by RFIDs, ATMs, vehicles, ambulances, traffic lights, streetlights,

waste containers are examples of where spatial database are used.

 Spatial database functions optimally for spatial queries. A spatial database can perform
typical SQL queries, such as select statements and performs a wide variety of spatial
operations. Spatial database has the following features:

 ● Can perform geometry constructors. For example, creating new geometries

 ● Can define a shape using the vertices (points or nodes)

 ● Can perform observer functions using queries which replies specific spatial information
such as location of the centre of a geometric object Can perform spatial measurements
which mean computing distance between geometries, lengths of lines, areas of polygons
and other parameters

 Can change the existing features to new ones using spatial functions and can predicate
spatial relationships between geometries using true or false type queries
 Can perform spatial measurements which mean computing distance between geometries,
lengths of lines, areas of polygons and other parameters

 ● Can change the existing features to new ones using spatial functions and can predicate
spatial relationships between geometries using true or false type queries

Cloud Computing Features and Advantages:

 Essential features of cloud storage and computing are:

 ● On demand self-service to users for the provision of storage, computing servers,

software delivery and server time

 ● Resource pooling in multi-tenant model

 ● Broad network accessibility in virtualised environment to heterogeneous users,

clients, systems and devices

 ● Elasticity

 ● Massive scale availability

 ● Scalability

 ● Maintainability

 ● Homogeneity

● Virtualisation

 Cloud Computing Concerns:

 Concerns in usage of cloud computing are:

 ● Requirement of a constant high-speed Internet connection

 Limitations of the services available

 ● Possible data loss

 ● Non delivery as per defined SLA specified performance

 ● Different APIs and protocols used at different clouds

 ● Security in multi-tenant environment needs high trust and low risks

 ● Loss of users’ control

Cloud Deployment Models:

 Following are the four cloud deployment models: 1. Public cloud: This model is
provisioned by educational institutions, industries, government institutions or
businesses or enterprises and is open for public use.

 2. Private cloud: This model is exclusive for use by institutions, industries, businesses or
enterprises and is meant for private use in the organisation by the employees and
associated users only.

 3. Community cloud: This model is exclusive for use by a community formed by

institutions, industries, businesses or enterprises, and for use within the community
organisation, employees and associated users. The community specifies security and
compliance considerations

 4. Hybrid cloud: A set of two or more distinct clouds (public, private or community) with
distinct data stores and applications that bind between them to deploy the proprietary
or standard technology.

 Cloud platform architecture is a virtualised network architecture consisting of a cluster

of connected servers over the data centres and Service Level Agreements (SLAs)
between them.

 A cloud platform controls and manages resources, and dynamically provisions the
networks, servers and storage. Cloud platform applications and network services are
utility, grid and distributed services. Examples of cloud platforms are Amazon EC2,
Microsoft Azure, Google App Engine, Xively, Nimbits, AWS IoT, CISCO IoT, IOx and Fog,
IBM IoT Foundation, TCS Connected Universe Platform.

EVERYTHING AS A SERVICE AND CLOUD SERVICE MODELS:

 Cloud connects the devices, data, applications, services, persons and business. Cloud
services can be considered as distribution service—a service for linking the resources
(computing functions, data store, processing functions, networks, servers and
applications) and for provision of coordinating between the resources.

 Figure 6.2 shows four cloud service models and examples. Cloud computing can be
considered by a simple equation: Cloud Computing = SaaS + Paas + IaaS + DaaS … 6.2
 SaaS means Software as a Service. The software is made available to an application or
service on demand. SaaS is a service model where the applications or services deploy
and host at the cloud, and are made available through the Internet on demand by the
service user. The software control, maintenance, updation to new version and
infrastructure, platform and resource requirements are the responsibilities of the cloud
service provider.

 PaaS means Platform as a Service. The platform is made available to a developer of an

application on demand. PaaS is a service model where the applications and services
develop and execute using the platform (for computing, data store and distribution
services) which is made available through the Internet on demand for the developer of
the applications. The platform, network, resources, maintenance, updation and security
as per the developers’ requirements are the responsibilities of the cloud service
provider.

 IaaS means Infrastructure as a Service. The infrastructure (data stores, servers, data
centres and network) is made available to a user or developer of application on
demand. Developer

installs the OS image, data store and application and controls them at the infrastructure.
IaaS is a service model where the applications develop or use the infrastructure which is
made available through the Internet on demand on rent (pay as per use in multi-tenancy
model) by a developer or user. IaaS computing systems, network and security are the
responsibilities of the cloud service provider. DaaS means Data as a Service

 Data at a data centre is made available to a user or developer of application on demand.

DaaS is a service model where the data store or data warehouse is made available
through the Internet on demand on rent (pay as per use in multi tenancy model) to an
enterprise. The data centre management, 24×7 power, control, network, maintenance,
scale up, data replicating and mirror nodes and systems as well as physical security are
the responsibilities of the data centre service provider.

 Data at a data centre is made available to a user or developer of application on demand.

DaaS is a service model where the data store or data warehouse is made available
through the Internet on demand on rent (pay as per use in multi tenancy model) to an
enterprise. The data centre management, 24×7 power, control, network, maintenance,
scale up, data replicating and mirror nodes and systems as well as physical security are
the responsibilities of the data centre service provider.