2118 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 65, NO.

7, JULY 2018

A 2.1-GHz Third-Order Cascaded PLL With

Sub-Sampling DLL and Clock-Skew-
Sampling Phase Detector
Zhiqiang Huang , Bingwei Jiang, and Howard C. Luong, Fellow, IEEE

Abstract— A high-order cascaded phase-locked loop (PLL)

architecture using a sub-sampling delay-locked loop (DLL) is pro-
posed to break the tradeoff between the loop bandwidth and the
number of integrator in the feedback loop without significantly
degrading the settling time or reference spur. A clock-skew-
sampling phase detector is also proposed to extend the stable
detection range of the sub-sampling phase detector. Implemented
in a 65-nm CMOS process, a prototype of the proposed two-
stage third-order cascaded PLL measures a 4.2-µs settling time,
1.05-ps integrated jitter, and −113-dBc/Hz in-band phase noise at
a 2.1-GHz output frequency while consuming 3.84 mW at 1.2-V
supply voltage and occupying a core chip area of 0.043 mm2 . Fig. 1. PLL’s optimal loop bandwidth for minimum integrated jitter.
Index Terms— Inductor-less, cascaded PLL, sub-sampling
DLL, ring oscillation, clock-skew-sampling, and phase detector.
they intrinsically have a sample-and-hold operation and loop
I. I NTRODUCTION delay, which introduce a large phase shift at high frequencies
and degrade the stability [3]. Even worse, the RO tends to
A S ONE of the critical components in almost all commu-
nication systems, a stable frequency synthesizer with low
jitter and phase noise is highly desired. Moreover, a compact
have very large frequency drift and is very sensitive to supply
noise since the delay of the inverter cells highly depends on
frequency synthesizer would save chip area and allow more the supply voltage and temperature. In system-on-chip design,
complex systems to be integrated [1], [2]. LC-oscillator-based the noises from supply, substrate and temperature variation,
phase-locked loops (LC-PLLs) can achieve good phase noise etc., can modulate the VCO’s oscillation frequency and are
because their relatively narrow-band LC tanks help suppress transferred into phase noise and frequency drift at VCO’s
the noise. However, the required inductors occupy a large chip output. Because the frequency drift is proportional to the
area, especially in the low frequency range of a few GHz and derivative of phase noise at low offset frequency over time,
below. the suppression of phase noise is equivalent to suppress the
By eliminating the inductors, ring-oscillator-based PLLs frequency drift. In order to realize a compact PLL using a RO
(RO-PLLs) are much more suitable than LC-PLLs to realize while still achieving high performance in terms of integrated
compact frequency synthesizers. However, with noisy delay jitter, supply-noise induced phase noise, etc., the PLL should
cells in the RO and without a high-Q tank to filter out be able to support a wide optimal loop bandwidth to achieve
noise, such RO-PLLs suffer from poor phase noise. Moreover, minimum jitter and a large loop gain to suppress the frequency
as shown in Fig. 1, RO-PLLs need a much larger optimal drift and phase noise introduced by noise sources, such as
loop bandwidth BWopt,Ring for minimum integrated jitter, supply noise.
which is the offset frequency at which the in-band phase Existing PLL architectures can be classified into different
noise is equal to the oscillator phase noise. Unfortunately, types based on the number of integrators in the feedback
PLLs usually cannot provide a wide loop bandwidth because loop [4]–[6]. As shown in Fig. 2(a), a Type-I PLL consists
of a voltage-controlled oscillator (VCO) as an integrator and
Manuscript received August 15, 2017; revised October 12, 2017 and an RC low-pass filter. Because there is only one integrator
November 10, 2017; accepted November 28, 2017. Date of publication
December 29, 2017; date of current version May 29, 2018. This work that introduces a phase shift of 90°, the feedback loop will
was supported by the Hong Kong General Research Funding under Grant have a large phase margin to tolerate the phase shift of the
16243116. This paper was recommended by Associate Editor A. Worapishet. sample-and-hold and to support a wide loop bandwidth up to
(Corresponding author: Zhiqiang Huang.)
The authors are with the Department of Electronic and Computer Engi- half the reference frequency, which in turn results in minimum
neering, The Hong Kong University of Science and Technology, Hong Kong jitter and fast settling time. On the other hand, one integrator
(e-mail: zhuangah@ust.hk, eeluong@ust.hk). can only provide a loop gain of 20 dB/decade, which is not
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org. enough to achieve sufficient suppression of frequency drift and
Digital Object Identifier 10.1109/TCSI.2017.2779514 supply-noise induced phase noise.
1549-8328 © 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
HUANG et al.: 2.1-GHz THIRD-ORDER CASCADED PLL 2119

Fig. 3. (a) Injection-locked PLL architecture, and (b) timing diagram of

injection-locking.
Fig. 2. PLL architecture: (a) Type-I PLL, (b) Type-II PLL, and
(c) Type-III PLL.
and requires a smaller frequency multiplication ratio with
smaller injection strength to reduce the reference spur. Another
problem is that the two parallel phase-locking mechanisms,
By adding one or two more integrators to the loop filter,
namely injection locking and feedback-loop locking, will tend
a Type-II or Type-III PLL is formed, as shown in Fig. 2(b) and
to “fight” with each other during the locking state [8], and
Fig. 2(c), with a loop gain of 40 or 60 dB/decade, respectively,
to lock the oscillator output at different output phases in the
to achieve smaller frequency drift and better supply-noise
presence of mismatches, which will potentially slow down the
sensitivity. However, with two or more integrators in the
settling time.
loop, the phase margin becomes much smaller. Because the
In order to break the trade-off between loop bandwidth
intrinsic sample-and-hold operation has a smaller phase shift at
and number of the loop order without significantly degrading
a lower frequency, the loop bandwidth needs to be reduced to
performance in terms of settling time or reference spur, this
guarantee a sufficient phase-margin, which unfortunately slows
work introduces a cascaded PLL architecture with a sub-
down the settling time. In practice, the PLL’s loop bandwidth
sampling DLL. A clock-skew-sampling phase detector is also
is limited to fref /10 because of stability consideration, where
proposed to extend the stable detection range of the sub-
fref is reference frequency. As we can see, there is a trade-
sampling phase detector. Significantly expanding on our previ-
off between loop bandwidth and number of integrators in the
ous work [10], this paper presents more analysis, more detailed
feedback loop.
circuit implementation, and more measurement results.
The injection-locked PLL (IL-PLL), or multiplying delay-
The paper is organized as follows. Section II describes the
locked loop (MDLL), is another PLL architecture to achieve
cascaded PLL with sub-sampling DLL. Section III analyzes
wide loop bandwidth [7]–[9]. As shown in Fig. 3(a), in an
the clock-skew-sampling phase detector and compares it with
IL-PLL, a clean reference input followed by a pulse generator
a traditional sub-sampling phase detector. Section IV presents
is injected into the oscillator, and the PLL output phase is
a two-stage cascaded PLL design with detailed circuit imple-
realigned to the reference input. Because of injection-locking
mentation. Section V discusses the measurement setup and
without phase detector and charge pump, the IL-PLL/MDLL
results. Finally, conclusions are drawn in Section VI.
exhibits better in-band phase noise and thus lower integrated
jitter than feedback-loop based PLL. As shown in Fig. 3(b), the
output phase error θe of the injection-locked oscillator (ILO) II. P ROPOSED C ASCADED PLL A RCHITECTURE
is corrected by β ∗ θe through injection, where β is the W ITH S UB -S AMPLING DLL
phase error correction strength, and the residual phase error As described in Section I, existing PLL architectures employ
accumulates in the following cycles. Consequently, the ILO a single feedback loop. For a single third-order feedback
effectively forms a first-order feedback loop and provides first- loop system with phase shift θ1 , θ2 and θ3 for each stage,
order high-pass filtering for the oscillator’s output phase noise, as shown in Fig. 4(a), the total phase shift accumulated in the
while the transfer function from the reference phase noise to loop becomes θ1 + θ2 + θ3 , leaving a small phase margin.
the output is a first-order low-pass response. With the first- As the purpose of a PLL is to suppress the phase noise
order operation, the injection-locking can provide wideband of the VCO and force the output phase ϕout to synchronize
high-pass rejection for the VCO’s phase noise. However, with with the reference input phase ϕin , the single high-order
a first-order high-pass filter at the oscillator output, the PLL’s feedback loop can be broken into two low-order feedback
loop order is reduced by one, and the loop gain is reduced loops to provide the same order of phase noise suppression
accordingly. for the VCO, as shown in Fig. 4(b). The first loop is a
Along with the ILO’s first-order operation, the IL-PLL conventional feedback loop with a phase shift of θ1 + θ2
has the same order of phase-noise rejection as a regular and phase error ϕ1 = ϕout1 - ϕin , while the second loop
PLL. However, it needs a pulse generator to enhance and with phase shift θ3 is used to cancel the phase error ϕ1 to
directly inject the harmonic tones into the oscillator, which minimize the output phase error ϕout = ϕout - ϕin , resulting
will significantly degrade the PLL’s output reference spur in a high-order system. Compared with a single high-order
2120 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 65, NO. 7, JULY 2018

Fig. 4. (a) Single high-order feedback loop, and (b) cascaded high-order
feedback loop.

feedback loop, the cascaded high-order feedback loop has

Fig. 5. Block diagrams of (a) sub-sampling DLL, (b) cascaded PLL, and
a smaller phase shift in each feedback loop and is more (c) multi-stage cascaded PLL.
stable.

with another sub-sampling DLL for even more phase-noise

A. Sub-Sampling Delay-Locked Loop (DLL)
suppression, as shown in Fig. 5(c). In this way, it becomes an
In order to realize the second loop to cancel the resid- m-stage cascaded PLL consisting of one integer-N PLL as the
ual phase error from the first loop, a sub-sampling DLL first stage, followed by (m-1) sub-sampling DLLs. Compared
is proposed, as shown in Fig. 5(a). The sub-sampling DLL with the conventional PLLs, the order of the m-stage cascaded
consists of a high-frequency noisy source ϕn1 to drive a PLL is increased by (m-1), which helps increase phase-
voltage-controlled delay line (VCDL) and a sub-sampling noise rejection without degrading the phase margin and loop
phase detector (PD) to detect the residual phase error ϕe at bandwidth
the input of the PD. The phase error is fed back through a
first-order loop filter to control and adjust the VCDL delay to
suppress the phase noise of the noisy input source. As such, C. Noise Transfer Function
the sub-sampling DLL becomes a first-order feedback loop and A phase-domain noise model with loop gain G(s) for
the phase transfer function from the noise source ϕn1 to the the sub-sampling DLL is shown in Fig. 6(a), where Kd is
output ϕn2 exhibits a high-pass response, while that from the the PD gain, KVCDL is the VCDL control gain, and HLF (s)
reference input ϕref to the output ϕn2 is a low-pass function. is the transfer function of the loop filter. The noise transfer
This architecture is similar to a Type-II DLL [11], which is function from the VCDL noise ϕVCDL and input phase noise
widely used in source-synchronous wire-line communication ϕn1 to the sub-sampling DLL output phase ϕn2 is
systems to recover the input clock. Because the sub-sampling ϕn2 ϕn2 1 1
DLL is a first-order feedback loop with a large phase margin, = = = . (1)
ϕn1 ϕVCDL 1 + G(s) 1 + KVCDL Kd HLF (s)
it is capable of rejecting the phase noise of a noisy input
source over a wide frequency range, as in IL-PLLs [8] and Exhibiting a high-pass response, the VCDL noise and input
Type-I PLLs [4]. By using the high-gain phase detection of phase noise at low frequency offset are suppressed before
the sub-sampling PD to suppress charge-pump noise [12], [13], propagating to the next stage. With suppressed output phase
the sub-sampling DLL is expected to have good in-band phase noise, the delay range of the VCDL at the next stage of
noise. Because the VCDL is used to cancel the phase noise of multi-stage cascaded PLL can be reduced, resulting in an
noisy source ϕn1 , the tuning range of VCDL has to be larger insignificant effect on the out-band phase noise of the cascaded
than the phase variation range of noisy source ϕn1 to ensure PLL with more stages of the sub-sampling DLL.
proper locking. Because of the sub-sampling operation, the output phase
noise ϕn2 at high frequency offset from the VCDL noise
ϕVCDL and input phase noise ϕn1 is down-converted between
B. Cascaded PLL Architecture −0.5fref and 0.5fref and introduces folded noise ϕsub. For
For the sub-sampling DLL to be locked with a small phase the VCO, the phase noise at high frequency offset is much
error, the frequency of the noisy input source should be lower than at low frequency offset, which introduces minor
an integral multiple of the reference frequency. As a result, folded noise. But for VCDL, the wide-band phase noise
the cascaded PLL uses an integer-N PLL as a noisy input introduces folded noise 10log10(N−1) dB higher than ϕVCDL ,
source and is cascaded with a first-order sub-sampling DLL where N is the frequency division ratio. Fortunately, the delay
to provide wideband high-pass phase-noise rejection to the line phase noise is much lower than the VCO phase noise [14],
output of the integer-N PLL, as shown in Fig. 5(b). With the which introduces negligible folded noise and allows using
output frequency of the cascaded PLL still being an integral a low-power VCDL. Similar to the reference phase noise
multiple of the reference frequency, it can be further cascaded ϕn,ref , and charge-pump/PD noise Vn,CP + Vn,PD , the folded
HUANG et al.: 2.1-GHz THIRD-ORDER CASCADED PLL 2121

Fig. 7. (a) Sub-sampling phase detector, and (b) clock-skew-sampling phase

Fig. 6. Phase-domain model for (a) sub-sampling DLL, and detector.
(b) cascaded PLL.

be written as
noise ϕsub also affects the in-band phase noise and exhibits a
ϕnm N · Gm (s)
low-pass transfer function: =
ϕn,ref 1 + Gm (s)
ϕn2 ϕn2 ϕn2 ϕn2 
k=m−1
= = = N · Gk (s)
Vn,PD Vn,CP Nϕn,ref ϕsub +
Kd Kd [1 + Gk (s)] · · · [1 + Gm (s)]
k=1
G(s) KVCDL Kd HLF (s) N·Gm (s)
= = (2) ≈ . (4)
1 + G(s) 1 + KVCDL Kd HLF (s) 1 + Gm (s)

As for the charge-pump noise Vn,CP and phase detector As long as the last stage has larger bandwidth than the previous
noise Vn,PD , including supply-noise induced noise, they can stages, the reference phase noise to the output is always
be greatly suppressed with a high phase detection gain Kd , a first-order low-pass filtering, even with more cascaded
when referred to the sub-sampling DLL output. stages.
Fig. 6(b) shows the noise model of the cascaded PLL with The folded noises from previous stages are also first
Gm (s) as the loop gain of the mth stage. The VCO phase low-pass filtered and then high-pass rejected by the last
noise ϕVCO is first high-pass rejected by the conventional PLL stage, resulting in negligible output phase noise at any fre-
and then further high-pass rejected by each additional stage of quency offset. Then the overall folded noise is dominated
the sub-sampling DLLs with a transfer function to the output by the last stage ϕsubm, with the low-pass transfer function
phase noise ϕnm given by shown in (2).

ϕnm 
k=m
1
= . (3) III. P ROPOSED C LOCK -S KEW-S AMPLING
ϕVCO 1 + Gk (s) P HASE D ETECTOR
k=1

A. Conventional Sub-Sampling Phase Detector

With the high-order high-pass transfer function, the phase
noise and frequency drift are highly suppressed before trans- As shown in Fig. 7(a), the conventional sub-sampling PD
ferring to output ϕnm . Same to the VCO’s phase noise, detects the output phase by sampling the VCO output using
the VCDL noises, including supply-noise induced phase noise a MOSFET switch, and the phase error is converted into a
of VCDL, are also suppressed by the following stages of sub- sampled voltage Vsamp to control the charge pump’s current.
sampling DLLs with high-order high pass response. Besides, The PLL can work correctly with a phase error between
the VCDL has smaller supply-noise sensitivity and control ±0.25 TVCO , where TVCO is the VCO period. Outside this
gain than VCO, which makes it contribute minor supply-noise range, the phase detection gain becomes negative, converting
induced phase noise. the negative feedback loop to a positive feedback loop and
For the reference phase noise, there are two main paths to making the PLL unstable. In addition, because the phase
the output. One path is first low-pass filtered by the previous detection gain depends on the oscillation amplitude, AVCO ,
stages and then high-pass rejected by the last stage, while the which is limited by the supply voltage, the sub-sampling
another path is directly low-pass filtered through the last stage. detection gain is limited, which in turns limits the suppression
Consequently, the reference phase noise transfer function can of the charge pump’s input referred noise.
2122 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 65, NO. 7, JULY 2018

Fig. 8. Linear detection range with input jitter distribution.

B. Proposed Clock-Skew-Sampling Phase Detector

To boost the detection gain and extend the stable detection Fig. 9. Block diagram of two-stage cascaded PLL.
range, a clock-skew-sampling technique is proposed, as shown
in Fig. 7(b). Instead of directly sampling the VCDL output,
a re-timer is added to re-time the frequency divider output DIV as shown in Fig.8. However, when the input jitter is out of this
from the first stage by the rising edges of the VCDL output, range, the detection output only has two values and behaves
and the output of the re-timer DIVRE is then sampled. As a as a bang-bang PD, which introduces quantization noise [15]
result, the stable detection range is extended from ±0.25 TVCO and degrades in-band phase noise. In order to guarantee linear
to ±0.5Tref , where Tref is the reference period. For the same operation, the input rise time Tr should be larger than the
slew rate SR of the VCO and DIVRE , the clock-skew-sampling input peak-to-peak jitter. To ensure proper rise time, variable
and the sub-sampling have the same phase-to-voltage detection sampling capacitor and time amplifier can be used to adjust
gain: the rise time and input phase error.
Vsamp Vsamp TVCO
GPD = = tin = 2π SR. (5)
ϕVCO 2π TVCO IV. C IRCUIT I MPLEMENTATION OF THE P ROPOSED
T WO -S TAGE C ASCADED PLL
where ϕVCO is the VCO output phase.
Compared with the sub-sampling PD, the clock-skew- A. System Architecture
sampling PD can achieve a higher phase-detection gain by Fig. 9 shows the block diagram of the proposed two-stage
reducing the rise time to increase the slew rate SR instead of cascaded PLL with clock-skew-sampling PD. It consists of
using a higher supply voltage. To further enhance the phase- an integer-N Type-II PLL for frequency acquisition and phase
detection gain, a time amplifier [16] can be used to amplify locking and a cascaded clock-skew-sampling DLL to provide
the input phase error before being detected by the clock-skew- third-order phase locking. The first-stage Type-II PLL consists
sampling PD. With a 120-ps rise time and a time-amplifier gain of an RO operating from 1.1 GHz to 2.1 GHz and a frequency
of 5 at a 1.2-V supply, the phase-detection gain of the proposed divider with a division ratio from 16 to 31, and is locked to
time-amplified clock-skew-sampling PD becomes equivalent a reference frequency of 67.74 MHz by a phase-frequency
to that of sub-sampling with a VCO amplitude of 4 V at detector (PFD), a charge pump (CP), and a first-order loop
2.1 GHz. Moreover, since the input phase error is amplified filter. Because of a low loop gain and a narrow loop bandwidth
before being sampled, the input referred sampling noise can for rejecting the RO phase noise, the first-stage Type-II PLL
also be reduced. The noise of the clock-skew-sampling PD is has high output phase noise.
also caused by the sampling noise. With a sampling capacitor By cascading the first-stage Type-II PLL with a wideband
C and reference frequency fref , the PLL’s in-band phase noise first-order clock-skew-sampling DLL , the proposed cascaded
due to the PD is given by PLL provides a wideband third-order phase noise rejection
kT to the first-stage PLL output. Instead of using a conventional
ζin−band = . (6) sub-sampling PD, the proposed clock-skew-sampling DLL
C · fre f · G 2P D
employs a clock-skew-sampling PD, which consists of a
Compared with the sub-sampling PD with sinusoidal trans- VCDL with a gain of 100 ps/V, a clock-skew-sampler with a
fer function which can only be approximated as linear within a re-timer to convert the VCDL output phase error into voltage,
narrow range around the zero-crossing point, the clock-skew- and a CP followed by a capacitor as a loop filter to integrate
sampling PD can provide a linear transfer function as long the phase error and adjust the VCDL delay.
as the charging/discharging current to sampling capacitor C
is constant. With a high output-impedance current source as
buffer to drive the clock-skew-sampling PD, a wide linear B. VCO
detection range can be maintained. The clock-skew-sampling The VCO is designed as a three-stage differential inverter-
detector is linear when the input jitter is within the rise time, based ring oscillator, as shown in Fig.10. Instead of using a
HUANG et al.: 2.1-GHz THIRD-ORDER CASCADED PLL 2123

Fig. 10. Schematic of VCO.

starved-inverter topology with current tail to tune the oscilla-

tion frequency, which contributes more noise and causes phase
Fig. 11. Schematic of VCDL.
noise degradation for a lower tail current, the implemented
VCO employs a 5-fF varactor for PLL fine tuning and a 60-fF
switched capacitor array for coarse tuning. In order to achieve
oscillation frequency around 2-GHz, the inverter cells use a
4-um/0.13-um PMOS and 2-um/0.13-um NMOS instead of
using minimum gate length. The 2.1-GHz VCO exhibits a
phase noise of −116 dBc/Hz at 10-MHz offset with 1.2-V
supply.

C. Voltage Controlled Delay Line (VCDL)

In order to ensure that the two-stage cascaded PLL can
be locked correctly, the output phase range of the first-stage
Type-II PLL should be within the input range of the clock- Fig. 12. Time diagram of two-stage cascaded PLL: (a) without delay td
(b) with delay td .
skew-sampling DLL, which is the tuning range of the VCDL.
The output phase of the first stage not only includes the phase
noise, but also the static phase shift. Fortunately, the static ϕn1 and is not able to synchronize with the reference input.
phase shift can be calibrated with the delay line, as will be In order to make the clock-skew-sampling DLL lock correctly,
discussed in subsection D. Assuming the output peak-to-peak a delay line td is inserted at the output of the frequency
jitter of the first stage is around 50 ps, the delay range of the divider, as shown in Fig.9. In this case, the output of the
VCDL is designed as 100 ps to cover the output jitter range Type-II PLL becomes earlier than the reference input with
of the first stage with enough margin. As depicted in Fig.11, time shift td , as depicted in Fig. 12(b). Then the clock-skew-
the VCDL consists of a 4-stage differential delay cell with sampling DLL will tune the delay of the VCDL tVCDL to be
an inverter loaded by a varactor to tune the delay and a td and force the output ϕn2 to synchronize with the reference
cross-coupled inverter buffer to prevent amplitude degradation. input REF. As we can see, the static delay td sets the DC
Because the delay line has much lower phase noise than control voltage of the VCDL. By using a time delay value
a VCO, a smaller size can be used to lower the power td at the middle of the VCDL’s delay range, the DC control
consumption. The input inverter cells inv1,2 consist of a voltage will be around half of the supply voltage to maximize
0.4-um//0.2-um PMOS and 0.2-um/0.2-um NMOS, while the the dynamic range. Because the frequency divider has different
output inverter cell inv3∼6 has a shorter gate length to boost delays with different division ratios, the output phase of the
the gain with a 0.4um-/0.06-um PMOS and 0.2-um/0.06-um Type-II PLL is also changed, and the delay range requirement
NMOS. With a 2-fF varactor and control voltage VC tuned of the VCDL should also be increased. In order to avoid delay
from 0.1 V to 1.1 V, the delay of the VCDL is tuned from variation, a re-timer is used at the frequency divider output to
330 ps to 430 ps. The simulated phase noise of the VCDL synchronize the re-timed frequency divider output with the
is −145 dBc/Hz at 2.1 GHz, which sets the limit for the Type-II PLL output. For multi-stage cascaded PLL with more
noise floor of the cascaded PLL. With a division ratio of 31, clock-skew-sampling DLLs, more delay lines should be added
the folded noise becomes −130 dBc/Hz, which is below the in the feedback paths of previous stages to adjust the output
in-band phase noise of the cascaded PLL. phases of previous stages earlier than reference input REF
and make the output of last stage clock-skew-sampling DLL
D. Static Delay Compensation synchronized with reference input.
Normally the output of a Type-II PLL ϕn1 is forced to
synchronize with the reference input REF at the same rising E. Clock-Skew Sampling PD and Charge Pump
edge, as shown in Fig. 12(a). However, with the non-zero delay Fig. 13 shows the schematic of the clock-skew sampler
of the VCDL, the output of the clock-skew-sampling DLL ϕn2 and CP, which are similar to the conventional sub-sampling
at the second stage has a time shift tVCDL with respect to PLL [12], [13]. A buffer is used at the input of the clock-
2124 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 65, NO. 7, JULY 2018

Fig. 13. Schematic of clock-skew sampler and charge pump.

Fig. 15. Measured phase noise at the output of the first-stage Type-II PLL
and of the two-stage cascaded PLL and simulated phase noise at second stage
output.

Fig. 14. Die micrograph of the proposed two-stage cascaded PLL. Fig. 16. VCO’s supply noise rejection measurement result.

skew sampler to avoid slew rate degradation caused by the

sampling capacitor. Because the threshold voltage of sampling
switch Msw limits the output Vsamp below the supply voltage,
a low-threshold-voltage NMOS is used to maximize the output
swing. Besides this, the input differential pair of the CP should
adopt a PMOS transistor to match the output range of the
sampled voltage Vsamp . The CP control pulse Pul is generated
by the reference input with the delay line and AND gate
to achieve a non-overlapping pulse and forms a master-slave
sampler with clock-skew sampler. To avoid the input range
saturation of the clock-skew sampler, the rise time is designed
as 50 ps, which is larger than the peak-to-peak jitter of 13 ps at
the cascaded PLL output with a time amplifier gain of 3. With
a slew rate of 1 V/50 ps, a time amplifier gain of 3, 67.74-MHz
reference and 33-fF sampling capacitor C, the clock- skew- Fig. 17. In-band phase noise of the proposed cascaded PLL versus the charge
pump current.
sampling PD contributes a negligible in-band phase noise
of −160dBc/Hz.
PLL and of the cascaded PLL with reference frequency
of 67.74 MHz and −3-dB bandwidths of 10 MHz and 40MHz.
V. E XPERIMENTAL R ESULTS With the 10-MHz-bandwidth configuration for minimum jitter,
The proposed cascaded PLL is fabricated in a 65-nm the cascaded PLL measures phase noise at a 1-MHz offset
CMOS process and consumes 3.84 mW from a supply voltage of −108.3 dBc/Hz and integrated jitter from 1 KHz to
of 1.2 V. Fig. 14 shows the die micrograph, which occupies 50 MHz of 1.05 ps (as compared to −93.3 dBc/Hz and
a 0.043 mm2 area. The clock-skew-sampling DLL occupies 3.67 ps at the output of the first stage). With the 40-MHz
0.01 mm2 and consumes 0.96 mW power, which are only bandwidth configuration for minimum in-band phase noise,
1/4 of the total core chip area and 1/4 of the total power the in-band phase noise at 100-KHz offset at the output of
consumption. the cascaded PLL is improved by 24 dB to −112.6 dBc/Hz
In order to demonstrate the phase-noise rejection capa- from −88.6 dBc/Hz at the first-stage output. From the phase
bility of the clock-skew-sampling DLL, Fig. 15 shows the noise spectrum, the −3-dB bandwidth can reach 40 MHz, even
measured output phase noise spectra of the first-stage Type-II with a reference frequency as low as 67.74 MHz. Because
HUANG et al.: 2.1-GHz THIRD-ORDER CASCADED PLL 2125

TABLE I
P ERFORMANCE S UMMARY AND C OMPARISON OF THE P ROPOSED C ASCADED PLL

Fig. 18. Measured settling behavior of the first-stage Type-II PLL (top) and
of the proposed cascaded PLL (bottom).

the sample-and-hold introduces larger phase shift with wider

bandwidth, the phase margin becomes smaller and introduces
larger jitter peaking. By using the transfer function of sub- Fig. 19. Measured reference spur of the first-stage Type-II PLL (top) and
sampling DLL (1) and (2) with sample-and-hold, the numerical of the proposed cascaded PLL (bottom).
simulation results shows the same jitter peaking as measure-
ment with 40-MHz −3dB bandwidth (0.6fref ). to settle the center frequency error below frequency noise,
For supply rejection, a −74-dBm 1-MHz noise source is respectively, demonstrating that the clock-skew-sampling DLL
applied to the RO supply to introduce periodic frequency drift. has a negligible effect on the overall settling time.
As shown in Fig. 16, the measured 1-MHz spurs are −22 dBc Fig. 19 shows the output reference spur of the first-stage
at the first-stage output and are improved by 24 dB to −46 dBc integer-N PLL and of the cascaded PLL, which is mainly
at the cascaded PLL output. Fig.17 shows the in-band phase limited by the poor layout isolation. The output reference
noise of the cascaded PLL with different CP currents. Thanks spur of the first stage is only degraded by 0.1 dB, from
to the high-gain phase detection of the time-amplified clock- −45.2 dBc to −45.1 dBc. Table I summarizes and compares
skew-sampling PD, the in-band phase noise is suppressed to the performance with existing PLLs. Thanks to the proposed
−112.6 dBc/Hz only with a 90-uA current. In order to measure cascaded PLL architecture, the proposed two-stage 3rd -order
the settling behavior of the cascaded PLL and of the first- cascaded PLL can provide wider loop bandwidth and more
stage Type-II PLL, a VSA89600 vector signal analyzer is supply-noise induced phase noise rejection than Type-III PLL.
used to demodulate the output frequency, as shown in Fig. 18. Because of wide loop bandwidth to achieve minimum jitter,
By toggling the digital control signals, the first-stage Type-II the proposed cascaded PLL achieves comparable integrated
PLL and the cascaded PLL measure an estimated settling time jitter as Type-I PLL [4] and IL-PLL [17], [21]. Because the
of 4.0 us and 4.2 us for a frequency change of ∼20 MHz reference spur is dominated by the first-stage Type-II PLL,
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R EFERENCES
Zhiqiang Huang was born in Zhangzhou, China,
[1] N. Klemmer et al., “A 45 nm CMOS RF-to-bits LTE/WCDMA in 1990. He received the B.E. degree in integrated
FDD/TDD 2×2 MIMO base-station transceiver SoC with 200 MHz RF circuit design and integrated systems from the Uni-
bandwidth,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. versity of Electronic Science and Technology of
Papers, Feb. 2016, pp. 164–165. China, Chengdu, China, in 2012, and the Ph.D.
[2] J. Savoj et al., “Design of high-speed wireline transceivers for backplane degree from The Hong Kong University of Science
communications in 28 nm CMOS,” in Proc. CICC, Sep. 2012, pp. 1–4. and Technology, Hong Kong, in 2017. His research
[3] J. W. M. Bergmans, “Effect of loop delay on phase margin of first- interests include frequency synthesis from RF to
order and second-order control loops,” IEEE Trans. Circuits Syst. II, mm-wave in CMOS.
Exp. Briefs, vol. 52, no. 10, pp. 621–625, Oct. 2005.
[4] L. Kong and B. Razavi, “A 2.4 GHz 4 mW inductorless RF synthesizer,”
in IEEE ISSCC Dig. Tech. Papers, Feb. 2015, pp. 450–451.
[5] K. J. Wang and I. Galton, “A discrete-time model for the design of type- Bingwei Jiang received the B.Eng. degree in elec-
II PLLs with passive sampled loop filters,” IEEE Trans. Circuits Syst. I, tronic science and technology from the University
Reg. Papers, vol. 58, no. 2, pp. 264–275, Feb. 2011. of Electronic Science and Technology of China
in 2011 and the M.Eng. degree in circuit and system
[6] A. Sai, Y. Kobayashi, S. Saigusa, O. Watanabe, and T. Itakura, “A digi-
from Southeast University, Nanjing, China, in 2014.
tally stabilized type-III PLL using ring VCO with 1.01 psrms integrated
He is currently with the Department of Electronic
jitter in 65 nm CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC)
and Computer Engineering, The Hong Kong Uni-
Dig. Tech. Papers, Feb. 2012, pp. 248–249.
versity of Science and Technology, with a focus
[7] S. Ye, L. Jansson, and I. Galton, “A multiple-crystal interface PLL with on frequency generation circuit design and its
VCO realignment to reduce phase noise,” IEEE J. Solid-State Circuits, applications.
vol. 37, no. 12, pp. 1795–1803, Dec. 2002.
[8] J. Lee and H. Wang, “Study of subharmonically injection-locked PLLs,”
IEEE J. Solid-State Circuits, vol. 44, no. 5, pp. 1539–1553, May 2009.
[9] J.-C. Chien et al., “A pulse-position-modulation phase-noise-reduction Howard C. Luong (F’14) received the B.S., M.S.,
technique for a 2-to-16 GHz injection-locked ring oscillator in 20 nm and Ph.D. degrees from the University of California
CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. at Berkeley in 1988, 1990, and 1994, respectively,
Papers, Feb. 2014, pp. 52–53. all in electrical engineering and computer sciences.
[10] Z. Huang, B. Jiang, L. Li, and H. C. Luong, “A 4.2 μs-settling- Since 1994, he has been with the EEE Faculty, The
time 3rd-order 2.1 GHz phase-noise-rejection PLL using a cascaded Hong Kong University of Science and Technology,
time-amplified clock-skew sub-sampling DLL,” in IEEE Int. Solid-State where he is currently a Professor.
Circuits Conf. (ISSCC) Dig. Tech. Papers, Jan./Feb. 2016, pp. 40–41. He has co-authored three technical books Design
[11] M.-J. E. Lee et al., “Jitter transfer characteristics of delay-locked loops— Techniques for Transformer-Based VCOs and
Theories and design techniques,” IEEE J. Solid-State Circuits, vol. 38, Frequency Dividers, Low-Voltage RF CMOS
no. 4, pp. 614–621, Apr. 2003. Frequency Synthesizers, and Design of Low-Voltage
[12] X. Gao, E. A. M. Klumperink, M. Bohsali, and B. Nauta, “A 2.2 GHz CMOS Switched-Opamp Switched-Capacitor Systems. His research interests
7.6 mW sub-sampling PLL with −126 dBc/Hz in-band phase noise and are in RF and analog integrated circuits and systems for wireless and portable
0.15 psrms jitter in 0.18 μm CMOS,” in IEEE Int. Solid-State Circuits applications.
Conf. (ISSCC) Dig. Tech. Papers, Feb. 2009, pp. 392–393. Dr. Luong was an IEEE Solid-State Circuits Society Distinguished
[13] X. Gao, E. A. M. Klumperink, G. Socci, M. Bohsali, and B. Nauta, Lecturer from 2012 to 2014. He is currently serving as a Technical
“Spur-reduction techniques for PLLs using sub-sampling phase detec- Program Committee Member of the IEEE International Solid-State Circuits
tion,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Conference and an Associate Editor of the IEEE S OLID -S TATE C IRCUITS
Feb. 2010, pp. 474–475. L ETTER and the IEEE V IRTUAL J OURNAL ON RFIC.