HIGH-VOLTAGE CMOS RF SWITCH WITH ENHANCED SWITCHING
SPEED
NAME: ROHAN BAGCHI, ROLL NO: 23M1106
Introduction
In modern RF front-end applications, high-voltage, high-linearity switches are essential for
tasks such as adaptive antenna tuning, power amplifier load modulation, and
transmit/receive switching. Traditional designs, while effective in handling high voltage and
maintaining low power loss, often suffer from slow switching times due to inherent resistive
and capacitive delays in the stacked MOSFET structures. To address this, several approaches
have been explored, though most introduce compromises in linearity, power loss, or silicon
area efficiency. This paper presents a novel approach to improving switching times in high-
voltage CMOS RF switches without sacrificing key RF performance parameters, such as
linearity and insertion loss.
Working Principle
The key improvement in switching speed is achieved through the use of an auxiliary control
circuit that bypasses high-ohmic bias resistors during the switching event. This auxiliary
circuit effectively reduces the RC time constant of the gate control of the MOSFETs. During
the switch from OFF to ON, a positive pulse is applied to the auxiliary NMOS devices,
allowing them to short the bias resistors, rapidly charging the gate. Similarly, during the ON
to OFF transition, a negative pulse triggers the PMOS devices to discharge the gate, reducing
the switch-off time. This dynamic control of the gate charging and discharging significantly
accelerates the switching process without compromising the switch's power-handling
capabilities.
Material and Technology Used
The proposed RF switch is fabricated using a 65 nm CMOS technology optimized for high-
voltage applications. This technology is well-suited for RF front-end circuits that demand
both high linearity and voltage handling. The use of high-ohmic substrates and carefully
sized MOSFETs ensures that the switch can withstand up to 80 V peak RF voltage while
maintaining low insertion loss. Key components in the design include high-ohmic resistors
for biasing, stacked MOSFETs, and minimum-sized auxiliary transistors that control the gate
charging and discharging process. These components work together to ensure fast switching
times without degrading performance in terms of power loss or harmonic distortion.
Fabrication Process
The switch design utilizes a 65 nm CMOS fabrication process, which allows for precise
control over the transistor dimensions and circuit layout. The fabrication process involves
the stacking of 26 identical MOSFET elements, where the largest component is the main
switch transistor, occupying the majority of the silicon area. Key fabrication steps include the
integration of high-ohmic bias resistors and the implementation of the auxiliary control
circuitry. The fabricated switch is then flip-chip bonded into a leadless plastic package and
mounted on a printed circuit board for testing. The small area required for the auxiliary
circuitry ensures that the overall silicon footprint remains efficient, while the flip-chip
packaging facilitates high-frequency testing and performance evaluation.
Applications
This high-voltage CMOS RF switch is highly suitable for a range of RF front-end applications,
including adaptive antenna tuning, load modulation in power amplifiers, and
transmit/receive switching in mobile devices. The ability to achieve fast switching times
without compromising power handling or linearity makes it an ideal solution for high-
frequency cellular and wireless communication systems. Additionally, the low insertion loss
and minimal harmonic distortion make it well-suited for applications where signal integrity is
critical, such as in 5G networks and other advanced wireless technologies.
Schematics
Fig. 1: Schematic diagram of the state-of-art
RF switch
Fig. 2: Schematic diagram of
the RF switch with proposed
switching time acceleration
Fig. 3: Time Diagram of the
schematic in Fig.2
