AND SEQUENTIAL CIRCUIT DESIGN Student’s name: Phan Mạnh Đức Class: TT02 Student ID: 2350004 Date:
A. PRELAB
Question 1: Design Full Adder block.
A full adder is a combinational circuit that performs the arithmetic sum of three input bits. It consists of three inputs and two outputs. Two of the input variables, denoted by A and B, represent the two significant bits to be added. The third input, Ci (input carry), represents the carry from previous lower significant position. Two outputs are S (Sum) and Co (output carry). Table 0.1 The truth table of the Full Adder
Truth table: Logic Diagram:
A B Ci S Co 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 Implement Full Adder on breadboard using logic gates. List all required ICs: - 74LS86 - 74LS08 - 74LS32 Appendix 2: Sample lab.
Application Circuit: GND
+5V
8 14
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14
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10
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10 1 2 34
ON 1
7 GND +5V
Question 2: Design a 4 bit full adder/full subtractor circuit using IC 74LS283. The circuit has three inputs: Sel (1bit), A (4bit) và B (4bit) and 2 outputs: S (4bit), Cout (1bit). - When Sel = 0, S = A + B - When Sel = 1, S = A – B 74LS283 is an IC 4-bit ripple-carry adder. It adds two 4-bit binary numbers [A (A4A3A2A1) and B (B4B3B2B1)] and a carry in bit (Cin). It is composed of four fulladders. The augend’s bits of “B” are added to the addend bits of “A” respectfully of their binary position. Each bit addition produces a sum (S) and a carry out (Co). The carry out is then transmitted to the carry in (Ci) of the next higher-order bit. The final result produces a sum of four bits S (S4S3S2S1) plus a carry out (Cout) bit. Appendix 2: Sample lab.
Figure 0.1: 4-bit parallel adder
Figure 0.2: IC 74LS283 – pin diagram
Draw logic diagram and show how to design: 4-bit parallel adder Appendix 2: Sample lab.
List all required IC to implement 4-bit parallel adder circuit:
- 74LS86 - 74LS283 Appendix 2: Sample lab.
Application circuit:
Question 3: Design 0 →7 up counter, using IC D-FF 74LS74
Asynchronous counters are counters that are configured such that all flip-flops are not triggered simultaneously by a common clock. Since each flip-flop in the counter is triggered by the flip-flop in series before it, these counters are also referred to as ripple counters. There are many types of asynchronous counters. An UP counter counts in an ascending sequenc e while a DOWN counter counts in a descending sequence. A counter can also count UP and DOWN on command; such a counter is known as an UP/DOWN counter. Appendix 2: Sample lab.
Figure 0.3: Schematic symbol and Function symbol of IC 74LS74
Logic diagram of 0 – 7 up counter:
Appendix 2: Sample lab.
Application circuit: Appendix 2: Sample lab.
Question 4: Design sequential circuit for the state diagram in Figure 3.4: State table:
TT hiện tại Ngõ vào TT kế tiếp
S1 S0 X S1+ S0+ A 0 0 0 A 0 0 A 0 0 1 B 0 1 B 0 1 0 A 0 0 B 0 1 1 D 1 1 C 1 0 0 A 0 0 C 1 0 1 B 0 1 D 1 1 0 A 0 0 D 1 1 1 C 1 0 Figure 0.4 Table 0.2
