VND5E160J-E

Double channel high side driver for automotive applications

Features
Max supply voltage VCC 41V
Operating voltage range VCC 4.5 to 28V
Max on-state resistance (per ch.) RON 160 m
Current limitation (typ) ILIMH 10A
PowerSSO-12
Off state supply current IS 2 µA(1)
1. Typical value with all loads connected.
Application
■ General
■ All types of resistive, inductive and capacitive
– Inrush current active management by
loads
power limitation
– Very low stand-by current Description
– 3.0V CMOS compatible inputs
– Optimized electromagnetic emissions The VND5E160J-E is a double channel high-side
– Very low electromagnetic susceptibility driver manufactured in the ST proprietary
VIPower M0-5 technology and housed in the tiny
– In compliance with the 2002/95/EC
PowerSSO-12 package.
european directive
■ Diagnostic functions The VND5E160J-E is designed to drive automotive
grounded loads delivering protection, diagnostics
– Open Drain status output
and easy 3V and 5V CMOS-compatible interface
– On-state open load detection with any microcontroller.
– Off-state open load detection
The device integrates advanced protective
– Output short to VCC detection
functions such as load current limitation, inrush
– Overload and short to ground (power and overload active management by power
limitation) indication limitation, over-temperature shut-off with auto-
– Thermal shut-down indication restart and over-voltage active clamp.
■ Protections A dedicated active low digital status pin is
– Undervoltage shut-down associated with every output channel in order to
– Overvoltage clamp provide Enhanced diagnostic functions including
– Load current limitation fast detection of overload and short-circuit to
– Self limiting of fast thermal transients ground, over-temperature indication, short-circuit
to VCC diagnosis and ON & OFF state open-load
– Protection against loss of ground and loss
detection.
of VCC
– Over-temperature shut-down with The diagnostic feedback of the whole device can
autorestart (thermal shut-down) be disabled by pulling the STAT_DIS pin up, thus
allowing wired-ORing with other similar devices.
– Reverse battery protected (a)
– Electrostatic discharge protection a. See Application schematic on page 22.

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Contents VND5E160J-E

Contents

1 Block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 22
3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 22
3.1.2 Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 23
3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.4 Open load detection in Off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.5 Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 25

4 Package and PC board thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.1 PowerSSO-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.3 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

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VND5E160J-E List of tables

List of tables

Table 1. Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 2. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 5. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 6. Switching (VCC=13V; Tj=25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 7. Status pin (VSD=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 8. Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 9. Openload detection (8V<VCC<18V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 10. Logic Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 11. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 12. Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 13. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 14. PowerSSO-12 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 15. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 16. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

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List of figures VND5E160J-E

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. Normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8. Undervoltage shut-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9. Overload or Short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10. Intermittent Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11. Open Load with external pull-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 12. Open Load without external pull-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 13. Short to VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 14. TJ evolution in Overload or Short to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 15. Off state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 16. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 17. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 18. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 19. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 20. Low level STAT_DIS current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 21. On state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 22. High level STAT_DIS current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 23. On state resistance vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 24. Low level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 25. ILIM vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 26. Turn-On voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 27. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 28. Turn-Off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 29. STAT_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 30. High level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 31. Low level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 32. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 33. Open load detection in Off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 34. Maximum turn-off current versus inductance (for each channel) . . . . . . . . . . . . . . . . . . . . 25
Figure 35. PowerSSO-12 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 36. Rthj-amb vs. PCB copper area in open box free air condition (one channel ON). . . . . . . . 26
Figure 37. PowerSSO-12 thermal impedance junction ambient single pulse (one channel ON). . . . . 27
Figure 38. Thermal fitting model of a double channel HSD in PowerSSO-12 . . . . . . . . . . . . . . . . . . . 27
Figure 39. PowerSSO-12 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 40. PowerSSO-12 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 41. PowerSSO-12 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

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VND5E160J-E Block diagram and pin configuration

1 Block diagram and pin configuration

Figure 1. Block diagram

VCC

Signal Clamp

Undervoltage Control & Diagnostic 1

Power
Clamp

CONTROL & DIAGNOSTIC

IN1 DRIVER

IN2 VON CH 1
Limitation

Channels 2
Over Current
temp. Limitation

OFF State
CH 2
Open load
ST_
DIS ON State
Open load OUT2

ST1

ST2
OUT1
OVERLOAD PROTECTION
LOGIC (ACTIVE POWER LIMITATION)

GND

Table 1. Pin function

Name Function

VCC Battery connection.

OUTPUTn Power output.
Ground connection. Must be reverse battery protected by an external
GND
diode/resistor network.
Voltage controlled input pin with hysteresis, CMOS compatible. Controls output
INPUTn
switch state.
STATUSn Open Drain digital diagnostic pin.
STAT_DIS Active high CMOS compatible pin, to disable the STATUS pin.

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Block diagram and pin configuration VND5E160J-E

Figure 2. Configuration diagram (top view)

TAB = Vcc

GND 12 N.C.
1
STAT_DIS 2 11 OUTPUT 1
INPUT 1 3 10 OUTPUT 1
STATUS 1 4 9 OUTPUT 2
STATUS 2 5 8 OUTPUT 2
6 7
INPUT 2 N.C.

Table 2. Suggested connections for unused and not connected pins

Connection / pin Status N.C. Output Input STAT_DIS

Floating X X X X X
Not Not Through 10k Through 10k
To ground X
allowed allowed resistor resistor

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VND5E160J-E Electrical specifications

2 Electrical specifications

Figure 3. Current and voltage conventions

IS
VCC
VCC
VFn

ISD IOUTn
STAT_DIS OUTPUTn
VSD VOUTn
IINn ISTATn
INPUTn STATUSn
VINn VSTATn
GND

IGND

Note: VFn = VOUTn - VCC during reverse battery condition.

2.1 Absolute maximum ratings

Stressing the device above the ratings listed in the “Absolute maximum ratings” tables may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to the conditions in the “Absolute maximum
ratings” tables for extended periods may affect device reliability. Refer also to the
STMicroelectronics SURE Program and other relevant quality documents.

Table 3. Absolute maximum ratings

Symbol Parameter Value Unit

VCC DC supply voltage 41 V

- VCC Reverse DC supply voltage 0.3 V
- IGND DC reverse ground pin current 200 mA
IOUT DC output current Internally limited A
- IOUT Reverse DC output current 6 A
IIN DC input current +10 / -1 mA
ISTAT DC status current +10 / -1 mA
ISTAT_DIS DC status disable current +10 / -1 mA
Maximum switching energy (single pulse)
EMAX 36 mJ
(L=8mH; RL=0; Vbat=13.5V; Tjstart=150ºC; IOUT = IlimL(Typ.) )

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Electrical specifications VND5E160J-E

Table 3. Absolute maximum ratings

Symbol Parameter Value Unit

Electrostatic discharge
(Human body model: R=1.5KC=100pF)
– INPUT 4000 V
VESD – STATUS 4000 V
– STAT_DIS 4000 V
– OUTPUT 5000 V
– VCC 5000 V
VESD Charge device model (CDM-AEC-Q100-011) 750 V
Tj Junction operating temperature - 40 to 150 °C
Tstg Storage temperature - 55 to 150 °C

2.2 Thermal data

Table 4. Thermal data
Symbol Parameter Max. value Unit

Thermal resistance junction-case

Rthj-case 8 °C/W
(with one channel ON)
Rthj-amb Thermal resistance junction-ambient See Figure 36. °C/W

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VND5E160J-E Electrical specifications

2.3 Electrical characteristics

Values specified in this section are for 8V<VCC<28V; -40°C< Tj <150°C, unless otherwise
stated.

Table 5. Power section

Symbol Parameter Test conditions Min. Typ. Max. Unit

VCC Operating supply voltage 4.5 13 28 V

VUSD Undervoltage shut-down 3.5 4.5 V
Undervoltage shut-down
VUSDhyst 0.5 V
hysteresis
IOUT=1A; Tj=25°C 160 m
RON On state resistance (1) IOUT=1A; Tj=150°C 320 m
IOUT=1A; VCC=5V; Tj= 25°C 210 m
Vclamp Clamp voltage IS=20 mA 41 46 52 V

Off State; VCC=13V; VIN=VOUT=0V;

Tj=25°C 2(2) 5(2) µA
IS Supply current
On State; VIN=5V; VCC=13V;
IOUT=0A 3 6 mA
VIN=VOUT=0V; VCC=13V; Tj=25°C 0 0.01 3 µA
IL(off1) Off state output current (1)
VIN=VOUT=0V; VCC=13V; Tj=125°C 0 5 µA
Output - VCC diode
VF -IOUT=0.6A; Tj=150°C 0.7 V
voltage (1)
1. For each channel.
2. PowerMOS leakage included.

Table 6. Switching (VCC=13V; Tj=25°C)

Symbol Parameter Test conditions Min. Typ. Max. Unit

RL=13
td(on) Turn-On delay time 10 µs
(see Figure 6.)
RL=13
td(off) Turn-Off delay time 15 µs
(see Figure 6.)
See
dVOUT/dt(on) Turn-On voltage slope RL=13 V/µs
Figure 26.
See
dVOUT/dt(off) Turn-Off voltage slope RL=13 V/µs
Figure 28.

Switching energy losses RL=13

WON 70 µJ
during twon (see Figure 6.)

Switching energy losses RL=13

WOFF 40 µJ
during twoff (see Figure 6.)

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Electrical specifications VND5E160J-E

Table 7. Status pin (VSD=0)

Symbol Parameter Test conditions Min. Typ. Max. Unit

Status low output

VSTAT ISTAT= 1.6 mA, VSD=0V 0.5 V
voltage
Normal operation or VSD=5V,
ILSTAT Status leakage current 10 µA
VSTAT= 5V
Status pin input Normal operation or VSD=5V,
CSTAT 100 pF
capacitance VSTAT= 5V
ISTAT= 1mA 5.5 7 V
VSCL Status clamp voltage
ISTAT= - 1mA -0.7 V

Table 8. Protection (1)

Symbol Parameter Test conditions Min. Typ. Max. Unit

DC short circuit VCC=13V 7 10 14 A

IlimH
current 5V<VCC<28V 14 A

Short circuit current VCC=13V

IlimL 2.5 A
during thermal cycling TR<Tj<TTSD
Shutdown
TTSD 150 175 200 °C
temperature
TR Reset temperature TRS + 1 TRS + 5 °C
Thermal reset of
TRS 135 °C
STATUS
Thermal hysteresis
THYST 7 °C
(TTSD - TR)
Status delay in
tSDL Tj>TTSD (see Figure 4.) 20 µs
overload conditions
Turn-off output voltage
VDEMAG IOUT=1A; VIN=0; L=20mH VCC-41 VCC-46 VCC-52 V
clamp
IOUT= 0.03A
Output voltage drop
VON (see Figure 5.) 25 mV
limitation
Tj=-40°C...+150°C
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.

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VND5E160J-E Electrical specifications

Table 9. Open load detection (8V<VCC<18V)

Symbol Parameter Test conditions Min. Typ. Max. Unit

Openload ON state
IOL VIN = 5V 10 40 mA
detection threshold
Openload ON state IOUT = 0A, VCC=13V
tDOL(on) 200 µs
detection delay (See Figure 4.)
Delay between INPUT
falling edge and
tPOL I = 0A (see Figure 4.) 200 500 1200 µs
STATUS rising edge in OUT
open load condition
Openload OFF state
VOL voltage detection VIN = 0V 2 4 V
threshold
Output short circuit to
tDSTKON Vcc detection delay at (See Figure 4.) 180 tPOL µs
turn off
VIN= 0V; VOUT= 4V
Off state output
IL(off2) (see Section 3.4: Open load -75 0 µA
current (1)
detection in Off state)
Delay response from
output rising edge to
td_vol VIN= 0V; VOUT= 4V 20 µs
STATUS falling edge in
open load
1. For each channel.

Table 10. Logic Input

Symbol Parameter Test conditions Min. Typ. Max. Unit

VIL Input low level 0.9 V

IIL Low level input current VIN = 0.9V 1 µA
VIH Input high level 2.1 V
IIH High level input current VIN = 2.1V 10 µA
VI(hyst) Input hysteresis voltage 0.25 V
IIN = 1mA 5.5 7 V
VICL Input clamp voltage
IIN = -1mA -0.7 V
VSDL STAT_DIS low level voltage 0.9 V
ISDL Low level STAT_DIS current VSD=0.9V 1 µA
VSDH STAT_DIS high level voltage 2.1 V
ISDH High level STAT_DIS current VSD=2.1V 10 µA
VSD(hyst) STAT_DIS hysteresis voltage 0.25 V
ISD=1mA 5.5 7 V
VSDCL STAT_DIS clamp voltage
ISD=-1mA -0.7 V

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Electrical specifications VND5E160J-E

Figure 4. Status timings

OPEN LOAD STATUS TIMING (without external pull-up) OPEN LOAD STATUS TIMING (with external pull-up)

VIN IOUT < IOL VIN IOUT < IOL

VOUT < VOL VOUT > VOL

VSTAT VSTAT

tDOL(on) tDOL(on)
tPOL

OUTPUT STUCK TO Vcc OVER TEMP STATUS TIMING

IOUT > IOL Tj > TTSD

VIN
VOUT > VOL VIN

VSTAT
VSTAT
tDOL(on) tDSTKON tSDL tSDL

Figure 5. Output voltage drop limitation

Vcc-Vout

Tj=150oC Tj=25oC

Tj=-40oC

Von

Iout
Von/Ron(T)

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VND5E160J-E Electrical specifications

Figure 6. Switching characteristics

VOUT
tWon tWoff

90%
80%

dVOUT/dt(on) dVOUT/dt(off)

tr 10% tf

INPUT
td(on) td(off)

Table 11. Truth table

Conditions INPUTn OUTPUTn STATUSn (VSD=0V)(1)

L L H
Normal operation
H H H
L L H
Overtemperature
H L L
L L X
Undervoltage
H L X
H X H
Overload & (no power limitation)
Short circuit to GND H Cycling L
(power limitation)
L H L(2)
Output voltage > VOL
H H H
L L H(3)
Output current < IOL
H H L
1. If the VSD is high, the STATUS pin is in a high impedance.
2. The STATUS pin is low with a delay equal to tDSTKON after INPUT falling edge.
3. The STATUS pin becomes high with a delay equal to tPOL after INPUT falling edge.

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Electrical specifications VND5E160J-E

Table 12. Electrical transient requirements

ISO 7637-2: Test levels Number of
2004(E) Burst cycle / pulse Delays and
pulses or
repetition time Impedance
Test pulse III IV test times

5000
1 -75 V -100 V 0.5 s 5s 2 ms, 10 
pulses
5000
2a +37 V +50 V 0.2 s 5s 50 s, 2 
pulses

3a -100 V -150 V 1h 90 ms 100 ms 0.1 s, 50 

3b +75 V +100 V 1h 90 ms 100 ms 0.1 s, 50 

4 -6 V -7 V 1 pulse 100 ms, 0.01 

5b(2) +65 V +87 V 1 pulse 400 ms, 2 

ISO 7637-2: Test level results(1)

2004(E)
Test pulse III IV

1 C C

2a C C

3a C C

3b C C

4 C C

5b(2) C C

1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b.
2. Valid in case of external load dump clamp: 40V maximum referred to ground.

Class Contents

C All functions of the device are performed as designed after exposure to disturbance.

One or more functions of the device are not performed as designed after exposure to
E
disturbance and cannot be returned to proper operation without replacing the device.

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VND5E160J-E Electrical specifications

2.4 Waveforms

Figure 7. Normal operation

Normal operation

INPUT
Nominal load Nominal load

IOUT

VSTATUS

VST_DIS

Figure 8. Undervoltage shut-down

Undervoltage shut-down

VUSDhyst
VUSD
VCC

INPUT

IOUT

UNDEFINED

VSTATUS

VST_DIS

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Electrical specifications VND5E160J-E

Figure 9. Overload or Short to GND

Overload or Short to GND

INPUT
Power Limitation
ILimH > Thermal cycling
ILimL >
IOUT

VSTATUS

VST_DIS

Figure 10. Intermittent Overload

Intermittent Overload

INPUT
Overload
ILimH >
Nominal load
ILimL >
IOUT

VSTATUS

VST_DIS

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VND5E160J-E Electrical specifications

Figure 11. Open Load with external pull-up

Open Load
with external pull-up

INPUT
VPU > VOL

VOL
VOUT

IOUT

tDOL(on)

VSTATUS

VST_DIS

Figure 12. Open Load without external pull-up

Open Load
without external pull-up

INPUT

VOUT

IOUT < IOL

IOL
IOUT

tDOL(on)
tPOL
VSTATUS

VST_DIS

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Electrical specifications VND5E160J-E

Figure 13. Short to VCC

Short to VCC
Resistive Hard
Short to VCC Short to VCC

INPUT
VOUT > VOL VOUT > VOL

VOL
VOUT

IOUT > IOL

IOUT < IOL
IOL
IOUT

tDOL(on)
tDSTK(on)
VSTATUS

VST_DIS

Figure 14. TJ evolution in Overload or Short to GND

TJ evolution in
Overload or Short to GND

INPUT
Self-limitation of fast thermal transients TTSD
THYST
TR

TJ_START
TJ
Power Limitation
ILimH >

< ILimL

IOUT

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VND5E160J-E Electrical specifications

2.5 Electrical characteristics curves

Figure 15. Off state output current Figure 16. High level input current

Iloff (nA) Iih (µA)

300 5

4,5
250 Vin=2.1V
Off State
Vcc=13V 4
Vin=Vout=0V
200
3,5

150 3

2,5
100

50
1,5

0 1
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175
Tc (°C) Tc (°C)

Figure 17. Input clamp voltage Figure 18. Input high level

Vicl (V) Vih (V)

7 3

6,8 lin=1mA 2,5

6,6
2

6,4
1,5
6,2

1
6

0,5
5,8

5,6 0
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175
Tc (°C) Tc (°C)

Figure 19. Input low level Figure 20. Low level STAT_DIS current

Vil (V) Isdl (µA)

2 5

4,5
1,8
Vsd= 0.9V
4
1,6
3,5
1,4
3

1,2 2,5

2
1
1,5
0,8
1
0,6
0,5

0,4 0
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175
Tc (°C) Tc (°C)

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Electrical specifications VND5E160J-E

Figure 21. On state resistance vs Tcase Figure 22. High level STAT_DIS current

Ron (mOhm) Isdh (µA)

300 5

4,5
Iout= 1A Vsd= 2.1V
250 Vcc=13V
4

3,5
200

150
2,5

2
100
1,5

50 1
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175
Tc (°C) Tc (°C)

Figure 23. On state resistance vs VCC Figure 24. Low level input current

Ron (mOhm) Iil (µA)

300 5

Tc=150°C
4,5
Vin=0.9V
250
4
Tc=125°C

3,5
200

150 Tc=25°C 2,5

2
100
Tc=-40°C 1,5

50 1
0 5 10 15 20 25 30 35 -50 -25 0 25 50 75 100 125 150 175
Vcc (V) Tc (°C)

Figure 25. ILIM vs Tcase Figure 26. Turn-On voltage slope

Ilimh (A) (dVout/dt )On (V/ms)

20 1000

900
Vcc=13V
Vcc=13V RI=13 Ohm
15 800

700

10 600

500

5 400

300

0 200
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 175
Tc (°C) Tc (°C)

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VND5E160J-E Electrical specifications

Figure 27. Undervoltage shutdown Figure 28. Turn-Off voltage slope

Vusd (V) (dVout/dt )Off (V/ms)

7 1400

6 1200
Vcc=13V
RI= 13 Ohm
5 1000

4 800

3 600

2 400

1 200

0 0
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175

Tc (°C) Tc (°C)

Figure 29. STAT_DIS clamp voltage Figure 30. High level STAT_DIS voltage

Vsdcl(V) VsdH(V)
10 3

9
2,5
Isd = 1 mA
8
2

7
1,5
6

1
5

0,5
4

3 0
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175
Tc (°C) Tc (°C)

Figure 31. Low level STAT_DIS voltage

VsdL(V)
3

2,5

1,5

0,5

0
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)

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Application information VND5E160J-E

3 Application information

Figure 32. Application schematic

+5V +5V
VCC

Rprot STAT_DIS

Dld
Rprot INPUT
MCU
OUTPUT
Rprot STATUS

GND

RGND
VGND DGND

Note: Channels 2 has the same internal circuit as channel 1.

3.1 GND protection network against reverse battery

3.1.1 Solution 1: resistor in the ground line (RGND only)

This solution can be used with any type of load.
The following is an indication on how to dimension the RGND resistor.
1. RGND  600mV / (IS(on)max).
2. RGND VCC) / (-IGND)
where -IGND is the DC reverse ground pin current and can be found in the absolute
maximum rating section of the device datasheet.
Power dissipation in RGND (when VCC<0: during reverse battery situations) is:
PD= (-VCC)2/RGND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the
maximum on-state currents of the different devices.
Please note that if the microprocessor ground is not shared by the device ground then the
RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output
values. This shift will vary depending on how many devices are ON in the case of several
high side drivers sharing the same RGND.

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VND5E160J-E Application information

If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests Solution 2 is used (see below).

3.1.2 Solution 2: diode (DGND) in the ground line

A resistor (RGND=1kshould be inserted in parallel to DGND if the device drives an
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (~600mV) in the input
threshold and in the status output values, if the microprocessor ground is not common to the
device ground. This shift will not vary if more than one HSD shares the same diode/resistor
network.

3.2 Load dump protection

Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds to
VCC max DC rating. The same applies if the device is subject to transients on the VCC line
that are greater than the ones shown in the ISO T/R 7637/2 table.

3.3 MCUI/Os protection

If a ground protection network is used and negative transient are present on the VCC line,
the control pins will be pulled negative. ST suggests that a resistor (Rprot) be inserted in line
to prevent the µC I/Os pins to latch-up.
The value of these resistors is a compromise between the leakage current of µC and the
current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC
I/Os.
-VCCpeak/Ilatchup  Rprot  (VOHC-VIH-VGND) / IIHmax
Calculation example:
For VCCpeak= - 100V and Ilatchup  20mA; VOHC  4.5V
5k  Rprot  180k.
Recommended Rprot value is 10k

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Application information VND5E160J-E

3.4 Open load detection in Off state

Off-state open-load detection requires an external pull-up resistor (RPU) connected between
the OUTPUT pin and a positive supply voltage (VPU) like the +5V line used to supply the
microprocessor.
The external resistor has to be selected according to the following requirements:
1. No false open load indication when load is connected: in this case we have to avoid
VOUT to be higher than VOlmin; this results in the following condition
VOUT=(VPU/(RL+RPU))RL<VOlmin.
2. No misdetection when load is disconnected: in this case the VOUT has to be higher than
VOLmax; this results in the following condition RPU<(VPU–VOLmax)/IL(off2).
Because Is(OFF) may significantly increase if Vout is pulled high (up to several mA), the pull-
up resistor RPU should be connected to a supply that is switched OFF when the module is in
standby.
The values of VOLmin, VOLmax and IL(off2) are available in the Electrical characteristics
section.

Figure 33. Open load detection in Off state

V batt. VPU

VCC

RPU

DRIVER
INPUT + IL(off2)
LOGIC

OUT
+
R
-
STATUS
VOL
RL

GROUND

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VND5E160J-E Application information

3.5 Maximum demagnetization energy (VCC = 13.5V)

Figure 34. Maximum turn-off current versus inductance (for each channel)

100

A
10
C B

1
I (A)

0,1
0,1 1 L (mH) 10 100

A: Tjstart = 150°C single pulse

B: Tjstart = 100°C repetitive pulse
C: Tjstart = 125°C repetitive pulse

VIN, IL

Demagnetization Demagnetization Demagnetization

Note: Values are generated with RL = 0 

In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse
must not exceed the temperature specified above for curves A and B.

25/34
Package and PC board thermal data VND5E160J-E

4 Package and PC board thermal data

4.1 PowerSSO-12 thermal data

Figure 35. PowerSSO-12 PC board

Note: Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4
area= 77mm x 86mm, PCB thickness=1.6mm, Cu thickness=70µm (front and back side),
Copper areas: from minimum pad lay-out to 8cm2).

Figure 36. Rthj-amb vs. PCB copper area in open box free air condition (one channel ON)

RTHj_amb( ° C/ W)
70

65

60

55

50

45

40
0 2 4 6 8 10
PCB Cu heat sink area ( cm^ 2)

26/34
VND5E160J-E Package and PC board thermal data

Figure 37. PowerSSO-12 thermal impedance junction ambient single pulse (one
channel ON)

ZTH ( ° C/ W)
100 Footprint

2 cm2

8 cm2

10

1
0,001 0,01 0,1 1 10 100 1000
Time ( s)

Equation 1: pulse calculation formula

Z = R +Z 1 – 
TH TH THtp
where  = tP/T

Figure 38. Thermal fitting model of a double channel HSD in PowerSSO-12 (b)

b. The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.

27/34
Package and PC board thermal data VND5E160J-E

Table 13. Thermal parameters

Area/island (cm2) Footprint 2 8

R1= R7 (°C/W) 1.2

R2= R8 (°C/W) 6

R3 (°C/W) 3

R4 (°C/W) 8 8 7

R5 (°C/W) 22 15 10

R6 (°C/W) 26 20 15

C1= C7 (W.s/°C) 0.0008

C2= C8 (W.s/°C) 0.0016

C3 (W.s/°C) 0.0166

C4 (W.s/°C) 0.2 0.1 0.1

C5 (W.s/°C) 0.27 0.8 1

C6 (W.s/°C) 3 6 9

28/34
VND5E160J-E Package and packing information

5 Package and packing information

5.1 ECOPACK® packages

In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second-level interconnect. The category of
Second-Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.

5.2 Package mechanical data

Figure 39. PowerSSO-12 package dimensions

29/34
Package and packing information VND5E160J-E

Table 14. PowerSSO-12 mechanical data

Millimeters
Symbol
Min. Typ. Max.

A 1.250 1.620

A1 0.000 0.100

A2 1.100 1.650

B 0.230 0.410

C 0.190 0.250

D 4.800 5.000

E 3.800 4.000

e 0.800

H 5.800 6.200

h 0.250 0.500

L 0.400 1.270

k 0° 8°

X 2.200 2.800

Y 2.900 3.500

ddd 0.100

30/34
VND5E160J-E Package and packing information

5.3 Packing information

Figure 40. PowerSSO-12 tube shipment (no suffix)

B Base Q.ty 100

C Bulk Q.ty 2000
Tube length (± 0.5) 532
A 1.85
A
B 6.75
C (± 0.1) 0.6

All dimensions are in mm.

Figure 41. PowerSSO-12 tape and reel shipment (suffix “TR”)

REEL DIMENSIONS

Base Q.ty 2500

Bulk Q.ty 2500
A (max) 330
B (min) 1.5
C (± 0.2) 13
F 20.2
G (+ 2 / -0) 12.4
N (min) 60
T (max) 18.4

TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width W 12
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 8
Hole Diameter D (± 0.05) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.1) 5.5
Compartment Depth K (max) 4.5
Hole Spacing P1 (± 0.1) 2
End
All dimensions are in mm.

Start
Top No components Components No components
cover
tape 500mm min 500mm min
Empty components pockets
saled with cover tape.

User direction of feed

31/34
Order codes VND5E160J-E

6 Order codes

Table 15. Device summary

Order codes
Package
Tube Tape and reel
PowerSSO-12 VND5E160J-E VND5E160JTR-E

32/34
VND5E160J-E Revision history

7 Revision history

Table 16. Document revision history

Date Revision Changes

28-Jun-2007 1 Initial release.

Document restructured.
Changed Description on cover page.
Table 9: Open load detection (8V<VCC<18V): added td_vol parameter.
18-Feb-2008 2 Changed Section 2.4: Waveforms.
Added Section 2.5: Electrical characteristics curves.
Added Section 3.5: Maximum demagnetization energy (VCC = 13.5V).
Added Section 4.1: PowerSSO-12 thermal data.
20-Sep-2013 3 Updated Disclaimer

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 VND5E160J-E

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