Introduction to Microprocessors

Dr.B.K.N.Srinivasarao
Asst.Professor
Dept of ECE, NIT Warangal
 HISTORICAL PERSPECTIVE
• 1st generation: 1945 - 1955
– Tubes, punchcards
• 2nd generation: 1955 - 1965
– transistors
• 3rd generation: 1965 – 1980
– Integrated circuits
• 4th generation: 1980 – 1990
– PCs and Workstations
• 5th generation: 1990 -
– PC networks and network operating
systems

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 1st generation (1945-1955)
• Programming was done in machine language
• No operating system
• Programming and maintenance done by one group
of people

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 ENIAC – The first Electronic Computer (1946)

18,000 tubes
300 Tn
170 KWatt

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 OUTPUT and Memory

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 INPUT system

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 2nd generation (1955-1965)
• Transistor-based
• Clear distinction between designers, manufacturers,
users, programmers, and support personnel.
• Only afforded by governments, universities or large
companies (Costly)
• Program was first written on paper (FORTRAN) and then
punched into cards
• Cards were then delivered to the user.
• Mostly used for scientific and technical calculations
– Solving differential equations

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 3rd generation (1965-1980)
• IC-based operation
• IBM developed compatible systems
• Tradeoffs in performance, memory, I/O etc.
• Greater MHz

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 4th generation (1980-1990)
• LSI-based PCs
• Significantly cheaper
• User-friendly software
• 2 dominant operating systems:
– MS DOS: IBM PC (8088, 80286, 80386, 80486)
– UNIX: RISC workstations

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 Computer

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 5th generation (1990-)
• PC networks
• Network operating systems
• Each machine runs its own operating system
• Users don’t care where their programs are
being executed

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 Why do we need to learn
Microprocessors/controllers?

• The microprocessor is the core of

computer systems.
• Nowadays many communication, digital
entertainment, portable devices, are
controlled by them.
• A designer should know what types of
components he needs, ways to reduce
production costs and product reliable.
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 The necessary tools for a
microprocessor/controller
• CPU: Central Processing Unit
• I/O: Input /Output
• Bus: Address bus & Data bus
• Memory: RAM & ROM
• Timer
• Interrupt
• Serial Port
• Parallel Port

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 Microprocessors:
General-purpose microprocessor
• CPU for Computers
• No RAM, ROM, I/O on CPU chip itself
• Example：Intel’s x86, Motorola’s 680x0

Many chips on mother’s board

Data Bus
CPU
General-
Serial
Purpose RAM ROM I/O Timer COM
Micro- Port
Port
processor
Address Bus

General-Purpose Microprocessor System

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 Microcontroller :
• A smaller computer
• On-chip RAM, ROM, I/O ports...
• Example：Motorola’s 6811, Intel’s 8051, Zilog’s Z8 and PIC 16X

CPU RAM ROM

A single chip
Serial
I/O Timer COM
Port
Port
Microcontroller

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Microprocessor vs. Microcontroller
Microprocessor Microcontroller
• CPU is stand-alone, • CPU, RAM, ROM, I/O and
RAM, ROM, I/O, timer timer are all on a single
are separate chip
• designer can decide on the • fix amount of on-chip
amount of ROM, RAM ROM, RAM, I/O ports
and I/O ports. • for applications in which
• expensive cost, power and space are
• versatility critical
• general-purpose • single-purpose

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 MICROPROCESSOR
• A microprocessor is a CPU on a single chip.

• It is a complete computation engine that is fabricated on a

single chip

• The microprocessor you are using might be a Multi-core,

Pentium, AMD, a PowerPC, a Sun-SPARC or any of the many
other brands and types of Microprocessors.

• If a microprocessor, its associated support circuitry, memory

and peripheral I/O components are implemented on a single
chip, it is a microcontroller.

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 Why Intel came up with the idea?
• A Japanese calculator manufacturer – Busicom
wanted Intel to develop 16 separate IC’s for a
line of new calculators
• Intel, at that point in time known only as a
memory manufacturer, was quite small and
did not have the resources to do all 16 chips.
• Ted Hoff came up with the idea of doing all 16
on a single chip.
• Later, Intel realized that the 4004 could have
other uses as well
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 JOURNEY OF MICROPROCESSORS
• In 1971 Intel released the first 4-bit
microprocessor.

• 4004 has 2300 transistors, 640 bytes of

memory addressing capacity and a 108
kHz clock speed.

• It performs add and subtract operations,

and it could only do that 4 bits at a time.

• The 4004 powered one of the first

portable electronic calculators.

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 Busicom Calculator

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 JOURNEY OF MICROPROCESSORS
• The Intel 4004 was quickly replaced by the 8-bit
microprocessor 8008 (1972).
• 8085 was widely used in control applications & small
computers also were designed using 8085 as CPU-also known
as ‘Microcomputers’.

• Most microcomputers are now built with 32, 64, and 128-bit
microprocessor.

• The 8-bit microprocessors are being used as programmable

logic devices in control applications & more powerful μ-
processors are being used for mathematical computing & in
data processing.
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 JOURNEY OF MICROPROCESSORS (Intel)
Processor Process Internal Data Bus Max. No. of Date
(Micron) Register Size Width Memory Transistors Introduced

8085 3.0 8-bit 8-bit 64K 6500 Mar. 77

8088 3.0 16-bit 8-bit 1MB 29,000 June '79
8086 3.0 16-bit 16-bit 1MB 29,000 June '78
286 1.5 16-bit 16-bit 16MB 134,000 Feb. '82
386SX 1.5, 1.0 32-bit 16-bit 16MB 275,000 June '88

386SL 1.0 32-bit 16-bit 16MB 855,000 Oct. '90

386DX 1.5, 1.0 32-bit 32-bit 4GB 275,000 Oct. '85

486SX 1.0, 0.8 32-bit 32-bit 4GB 1.185M Apr. '91

486SX2 0.8 32-bit 32-bit 4GB 1.2M Apr.94

Pentium 0.35, 32-bit 64-bit 4GB 4.5 Jan 97
MMX 0.25
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 8085 Microprocessor
• It is an 8-bit microprocessor designed by Intel in
1977 using NMOS technology.
• It has the following configuration −
– 8-bit data bus
– 16-bit address bus, which can address upto 64KB
– A 16-bit program counter
– A 16-bit stack pointer
– Six 8-bit registers arranged in pairs: BC, DE, HL
– Requires +5V supply to operate at 3.2 MHZ single
phase clock
• Used for Control Applications

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 8085 Architecture

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 8086 Microprocessor
• 8086 Microprocessor is an enhanced version of
8085Microprocessor that was designed by Intel in 1978.
• It is a 16-bit Microprocessor having 20 address lines and 16
data lines that provides up to 1MB storage.
• It consists of powerful instruction set, which provides
operations like multiplication and division easily.
• It supports two modes of operation, i.e. Maximum mode
and Minimum mode.
• Maximum mode is suitable for system having multiple
processors.
• Minimum mode is suitable for system having a single
processor.
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 Features of 8086
• It has an instruction queue, which is capable of storing six
instruction bytes from the memory resulting in faster
processing.
• It was the first 16-bit processor having 16-bit ALU, 16-bit
registers, internal data bus, and 16-bit external data bus
resulting in faster processing.
• It uses two stages of pipelining, i.e. Fetch Stage and Execute
Stage, which improves performance.
• Fetch stage can prefetch up to 6 bytes of instructions and
stores them in the queue.
• Execute stage executes these instructions.
• It has 256 vectored interrupts.

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 Comparison between 8085 & 8086
Microprocessor
• Size − 8085 is 8-bit microprocessor, whereas 8086 is 16-bit
microprocessor.
• Address Bus − 8085 has 16-bit address bus while 8086 has
20-bit address bus.
• Memory − 8085 can access up to 64Kb, whereas 8086 can
access up to 1 Mb of memory.
• Instruction − 8085 doesn’t have an instruction queue,
whereas 8086 has an instruction queue.
• Pipelining − 8085 doesn’t support a pipelined architecture
while 8086 supports a pipelined architecture.
• I/O − 8085 can address 2^8 = 256 I/O's, whereas 8086 can
access 2^16 = 65,536 I/O's.
• Cost − The cost of 8085 is low whereas that of 8086 is high.

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 MOV AX,1234
MOV BX,4321
ADD AX,BX
HLT

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 Memory and I/O Interfacing

Memory Mapped I/O or I/O mapped I/O

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 INTERFACING
• The 8255 is a widely used, programmable
parallel I/O device.
• It can be programmed to transfer data under
various conditions, from simple I/O to
interrupt I/O.
• It is flexible, versatile and economical (when
multiple I/O ports are required). It is an
important general purpose I/O device that can
be used with almost any microprocessor.

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 Interfacing of ADC to 8086 through 8255

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 Memory Interfacing

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 MICROCONTROLLER

External interrupts
On-chip Timer/Counter

Interrupt ROM for

On-chip Timer 1 Counter
Control program
code RAM Timer 0 Inputs

CPU

Bus Serial
4 I/O Ports
OSC Control Port

P0 P1 P2 P3 TxD RxD
Address/Data

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 How to select a Microcontroller
1. meeting the computing needs of the task efficiently
and cost effectively
• speed, the amount of ROM and RAM, the number of I/O
ports and timers, size, packaging, power consumption
• easy to upgrade
• cost per unit
2. availability of software development tools
• assemblers, debuggers, C compilers, emulator, simulator,
technical support
3. wide availability and reliable sources of the
microcontrollers.

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 Current Processors
– Raspberry Pi and Arduino
– become invaluable tools
– They are both extremely popular options
– also very budget-friendly
– Both have their pros and cons, but also their own
particular applications.

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 Raspberry Pi
• The Raspberry Pi is, effectively, a mini
computer on one board.
• It comes with a dedicated processor, memory,
graphics driver and inputs and outputs like
HDMI.
• Raspberry Pi boards run a specially designed
version of the Linux operating system as well.

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 Raspberry Pi

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 Oracle's New Supercomputer Has
1,060 Raspberry Pis

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 Arduino
• Unlike the Raspberry Pi, Arduino boards are
actually micro-controllers rather than 'full'
computers.
• Arduino lacks a full operating system but can run
written code that is interpreted by its firmware.
• Flexibility of executing code directly with no OS
overhead.
• Arduino has no API and cannot provide user
interactivity as there is no operating system.
• It basically runs code on 'bare metal'

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 Applications
• Home automation
• Intelligent door camera
• E-farming
• Robotics and Control Systems
• Weighing Machines
• Medical Instrument
• Washing Machine
• Microwave Oven

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Architecture of 8086
Architecture of 8086 Microprocessor
• The architecture of 8086 microprocessor provides
• a 16‐bit ALU
• a set of 16‐bit registers
• segmented memory addressing capability
• a rich instruction set
• powerful interrupt structure
• pre fetched instruction queue for overlapped fetching and
execution etc.
• To improve the performance by implementing the
parallel processing concept the architecture of the 8086
is divided into two independent sections.
• Bus Interface Unit (BIU) and
• Execution Unit (EU).
Architecture of 8086 Microprocessor
• The BIU sends out addresses, fetches instructions, read data from
ports and memory and writes data to ports and memory.
• The BIU handles all transfers of data and addresses on the buses
required by the Execution Unit
• whereas the Execution Unit tells the BIU where to fetch
instructions or data from, decodes the instructions and executes
the instructions.
• The BIU contains
• the circuit for physical address calculations
• a pre decoding instruction byte queue (6 bytes long)
• four 16‐bit segment registers (ES, CS, SS, DS)
• 16‐bit instruction pointer (IP)
• The EU contains
• control circuitry, instruction decoder and ALU
• 16‐bit flag registers
• four 16‐bit general purpose registers (AX, BX, CX, DX)
• 16‐bit pointer registers (SP, BP) and
• 16‐bit index registers (SI, DI)
Execution Unit
• Control Circuitry, Instruction Decoder and ALU:
• The EU contains control circuitry which directs internal
operations.
• A decoder in the EU translates instructions fetched from
memory into a series of actions which the EU carries out.
• The EU has a 16‐bit arithmetic logic unit which can add,
subtract, AND, OR, XOR, increment, decrement, complement,
or shift binary numbers.
• Flag Register:
• The 8086 16‐bit flag register contents indicate the results of
computations in the ALU. It also contains some flag bits to
control the CPU operations.
• A flag is a flip‐flop that indicates some condition produced by
the execution of an instruction or controls certain operations
of the EU.
Flag Register

Control Flags

Trap Flag (TF): It is used to set the Trace Mode i.e. start Single Stepping Mode. Here the µP is
interrupted after every instruction so that, the program can be debugged.

Interrupt Enable Flag (IF): It is used to mask (disable) or unmask (enable) the INTR interrupt.

Direction Flag (DF): If this flag is set, SI and DI are in auto‐decrementing mode in String Operations.
Status Flags
1. Carry flag (CY): It is set whenever there is a carry {or borrow} out of the
MSB of a the result (D7 bit for an 8-bit operation and D15 bit for a 16-bit
operation).

2. Parity Flag (PF): It is set if the result has even parity.

3. Auxiliary Carry Flag (AC): It is set if a carry is generated out of the Lower
Nibble. It is used only in 8-bit operations like DAA and DAS.

4. Zero Flag (ZF): It is set if the result is zero.

5. Sign Flag (SF): It is set if the MSB of the result is 1. For signed operations,
such a number is treated as –ve.

6. Overflow Flag (OF): It will be set if the result of a signed operation is too
large to fit in the number of bits available to represent it. It can be checked
using the instruction INTO (Interrupt on Overflow).
Execution Unit ‐ Registers
• General registers are used for temporary storage and manipulation
of data and instructions
• Accumulator register consists of two 8‐bit registers AL and AH, which
can be combined together and used as a 16‐bit register AX
• Accumulator can be used for I/O operations and string manipulation
• Base register consists of two 8‐bit registers BL and BH, which can be
combined together and used as a 16‐bit register BX
• BX register usually contains a data pointer used for based, based
indexed or register indirect addressing
• Count register consists of two 8‐bit registers CL and CH, which can
be combined together and used as a 16‐bit register CX
• Count register can be used as a counter in string manipulation and
shift/rotate instructions
Execution Unit ‐ Registers
• Data register consists of two 8‐bit registers DL and DH, which can be
combined together and used as a 16‐bit register DX
• Data register can be used as a port number in I/O operations
• In integer 32‐bit multiply and divide instruction the DX register
contains high‐order word of the initial or resulting number
Execution Unit ‐ Pointers
• Stack Pointer (SP) is a 16‐bit register pointing to program stack
• Base Pointer (BP) is a 16‐bit register pointing to data in stack
segment. BP register is usually used for based, based indexed or
register indirect addressing.
• Source Index (SI) is a 16‐bit register. SI is used for indexed, based
indexed and register indirect addressing, as well as a source data
addresses in string manipulation instructions.
• Destination Index (DI) is a 16‐bit register. DI is used for indexed,
based indexed and register indirect addressing, as well as a
destination data addresses in string manipulation instructions.
Bus Interface Unit
• The BIU has
• Instruction stream byte queue
• A set of segment registers
• Instruction pointer
Memory Segmentation
 BIU – Instruction Byte Queue
• 8086 instructions vary from 1 to 6 bytes
• Therefore fetch and execution are taking place concurrently in order to
improve the performance of the microprocessor
• The BIU feeds the instruction stream to the execution unit through a 6 byte
prefetch queue
• This prefetch queue can be considered as a form of loosely coupled pipelining
• Execution and decoding of certain instructions do not require the use of buses
• While such instructions are executed, the BIU fetches up to six instruction
bytes for the following instructions (the subsequent instructions)
• The BIU store these prefetched bytes in a first‐in‐first out register by name
instruction byte queue
• When the EU is ready for its next instruction, it simply reads the instruction
byte(s) for the instruction from the queue in BIU
Segment: Offset Notation
• The total addressable memory size is 1MB

• Most of the processor instructions use 16‐bit pointers the processor

can effectively address only 64 KB of memory

• To access memory outside of 64 KB the CPU uses special segment

registers to specify where the code, stack and data 64 KB segments
are positioned within 1 MB of memory
Segment: Offset Notation
• A simple scheme would be to order the bytes in a serial fashion and
number them from 0 (or 1) to the end of memory

• The scheme used in the 8086 is called segmentation

• Every address has two parts, a SEGMENT and an OFFSET

(Segmnet:Offset )

• The segment indicates the starting of a 64 kilobyte portion of memory,

in multiples of 16

• The offset indicates the position within the 64k portion

• Absolute address = (segment * 16) + offset

Segment Registers
• The memory of 8086 is divided into 4 segments namely
• Code segment (program memory)
• Data segment (data memory)
• Stack memory (stack segment)
• Extra memory (extra segment)
• Program memory – Program can be located anywhere in memory
• Data memory – The processor can access data in any one out of 4
available segments
• Stack memory – A stack is a section of the memory set aside to store
addresses and data while a subprogram executes
• Extra segment – This segment is also similar to data memory where
additional data may be stored and maintained.
 Segment Registers
• Code Segment (CS) register is a 16‐bit register containing address of 64
KB segment with processor instructions
• The processor uses CS segment for all accesses to instructions
referenced by instruction pointer (IP) register
• Stack Segment (SS) register is a 16‐bit register containing address of
64KB segment with program stack
• By default, the processor assumes that all data referenced by the stack
pointer (SP) and base pointer (BP) registers is located in the stack
segment.
• Data Segment (DS) register is a 16‐bit register containing address of
64KB segment with program data
• By default, the processor assumes that all data referenced by general
registers (AX, BX, CX, DX) and index register (SI, DI) is located in the data
segment
• Extra Segment (ES) register is a 16‐bit register containing address of
64KB segment, usually with program data
• By default, the processor assumes that the DI register references the ES
segment in string manipulation instructions
Intel 8086
⚫ Intel8086 was launched
in 1978.
⚫ Itwas the first 16-bit
microprocessor.
⚫ This microprocessor had
major improvement over
the execution speed of
8085.
⚫ Itis available as 40-pin
Dual-Inline-Package
(DIP).
Intel 8086
⚫ It
is available in three
versions:
◾8086 (5 MHz)

◾8086-2 (8 MHz)

◾8086-1 (10 MHz)

⚫ Itconsists of 29,000
transistors.
Intel 8086
⚫ Ithas a 16 line data
bus.
⚫ And 20 line address
bus.
⚫ Itcould address up to
1 MB of memory.
⚫ Ithas more than
20,000 instructions.
⚫ Itsupports
multiplication and
division.
Pin Diagram of Intel 8086
 AD0 – AD15
Pin 16‐2, 39 (Bi‐directional)

⚫ These lines are multiplexed bi-

directional address/data bus.
⚫ DuringT1, they carry lower
order 16-bit address.
⚫ Inthe remaining clock cycles,
they carry 16-bit data.
⚫ AD0-AD7 carry lower order byte
of data.
⚫ AD8-AD15 carry higher order
byte of data.
 A19/S6, A18/S5, A17/S4, A16/S3
Pin 35‐38 (Unidirectional)

⚫ Theselines are
multiplexed unidirectional
address and status bus.
⚫ DuringT1, they carry
higher order 4-bit address.
⚫ Inthe remaining clock
cycles, they carry status
signals.
 BHE /S7
Pin 34 (Output)

⚫ BHE stands for Bus High

Enable.
⚫ BHE signal is used to
indicate the transfer of data
over higher order data bus
(D8 – D15).
⚫ 8-bitI/O devices use this
signal.
⚫ Itis multiplexed with status
pin S7.
 RD (Read)
Pin 32 (Output)

⚫ It
is a read signal used for
read operation.
⚫ It is an output signal.
⚫ It is an active low signal.
 READY
Pin 22 (Input)

⚫ This is an acknowledgement
signal from slower I/O
devices or memory.
⚫ It is an active high signal.
⚫ When high, it indicates that
the device is ready to
transfer data.
⚫ When low, then
microprocessor is in wait
state.
 RESET
Pin 21 (Input)

⚫ It is a system reset.
⚫ It is an active high signal.
⚫ When high,
microprocessor enters into
reset state and terminates
the current activity.
⚫ Itmust be active for at
least four clock cycles to
reset the microprocessor.
 INTR
Pin 18 (Input)

⚫ Itis an interrupt request

signal.
⚫ It is active high.
⚫ It is level triggered.
 NMI
Pin 17 (Input)

⚫ Itis a non-maskable
interrupt signal.
⚫ It is an active high.
⚫ Itis an edge triggered
interrupt.
 TEST
Pin 23 (Input)

⚫ It
is used to test the
status of math co-
processor 8087.
⚫ TheBUSY pin of 8087 is
connected to this pin of
8086.
⚫ If
low, execution continues
else microprocessor is in
wait state.
 CLK
Pin 19 (Input)

⚫ Thisclock input provides

the basic timing for
processor operation.
⚫ It
is symmetric square
wave with 33% duty cycle.
⚫ The range of frequency of
different versions is 5
MHz, 8 MHz and 10 MHz.
 VCC and VSS
Pin 40 and Pin 20 (Input)

⚫ VCC is power supply signal.

⚫+5V DC is supplied
through this pin.
⚫ VSS is ground signal.
 MN /MX
Pin 33 (Input)

⚫ 8086 works in two modes:

◾Minimum Mode

◾Maximum Mode

⚫ IfMN/MX is high, it works

in minimum mode.
⚫ IfMN/MX is low, it works
in maximum mode.
 MN /MX
Pin 33 (Input)

⚫ Pins24 to 31 issue two

different sets of signals.
⚫ Oneset of signals is issued
when CPU operates in
minimum mode.
⚫ Otherset of signals is
issued when CPU operates
in maximum mode.
Pin Description for Minimum
Mode
 INTA
Pin 24 (Output)

⚫ This
is an interrupt
acknowledge signal.
⚫ When microprocessor
receives INTR signal, it
acknowledges the
interrupt by generating
this signal.
⚫ It is an active low signal.
 ALE
Pin 25 (Output)

⚫ Thisis an Address Latch

Enable signal.
⚫ Itindicates that valid
address is available on bus
AD0 – AD15.
⚫ Itis an active high signal
and remains high during T1
state.
⚫ It is connected to enable pin
of latch 8282.
 DEN
Pin 26 (Output)

⚫ Thisis a Data Enable

signal.
⚫ This
signal is used to
enable the transceiver
8286.
⚫ Transceiveris used to
separate the data from the
address/data bus.
⚫ It is an active low signal.
 DT /R

• Pin 27 (Output)
⚫ This is a Data Transmit/Receive signal.
⚫ Itdecides the direction of data flow through the
transceiver.
⚫ When it is high, data is transmitted out.
⚫ When it is low, data is received in.
 M /IO
Pin 28 (Output)

⚫ Thissignal is issued by the

microprocessor to
distinguish memory access
from I/O access.
⚫ When it is high, memory is
accessed.
⚫ When it is low, I/O devices
are accessed.
 WR
Pin 29 (Output)

⚫ It is a Write signal.
⚫ It
is used to write data in
memory or output device
depending on the status of
M/IO signal.
⚫ It is an active low signal.
 HLDA
Pin 30 (Output)

⚫ Itis a Hold Acknowledge

signal.
⚫ It
is issued after receiving
the HOLD signal.
⚫ It is an active high signal.
 HOLD
Pin 31 (Input)

⚫ When DMA controller

needs to use address/data
bus, it sends a request to
the CPU through this pin.
⚫ It is an active high signal.
⚫ When microprocessor
receives HOLD signal, it
issues HLDA signal to the
DMA controller.
Pin Description for Maximum
Mode

28
 QS1 and QS0
Pin 24 and 25 (Output)

⚫ These pins provide the

status of instruction
queue.
QS1 QS0 Status
0 0 No operation
1 1 1st byte of opcode from queue
2 0 Empty queue
1 1 Subsequent byte from queue
 S0, S1, S2
Pin 26, 27, 28 (Output)

⚫ These status signals

indicate the operation
being done by the
microprocessor.
⚫ This
information is
required by the Bus
Controller 8288.
⚫ Buscontroller 8288
generates all memory and
I/O control signals.
 S0, S1, S2
Pin 26, 27, 28 (Output)

S2 S1 S0 Status
0 0 0 Interrupt Acknowledge
0 0 1 I/O Read
0 1 0 I/O Write
0 1 1 Halt
1 0 0 Opcode Fetch
1 0 1 Memory Read
1 1 0 Memory Write
1 1 1 Passive
 LOCK
Pin 29 (Output)

⚫ Thissignal indicates that

other processors should not
ask CPU to relinquish the
system bus.
⚫ When it goes low, all
interrupts are masked and
HOLD request is not
granted.
⚫ Thispin is activated by using
LOCK prefix on any
instruction.
 RQ/GT1 and RQ/GT0
Pin 30 and 31 (Bi‐directional)
⚫ These are Request/Grant
pins.
⚫ Otherprocessors request the
CPU through these lines to
release the system bus.
⚫ Afterreceiving the request,
CPU sends acknowledge
signal on the same lines.
⚫ RQ/GT0 has higher priority
than RQ/GT1.
Instruction set of 8086
 Instruction Set of 8086
⚫An instruction is a binary pattern designed
inside a microprocessor to perform a specific
function.
⚫The entire group of instructions that a
microprocessor supports is called
Instruction Set.
⚫8086 has more than 20,000 instructions.
Classification of Instruction Set
⚫ Data Transfer Instructions

⚫ Arithmetic instructions

⚫ Bit Manipulation Instructions

⚫ Program Execution Transfer Instructions (Branch Instructions)

⚫ String manipulation instructions:

⚫ Machine control instructions

⚫ Flag manipulation instructions:

 Data Transfer Instructions
⚫These instructions are used to transfer data
from source to destination.
⚫The operand can be a constant, memory
location, register or I/O port address.
 Data Transfer Instructions
⚫ MOV Des, Src:
⚫ Src operand can be register, memory location or immediate
operand.
⚫ Des can be register or memory operand.

⚫ Both Src and Des cannot be memory location at the same

time.
⚫ E.g.:
⚫ MOV CX, 037A H
⚫ MOV AL, BL
⚫ MOV BX, [0301 H]
 Data Transfer Instructions
⚫ PUSH Operand:
⚫ It pushes the operand into top of stack.

⚫ E.g.: PUSH BX

⚫ POP Des:
⚫ It pops the operand from top of stack to Des.

⚫ Des can be a general purpose register, segment register

(except CS) or memory location.
⚫ E.g.: POP AX
 Data Transfer Instructions
⚫ XCHG Des, Src:
⚫ This instruction exchanges Src with Des.

⚫ It cannot exchange two memory locations directly.

⚫ E.g.: XCHG DX, AX

 Data Transfer Instructions
⚫ IN Accumulator, Port Address:
⚫ It transfers the operand from specified port to accumulator
register.

⚫ E.g.: IN AX, 0028 H

⚫ OUT Port Address, Accumulator:

⚫ It transfers the operand from accumulator to specified port.

⚫ E.g.: OUT 0028 H, AX

 Data Transfer Instructions
⚫LEA Register, Src:
⚫It loads a 16-bit register with the offset
address of the data specified by the Src.
⚫E.g.: LEA BX, [DI]
⚫ This instruction loads the contents of DI
(offset) into the BX register.
 Data Transfer Instructions
⚫LDS Des, Src:
⚫ It loads 32-bit pointer from memory source to
destination register and DS.
⚫ The offset is placed in the destination register and the
segment is placed in DS.
⚫ To use this instruction the word at the lower memory
address must contain the offset and the word at the
higher address must contain the segment.
⚫ E.g.: LDS BX, [0301 H]
 Data Transfer Instructions
⚫LES Des, Src:
⚫ It loads 32-bit pointer from memory source to
destination register and ES.
⚫ The offset is placed in the destination register and the
segment is placed in ES.
⚫ This instruction is very similar to LDS except that it
initializes ES instead of DS.
⚫ E.g.: LES BX, [0301 H]
 Data Transfer Instructions
⚫ LAHF:

⚫ It copies the lower byte of flag register to AH.

⚫ SAHF:

⚫ It copies the contents of AH to lower byte of f lag register.

⚫ PUSHF:

⚫ Pushes flag register to top of stack.

⚫ POPF:

⚫ Pops the stack top to flag register.

 Arithmetic Instructions
⚫ADD Des, Src:
⚫It adds a byte to byte or a word to word.

⚫It effects AF, CF, OF, PF, SF, ZF flags.

⚫E.g.:

⚫ ADD AL, 74H

⚫ ADD DX, AX
⚫ ADD AX, [BX]
 Arithmetic Instructions
⚫ADC Des, Src:
⚫It adds the two operands with CF.

⚫It effects AF, CF, OF, PF, SF, ZF flags.

⚫E.g.:

⚫ ADC AL, 74H

⚫ ADC DX, AX
⚫ ADC AX, [BX]
 Arithmetic Instructions
⚫SUB Des, Src:
⚫ It subtracts a byte from byte or a word from word.

⚫ It effects AF, CF, OF, PF, SF, ZF f lags.

⚫ For subtraction, CF acts as borrow f lag.

⚫ E.g.:
⚫ SUB AL, 74H
⚫ SUB DX, AX
⚫ SUB AX, [BX]
 Arithmetic Instructions
⚫SBB Des, Src:
⚫It subtracts the two operands and also the
borrow from the result.
⚫It effects AF, CF, OF, PF, SF, ZF flags.

⚫E.g.:
⚫ SBB AL, 74H
⚫ SBB DX, AX
⚫ SBB AX, [BX]
 Arithmetic Instructions
⚫INC Src:
⚫It increments the byte or word by one.

⚫The operand can be a register or memory

location.
⚫It effects AF, OF, PF, SF, ZF f lags.

⚫CF is not effected.

⚫E.g.: INC AX
 Arithmetic Instructions
⚫DEC Src:
⚫It decrements the byte or word by one.

⚫The operand can be a register or memory

location.
⚫It effects AF, OF, PF, SF, ZF f lags.

⚫CF is not effected.

⚫E.g.: DEC AX
 Arithmetic Instructions
⚫ AAA (ASCII Adjust after Addition):
⚫ The data entered from the terminal is in ASCII format.

⚫ In ASCII, 0 – 9 are represented by 30H – 39H.

⚫ This instruction allows us to add the ASCII codes.

⚫ This instruction does not have any operand.

⚫ Other ASCII Instructions:

⚫ AAS (ASCII Adjust after Subtraction)

⚫ AAM (ASCII Adjust after Multiplication)

⚫ AAD (ASCII Adjust Before Division)

 Arithmetic Instructions
⚫DAA (Decimal Adjust after Addition)
⚫ It is used to make sure that the result of adding two BCD
numbers is adjusted to be a correct BCD number.
⚫ It only works on AL register.

⚫ DAS (Decimal Adjust after Subtraction)

⚫ It is used to make sure that the result of subtracting two
BCD numbers is adjusted to be a correct BCD number.
⚫ It only works on AL register.
 Arithmetic Instructions
⚫NEG Src:
⚫It creates 2’s complement of a given
number.
⚫That means, it changes the sign of a
number.
 Arithmetic Instructions
⚫ CMP Des, Src:
⚫ It compares two specified bytes or words.

⚫ The Src and Des can be a constant, register or memory

location.
⚫ Both operands cannot be a memory location at the same
time.
⚫ The comparison is done simply by internally subtracting
the source from destination.
⚫ The value of source and destination does not change, but
the flags are modified to indicate the result.
 Arithmetic Instructions
⚫ MUL Src:
⚫ It is an unsigned multiplication instruction.

⚫ It multiplies two bytes to produce a word or two words to

produce a double word.
⚫ AX = AL * Src

⚫ DX : AX = AX * Src

⚫ This instruction assumes one of the operand in AL or AX.

⚫ Src can be a register or memory location.

⚫ IMUL Src:
⚫ It is a signed multiplication instruction.
 Arithmetic Instructions
⚫DIV Src:
⚫ It is an unsigned division instruction.

⚫ It divides word by byte or double word by word.

⚫ The operand is stored in AX, divisor is Src and the

result is stored as:
⚫ AH = remainder AL = quotient

⚫IDIV Src:
⚫ It is a signed division instruction.
 Arithmetic Instructions
⚫CBW (Convert Byte to Word):
⚫ This instruction converts byte in AL to word in AX.

⚫ The conversion is done by extending the sign bit of AL

throughout AH.

⚫ CWD (Convert Word to Double Word):

⚫ This instruction converts word in AX to double word in
DX : AX.
⚫ The conversion is done by extending the sign bit of AX
throughout DX.
 Bit Manipulation Instructions
⚫ These instructions are used at the bit level.

⚫ These instructions can be used for:

⚫ Testing a zero bit

⚫ Set or reset a bit

⚫ Shift bits across registers

 Bit Manipulation Instructions
⚫ NOT Src:
⚫ It complements each bit of Src to produce 1’s
complement of the specified operand.
⚫ The operand can be a register or memory location.
 Bit Manipulation Instructions
⚫ AND Des, Src:
⚫ It performs AND operation of Des and Src.

⚫ Src can be immediate number, register or memory

location.
⚫ Des can be register or memory location.

⚫ Both operands cannot be memory locations at the same

time.
⚫ CF and OF become zero after the operation.

⚫ PF, SF and ZF are updated.

 Bit Manipulation Instructions
⚫ OR Des, Src:
⚫ It performs OR operation of Des and Src.

⚫ Src can be immediate number, register or memory

location.
⚫ Des can be register or memory location.

⚫ Both operands cannot be memory locations at the same

time.
⚫ CF and OF become zero after the operation.

⚫ PF, SF and ZF are updated.

 Bit Manipulation Instructions
⚫ XOR Des, Src:
⚫ It performs XOR operation of Des and Src.

⚫ Src can be immediate number, register or memory

location.
⚫ Des can be register or memory location.

⚫ Both operands cannot be memory locations at the same

time.
⚫ CF and OF become zero after the operation.

⚫ PF, SF and ZF are updated.

 Bit Manipulation Instructions
⚫ SHL Des, Count:
⚫ It shift bits of byte or word left, by count.

⚫ It puts zero(s) in LSBs.

⚫ MSB is shifted into carry flag.

⚫ If the number of bits desired to be shifted is 1, then the

immediate number 1 can be written in Count.
⚫ However, if the number of bits to be shifted is more than
1, then the count is put in CL register.
 Bit Manipulation Instructions
⚫ SHR Des, Count:
⚫ It shift bits of byte or word right, by count.

⚫ It puts zero(s) in MSBs.

⚫ LSB is shifted into carry flag.

⚫ If the number of bits desired to be shifted is 1, then the

immediate number 1 can be written in Count.
⚫ However, if the number of bits to be shifted is more than
1, then the count is put in CL register.
 Bit Manipulation Instructions
⚫ ROL Des, Count:
⚫ It rotates bits of byte or word left, by count.

⚫ MSB is transferred to LSB and also to CF.

⚫ If the number of bits desired to be shifted is 1, then the

immediate number 1 can be written in Count.
⚫ However, if the number of bits to be shifted is more than
1, then the count is put in CL register.
 Bit Manipulation Instructions
⚫ ROR Des, Count:
⚫ It rotates bits of byte or word right, by count.

⚫ LSB is transferred to MSB and also to CF.

⚫ If the number of bits desired to be shifted is 1, then the

immediate number 1 can be written in Count.
⚫ However, if the number of bits to be shifted is more than
1, then the count is put in CL register.
 Program Execution Transfer Instructions
⚫ These instructions cause change in the sequence of the
execution of instruction.
⚫ This change can be through a condition or sometimes
unconditional.
⚫ The conditions are represented by flags.
 Program Execution Transfer Instructions
⚫ CALL Des:
⚫ This instruction is used to call a subroutine or function
or procedure.
⚫ The address of next instruction after CALL is saved onto
stack.

⚫ RET:
⚫ It returns the control from procedure to calling program.

⚫ Every CALL instruction should have a RET.

 Program Execution Transfer Instructions
⚫ JMP Des:
⚫ This instruction is used for unconditional jump from
one place to another.

⚫ Jxx Des (Conditional Jump):

⚫ All the conditional jumps follow some conditional
statements or any instruction that affects the flag.
 Conditional Jump Table
Mnemonic Meaning Jump Condition
JA Jump if Above CF = 0 and ZF = 0
JAE Jump if Above or Equal CF = 0
JB Jump if Below CF = 1
JBE Jump if Below or Equal CF = 1 or ZF = 1
JC Jump if Carry CF = 1
JE Jump if Equal ZF = 1
JNC Jump if Not Carry CF = 0
JNE Jump if Not Equal ZF = 0
JNZ Jump if Not Zero ZF = 0
JPE Jump if Parity Even PF = 1
JPO Jump if Parity Odd PF = 0
JZ Jump if Zero ZF = 1
 Program Execution Transfer Instructions
⚫ Loop Des:
⚫ This is a looping instruction.

⚫ The number of times looping is required is placed in the CX register.

⚫ With each iteration, the contents of CX are

decremented.

⚫ ZF is checked whether to loop again or not.

MOV CX,0005H ; Number of times in CX

MOV BX, 0FF7H ; Data to BX
Go: MOV AX, 2030H
OR BX,AX
AND DX,AX
LOOP Go
 String Instructions
⚫ String in assembly language is just a sequentially
stored bytes or words.
⚫ There are very strong set of string instructions in 8086.

⚫ By using these string instructions, the size of the

program is considerably reduced.
REP
MOVSB/MOVSW
CMPSB/CMPSW
SCASB/SCASW
STOSB/STOSW
LODSB/LODSW
 String Instructions
⚫ CMPS Des, Src:
⚫ It compares the string bytes or words.

⚫ SCAS String:
⚫ It scans a string.

⚫ It compares the String with byte in AL or with word in

AX.
 String Instructions
⚫ MOVS / MOVSB / MOVSW:
⚫ It causes moving of byte or word from one string to
another.
⚫ In this instruction, the source string is in Data Segment
and destination string is in Extra Segment.
⚫ SI and DI store the offset values for source and
destination index.
 String Instructions
⚫ REP (Repeat):
⚫ This is an instruction prefix.

⚫ It causes the repetition of the instruction until CX

becomes zero.
⚫ E.g.: REP MOVSB STR1, STR2

⚫ It copies byte by byte contents.

⚫ REP repeats the operation MOVSB until CX becomes zero.

Processor Control Instructions
⚫ These instructions control the processor itself.

⚫ 8086 allows to control certain control flags that:

⚫ causes the processing in a certain direction

⚫ processor synchronization if more than one

microprocessor attached.
 Example code
MOV AX, 4000H; initialize data segment register
MOV DS,AX
MOV ES,AX ; initialize extra segment register
LEA SI,TEST-MESS ;point SI at source string
LEA DI,NEW-LOC ;point DI at destination string
MOV CX,23 H; use CX register as counter
CLD ; clear DF, so pointers auto increment
REP MOVSB ; after each string element is moved
move string byte until all moved
Flag manipulation instructions
CLC – clear carry flag
CMC – Complement carry flag
STC – Set carry flag
CLD – clear direction flag
STD - Set direction flag
CLI – clear interrupt flag
STI – Set interrupt flag
 Machine control instructions
WAIT – Wait for Test input pin to go low
HLT – Halt the processor
NOP – No operation
ESC – Escape to external device send the instruction to
coprocessor
LOCK – Bus lock instruction prefix.
Contents:
Introduction
Block Diagram and Pin Description of the
8051
Registers
Memory mapping in 8051
I/O Port Programming
Addressing modes
Instruction set

1
Why do we need to learn
Microprocessors/controllers?

 The microprocessor is the core of computer

systems.
 Nowadays many communication, digital
entertainment, portable devices, are
controlled by them.
 A designer should know what types of
components he needs, ways to reduce
production costs and product reliable.

2
Different aspects of a
microprocessor/controller

 Hardware :Interface to the real world

 Software :order how to deal with inputs

3
The necessary tools for a
microprocessor/controller
 CPU: Central Processing Unit
 I/O: Input /Output
 Bus: Address bus & Data bus
 Memory: RAM & ROM
 Timer
 Interrupt
 Serial Port
 Parallel Port

4
 Microprocessors:
General-purpose microprocessor
 CPU for Computers
 No RAM, ROM, I/O on CPU chip itself
 Example：Intel’s x86, Motorola’s 680x0

Many chips on mother’s board

Data Bus
CPU
General-
Serial
Purpose RAM ROM I/O Timer COM
Micro- Port
Port
processor
Address Bus

General-Purpose Microprocessor System

5
Microcontroller :
 A smaller computer
 On-chip RAM, ROM, I/O ports...
 Example：Motorola’s 6811, Intel’s 8051, Zilog’s Z8 and PIC
16X

CPU RAM ROM

A single chip
Serial
I/O Timer COM
Port
Port
Microcontroller

6
Microprocessor vs. Microcontroller
Microprocessor Microcontroller
 CPU is stand-alone, RAM, • CPU, RAM, ROM, I/O and
ROM, I/O, timer are separate timer are all on a single chip
 designer can decide on the • fix amount of on-chip ROM,
amount of ROM, RAM and RAM, I/O ports
I/O ports.
• for applications in which cost,
 expansive power and space are critical
 versatility • single-purpose
 general-purpose

7
 Embedded System

 Embedded system means the processor is embedded into that

application.
 An embedded product uses a microprocessor or microcontroller to
do one task only.
 In an embedded system, there is only one application software that
is typically burned into ROM.
 Example：printer, keyboard, video game player

8
 Three criteria in Choosing a Microcontroller

1. meeting the computing needs of the task efficiently and cost

effectively
• speed, the amount of ROM and RAM, the number of I/O ports
and timers, size, packaging, power consumption
• easy to upgrade
• cost per unit
2. availability of software development tools
• assemblers, debuggers, C compilers, emulator, simulator,
technical support
3. wide availability and reliable sources of the microcontrollers.

9
 Block Diagram
External interrupts
On-chip Timer/Counter

Interrupt ROM for

On-chip Timer 1 Counter
Control program
code RAM Timer 0 Inputs

CPU

Bus Serial
4 I/O Ports
OSC Control Port

P0 P1 P2 P3 TxD RxD
Address/Data

10
11
Pin Description of the 8051

P1.0 1 40 Vcc
P1.1 2 39 P0.0(AD0)
P1.2 3 38 P0.1(AD1)
P1.3
P1.4
4
5
8051 37
36
P0.2(AD2)
P0.3(AD3)
P1.5 6 (8031) 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
RST 9 32 P0.7(AD7)
(RXD)P3.0 10 31 EA/VPP
(TXD)P3.1 11 30 ALE/PROG
(INT0)P3.2 12 29 PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)

12
Pins of 8051

 Vcc (pin 40)

 Vcc provides supply voltage to the chip.
 The voltage source is +5V.
 GND (pin 20): ground
 XTAL1 and XTAL2 (pins 19,18)

13
XTAL Connection to 8051

 Using a quartz crystal oscillator

 We can observe the frequency on the XTAL2 pin.

C2
XTAL2
30pF

C1
XTAL1
30pF

GND

14
Pins of 8051
 RST (pin 9): reset
 It is an input pin and is active high, normally low.
 The high pulse must be high at least 2 machine cycles.
 It is a power-on reset.
 Upon applying a high pulse to RST, the
microcontroller will reset and all values in registers
will be lost.
 Reset values of some 8051 registers
 ACC, B, DPTR, and Most of the registers having 0
 SP=07H, Port pins are logic 1

15
Power-On RESET Circuit
Vcc

10 uF 31
EA/VPP
30 pF X1
19
11.0592 MHz
8.2 K
X2
18
30 pF
9 RST

16
Pins of 8051

 /EA（pin 31）：external access

 There is no on-chip ROM in 8031 and 8032 .
 The /EA pin is connected to GND to indicate the code is
stored externally.
 /PSEN ＆ ALE are used for external ROM.
 For 8051, /EA pin is connected to Vcc.
 “/” means active low.
 /PSEN（pin 29）：program store enable
 This is an output pin and is connected to the OE pin of the
ROM.

17
Pins of 8051
 ALE（pin 30）: address latch enable
 It is an output pin and is active high.
 8051 port 0 provides both address and data.
 The ALE pin is used for de-multiplexing the address
and data by connecting to the G pin of the 74LS373
latch.
 I/O port pins
 The four ports P0, P1, P2, and P3.
 Each port uses 8 pins.
 All I/O pins are bi-directional.

18
Pins of I/O Port
 The 8051 has four I/O ports
 Port 0 （pins 32-39）：P0（P0.0～P0.7）
 Port 1（pins 1-8） ：P1（P1.0～P1.7）
 Port 2（pins 21-28）：P2（P2.0～P2.7）
 Port 3（pins 10-17）：P3（P3.0～P3.7）
 Each port has 8 pins.
 Named P0.X （X=0,1,...,7）, P1.X, P2.X, P3.X
 Ex：P0.0 is the bit 0（LSB）of P0
 Ex：P0.7 is the bit 7（MSB）of P0
 These 8 bits form a byte.
 Each port can be used as input or output (bi-direction).

19
Hardware Structure of I/O Pin
 Each pin of I/O ports
 Internal CPU bus：communicate with CPU
 A D latch store the value of this pin
 D latch is controlled by “Write to latch”
 Write to latch＝1：write data into the D latch
 2 Tri-state buffer：
 TB1: controlled by “Read pin”
 Read pin＝1：really read the data present at the pin
 TB2: controlled by “Read latch”
 Read latch＝1：read value from internal latch
 A transistor M1 gate
 Gate=0: open
20
 Gate=1: close
D Latch:

21
A Pin of Port 1
Read latch Vcc
TB2
Load(L1)

Internal CPU D Q P1.X

bus P1.X pin

Write to latch Clk Q M1

TB1
Read pin

8051 IC 22
 Writing “1” to Output Pin P1.X
Read latch Vcc
TB2
Load(L1) 2. output pin is
1. write a 1 to the pin Vcc
D Q
1 P1.X
Internal CPU
bus P1.X pin
0 output 1
Write to latch Clk Q M1

TB1
Read pin

8051 IC 23
 Writing “0” to Output Pin P1.X
Read latch Vcc
TB2
Load(L1) 2. output pin is
1. write a 0 to the pin ground
D Q
0 P1.X
Internal CPU
bus P1.X pin
1 output 0
Write to latch Clk Q M1

TB1
Read pin

24
 Reading “High” at Input Pin
Read latch Vcc 2. MOV A,P1
TB2 external pin=High
1. write a 1 to the pin MOV Load(L1)
P1,#0FFH

1 1 P1.X pin
Internal CPU bus D Q
P1.X
0 M1
Write to latch Clk Q

TB1
Read pin
3. Read pin=1 Read latch=0
Write to latch=1

25
 Reading “Low” at Input Pin
Read latch Vcc 2. MOV A,P1
TB2
1. write a 1 to the pin Load(L1) external pin=Low
MOV P1,#0FFH
1 0 P1.X pin
Internal CPU bus D Q
P1.X
0 M1
Write to latch Clk Q

TB1
Read pin
3. Read pin=1 Read latch=0
Write to latch=1

26
Port 3 Alternate Functions

P3 Bit Function Pin

P3.0 RxD 10
P3.1 TxD 11
P3.2 INT0 12
P3.3 INT1 13
P3.4 T0 14
P3.5 T1 15
P3.6 WR 16
P3.7 RD 17
27
 Registers
A

R0
DPTR DPH DPL
R1

R2 PC PC
R3

R4 Some 8051 16-bit Register

R5

R6

R7

Some 8-bitt Registers of

the 8051

28
Memory mapping in 8051

 ROM memory map in 8051 family

4k 8k 32k
0000H 0000H 0000H

0FFFH
DS5000-32

1FFFH
8751
AT89C51
8752
AT89C52 7FFFH

from Atmel Corporation

from Dallas Semiconductor

29
RAM memory space allocation in the 8051
7FH

Scratch pad RAM

30H

2FH
Bit-Addressable RAM

20H
1FH Register Bank 3
18H
17H
Register Bank 2
10H
0FH (Stack) Register Bank 1
08H
07H
Register Bank 0
00H

30
Memory Space

31
Bit Addressable RAM

Summary
of the 8051
on-chip
data
memory
(RAM)

32
 Bit Addressable RAM

Summary
of the 8051
on-chip
data
memory
(Special
Function
Registers)

33
Register Banks

 Four banks of 8 byte-sized registers, R0 to R7

 Addresses are :
18 - 1F for bank 3
10 - 17 for bank 2
08 - 0F for bank 1
00 - 07 for bank 0 (default)

34
 Address Multiplexing for External Memory

Multiplexing
the address
(low-byte)
and data
bus

35
 Accessing External Code Memory

Accessing
external
code
memory

36
37
 Accessing External
Data Memory

Figure
2-11
Interface
to 1K
RAM

38
Assembler Directives

 Assembler Directives are Instructions for the

ASSEMBLER
 NOT 8051 instructions
 Examples:
cseg stands for “code segment”
cseg 1000h ;address of next instruction
is 1000h
GREEN_LED equ P1.6 ;symbol for Port 1, bit 6

39
Assembler Directives
 DATA
 Used to define a name for memory locations
SP DATA 0x81 ;special function registers
MY_VAL DATA 0x44 ;RAM location

Address
 EQU
 Used to create symbols that can be used to
represent registers, numbers, and addresses
LIMIT EQU 2000
VALUE EQU LIMIT – 200 + 'A'
SERIAL EQU SBUF
COUNT EQU R5
MY_VAL EQU 0x44 Registers, numbers, addresses

40
Addressing Modes

 The various addressing modes of a microprocessor are

determined when it is designed, and therefore cannot be
changed by the programmer.
 The 8051 provides a total of five distinct addressing modes.
(1) immediate
(2) register
(3) direct
(4) register indirect
(5) indexed

41
Immediate addressing mode

 The operand comes immediately after the op-code.

 The immediate data must be preceded by the pound sign,
"#".

42
Register addressing mode

 Register addressing mode involves the use of registers to

hold the data to be manipulated.

43
ACCESSING MEMORY USING VARIOUS
ADDRESSING MODES

Direct addressing mode

There are 128 bytes of RAM in the 8051.
The RAM has been assigned addresses 00 to 7FH.
 1. RAM locations 00 - 1 FH are assigned to the register
banks and stack.
 2. RAM locations 20 - 2FH are set aside as bit-addressable
space to save singlebit data.
 3. RAM locations 30 - 7FH are available as a place to save
byte-sized data.

44
Direct addressing mode

 It is most often used to access RAM locations 30 - 7FH.

 This is due to the fact that register bank locations are

accessed by the register names of R0 - R7.

 There is no such name for other RAM locations so must use

direct addressing.

45
Direct addressing mode

 In the direct addressing mode, the data is in a RAM memory

location whose address is known, and this address is given as
a part of the instruction.

46
Special Function Registers

In the 8051, registers A, B, PSW, and DPTR are

part of the group of registers commonly referred to
as SFR.
The SFR can be accessed by their names or by their
addresses.
For example, register A has address E0H and
register B has been designated the address F0H.

47
SFR

48
ACCESSING MEMORY USING VARIOUS
ADDRESSING MODES

SFR registers and their addresses 49

Stack and direct addressing mode

 Another major use of direct addressing mode is the stack.

 In the 8051 family, only direct addressing mode is allowed
for pushing onto the stack.
 An instruction such as "PUSH A" is invalid. Pushing the
accumulator onto the stack must be coded as "PUSH
0E0H.
 Direct addressing mode must be used for the POP instruction
as well.
 "POP 04" will pop the top of the stack into R4 of bank 0.

50
Register indirect addressing mode

 A register is used as a pointer to the data.

 If the data is inside the CPU, only registers R0 and R 1 are

used for this purpose.

 R2 - R7 cannot be used to hold the address of an operand

located in RAM when using indirect addressing mode.

 When RO and R 1 are used as pointers they must be

preceded by the @ sign.

51
Register indirect addressing mode

52
Advantage of register indirect addressing mode

One of the advantages of register indirect

addressing mode is that it makes accessing data
dynamic rather than static as in the case of direct
addressing mode.

Looping is not possible in direct addressing mode.

This is the main difference between the direct and

register indirect addressing modes.

53
Advantage of register indirect addressing mode

54
Limitation of register indirect addressing mode in the 8051

 R0 and R1 are the only registers that can be used for pointers
in register indirect addressing mode.

 Since R0 and Rl are 8 bits wide, their use is limited to

accessing any information in the internal RAM (scratch pad
memory of 30H - 7FH, or SFR).

 To access data stored in external RAM or in the code space

of on-chip ROM, we need a 16-bit pointer, the DPTR.

55
Indexed addressing mode and on-chip ROM access

 Indexed addressing mode is widely used in accessing data

elements of look-up table entries located in the program
ROM space of the 8051.
 The instruction used for this purpose is :
MOVC A, @ A+DPTR
 The 16-bit register DPTR and register A are used to form the
address of the data element stored in on-chip ROM.
 Because the data elements are stored in the program (code)
space ROM of the 8051, the instruction MOVC is used
instead of MOV. The "C" means code.
 In this instruction the contents of A are added to the 16-bit
register DPTR to form the 16bit address of the needed data.

56
Indexed addressing mode and MOVX instruction

 The 8051 has another 64K bytes of memory space set aside
exclusively for data storage.
 This data memory space is referred to as external memory
and it is accessed by the MOVX instruction.
 The 8051 has a total of 128K bytes of memory space since
64K bytes of code added to 64K bytes of data space gives us
128K bytes.
 One major difference between the code space and data space
is that, unlike code space, the data space cannot be shared
between code and data.

57
BIT ADDRESSES FOR I/O AND RAM

58
BIT ADDRESSES FOR I/O AND RAM

59
Instruction set
 Arithmetic Instructions
 Logical Instruction
 Data Transfer
 Boolean Variable Manipulation
 Program Branching

60
Arithmetic Instructions

61
Logical Instructions

62
Data Transfers

63
Data Transfers

64
Boolean Manipulation Instructions

65
Program Branching Instructions

66
Interrupts, Timers and Serial
Communication
Interrupts
Interrupt Sources:
• The 8051 architecture can handle interrupts from 5 sources.
• Two external interrupt lines, two timers and the serial interface.
• Each one of these is assigned an interrupt vector address.
External Interrupts
• Port P3 of 8051 is a multi-function port.
• Different lines of this port carry out functions which are additional to
data input-output on the port.
Interrupts
• Additional functions of Port 3 lines Lines P3.2 and P3.3 can be used as
interrupt inputs.
• Interrupts will be caused by a ‘LOW’ level, or a negative edge on these
lines.
• Half of the special function register TCON is used for setting the
conditions for causing interrupts from external sources.
TCON Register
• IT1 and IT0 are the “Interrupt Type” flags for external sources 1 and 0
respecively.
• These decide whether a negative going edge or a ‘LOW’ level will cause an
interrupt.
• If the bit is set, the corresponding interrupt is edge sensitive.
• If it is cleared,the interrupt is level sensitive.
• IE1 and IE0 are the status flags for the two external interrupt lines.
• If the flag is 1, the selected type of event (edge or level) has occured on the
corresponding interrupt line.
TCON Register:

• TF1: Timer 1 overflow flag.

• TR1: Timer 1 run control bit.
• TF0: Timer 0 overflag.
• TR0: Timer 0 run control bit.
• IE1: External interrupt 1 edge flag.
• IT1: External interrupt 1 type flag.
• IE0: External interrupt 0 edge flag.
• IT0: External interrupt 0 type flag.
Interrupt :
Interrupt Enable Register :

• EA : Global enable/disable.
• --- : Undefined.
• ET2 :Enable Timer 2 interrupt.
• ES :Enable Serial port interrupt.
• ET1 :Enable Timer 1 interrupt.
• EX1 :Enable External 1 interrupt.
• ET0 : Enable Timer 0 interrupt.
• EX0 : Enable External 0 interrupt.
Interrupt Priority Register

- IP.7,IP.6 Reserved for future use.

&IP.5
PS IP.4 It defines the serial port interrupt priority level.

PT1 IP.3 It defines the timer interrupt of 1 priority.

PX1 IP.2 It defines the external interrupt priority level.

PT0 IP.1 It defines the timer0 interrupt priority level.

PX0 IP.0 It defines the external interrupt of 0 priority level.

TIMERS
TIMERS
8051 SERIAL COMMUNICATION
Basics of serial communication
Start and stop bits
RS232 pins
Data communication classification
 RxD and TxD pins in the 8051
 TxD pin 11 of the 8051 (P3.1)
 RxD pin 10 of the 8051 (P3.0)
MAX232
MAX233
8051 SERIAL COMMUNICATION
PROGRAMMING
 SBUF register
MOV SBUF,#’D’ ;load SBUF=44H, ASCII for ‘D’
MOV SBUF,A ;copy accumulator into SBUF
MOV A,SBUF ;copy SBUF into accumulator
SCON (Serial control) register
SM0,SM1
SM0 and SM1 are D7 and D6 of the SCON

SM0 SM1
0 0 Serial Mode 0
0 1 Serial Mode 1,8 bit data,
1 stop bit, 1 start bit
1 0 Serial Mode 2
1 1 Serial Mode 3
Programming the 8051 to transfer data serially
Programming the 8051 to receive
data serially
 Doubling the baud rate in the
8051
1. To use a higher frequency crystal
2. To change a bit in the PCON register
D7 D0
SMO -- -- -- GF1 GF0 PD IDL
D

MOV A,PCON ;place a copy of PCON in ACC

SETB ACC.7 ;make D7=1
MOV PCON,A ;now SMOD=1 without
;changing any other bits
 Baud rates for SMOD=0
Machine cycle freq. = 11.0592 MHz / 12 = 921.6 kHz
and
921.6 kHz / 32 = 28,800 Hz since SMOD = 0
 Baud rates for SMOD=1
Machine cycle freq. = 11.0592 MHz / 12 = 921.6 kHz
and
921.6 kHz / 16 = 57,600 Hz since SMOD = 1
 Sample Programs
1. Write an ALP program for 8051 to arrange the given N-
numbers in an ascending order
2. Write an ALP program for 8051 to find the average of N-
numbers.
3. Write a program to monitor the bit P1.3. When it is high send
55H to port P2.
4. Write a program for 8051 to generate a square wave with 60%
duty cycle from port 1.
5. Write a program for 8051 to generate a Triangular wave with
2KHz frequency from port 3.
6. Write a program for 8051 to transfer the message "TECH"
serially at 9600 baud, 8-bit data, 1 stop bit. Do this
continuously.
 Assignment-1
Class: III ECE (Section: A&B)
Last Date to submit the assignment: 31/08/2024

1. Draw the architecture of 8086 microprocessor and explain the functions of BIU and
EU?
2. Explain the need for Memory segmentation in 8086.
3. Explain the register organization of 8086.
4. Draw the structure 8086 flag register and explain the function of each flags.
5. Explain the Physical memory organization of 8086.
6. Write an efficient assembly language program (minimum code length) for 8086 MP for
a system has four inputs and four outputs. The four output bits represents the gray code
equivalent of input binary number.
7. Write a program for 8086 processor to generate the Fibonacci series (Each number in
the Fibonacci series is the sum of the previous two numbers.)
8. Write an assembly language program for 8086 MP to model the 4x16 decoder.
9. Draw and explain the internal Architecture of 8051 microcontroller
10. Draw the pin diagram of 8051 and explain the functionality of each pin
11. List the addressing modes of the 8051 and explain each addressing mode with an
example.
12. List the timers and associated registers in 8051 and explain the various modes of
timers.
13. List the interrupts of 8051 and explain each.
14. Write an ALP program for 8051 to arrange the given N-numbers in an ascending
order
15. Write an ALP program for 8051 to find the average of N-numbers.
16. Write a program for 8051 to generate a square wave with 60% duty cycle from port 1.
ARM Processors
 Introduction
• ARM Acorn RISC Machine, is a family of reduced instruction set computing
(RISC) architectures for computer processors, configured for various
environments.
• Arm Holdings develops the architecture and licenses it to other companies,
who design their own products that implement one of those architectures
• including systems-on-chips (SoC) and systems-on-modules (SoM) that incorporate
memory, interfaces, radios, etc.
• It also designs cores that implement this instruction set and licenses these
designs to a number of companies that incorporate those core designs into
their own products.
 Acorn RISC Machine
• The official Acorn RISC Machine project started in October 1983. VLSI
Technology, Inc was chosen as silicon partner, since it already supplied Acorn with
ROMs and some custom chips.
• VLSI produced the first ARM silicon on 26 April 1985 – it worked first time and
came to be known as ARM1 by April 1985. The first "real" production systems
named ARM2 were available the following year.
• Its first practical application was as a second processor to the BBC Micro.
• The original aim of a principally ARM-based computer was achieved in 1987 with
the release of the Acorn Archimedes.
• The ARM2 featured a 32-bit data bus, a 26-bit address space and sixteen 32-bit
registers. Program code had to lie within the first 64 Mbyte of the memory, as the
program counter was limited to 26 bits because the top 4 and bottom 2 bits of the
32-bit register served as status flags.

• The ARM2 was possibly the simplest useful 32-bit microprocessor in the world,
with only 30,000 transistors (compare the transistor count with Motorola's six-
year older 68000 model with around 70,000 transistors).
 Apple, DEC, Intel: ARM6, StrongARM, XScale
• In the late 1980s Apple Computer and VLSI Technology started working with Acorn on
newer versions of the ARM core. The work was so important that Acorn spun off the design
team in 1990 into a new company called Advanced RISC Machines Ltd.
• For this reason, ARM is sometimes expanded as Advanced RISC Machine instead of Acorn
RISC Machine.
• The new Apple-ARM work would eventually turn into the ARM6, first released in early
1992. Apple used the ARM6-based ARM 610 as the basis for their Apple Newton PDA.
• In 1994, Acorn used the ARM 610 as the main CPU in their Risc PC computers. DEC
licensed the ARM6 architecture and produced the StrongARM. At 233 MHz this CPU drew
only 1 Watt of power.
• This work was later passed to Intel as a part of a lawsuit settlement, and Intel took the
opportunity to supplement their aging i960 line with the StrongARM. Intel later developed
its own high performance implementation known as Xscale.
 Licensing growth
• ARM2 had 30,000 transistors, while the ARM6 grew to only 35,000.

• ARM's business has always been to sell IP cores, which licensees use to
create microcontrollers and CPUs based on this core.

• The most successful implementation has been the ARM7TDMI with hundreds
of millions sold.

• The idea is that the Original Design Manufacturer combines the ARM core
with a number of optional parts to produce a complete CPU.
 Market Share
• In 2005, about 98% of all mobile phones sold used at least one Arm
processor.
• In 2010, producers of chips based on Arm architectures reported shipments
of 6.1 billion Arm‐based processors, representing 95% of smartphones, 35%
of digital televisions and set‐top boxes and 10% of mobile computers.
• In 2011, the 32‐bit Arm architecture was the most widely used architecture
in mobile devices and the most popular 32‐bit one in embedded systems.
• In 2013, 10 billion were produced and "Arm‐based chips are found in nearly
60 percent of the world's mobile devices”.
 Advantage of ARM
• Processors that have a RISC architecture typically require fewer transistors than
those with a complex instruction set computing (CISC) architecture (such as the
x86 processors found in most personal computers), which improves cost,
power consumption, and heat dissipation.
• These characteristics are desirable for light, portable, battery‐powered devices
— including smartphones, laptops and tablet computers, and other embedded
systems but are also useful for servers and desktops to some degree.
• For supercomputers, which consume large amounts of electricity, Arm is also a
power‐efficient solution.
 ARM Architecture
• Arm Holdings periodically releases updates to the architecture.
• Architecture versions Armv3 to Armv7 support 32‐bit address space and 32‐bit
arithmetic.
• Most architectures have 32‐bit fixed‐length instructions.
• The Thumb version supports a variable‐length instruction set that provides both
32‐ and 16‐bit instructions for improved code density.
• The Armv8‐A architecture added support for a 64‐bit address space and 64‐bit
arithmetic with its new 32‐bit fixed length instruction set.
 ARM Architecture
• The Arm architectures used in smartphones, PDAs and other mobile
devices range from Armv5 to Armv7‐A, used in low‐end and midrange
devices.
• Armv8‐A used in current high‐end devices.
• In 2009, some manufacturers introduced netbooks based on Arm
architecture CPUs, in direct competition with netbooks based on Intel
Atom.
• Arm Holdings offers a variety of licensing terms, varying in cost and
deliverables.
 ARM License
• Arm Holdings prices its IP based on perceived value.

• Lower performing Arm cores typically have lower license costs

than higher performing cores.

• In implementation terms, a synthesizable core costs more than a

hard macro (blackbox) core.
 Built on Arm Cortex Technology license
• In February 2016, Arm announced the Built on Arm Cortex Technology
license, often shortened to Built on Cortex (BoC) license.
• This license allows companies to partner with Arm and make
modifications to Arm Cortex designs.
• These design modifications will not be shared with other companies.
• These semi‐custom core designs also have brand freedom, for example
Kryo 280.
• Companies that are current licensees of Built on Arm Cortex Technology
include Qualcomm.
ARM architectures and Cores
ARM architectures and Cores
ARM architectures and Cores
 Processor Core Naming Conventions
• T - Thumb architecture extension -> two separate instruction sets
• 32-bit ARM Instructions
• 16-bit Thumb instructions
• Two execution states to select which instruction set to execute
• D - debug extension adds
• Scan chains 0 and 1 around the core
• Additional signals on the core to allow program execution to be controlled (from
Breakpoints and Watch points)
• M - Core has enhanced multiplier with instructions for 64-bit results.
• I - Embedded ICE Macrocell adds
• Logic to implement Breakpoints and Watch points, and use the debug features of the
core.
• Scan chain 2 to communicate with the Embedded ICE Macrocell
• Test Access Port Controller to allow access to the scan chains
• Bus splitter, providing unidirectional data buses
• S - Fully synthesizable
• E - DSP extensions
• Enhanced instructions for efficient fractional saturating arithmetic
• Single cycle 32x16 multiplier implementation
• 32x16 and 16x16 multiply instructions
• J - Java acceleration through Jazelle
• Embedded Jazelle hardware acceleration
• Reduced complexity & power consumption over a typical Java hardware
coprocessor solution
Naming of Classic ARM Processors; “(F)” Means Optional
Floating Point Unit
 ARM Architecture
 Based upon RISC Architecture with enhancements to meet requirements of
embedded applications
 A large uniform register file
 Load-store architecture

 Fixed length instructions

 32-bit processor (v1-v7), 64-bit processor (v8)
 Good speed/power
 High code density
Enhancement to Basic RISC
 Control over both ALU and shifter for every data processing operations
 ADD r2, r3, r4, LSL #2 ; r2 = r3 + (r4 * 4)

 Auto-increment and auto-decrement addressing modes

 To optimize program loops
 Load/Store multiple data instructions
 To maximize data throughput
 LDM, STM
 Conditional execution of instructions
 To maximize execution throughput
Embedded Processors
Application Processors
ARM Processor Family
Summary of Processor Characteristics
Pipeline
ARM Cortex Advanced Processors
Application Examples
Architecture History
Development of the ARM Architecture
v4 v5 v6 v7
Halfword and Improved SIMD Instructions
Thumb-2
signed halfword interworking CLZ Multi-processing
/ byte support Saturated arithmetic v6 Memory architecture
Architecture Profiles 7-
DSP MAC Unaligned data support
System mode instructions A - Applications 7-R
Extensions: - Real-time
Thumb Thumb-2 (6T2) 7-M - Microcontroller
instruction set Extensions: TrustZone® (6Z)
(v4T) Jazelle (5TEJ) Multicore (6K)
Thumb only (6-M)

 Note that implementations of the same architecture can be different

 Cortex-A8 - architecture v7-A, with a 13-stage pipeline
 Cortex-A9 - architecture v7-A, with an 8-stage pipeline
Architecture ARMv7 profiles
 Application profile (ARMv7-A)
 Memory management support (MMU)
 Highest performance at low power
 Influenced by multi-tasking OS system requirements
 TrustZone and Jazelle-RCT for a safe, extensible system
 e.g. Cortex-A5, Cortex-A9

 Real-time profile (ARMv7-R)

 Protected memory (MPU)
 Low latency and predictability ‘real-time’ needs
 Evolutionary path for traditional embedded business
 e.g. Cortex-R4

 Microcontroller profile (ARMv7-M, ARMv7E-M, ARMv6-M)

 Lowest gate count entry point
 Deterministic and predictable behavior a key priority
 Deeply embedded use
 e.g. Cortex-M3
 Armv8‐A Architecture
• The Armv8‐A architecture is the latest generation Arm architecture targeted at
the Applications ('A') profile.
• It introduces the ability to use 64‐bit and 32‐bit Execution states, known as
AArch64 and AArch32 respectively.
• The AArch64 Execution state supports the A64 instruction set, holds addresses
in 64‐bit registers and allows instructions in the base instruction set to use 64‐
bit registers for their processing.
• The AArch32 Execution state is a 32‐bit Execution state that preserves
backwards compatibility with the Armv7‐A architecture and enhances that
profile so that it can support some features included in the AArch64 state.
• It supports the T32 and A32 instruction sets.
ARM Architecture
ARM1 Processor Core
Architecture
• The ARM7TDMI processor has two instruction sets:
• the 32-bit ARM instruction set
• the 16-bit Thumb instruction set.
• Uses 0.25μm and less die-size facilitates low voltage operation and
low power consumption.
• Fully static operation.
• Large register set consists of sixteen 32-bit registers.
• There is a three stage pipeline.
• Thirty two-bit Reg ALU and high performance multiplier.
• Instructions process data with 8,16, and 32-bit data types.
Instruction compression
• Microprocessor architectures traditionally have the same width for
instructions and data.
• In comparison with 16-bit architectures, 32-bit architectures exhibit
higher performance when manipulating 32-bit data, and can address a
large address space much more efficiently.
• 16-bit architectures typically have higher code density than 32-bit
architectures, but approximately half the performance.
• Thumb implements a 16-bit instruction set on a 32-bit architecture to
provide:
• higher performance than a 16-bit architecture
• higher code density than a 32-bit architecture.
Thumb instruction set
• The Thumb instruction set is a subset of the most commonly used 32-bit ARM
instructions.
• Thumb instructions are each 16 bits long, and have a corresponding 32-bit ARM
instruction that has the same effect on the processor model.
• Thumb instructions operate with the standard ARM register configuration, allowing
excellent interoperability between ARM and Thumb states.
• On execution, 16-bit Thumb instructions are transparently decompressed to full 32-bit
ARM instructions in real time, without performance loss.
• Thumb has all the advantages of a 32-bit core:
• 32-bit address space
• 32-bit registers
• 32-bit shifter, and Arithmetic Logic Unit (ALU)
• 32-bit memory transfer.
• Thumb therefore offers a long branch range, powerful arithmetic operations, and a
large address space.
• Thumb code is typically 65% of the size of ARM code, and provides 160% of the
performance of ARM code when running from a 16-bit memory system.
• Thumb, therefore, makes the ARM7TDMI core ideally suited to embedded
applications with restricted memory bandwidth, where code density and footprint
is important.
• The availability of both 16-bit Thumb and 32-bit ARM instruction sets gives
designers the flexibility to emphasize performance or code size on a subroutine
level, according to the requirements of their applications.
• For example, critical loops for applications such as fast interrupts and DSP
algorithms can be coded using the full ARM instruction set then linked with
Thumb code.
ARM7TDMI processor core organization
 ARM7TDMI A[31:0]

Block Diagram
Address Register Address
Incrementer

PC bus
PC

REGISTER
BANK
ALU bus

Control Lines
INSTRUCCTION
DECODER
Multiplier
A bus

B bus
SHIFT

A.L.U.
Instruction Reg.

Thumb to
ARM
Write Data Reg. Read Data Reg.
translator

D[31:0]
 ARM Pipelining examples
ARM7TDMI Pipeline

FETCH DECODE EXECUTE

Reg. Reg.
Read Shift ALU Write

1 Clock cycle

ARM9TDMI Pipeline

FETCH DECODE EXECUTE MEMORY WRITE

Reg. Reg.
Shift ALU access
Read Write

1 Clock cycle

• Fetch: Read Op-code from memory to internal Instruction Register

• Decode: Activate the appropriate control lines depending on Opcode
• Execute: Do the actual processing
 ARM7TDMI Pipelining (I)

1 FETCH DECODE EXECUTE

2 FETCH DECODE EXECUTE

3 FETCH DECODE EXECUTE

instruction
time

• Simple instructions (like ADD) Complete at a rate of one per cycle

 ARM7TDMI Pipelining (II)
• More complex instructions:

1 ADD FETCH DECODE EXECUTE

2 STR FETCH DECODE Cal. ADDR Data Xfer.

3 ADD FETCH stall DECODE EXECUTE

4 ADD FETCH stall DECODE EXECUTE

5 ADD FETCH DECODE EXECUTE

instruction
time

STR : 2 effective clock cycles (+1 cycle)

 Data Sizes and instruction Sets
 The ARM is a 32‐bit architecture.

 When used in relation to the ARM:

 Byte means 8 bits
 Halfword means 16 bits (two bytes)
 Word means 32 bits (four bytes)

 Most ARM’s implement two instruction sets

 32‐bit ARM Instruction Set
 16‐bit Thumb Instruction Set
Which architecture is my processor?
Cotex‐M Processor Family
Cortex‐M0
 ARMv6-M Architecture
 16-bit Thumb-2 with system control
instructions
 Fully programmable in C
 3-stage pipeline
 AHB-Lite bus interface
 Fixed memory map
 1-32 interrupts
 Configurable priority levels
 Non-Maskable Interrupt support
 Low power support
 Core configured with or without
debug
 Variable number of watchpoints and
breakpoints
Cortex‐M3
 ARMv7-M Architecture
 Thumb-2 only
 Fully programmable in C
 3-stage pipeline
 Optional MPU
 AHB-Lite bus interface
 Fixed memory map
 1-240 interrupts
 Configurable priority levels
 Non-Maskable Interrupt support
 Debug and Sleep control
 Serial wire or JTAG debug
 Optional ETM
 CortexM3 and CortexM4 Features
• The Cortex‐M3 and Cortex‐M4 are processors designed by ARM. The Cortex‐M3
processor was released by ARM in 2005 and the Cortex‐M4 processor was
released in 2010
• The Cortex‐M3 and Cortex‐M4 processors use a 32‐bit architecture. Internal
registers in the register bank, the data path, and the bus interfaces are all 32 bits
wide.
• The Instruction Set Architecture (ISA) in the Cortex‐M processors is called the
Thumb ISA and is based on Thumb‐2 Technology which supports a mixture of 16‐
bit and 32‐bit instructions.
• Three‐stage pipeline design
• Harvard bus architecture with unified memory space: instructions and data use
the same address space
• 32‐bit addressing, supporting 4GB of memory space
 Cortex ‐M4 Features Contd..
• On‐chip bus interfaces based on ARM AMBA (Advanced Microcontroller Bus
Architecture) Technology, which allow pipelined bus operations for higher
throughput
• An interrupt controller called NVIC (Nested Vectored Interrupt Controller)
supporting up to 240 interrupt requests and from 8 to 256 interrupt priority
levels (dependent on the actual device implementation)
• Support for various features for OS (Operating System) implementation such as a
system tick timer, shadowed stack pointer
• Sleep mode support and various low power features
• Support for an optional MPU (Memory Protection Unit) to provide memory
protection features like programmable memory, or access permission control
• Support for bit‐data accesses in two specific memory regions using a feature
called Bit Band
 ISA used in Cortex‐M3 and Cortex‐M4 processors
• General data processing, including hardware divide instructions
• Memory access instructions supporting 8‐bit, 16‐bit, 32‐bit, and 64‐bit data, as
well as instructions for transferring multiple 32‐bit data
• Instructions for bit field processing
• Multiply Accumulate (MAC) and saturate instructions
• Instructions for branches, conditional branches and function calls
• Instructions for system control, OS support, etc.
 Cortex –M4 also supports
• Single Instruction Multiple Data (SIMD) operations
• Additional fast MAC and multiply instructions
• Saturating arithmetic instructions
• optional floating point instructions (single precision)
• Cortex‐M4 processor to deliver higher performance in DSP
applications, and to support floating point operations.
• some of the instructions available on both processors can be
executed in fewer clock cycles on the Cortex‐M4.
 Advantages of Cortex‐M Processors
• Low power The Cortex‐M processor designs are also optimized for low power
consumption. Currently, many Cortex‐M microcontrollers have power
consumption of less than 200 mA/MHz, with some of them well under 100
mA/MHz.
• The Cortex‐M processors also include support for sleep mode features and can be
used with various advanced ultra‐low power design technologies.
• Performance The Cortex‐M3 and Cortex‐M4 processors can deliver over 3
CoreMark/MHz and 1.25 DMIPS/MHz (based on the Dhrystone 2.1 benchmark).
This allows Cortex‐M3 and Cortex‐M4 microcontrollers to handle many complex
and demanding applications.
• Energy efficiency Combining low power and high‐performance characteristics,
the Cortex‐M3 and Cortex‐M4 processors have excellent energy efficiency. This
means that, you can still do a lot of processing, with a limited supply of energy
 Advantages Cortex‐M Contd..
• Code density The Thumb ISA provides excellent code density. This means that to
achieve the same tasks, you need a smaller program size. As a result you can
reduce cost and power consumption by using a microcontroller with smaller flash
memory size, and chip manufacturers can produce microcontroller chips with
smaller packages.
• Interrupts Cortex‐M3 and Cortex‐M4 processors have a configurable interrupt
controller design, which can support up to 240 vectored interrupts and multiple
levels of interrupt priorities (from 8 to 256 levels). Nesting of interrupts is
automatically handled by hardware, and the interrupt latency is only 12 clock
cycles for systems with zero wait state memory
• Ease of use, C friendly The Cortex‐M processors are very easy to use. In fact, they
are easier than compared to many 8‐bit processors because Cortex‐M processors
have a simple, linear memory map
 Advantages of Cortex‐M Contd..
• Scalability The Cortex‐M processor family allows easy scaling of designs from low‐
cost, simple microcontrollers costing less than a dollar to high‐end
microcontrollers running at 200MHz or more.
• You can also find Cortex‐M microcontrollers with multiprocessor designs. With all
these, due to the consistency of the processor architecture, you only need one
tool chain and you can reuse your software easily.
• Debug features The Cortex‐M processors include many debug features that allow
you to analyze design problems easily. Besides standard design features, which
you can find in most microcontrollers like halting and single stepping, you can
also generate a trace to capture program flow, data changes, profiling
information, and so on.
• OS support The Cortex‐M processors are designed with OS applications in mind.
A number of features are available to make OS implementation easier and make
OS operations more efficient. Currently there are over 30 embedded OSs
available for Cortex‐M processors.
 Advantages of Cortex‐M Contd..
• Versatile system features The Cortex‐M3 and Cortex‐M4 processors support a
number of system features such as bit addressable memory range (bit band
feature) and MPU (Memory Protection Unit)

• Software portability and reusability Since the architecture is very C friendly, you
can program almost everything in standard ANSI C. One of ARM’s initiatives called
CMSIS (Cortex Microcontroller Software Interface Standard) makes programming
for Cortex‐M processor based products even easier by providing standard header
files and an API for standard Cortex‐M processor functions. This allows better
software reusability and also makes porting application code easier.

• Choices (devices, tools, OS, etc.) One of the best things about using Cortex‐M
microcontrollers number amount of available choices. Besides the thousands of
microcontroller devices available, you also have a wide range of coins on software
development/debug tools, embedded OS, middleware, etc.
 Applications of ARM Cortex‐M Processors
• Microcontrollers: The Cortex‐M processor family is ideally suited for microcontroller
products consumer products, from toys to electrical appliances, or even specialized
products for Information Technology (IT), industrial, or even medical systems
• Automotive: Another application for the Cortex‐M3 and Cortex‐M4 processors is in the
automotive industry. As these processors offer great performance, very high energy
efficiency, and low interrupt latency, they are ideal for many real‐time control systems
and for highly integrated ASSPs (Application Specific Standard Products) for the
automotive industry.
• Data communications: The processor’s low power and high efficiency, coupled with
instructions in Thumb‐2 for bit‐field manipulation, make the Cortex‐M3 and Cortex‐M4
processors ideal for many communication applications, such as Bluetooth and ZigBee
• Industrial control: In industrial control applications, simplicity, fast response, and
reliability are key factors.
• Again, the interrupt support features on Cortex‐M3 and Cortex‐M4 processors, including
their deterministic behavior, automatic nested interrupt handling, MPU, and enhanced
fault‐handling, make them strong candidates in this area
 Applications of Cortex –M Processors
• Consumer products: In many consumer products, a high‐performance
microprocessor (or several) is used. The Cortex‐M3 and Cortex‐M4 processors,
being small, are highly efficient and low in power, and at the same time provide
the performance required for handling complex GUIs on LCD panels and various
communication protocols
• Systems‐on‐Chips (SoC): In some high‐end application processor designs, Cortex‐
M processors are used in various subsystems such as audio processing engines,
power management systems, FSM (Finite State Machine) replacement, I/O
control task off loading, etc.
• Mixed signal designs: In the IC design world, the digital and analog designs are
converging. While microcontrollers contain more and more analogue components
(e.g., ADC, DAC), some analog ICs such as sensors, PMIC (Power Management IC),
and MEMS (Microelectromechanical Systems) now also include processors to
provide additional intelligence.
Cortex –M4 block diagram
Data Sizes and instruction Sets
 The ARM is a 32‐bit architecture.

 When used in relation to the ARM:

 Byte means 8 bits
 Halfword means 16 bits (two bytes)
 Word means 32 bits (four bytes)

 Most ARM’s implement two instruction sets

 32‐bit ARM Instruction Set
 16‐bit Thumb Instruction Set
 Processor Modes
 The ARM has seven operating modes:
 User : unprivileged mode under which most tasks run

 FIQ : entered when a high priority (fast) interrupt is raised

 IRQ : entered when a low priority (normal) interrupt is raised

 SVC : (Supervisor) entered on reset and when a Software Interrupt

instruction is executed

 Abort : used to handle memory access violations

 Undef : used to handle undefined instructions

 System : privileged mode using the same registers as user mode

 The Registers
 ARM has 37 registers all of which are 32-bits long.
 1 dedicated program counter
 1 dedicated current program status register
 5 dedicated saved program status registers
 30 general purpose registers
 The current processor mode governs which of several banks is
accessible. Each mode can access
 a particular set of r0-r12 registers
 a particular r13 (the stack pointer, sp) and r14 (the link register, lr)
 the program counter, r15 (pc)
 the current program status register, cpsr

Privileged modes (except System) can also access

 a particular spsr (saved program status register)
 The ARM Register Set
Current Visible Registers
Current
Abort Mode Visible
r0 Registers
r1
r0
Undef
SVCMode
User
IRQ
FIQ Mode
Mode
Mode r2
r1
r3
r2 Banked out Registers
r4
r3
r5
Banked out Registers
r4
User,
r6
r5 FIQ IRQ SVC Undef
SYS
r7
r6 User FIQ IRQ SVC Undef Abort
r7
r8 r8
r8
r9 r8 r8
r9
r9
r10 r9 r9
r10
r10
r11 r10 r10
r11
r11 r11 r11
r12 r12
r12 r12 r12
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r15
r15 (pc)
(pc)

cpsr
cpsr
spsr spsr spsr spsr spsr spsr
 Special Registers
 Special function registers:
 PC (R15): Program Counter. Any instruction with PC as its destination register is a program branch

 LR (R14): Link Register. Saves a copy of PC when executing the BL instruction (subroutine call) or when
jumping to an exception or interrupt routine
‐ It is copied back to PC on the return from those routines

 SP (R13): Stack Pointer. There is no stack in the ARM architecture. Even so, R13 is usually reserved as a
pointer for the program‐managed stack

 CPSR : Current Program Status Register. Holds the visible status register

 SPSR : Saved Program Status Register. Holds a copy of the previous status register while executing
exception or interrupt routines
‐ It is copied back to CPSR on the return from the exception or interrupt
‐ No SPSR available in User or System modes
Register Organization Summary
User,
FIQ IRQ SVC Undef Abort
SYS
r0
r1
User
r2 mode
r3 r0-r7,
r4 r15, User User User User
r5 and mode mode mode mode
cpsr r0-r12, r0-r12, r0-r12, r0-r12,
r6
r15, r15, r15, r15,
r7 and and and and
r8 r8 cpsr cpsr cpsr cpsr
r9 r9
r10 r10
r11 r11
r12 r12
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r15 (pc)

cpsr
spsr spsr spsr spsr spsr

Note: System mode uses the User mode register set

Program Status Registers
31 28 27 24 23 16 15 8 7 6 5 4 0

N Z C V undefined I F T mode

f s x c

 Condition code flags Interrupt Disable bits.

 N = Negative result from ALU I = 1: Disables the IRQ.
 Z = Zero result from ALU F = 1: Disables the FIQ.
 C = ALU operation Carried out
 V = ALU operation oVerflowed
T Bit (Arch. with Thumb mode only)
T = 0: Processor in ARM state
 Mode bits T = 1: Processor in Thumb state
10000 User
Never change T directly (use BX instead)
10001 FIQ
Changing T in CPSR will lead to unexpected
10010 IRQ behavior due to pipelining
10011 Supervisor
10111 Abort Tip: Don’t change undefined bits.
11011 Undefined This allows for code compatibility with
11111 System newer ARM processors
 Program Counter (R15)
 When the processor is executing in ARM state:
 All instructions are 32 bits wide
 All instructions must be word aligned
 Therefore the PC value is stored in bits [31:2] and bits [1:0] are zero
 Due to pipelining, the PC points 8 bytes ahead of the current instruction, or 12 bytes ahead if
current instruction includes a register‐specified shift

 When the processor is executing in Thumb state:

 All instructions are 16 bits wide
 All instructions must be halfword aligned
 Therefore the PC value is stored in bits [31:1] and bit [0] is zero
 Exception Handling
 When an exception occurs, the ARM:
 Copies CPSR into SPSR_<mode>
 Sets appropriate CPSR bits:
 Changes to ARM state
 Changes to related mode
 Disables IRQ 0x1C FIQ
 Disables FIQ (only on fast interrupts) 0x18 IRQ
 Stores the return address in LR_<mode> 0x14 (Reserved)
 Sets PC to vector address 0x10 Data Abort
0x0C Prefetch Abort
 To return, exception handler needs to:
0x08 Software Interrupt
 Restore CPSR from SPSR_<mode>
0x04 Undefined Instruction
 Restore PC from LR_<mode> 0x00 Reset
(more about this later…)
Vector Table
This can only be done in ARM state.
 ARM pipeline
• The 3-stage pipeline

• The original 3-stage ARM pipeline that remained essentially unchanged from the first
ARM processor to the ARM7TDMI core.
• It is a classical fetch-decode-execute pipeline, which, in the absence of pipeline
hazards and memory accesses, completes one instruction per cycle.
• The first pipeline stage reads an instruction from memory and increments the value of
the instruction address register, which stores the value of the next instruction to be
fetched.
• The next stage decodes the instruction and prepares control signals required to execute
it on.
• The third stage does all the actual work: it reads operands from the register file,
performs ALU operations, reads or writes memory, if necessary, and finally writes
back modified register values.
• In case the instruction being executed is a data processing instruction, the result
generated by the ALU is written directly to the register file and the execution stage
completes in one cycle.
The 3-stage pipeline
 The 5-stage pipeline
• Only one memory port, which means that every data transfer instruction
causes a pipeline stall, because the next instruction cannot be fetched
while memory is being read or written.
• ARM9TDMI and later micro-architectures, is to use separate instruction
and data caches. This allows to modify the pipeline to avoid stalls on
data transfer instructions.
• First, to make the pipeline more balanced, ARM9TDMI moved the
register read step to the decode stage, since instruction decode stage was
much shorter than the execute stage. Second, the execute stage was split
into 3 stages.
• The first stage performs arithmetic computations,
• Second stage performs memory accesses
• Third stage writes the results back to the register file.
5-stage pipeline
 Processor Core Vs CPU Core
 Processor Core
– The engine that fetches instructions and execute them
– E.g.: ARM7TDMI, ARM9TDMI, ARM9E-S

 CPU Core virtual address

– Consists of the ARM processor

core and some tightly coupled instruction & ARM7TDMI
function blocks MMU
data cache
EmbeddedICE
& JTAG
– Cache and memory
management blocks

address
physical
– E.g.: ARM710T, ARM720T, instructions & data

ARM74T, ARM920T, ARM922T, write

buffer CP15
ARM940T, ARM946E-S, and
ARM966E-S AMBA interface

AMBA AMBA
address data
ARM710T

73
CPU cores
• ARMv1
First version of ARM processor
26‐bit addressing, no multiply / coprocessor

• ARMv2
ARM2, First commercial chip
Included 32‐bit result multiply instructions /
coprocessor support

74
 CPU cores
 ARMv2a
ARM3 chip with on‐chip cache
Added load and store
cache management

 ARMv3
ARM6, 32 bit addressing, virtual
memory support

75
ARM Processor Core
 Current low‐end ARM core for applications like digital
mobile phones
 TDMI
 T: Thumb, 16‐bit instruction set
 D: on‐chip Debug support, enabling the processor to halt in
response to a debug request
 M: enhanced Multiplier, yield a full 64‐bit result, high
performance
 I: Embedded ICE hardware
 Von Neumann architecture
 3‐stage pipeline

76
ARM Processor Core Diagram

77