IP Core Design

Lecture 1
SoC Design Process

Juinn-Dar Huang, Ph.D.

Assistant Professor
jdhuang@mail.nctu.edu.tw

September 2004
Introduction to SoC and Reusable IP
 SoC: System-on-a-Chip
• System
A collection of components and/or subsystems that are
appropriately interconnected to perform the specified
Juinn-Dar Huang

functions for end users

• An SoC design is a product creation process
which
– starts at identifying the end-user needs
jdhuang@mail.nctu.edu.tw
SoC Design Process

– ends at delivering a product with enough functional

satisfaction to overcome the payment from the end-
user

copyright © 2004 2
 Many Aspects to SoC
• SoC means different things for different people
– foundry process
– packaging
Juinn-Dar Huang

– analog and mixed-signal circuit design

– for digital design
– for EDA industry
– for system-level design
jdhuang@mail.nctu.edu.tw
SoC Design Process

• SoC presents challenges in all aspects

copyright © 2004 3
 An SoC Example
Juinn-Dar Huang
jdhuang@mail.nctu.edu.tw
SoC Design Process

copyright © 2004 " Source: ARM Solutions Smart Phones and Communicators 4
 Evolution of Silicon Design
Year 1997 1998 1999 2002

Process Technology 0.35u 0.25u 0.18u 0.13u

Juinn-Dar Huang

Design Cycle (month) 18 ~ 12 12 ~ 10 10 ~ 8 8~6

Derivative Cycle (month) 8~6 6~4 4~2 3~2

Silicon Complexity (gate) 200 ~ 500 k 1~2M 4~6M 10 ~ 25 M

Applications Cellular, PDAs, Set-top boxes, Internet Ubiquitous

DVD Wireless PDA appliances, computing
jdhuang@mail.nctu.edu.tw

Anything portable Intelligent, inter-

SoC Design Process

connected con-
trollers

copyright © 2004 " Source: “Surviving the SOC Revolution - A Guide to Platform-Based Design” by Henry Chang et al, KAP, 1999 5
 Benefits of SoC
• Reduce overall system cost
• Increase performance
Juinn-Dar Huang

• Lower power consumption

• Reduce size
– reduce components and routing in board level
jdhuang@mail.nctu.edu.tw
SoC Design Process

copyright © 2004 6
 Trends of VLSI Design

SoC
Design
Juinn-Dar Huang

Complexity Reuse
RTL

Synthesis

Gates
jdhuang@mail.nctu.edu.tw

Place & Route

SoC Design Process

Transistors
Design
On-Line Design Productivity
Polygons

Pattern Generation

1975 1980 1985 1990 1995 2000

copyright © 2004 7
 Productivity Gap

10M Logic Transistors/Chip 100M

Logic Transistors per Chip
Juinn-Dar Huang

Transistor/Staff Month
1M Transistor/Staff Month 10M
58%/Yr. Compound
100K 1M

Productivity
Complexity Growth Rate
10K 100K

1K 10K
jdhuang@mail.nctu.edu.tw

100 1K
SoC Design Process

10 21%/Yr. Compound 100

Productivity Growth Rate
1 10
1991

1999
2001
2003

2007
1987
1989

1993
1995
1997

2005

2009
1983
1985
1981

copyright © 2004 " Source: SEMATECH 8

 Problems in SoC Era
• Productivity gap
• Time-to-market pressure
Juinn-Dar Huang

• Difficult verification due to increasing complexity

• Difficult timing closure due to deep submicron
• Difficult integration due to various levels and
areas of expertise
jdhuang@mail.nctu.edu.tw
SoC Design Process

Solution:
Block-based design with reusable IPs

copyright © 2004 9
 How to Conquer the Complexity
• Use a known real entity
– a pre-designed component (reusable IPs)
– a platform
Juinn-Dar Huang

• Partition
– based on functionality
– hardware and software
• Modeling
jdhuang@mail.nctu.edu.tw
SoC Design Process

– at different level
– consistent and accurate

copyright © 2004 10
 Taxonomy
• Intellectual Property (IP)
– Intellectual Property means products, technology,
software, etc. that have been protected through patents,
copyrights, or trade secrets
Juinn-Dar Huang

• Virtual Component (VC)

– A block that meets the Virtual Socket Interface
Specification and is used as a component in the
Virtual Socket design environment
• Soft VCs are delivered in the form of synthesizable HDL
jdhuang@mail.nctu.edu.tw
SoC Design Process

• Firm VCs have been optimized in structure and in topology for

performance and area through floorplanning/placement,
possibly using a generic technology library
• Hard VCs have been optimized for power, size, or
performance and mapped to a specific technology

copyright © 2004 11
 Solution for SoC Problems
• IPs
• Reusable IPs
Juinn-Dar Huang

• System integration with reusable IPs

– physical implementation
– IP interfacing
– system verification
jdhuang@mail.nctu.edu.tw

– SoC testing
SoC Design Process

– hardware/software co-design

copyright © 2004 12
 Key to Successful SoC
For macro creators
• Design reusable soft macros
Juinn-Dar Huang

• Design reusable hard macros

For macro integrators

• Integrate soft and hard macros into an SoC design
jdhuang@mail.nctu.edu.tw
SoC Design Process

• Verify functionality and timing in large SoC designs

copyright © 2004 13
 Design for Use
To be reusable, be usable first
• Good documentation
Juinn-Dar Huang

• Good code quality

• Through commenting
• Well-designed verification environments and suits
• Robust scripts
jdhuang@mail.nctu.edu.tw
SoC Design Process

copyright © 2004 14
 Design for Reuse
• Design to maximize the flexibility
– configurable, parameterizable
• Design for use in multiple technologies
Juinn-Dar Huang

– portable
• Design with standard-based interfaces
• Design with complete verification process
jdhuang@mail.nctu.edu.tw

– robust and verified

SoC Design Process

• Design verified to a high level of confidence

– physical prototype, demo system
• Design with full document set

copyright © 2004 15
 To Be Reusable or not to Be
• Treat design reuse as a burden because it seems
to lengthen the design cycle - Common Fallacy
Reuse vs. use-once design fashion
Juinn-Dar Huang

• 2x-3x development cost for reuse design

• 10x-100x productivity in successive designs
• The only way to design million-gate chips is to
jdhuang@mail.nctu.edu.tw

employ reuse methodology

SoC Design Process

• Barriers to the adoption of reuse are managerial

and cultural in nature

copyright © 2004 16
SoC Design Process
 SoC Design Flow
• To meet SoC design challenges, design flow
changes from
– a waterfall model to a spiral model
Juinn-Dar Huang

– a top-down flow to a combination of top-down and

bottom-up
jdhuang@mail.nctu.edu.tw
SoC Design Process

copyright © 2004 18
 Waterfall Model

Specification Timing
Development Verification
Juinn-Dar Huang

RTL Code Place and Route

Development
jdhuang@mail.nctu.edu.tw

Functional Prototype
SoC Design Process

Verification Build and Test

Synthesis System Integration

and S/W Test

copyright © 2004 19
 Spiral Model
System Design and Verification
PHYSICAL TIMING HARDWARE SOFTWARE
Physical Timing Hardware Software
Juinn-Dar Huang

Specification: Specification: Specification: Specification:

area,power, I/O timing, algorithm application
clock design frequency development prototype
& macro development
decomposition
Preliminary Block timing Block Application
floorplan specification selection/ prototype
design testing
jdhuang@mail.nctu.edu.tw

Updated Block Block Application

SoC Design Process

floorplan synthesis verification development

Updated Top-level Application
floorplan RTL testing
Trial Top-level Top-level Application
placement synthesis verification testing

Final floorplan, place and route - Tapeout

copyright © 2004 20
 Waterfall vs. Spiral
Waterfall
• Worked well up to 100K gates and down .5µ
Juinn-Dar Huang

• H/W and S/W development are serialized

Spiral
• Parallel, concurrent H/W and S/W development
jdhuang@mail.nctu.edu.tw
SoC Design Process

• Parallel verification and synthesis

• Develop modules only if not available
• Planned iteration throughout

copyright © 2004 21
 Top-Down vs. Bottom-Up
Top-down
• Recursively partition the design into manageable
macros
Juinn-Dar Huang

• Design or select the appreciate macros

• Recursively integrate macros into the top-level
• Fail and iterate if any low-level block turns out to
jdhuang@mail.nctu.edu.tw

be unfeasible
SoC Design Process

Combination of top-down and bottom-up

• building critical blocks at the early stage
• Library of pre-verified reusable macros facilitates
this process
copyright © 2004 22
 Baseline
Minimize the overall design time
• Minimize the number of iterations, especially in
major loops
Juinn-Dar Huang

• Iterate in tight and local loop only

• Under spiral model
– one stage can begin before the previous one is
jdhuang@mail.nctu.edu.tw

completed
SoC Design Process

– no stage can be completed until the previous one is

completed
Advise
– carefully specify a design is the best way to minimize
the iterations
copyright © 2004 23
 Specification Requirement
• Functionality
• Performance/area/power
Juinn-Dar Huang

• Test coverage
• External interface to other hardware blocks
• Interface timing
• Interface to software
jdhuang@mail.nctu.edu.tw
SoC Design Process

copyright © 2004 24
 Types of Specification (1/2)
• Natural language
– ambiguities, incompleteness, error-prone
Juinn-Dar Huang

• Formal specification
– written by a formal specification language
– formal verification can be used to check whether a
specific implementation meets the specification
jdhuang@mail.nctu.edu.tw
SoC Design Process

– to date, not been used widely

copyright © 2004 25
 Types of Specification (2/2)
• Executable specification
– usually written in C/C++, SystemC
– verify basic functionality and I/F between H/W and S/W
Juinn-Dar Huang

– enables the S/W development earlier

– to date, addresses functional behavior only
– complemented by a written document describing
physical specifications
jdhuang@mail.nctu.edu.tw
SoC Design Process

copyright © 2004 26
 System Design Process
IDENTIFY
System Requirements
Juinn-Dar Huang

WRITE WRITE WRITE

Preliminary Spec. Hardware Spec. DEFINE Software Spec.
DEVELOP Interface DEVELOP
Architectural Model Prototype of SW
DEVELOP
High-Level
Behavioral Model PARTITION HW/SW DEVELOP
C/C++/COSSAP/SPW
jdhuang@mail.nctu.edu.tw

into Macros COSIMULATION Software

SoC Design Process

REFINE and TEST Macro 1 Macro n

Algorithm

WRITE
DETERMINE Preliminary Spec.
HW/SW Partition for Macros

copyright © 2004 27
 IP Core Design

Lecture 2
System-Level Design Issues

Juinn-Dar Huang, Ph.D.

Assistant Professor
jdhuang@mail.nctu.edu.tw

September 2004
 System-Level Design Issues
• Fundamental consensus
– well-designed IPs is the key to successful SoC design
• System-level guidelines
Juinn-Dar Huang

– for producing well-designed IPs

– for integrating well-designed IPs into an SoC design
System-Level Design Issues

– mostly driven by IP integrators and chip designers

• Cornerstones of these guidelines
jdhuang@mail.nctu.edu.tw

– DISCIPLINE
– SIMPLICITY
– LOCALITY

copyright © 2004 1
 Interface and Timing Closure
• Timing problem due to deep-submicron
– increasingly significant wire delay
– wireload model becomes imprecise
Juinn-Dar Huang

– hard to achieve the timing closure

• Tactics
System-Level Design Issues

– register all inputs/outputs of the macro

– register all outputs of the subblock within the macro
jdhuang@mail.nctu.edu.tw

– timing-driven placement and routing

copyright © 2004 2
 Case Study: PCI
<= 7ns @ 33MHz
PCI <= 3ns @ 66MHz

REG
Timing closure very
Juinn-Dar Huang

PCI Logic
difficult @ 66MHz

CLK
System-Level Design Issues

<= 1.7ns @ 66MHz

jdhuang@mail.nctu.edu.tw

PCI-X <= 1.2ns @ 133MHz

REG
PCI Logic Timing closure not
difficult @ 66 or 133MHz

CLK

copyright © 2004 3
 Synchronous vs. Asynchronous
• Synchronous
– avoid asynchronous and mutli-cycle paths
– accelerate synthesis and simulation
Juinn-Dar Huang

– ease static timing analysis

• Register-based
System-Level Design Issues

– use (positive) edge-triggered flip-flop

– latches should be judiciously used, small memory/FIFO
jdhuang@mail.nctu.edu.tw

copyright © 2004 4
 Clocking
• Minimize the number of clock domains
– isolate the interface between two domains
– careful synchronizer design to avoid metastability
Juinn-Dar Huang

• Document the clocking scheme

– required frequencies
System-Level Design Issues

– timing requirements to interface with the rest of the

system
jdhuang@mail.nctu.edu.tw

• PLL
– disabling/bypassing mechanism
– ease testing

copyright © 2004 5
 Reset
• Synchronous reset
– easy to synthesize
– requires a free-running clock, especially at power-up
Juinn-Dar Huang

– hard to deal with tri-state bus initialization at power-up

• Asynchronous reset
System-Level Design Issues

– not require a free-running clock

– hard to implement, like clocks, CTS is usually required
jdhuang@mail.nctu.edu.tw

– synchronous de-assertion problem

– make STA and cycle-based simulation more difficult

• Asynchronous reset is preferred

copyright © 2004 6
 Asynchronous Set/Reset
• Internal generated asynchronous signal may
cause unwanted set or reset during scan shift
• Force internal generated asynchronous signal
Juinn-Dar Huang

inactive during test

System-Level Design Issues

power-on reset FF FF
reset to all FF
jdhuang@mail.nctu.edu.tw

power-on reset FF FF

reset to all FF

test_mode_n

copyright © 2004 7
 Design for Verification

• System-level verification plan should be developed/

documented before macro selection/design begins
Juinn-Dar Huang

• Macro-level verification plan should be developed/

System-Level Design Issues

documented before design begins

jdhuang@mail.nctu.edu.tw

– bottom-up verification

copyright © 2004 8
 System Interconnection
• Tri-state bus is not good
– bus contention problem
• reduce reliability
Juinn-Dar Huang

• one and only one driver at a time

– bus floating problem
• reduce reliability
System-Level Design Issues

• bus keeper
jdhuang@mail.nctu.edu.tw

– ATPG problem
– FPGA prototyping problem

Multiplexer is better than Tri-State

copyright © 2004 9
 IP-to-IP Interface
• FIFO-based (Traditional)
– FIFO-like input/output interface design
– many successful stories
Juinn-Dar Huang

– become more complicated (unmanageable) when the

number of IPs goes large
• Bus-based (Modern)
System-Level Design Issues

– eliminate direct IP-to-IP link

jdhuang@mail.nctu.edu.tw

– all IPs talk to a common bus (On-Chip Bus, OCB)

– handle IP-to-Bus problem only
– the backbone of IP-based SoC integration
• Choose the standard buses wherever possible

copyright © 2004 10
 11
Without Standard IP Interface

copyright © 2004
System-Level Design Issues
Juinn-Dar Huang jdhuang@mail.nctu.edu.tw
 12
Ideal SoC by Standard IP Interface

copyright © 2004
System-Level Design Issues
Juinn-Dar Huang jdhuang@mail.nctu.edu.tw
 13
OCB Example - AMBA

copyright © 2004
System-Level Design Issues
Juinn-Dar Huang jdhuang@mail.nctu.edu.tw
 Dynamic Power
Dynamic Power = ΣαfCV2
α: switching activity, f: frequency, C: capacitance, V: supply voltage
Juinn-Dar Huang

• Reduce supply voltage

– fabrication process improvement
• Reduce capacitance
System-Level Design Issues

– low-power cell and I/O library

jdhuang@mail.nctu.edu.tw

• Reduce switching activity

– architectural and RTL exploration
– power-driven synthesis
– gate-level re-power optimization

copyright © 2004 14
 Low Power Techniques
• RTL techniques used in my previous CPU designs
– clock gating
– half-cycle latch
Juinn-Dar Huang

– operand isolation
– datapath masking
System-Level Design Issues

– memory interface
jdhuang@mail.nctu.edu.tw

• Other techniques
– data bus encoding
– multiple VDD and Vt

copyright © 2004 15
 Clock Gating (1/2)
• Clock gating
– 50% - 70% power consumed in clock network reported
– gating the clock to an entire block
Juinn-Dar Huang

Block A
– gating the clock to a flip-flop Clock
generation
and gating
Block B
System-Level Design Issues

always @(posedge clk)

if(en)
jdhuang@mail.nctu.edu.tw

q <= q_nxt;
D Q
en
clk

assign clk1 = clk & en;

D Q
always @(posedge clk1) en Clock
q <= q_nxt;
clk gating
copyright © 2004 16
 Clock Gating (2/2)

Architecture Level Power Compiler

Clock Gating Clock Gating
Juinn-Dar Huang
System-Level Design Issues
jdhuang@mail.nctu.edu.tw

Considerations:
1. Clock Tree Power
2. Clock Tree Latency

copyright © 2004 17
 Clock Gating Analysis
From my previous 32-bit embedded processor
design experience
Juinn-Dar Huang

• Dhrystone 2.1 as benchmark

– 542 clock cycles
System-Level Design Issues

• Result
jdhuang@mail.nctu.edu.tw

Clock domain Flip-Flop Transition Transition Transition

number without gating with gating activity ratio
gated 1528 828176 98480 11.89%
non-gated 103 55826 55826 100.00%
total 1631 884002 154306 17.45%

94% F.F.’s are clock-gated

copyright © 2004 18
 Clock Gating During Scan Shift
Juinn-Dar Huang
System-Level Design Issues
jdhuang@mail.nctu.edu.tw

GN

• Using SE as the control point can get better fault coverage

• Latch GN stuck-at-0 fault is untestable

copyright © 2004 19
 System-Level Clocking
• Clock speed-down (power down mode)
– software-controlled frequency down-scaling
– frequency divided by 2, 4, 8, …
Juinn-Dar Huang

• Clock stop (sleep mode)

– software-controlled or external signal
System-Level Design Issues

– turn-off the clock completely

– re-activated by external interrupts
jdhuang@mail.nctu.edu.tw

copyright © 2004 20
 Half-Cycle Latch (1/2)

High Transition Nets

Juinn-Dar Huang

D Q Logic D Q Logic D Q
System-Level Design Issues
jdhuang@mail.nctu.edu.tw

clk
Guidelines: posedge FF + low-enable latch

Trade fault coverage for power consumption

copyright © 2004 21
 Half-Cycle Latch (2/2)

High Fanout Net

Combo
Juinn-Dar Huang

FF LAT
G

Clock
System-Level Design Issues

Clock
jdhuang@mail.nctu.edu.tw

High Fanout Net

Without Latch
High Fanout Net
With Latch

Power saved for the first half

cycle at the high fanout net

copyright © 2004 22
 Operand Isolation (1/4)

Shift Operation without operand isolation

A_Shifter_in
Juinn-Dar Huang

A Shifter_out
Shifter
B_Shifter_in output
System-Level Design Issues

ALU_out
A_ALU_in
jdhuang@mail.nctu.edu.tw

B
ALU
B_ALU_in

ALU has transition when Shifter operation executed

copyright © 2004 23
 Operand Isolation (2/4)

ALU Operation without operand isolation

A_Shifter_in
Juinn-Dar Huang

A Shifter_out
Shifter
B_Shifter_in output
System-Level Design Issues

ALU_out
A_ALU_in
jdhuang@mail.nctu.edu.tw

B
ALU
B_ALU_in

Shifter has transition when ALU operation executed

copyright © 2004 24
 Operand Isolation (3/4)

Shifter Operation with operand isolation

A_Shifter_in
FF
Juinn-Dar Huang

A Shifter_out
Shifter
FF

B_Shifter_in output
System-Level Design Issues

ALU_out
A_ALU_in
jdhuang@mail.nctu.edu.tw

FF
B
ALU
FF

B_ALU_in
ALU has no transition when Shifter operation executed

copyright © 2004 25
 Operand Isolation (4/4)

ALU Operation with operand isolation

A_Shifter_in
FF
Juinn-Dar Huang

A Shifter_out
Shifter
FF

B_Shifter_in output
System-Level Design Issues

ALU_out
A_ALU_in
jdhuang@mail.nctu.edu.tw

FF
B
ALU
FF

B_ALU_in
Shifter has no transition when ALU operation executed

copyright © 2004 26
 Datapath Masking

A B
C
Combo FF
Juinn-Dar Huang

en
enable
System-Level Design Issues

clock
enable
jdhuang@mail.nctu.edu.tw

A
B

Combo transition power can

be saved when enable is low

copyright © 2004 27
 Memory Interface
• Partition a large memory into several small blocks
– beware of trade-off
• Gray-coded address bus
Juinn-Dar Huang

– 4-bit LSB is generally enough

System-Level Design Issues

32KB
jdhuang@mail.nctu.edu.tw

64KB

32KB

copyright © 2004 28
 Data Bus Encoding
• Transition-based encoding
– P(0) ≠ P(1) ≠ ½
• Bus inverting
Juinn-Dar Huang

– limit the maximum # of transitions to bus_width / 2

• 2’s complement vs. sign-magnitude
System-Level Design Issues

– numbers cross over 0 frequently

jdhuang@mail.nctu.edu.tw

copyright © 2004 29
 Other Techniques
• Balanced logic
A A
B + B +
Juinn-Dar Huang

C + C +
D + D +

• Resource sharing
System-Level Design Issues

• Operand reduction
jdhuang@mail.nctu.edu.tw

– (A*X) + (X * X) + B Î (A + X) * X + B

copyright © 2004 30
 Design for Test (DFT)
• Memory test
– memory BIST is recommended
• Processor test
Juinn-Dar Huang

– chip-level test controller (including scan chain controller

and JTAG controller)
System-Level Design Issues

– combined with embedded ICE for OCD

• Other macros
jdhuang@mail.nctu.edu.tw

– full-scan is strongly recommended

• Logic BIST
– embedded stimulus generator and response checker
– not popular yet

copyright © 2004 31
 Single Stuck-At Fault Model
• Stuck-at-0
– a signal permanently low regardless the control
• Stuck-at-1
Juinn-Dar Huang

– a signal permanently high regardless the control

• Assume only one fault exists
System-Level Design Issues

– reduce complexity
jdhuang@mail.nctu.edu.tw

copyright © 2004 32
 Detecting Stuck-At Fault
Juinn-Dar Huang
System-Level Design Issues

• Detectable
jdhuang@mail.nctu.edu.tw

– Controllable
– Observable

copyright © 2004 33
 Deterministic Pattern Generation
• Apply pattern detecting the fault should be able to
– propagate the fault effect to PO (observability)
– exercise the fault from PI (controllability)
Juinn-Dar Huang
System-Level Design Issues
jdhuang@mail.nctu.edu.tw

copyright © 2004 34
 Fault Simulation
• Determine the faults detected by a test vector
• Performing logic simulation on
– one fault-free circuit
Juinn-Dar Huang

– various faulty circuits

• Fault detected if fault-free result differs from faulty result
• High complexity
System-Level Design Issues

– need long simulation time

– various algorithms to optimize the simulation time
jdhuang@mail.nctu.edu.tw

Faults also detected by vector 0001:

Stuck-at-1 on all pins of G1
Stuck-at-1 on the input of G2
Stuck-at-0 on the input of G3
Stuck-at-1 on the output of G3
Stuck-at-1 on the input of G4
Stuck-at-0 on the output of G4

copyright © 2004 35
 Automatic Test Pattern Generation
• ATPG
– read netlist
– build fault list/fault collapsing
Juinn-Dar Huang

– vector generation
– fault simulation
System-Level Design Issues

– vector compression
– vector writing (done)
jdhuang@mail.nctu.edu.tw

copyright © 2004 36
 Fault Coverage and Defect Level
• Yield (Y):
– the fraction of dies that are produced free of defects
• Fault Coverage(FC):
Juinn-Dar Huang

– FC = #(detected faults) / #(possible faults)

• Defect Level (DL):
System-Level Design Issues

– fraction of bad parts among the parts that pass all the
tests and are shipped
jdhuang@mail.nctu.edu.tw

– DL is measured in terms of DPM (defects per million),

– typical values claimed are less than 200 DPM, or
0.02%

copyright © 2004 37
 Sequential Circuit Pattern Generation
• Sequential circuit behavior
– hard to set internal FF to a desired value
• Long test pattern generation time
Juinn-Dar Huang

• Long test pattern length

• Low fault coverage
System-Level Design Issues
jdhuang@mail.nctu.edu.tw

copyright © 2004 38
 Full-Scan Methodology
Juinn-Dar Huang
System-Level Design Issues
jdhuang@mail.nctu.edu.tw

• Use combinational ATPG for sequential circuits

• Greatly reduce pattern length and pattern generation time
copyright © 2004 39
 IP Core Design

Lecture 3
(Soft) Macro Design Process

Juinn-Dar Huang, Ph.D.

Assistant Professor
jdhuang@mail.nctu.edu.tw

September 2004
 Macro Design Process
4 Major Phases
• Design top-level macro
Juinn-Dar Huang

• Design each subblock

• Integrate subblocks
• Macro productization
Macro Design Process
jdhuang@mail.nctu.edu.tw

copyright © 2004 1
 Characteristics of Good Soft IPs
• Configurability
• Standard interface
Juinn-Dar Huang

• Compliance for defensive design practices

• Complete set of deliverables
– synthesizable RTL
– verification suite (testbench)
Macro Design Process
jdhuang@mail.nctu.edu.tw

– related EDA scripts

– user documents

copyright © 2004 2
 Top-Level Macro Design Flow

Macro Develop detailed

specification technical spec.
Juinn-Dar Huang

Create behavioral model

Code testbench
Code behavioral model C/C++/HDL/
C/C++/HDL/SystemC SystemC • Behavioral model
• Secure evaluation model
• executable specification
Macro Design Process
jdhuang@mail.nctu.edu.tw

Verify • HW/SW co-simulation

behavioral model • S/W development

Partition
into subblocks

copyright © 2004 3
 Contents of Design Specification
• Overview • Manufacturing test method
• Functional description • S/W programming model
• Physical requirements – register map, ...
Juinn-Dar Huang

– area, performance, power,.. • S/W requirements

• Design requirements • Deliverables
– (RTL) design rules • Verification plan
• Block diagrams
Macro Design Process
jdhuang@mail.nctu.edu.tw

• External interface
– I/O pin list
– timing constraints on I/O
ports
– clock, reset signals

copyright © 2004 4
 Subblock Design Flow
Write
function spec.

Write
Juinn-Dar Huang

technical spec.

Develop Write RTL Develop

area/timing/power Run lint testbench
constraints C/C++/HDL/HVL

Synthesize Simulate Not

Macro Design Process
jdhuang@mail.nctu.edu.tw

enough

Power Analysis Measure

testbench coverage

Meet all
specified
Write creation guide
constraints
Pass - ready for integration

copyright © 2004 5
 Subblock Integration Flow
Subblock 1 Subblock 2 Subblock n

Determine configuration
Generate top-level RTL
Juinn-Dar Huang

Generate
top-level synthesis scripts
Functional Test
Run lint
Pass coverage test Synthesize
with reference library
Macro Design Process
jdhuang@mail.nctu.edu.tw

Ready for Scan insertion & ATPG

productization

Productize Power Analysis

soft macro

Productize
hard macro
copyright © 2004 6
 Soft Macro Productization
Ready for Productization

Develop Translate Synthesize to Create

specification Verilog < > VHDL multiple libraries User Documents
Juinn-Dar Huang

for prototype chip User Guide

Verification Guide
Design chip Regression Test Gate-Level Sim Integration Guide
on translated code on one technology Test Guide

Synthesize chip

Regression Test Formal Verification

Macro Design Process
jdhuang@mail.nctu.edu.tw

FPGA mapping on multiple RTL vs. Gates

simulators
Scan & ATPG

Back-end & Fab.

Test chip
on demo board Release

copyright © 2004 7