EEE411/CSE435/ETE412 - Section 1 and 2, VLSI Design, Date: Nov 28, 2021
Answer any 5:
1. a) What is Moor’s Law? List the ICs based on size and technology period. b) Show the VLSI Design Flow.
2. a) In Brief with Formulae - i. Line Resistance, ii. Sheet Resistance, ii. Line Capacitance, iii. Resistivity iv. Conductivity v. Permittivity (c) A interconnect line is made from a material that has resistively of ρ = 4 μω-cm. The interconnect is 1200 Å thick, where 1 Å (Angstrom) is 10-8 cm. The line has a width of 0.6 μm. i. Find the sheet resistance Rs of the line. ii. Find the line resistance for a line that is 125 μm long.
3. (a) List the guidelines of CMOS Ckt design to show why CMOS circuit gives inverted output. (b) Design a CMOS logic circuit of following function.
g= (a+b)(c+d) Implement the minimum-transistor nFET network and then apply bubble pushing to find the pFET network.
4. (a) List the physical layers of MOSFET Circuit and show those layers in figure that includes two metal layers too. (b) Design the circuits and layouts for a CMOS gate that implements the function
g = a+b. Start with truth table and then using conventional procedure(s) come up with optimized nFET and pFET ckt. List the corresponding colors forts different pattern in pattern layout.
5. (a) What is Transmission Gate? Design 4:1 MUX using TG gates.
b) Using Transmission Gate design a 2 input OR gate, show FET improvements compared to CMOS circuit OR gate.
6. (a) List the masking sequences which are used to define chip regions. In Brief (Any two) (i). Drawn Value and Effective Value (ii) Manhattan Rule and Aspect Ratio (iii) Latch up condition in bulk CMOS technology and its prevention. (b) Show the circuit and layout of a NAND2 gate using vertical FETs with aspect ratio of 2(W/L).
