BEE 271 Spring 2017
How to use the SignalTap II logic analyzer
Nicole Hamilton
SignalTap II is the builtin Quartus logic analyzer for debugging clocked sequential circuits
running on the FPGA. It’s comprised of a user interface running on the PC for setting it up
and viewing captured data plus the logic analyzer itself, which is compiled onto the FPGA
along with your design. The logic analyzer captures data on every positive edge of the clock
and then, when a trigger condition is met, transfers it to the PC for display.
The example used here is the simple a 32-bit counter included in Simulation.zip, posted
to the files area in Canvas. Download and unzip it and open the SimpleCounter.qpf file.
module CounterA(
input clock, reset,
input [ 31:0 ] resetValue,
output reg [ 31:0 ] count = 0 );
// Synchronous reset (synchronized to the clock)
always @( posedge clock )
count <= reset ? resetValue : count + 1;
endmodule
In this simple wrapper for the DE1-SoC board, the high-order 10 bits of the counter are tied
to the LEDs, the reset value is tied to the switches and the reset button to KEY[ 3 ].
module SimpleCounter(
input CLOCK_50,
input [ 3:0 ] KEY,
output [ 9:0 ] LEDR,
input [ 9:0 ] SW );
wire reset = ~KEY[ 3 ];
wire [ 31:0 ] count;
assign LEDR = count[ 31:22 ];
CounterA c ( CLOCK_50, reset, { SW, 22'b0 }, count );
endmodule
1
To add SignalTap II to the project, you must first compile it in Quartus or at least run
Analysis & Synthesis. (You can do just that single step by double-clicking the blue triangle.)
You must also plug in and power up a DE1-SoC board.
Then, from the Quartus main menu bar, select
Tools SignalTap II Logic Analyzer to start
SignalTap.
2
This will bring up the SignalTap II logic analyzer screen.
If you see this, “No device is selected”, it’s because you haven’t yet plugged in and powered
up a DE1-SoC board. Close the SignalTap window, plug in and power up the DE1-SoC and
then restart SignalTap.
3
This is what you should see.
Double clicking to add nodes opens the Node Finder. Filter on “SignalTap II: pre-synthesis”
nodes (i.e., the names used in your source, before optimization by the compiler), then click
List. You should see something like this.
4
Expanding the CounterA and the KEY nodes, Ctrl-left-click to select reset, count,
resetValue, KEY[3] and SW, then press > to copy them to right hand panel.
5
You should see this result. Press Insert, then Close.
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The SignalTap II window should now look like this. Click “…” to add a clock.
In Node Finder, select CLOCK_50. Signals will be sampled on the rising edge of this clock.
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In the SignalTap II window, right-click and select “Falling Edge” as the trigger condition.
8
Your result should look like this.
File Save as “SimpleCounter.stp”.
9
Yes, you do want to add this to your project.
Press the Compile button. This will trigger a complete recompile in Quartus.
10
If you get this error complaining about compiling with SignalTap in your project, you will
need to enable TalkBack in Quartus.
265013 Can't open SignalTap II Logic Analyzer. Verify that the
license file exists and is stored in the correct location. If you are
using the Quartus Prime Lite Edition software, you must turn on the
TalkBack feature to use the SignalTap II Logic Analyzer.
This is buried in Tools Options Internet Connectivity from the Quartus main menu bar.
Click “TalkBack Options…”.
11
Enable TalkBack, click OK twice to get back to Quartus, then retry the compile.
12
After the compile successfully finishes in Quartus, program the DE1-SoC.
13
Close and then re-open SignalTap II and click the continuous button.
14
It will then switch to acquisition mode.
15
Each time the reset key is pressed, the captured data is displayed. (The hex 3F3 is what
happened to be entered on the switches when I pressed reset.)
Zooming in:
On the falling edge of reset, as you release the button, it starts counting from the value
entered via the switches.
To end the session, press Esc. Occasionally, I find that SignalTap hangs and will not exit.
Unplugging the DE1-SoC will get it unstuck.
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