Computer Organization Laboratory CS39001

Assignment 07 — Single Cycle RISC Processor Design

• Instruction Set Architecture

KGP-RISC has the below Instruction Set Architecture (ISA).

Class Instruction Usage Meaning

Add add rs, rt 𝑟𝑠 ← (𝑟𝑠) + (𝑟𝑡)
Complement comp rs, rt 𝑟𝑠 ← 2'𝑠 𝐶𝑜𝑚𝑝𝑙𝑒𝑚𝑒𝑛𝑡 (𝑟𝑡)
Arithmetic
Add Immediate addi rs, imm 𝑟𝑠 ← (𝑟𝑠) + 𝑖𝑚𝑚
Complement Immediate compi rs, imm 𝑟𝑠 ← 2'𝑠 𝐶𝑜𝑚𝑝𝑙𝑒𝑚𝑒𝑛𝑡 (𝑖𝑚𝑚)
Logical AND and rs, rt 𝑟𝑠 ← (𝑟𝑠) ∧ (𝑟𝑡)
Logic
Logical XOR xor rs, rt 𝑟𝑠 ← (𝑟𝑠) ⊕ (𝑟𝑡)
Shift Left Logical shll rs, sh 𝑟𝑠 ← (𝑟𝑠) 𝑙𝑜𝑔 𝑙𝑒𝑓𝑡 𝑠ℎ𝑖𝑓𝑡𝑒𝑑 𝑏𝑦 𝑠ℎ
Shift Right Logical shrl rs, sh 𝑟𝑠 ← (𝑟𝑠) 𝑙𝑜𝑔 𝑟𝑖𝑔ℎ𝑡 𝑠ℎ𝑖𝑓𝑡𝑒𝑑 𝑏𝑦 𝑠ℎ
Shift Left Logical Variable shllv rs, rt 𝑟𝑠 ← (𝑟𝑠) 𝑙𝑜𝑔 𝑙𝑒𝑓𝑡 𝑠ℎ𝑖𝑓𝑡𝑒𝑑 𝑏𝑦 (𝑟𝑡)
Shift
Shift Right Logical Variable shrlv rs, rt 𝑟𝑠 ← (𝑟𝑠) 𝑙𝑜𝑔 𝑟𝑖𝑔ℎ𝑡 𝑠ℎ𝑖𝑓𝑡𝑒𝑑 𝑏𝑦 (𝑟𝑡)
Shift Right Arithmetic shra rs, sh 𝑟𝑠 ← (𝑟𝑠) 𝑎𝑟𝑖𝑡ℎ 𝑟𝑖𝑔ℎ𝑡 𝑠ℎ𝑖𝑓𝑡𝑒𝑑 𝑏𝑦 𝑠ℎ
Shift Right Arithmetic Variable shrav rs, rt 𝑟𝑠 ← (𝑟𝑠) 𝑎𝑟𝑖𝑡ℎ 𝑟𝑖𝑔ℎ𝑡 𝑠ℎ𝑖𝑓𝑡𝑒𝑑 𝑏𝑦 (𝑟𝑡)
Load Word lw rt, imm(rs) 𝑟𝑡 ← 𝑚𝑒𝑚[(𝑟𝑠) + 𝑖𝑚𝑚]
Memory
Store Word sw rt, imm(rs) 𝑚𝑒𝑚[(𝑟𝑠) + 𝑖𝑚𝑚] ← (𝑟𝑡)
Unconditional Branch bL 𝑔𝑜𝑡𝑜 𝐿
Branch Register br rs 𝑔𝑜𝑡𝑜 (𝑟𝑠)
Branch on < 0 bltz rs, L 𝑖𝑓 (𝑟𝑠) < 0 𝑡ℎ𝑒𝑛 𝑔𝑜𝑡𝑜 𝐿
Branch on flag 0 bz rs, L 𝑖𝑓 (𝑟𝑠) == 0 𝑡ℎ𝑒𝑛 𝑔𝑜𝑡𝑜 𝐿
Branch
Branch on flag not 0 bnz rs, L 𝑖𝑓 (𝑟𝑠) ! = 0 𝑡ℎ𝑒𝑛 𝑔𝑜𝑡𝑜 𝐿
Branch and Link bl L 𝑔𝑜𝑡𝑜 𝐿; (𝑟𝑎) ← (𝑃𝐶) + 4
Branch on Carry bcy L 𝑖𝑓 𝐶𝑎𝑟𝑟𝑦 == 1 𝑡ℎ𝑒𝑛 𝑔𝑜𝑡𝑜 𝐿
Branch on No Carry bncy L 𝑖𝑓 𝐶𝑎𝑟𝑟𝑦 == 0 𝑡ℎ𝑒𝑛 𝑔𝑜𝑡𝑜 𝐿

• Assumptions
- Word length of our processor is 32 bits.
- All registers and memory elements have 32 bit data.
- The address line of the memory is also 32 bit.
- The processor has a single-cycle instruction execution unit i.e., every instruction will take one
clock cycle to complete execution. There is no pipelining.
• Instruction Encodings
Register Addressing Mode
Instruction Encoding Type: R-Format (Register Addressing Mode)
Instructions having the same opcode can be differentiated by the bits in the 𝑓𝑢𝑛𝑐𝑡 field.

Opcode: 000 000

[These instructions require bitwise arithmetic to be performed on the operands]
add rs, rt
and rs, rt
xor rs, rt
comp rs, rt

Opcode: 000 001

[These instructions require shifting of bits in a register by a 6-bit shift amount]
shll rs, sh
shrl rs, sh
shra rs, sh

Opcode: 000 010

[These instructions require shifting bits in a register by a 32-bit shift amount stored in another
register]
shllv rs, rt
shrlv rs, rt
shrav rs, rt

opcode (6) rs (5) rt (5) shamt (6) funct (10)

opcode rs rt shamt funct

add rs rt — 0 000 000 000

and rs rt — 0 000 000 001

000 000
xor rs rt — 0 000 000 010

comp rs rt — 0 000 000 011

shll rs — sh 0 000 000 000

shrl 000 001 rs — sh 0 000 000 001

shra rs — sh 0 000 000 010

shllv rs rt — 0 000 000 000

shrlv 000 010 rs rt — 0 000 000 001

shrav rs rt — 0 000 000 010

Immediate Addressing Mode (Non-Memory Based)
Instruction Encoding Type: I-Format (Immediate Addressing Mode)
Instructions can only be differentiated by the 𝑜𝑝𝑐𝑜𝑑𝑒.

Opcode: 000 011

[This instruction requires adding a 21 bit immediate value to the value stored in a register]
addi rs, imm

Opcode: 000 100

[This instruction requires computing 2’s complement of a 21 bit immediate value]
compi rs, imm

opcode (6) rs (5) imm (21)

opcode rs imm

addi 000 011 rs imm

compi 000 100 rs imm

Immediate Addressing Mode (Memory Based)

Instruction Encoding Type: I-Format (Immediate Addressing Mode)
Instructions can only be differentiated by the 𝑜𝑝𝑐𝑜𝑑𝑒.

Opcode: 000 101

[This instruction loads a 4 byte word from the specified memory location to a register]
lw rt, imm(rs)

Opcode: 000 110

[This instruction stores the value in a register at a specified memory location]
sw rt, imm(rs)

opcode (6) rs (5) rt (5) imm (16)

opcode rs rt imm

lw 000 101 rs rt imm

sw 000 110 rs rt imm

Pseudo-Direct Addressing Mode

Instruction Encoding Type: (Pseudo-Direct Addressing Mode)
Instructions can only be differentiated by the 𝑜𝑝𝑐𝑜𝑑𝑒.

Opcode: 000 111

 [This instruction updates the program counter with a new instruction address.]
bL

Opcode: 001 000

[This instruction updates the program counter with a new instruction address and stores the current
address in the program counter in a register $ra]
bl L

Opcode: 001 001

[This instruction updates the program counter with a new instruction address if carry-out of the ALU
is 1]
bcy L

Opcode: 001 010

[This instruction updates the program counter with a new instruction address if carry-out of the ALU
is 0]
bncy L

opcode (6) address (26)

opcode address

b 000 111 L

bl 001 000 L

bcy 001 001 L

bncy 001 010 L

PC-Relative Addressing Mode

Instruction Encoding Type: (PC-relative Addressing Mode)
Instructions can only be differentiated by the 𝑜𝑝𝑐𝑜𝑑𝑒.

Opcode: 001 111

[This instruction updates the program counter with a new instruction address stored in a register]
br rs

Opcode: 001 111

[This instruction updates the program counter with a new instruction address if the value stored in
the register is less than 0]
bltz rs, L

Opcode: 001 111

[This instruction updates the program counter with a new instruction address if the value stored in
the register is equal to 0]
bz rs, L
Opcode: 001 111
[This instruction updates the program counter with a new instruction address if the value stored in
the register is not equal to 0]
bnz rs, L

opcode (6) rs (5) offset (21)

opcode rs offset

br 001 011 rs —

bltz 001 100 rs L

bz 001 101 rs L

bnz 001 110 rs L

• Future Extensions
The opcode field is given 6 bits in the instruction encoding. This means that the KGP-RISC
architecture can have 64 instructions with different opcodes. 15 of the 64 opcodes are used
already. Therefore, the ISA can be extended to include 49 new instructions with different
opcodes. Secondly, for the instructions belonging to R-type formatting, 10 bits are reserved for
the funct field that identifies the function type for similar types of arithmetic instructions. This
means that for each opcode, 1024 distinct R-type instructions can be written in the ISA. 3 opcodes
are used already in the R-type instructions for which respectively 4, 3, 3 instructions are written
with different funct fields. So for the already existing opcodes in the R-type instructions, a
total of 3062 new R-type instructions can be written without using any new opcodes. Adding
to this number in the best case if all the 49 remaining opcodes are used for R-type instructions,
since each opcode can support 1024 R-type instructions, a maximum of 53238 new R-type
instructions can be included in the architecture.

• Datapath Elements
The various datapath elements that will be needed in the processor that implements the
KGP-RISC ISA are as follows.
– Program Counter – Instruction Memory – Register File
– Arithmetic Logic Unit – Data Memory – Sign Extension Modules
– Main Controller – ALU Control Unit – 32-Bit Adder
– Multiplexors – Concatenation Modules – Zero Padding Modules
Multiplexors of different bus widths and number of inputs will be needed. Similarly, different sign
extension modules for different input bus widths will be needed. Besides these, some other helper
modules may also be needed to modularize the hardware design (like a special module that
determines the success of a branch instruction). These modules will become absolutely clear in
the datapath diagram of the single cycle execution unit.
• Processor Design for Single Cycle Execution Unit
The next page shows the complete datapath of the Single Cycle Execution RISC Architecture
with the control signals (highlighted in blue). All the datapath elements are clearly shown.
Following that, we have highlighted (in bold red) the datapath for each of the instructions that
shows the various phases of single cycle execution, from instruction fetch to write-data, that the
processor must go through to execute these instructions successfully. These independent
datapath diagrams for each instruction will make the functionality of the respective instructions of
KGP-RISC ISA much more clearer.
 Single Cycle Execution Unit for KGP-RISC Architecture
32
/32
/
BranchReg
32
/ 1
• BranchCarryType
M
U
• BranchCarryDep 32 0
X

/ 1
M
U
X
0

C[25..0] Text
28 32 • 1

• Left Shift 2 / Concatenate /

M
U
X
32-Bit
Adder • /
21 C[20..0] Left Shift 2 +
23-32 1
0

4 SignExtd M
32-Bit
32 (PC+4)[31..28]
/ Adder
U
X
FOUR / •. •
Text 0

•
26 2
/ /RegDest BranchNoRegNoCond

BranchComp
2
Mem2RegData /3
32 / 32 / Control /
ALUOp
MemWrite 3
/
C[31..26]

ALUSrc
RegWrite Comp
2
6 BranchCompType / Branch
Success
/

ALUResult[31]
•/
Text5 C[25..21] rs
PC
Read Reg1
Read Data1
•.
32
/ . Zero .

•
Read
C[20..16] rt
Address 5
/ • Read Reg2 Read Data2
•.

••
0 . 32
Instruction M
32-Bit
ALU
Result . / Address
C[31..0] •TText
•• Register
1 U
32
2 File 4
X Carry Read Data /
Instruction •ex 0
M 5
3
32
/ . 32
Memory t U / Write Reg
2
/ Write Data
X ZERO Data
RegID($ra) 1 Write Data 2M
Memory
7 1U
ALU
Control / 0X

32
16 /
16 Text C[15..0] 32
/ • /
16-32 Sign
Extension /
/
32

10
• C[9..0]
/ 32
/
6 6-32 32
C[15..10]
/ Pad Leading
Zeroes
/

21 C[20..0] 32
21-32 Sign
/ Extension /
 Datapath for R-Type Instructions
( add, and, xor, comp, shllv, shrlv, shrav )
32
/32
/
BranchReg
32
/ 1
• BranchCarryType
M
U
• BranchCarryDep 32 0
X

/ 1
M
U
X
0

C[25..0] Text
28 32 • 1

• Left Shift 2 / Concatenate /

M
U
X
32-Bit
Adder • 21
/
C[20..0] Left Shift 2 +
23-32 1
0

4 SignExtd M
32-Bit
32 (PC+4)[31..28]
/ Adder
U
X
FOUR / •
. •
Text 0

•
26 2
/ / RegDest BranchNoRegNoCond

BranchComp

2
Mem2RegData /3
32 / 32 / Control /
ALUOp
MemWrite 3
/
C[31..26]

ALUSrc
RegWrite Comp
2
6 BranchCompType / Branch
Success
/

ALUResult[31]
•
Text C[25..21] rs
PC
Read Reg1
Read Data1
• . . Zero .

•
Read
Address
•
C[20..16] rt
Read Reg2 Read Data2
• .

••
0 32-Bit .
M Result Address
Instruction ALU .
C[31..0] •TText
•• Register
1 U
X Carry Read Data
2 File 4

Instruction
•x
e
0
M 3
2
.
Memory t U Write Reg Write Data
X ZERO Data
RegID($ra) 1 Write Data 2M
7 Memory
ALU 1U
Control / 0X

16 Text C[15..0] 16 32
/ • /
16-32 Sign
Extension /

10
• C[9..0]
/ 32
/
6 6-32 32
C[15..10]
/ Pad Leading
Zeroes
/

21 C[20..0] 32
21-32 Sign
/ Extension /
 Datapath for R-Type Instructions
( shll, shrl, shra )
32
/32
/
BranchReg
32
/ 1
• BranchCarryType
M
U
• BranchCarryDep 32 0
X

/ 1
M
U
X
0

C[25..0] Text
28 32 • 1

• Left Shift 2 / Concatenate /

M
U
X
32-Bit
Adder • 21
/
C[20..0] Left Shift 2 +
23-32 1
0

4 SignExtd M
32-Bit
32 (PC+4)[31..28]
/ Adder
U
X
FOUR / •. •
Text 0

26
/ / RegDest
2
• BranchNoRegNoCond

BranchComp

2
Mem2RegData /3
32 / 32 / Control /
ALUOp
MemWrite 3
/
C[31..26]

ALUSrc
RegWrite Comp
2
6 BranchCompType / Branch
Success
/

ALUResult[31]
•
Text C[25..21] rs
PC
Read Reg1
Read Data1
• . . Zero .

•
Read
Address
•
C[20..16] rt
Read Reg2 Read Data2
• .

••
0 32-Bit .
M Result Address
Instruction ALU .
C[31..0] •TText
•• Register
1 U
X Carry Read Data
2 File 4

Instruction •ex 0
M 3
2
.
t Write Data
Memory U Write Reg
X ZERO Data
RegID($ra) 1 Write Data 2M
Memory
7 1U
ALU
Control / 0X

Text C[15..0] 16
•
16 16-32 Sign 32
/ / Extension /

10
• C[9..0]
/ 32
/
6 6-32 32
C[15..10]
/ Pad Leading
Zeroes
/

21 C[20..0] 32
21-32 Sign
/ Extension /
 Datapath for Non-Memory Based I-Type Instructions
( addi, compi )
32
/32
/
BranchReg
32
/ 1
• BranchCarryType
M
U
• BranchCarryDep 32 0
X

/ 1
M
U
X
0

C[25..0] Text
28 32 • 1

• Left Shift 2 / Concatenate /

M
U
X
32-Bit
Adder • 21
/
C[20..0] Left Shift 2
+ 23-32 1
0

4 SignExtd M
32-Bit
32 (PC+4)[31..28]
/ Adder
U
X
FOUR / •. •
Text 0

•
26 2
/ / RegDest BranchNoRegNoCond

BranchComp

2
Mem2RegData /3
32 / 32 / Control /
ALUOp
MemWrite 3
/
C[31..26]

ALUSrc
RegWrite Comp
2
6 BranchCompType / Branch
Success
/

•
C[25..21] rs

ALUResult[31]
Text
PC
Read Reg1
Read Data1
• . . Zero .

•
Read
Address
•
C[20..16] rt
Read Reg2 Read Data2
• .
••
0 32-Bit .
M Result Address
Instruction ALU .
C[31..0] •TText
•• Register
1 U
X Carry Read Data
2 File 4

Instruction •x
e
0
M 3
2
.
Memory t U Write Reg Write Data
X ZERO Data
RegID($ra) 1 Write Data 2M
Memory
7 1U
ALU
Control / 0X

Text C[15..0] 16
•
16 16-32 Sign 32
/ / Extension /
10

• C[9..0]
/ 32
/
6 6-32 32
C[15..10]
/ Pad Leading
Zeroes
/

21 C[20..0] 32
21-32 Sign
/ Extension /
 Datapath for Memory-Based I-Type Instructions
( lw )
32
/32
/
BranchReg
32
/ 1

• BranchCarryType
M
U
• BranchCarryDep 32 0
X

/ 1
M
U
X
0

C[25..0] Text
28 32 • 1

• Left Shift 2 / Concatenate /

M
U
X
32-Bit
Adder • 21
/
C[20..0] Left Shift 2
+ 23-32 1
0

4 SignExtd M
32-Bit
32 (PC+4)[31..28]
/ Adder
U
X
FOUR / •. •
Text 0

•
26 2
/ / RegDest BranchNoRegNoCond

BranchComp

2
Mem2RegData /3
32 / 32 / Control /
ALUOp
MemWrite 3
/
C[31..26]

ALUSrc
RegWrite Comp
2
6 BranchCompType / Branch
Success
/

•
Text C[25..21] rs

ALUResult[31]
PC
Read Reg1
Read Data1
• . . Zero .

•
Read

•
Address C[20..16] rt

Instruction
Read Reg2 Read Data2
• .
0
M
32-Bit
ALU
Result ••
.
.
Address
C[31..0] •TText
•• Register
1 U
X Carry Read Data
2 File 4

Instruction •x
e
0
M 3
2
.
Memory t U Write Reg Write Data
X ZERO Data
RegID($ra) 1 Write Data 2M
Memory
7 1U
ALU
Control / 0X

16 Text C[15..0] 16 32
/ • /
16-32 Sign
Extension /
10

• C[9..0]
/ 32
/
6 6-32 32
C[15..10]
/ Pad Leading
Zeroes
/

21 C[20..0] 32
21-32 Sign
/ Extension /
 Datapath for Memory-Based I-Type Instructions
( sw )
32
/32
/
BranchReg
32
/ 1
• BranchCarryType
M
U
• BranchCarryDep 32 0
X

/ 1
M
U
X
0

C[25..0] Text
28 32 • 1

• Left Shift 2 / Concatenate /

M
U
X
32-Bit
Adder • 21
/
C[20..0] Left Shift 2 +
23-32 1
0

4 SignExtd M
32-Bit
32 (PC+4)[31..28]
/ Adder
U
X
FOUR / •. •
Text 0

•
26 2
/ / RegDest BranchNoRegNoCond

BranchComp

2
Mem2RegData /3
32 / 32 / Control /
ALUOp
MemWrite 3
/
C[31..26]

ALUSrc
RegWrite Comp
2
6 BranchCompType / Branch
Success
/

ALUResult[31]
•
Text C[25..21] rs
PC
Read Reg1
Read Data1
• . . Zero .

•
Read

•
Address C[20..16] rt

Instruction
Read Reg2 Read Data2
• .
0
M
32-Bit
ALU
Result ••
.
.
Address
C[31..0] •TText
•• Register
1 U
X Carry Read Data
2 File 4

Instruction
•ex 0
M 3
2
.
Memory t U Write Reg Write Data
X ZERO Data
RegID($ra) 1 Write Data 2M
Memory
7 1U
ALU
Control / 0X

16 Text C[15..0] 16 32
/ • /
16-32 Sign
Extension /

10
• C[9..0]
/ 32
/
6 6-32 32
C[15..10]
/ Pad Leading
Zeroes
/

21 C[20..0] 32
21-32 Sign
/ Extension /
 Datapath for Instructions in Pseudo-Direct Addressing Mode
(b)
32
/32
/
BranchReg
32
/ 1
• BranchCarryType
M
U
• BranchCarryDep 32 0
X

/ 1
M
U
X
0

C[25..0] Text
28 32 • 1

• Left Shift 2 / Concatenate /

M
U
X
32-Bit
Adder • 21
/
C[20..0] Left Shift 2 +
23-32 1
0

4 SignExtd M
32-Bit
32 (PC+4)[31..28]
/ Adder
U
X
FOUR / •. •
Text 0

•
26 2
/ /RegDest BranchNoRegNoCond

BranchComp

2
Mem2RegData /3
32 / 32 / Control /
ALUOp
MemWrite 3
/
C[31..26]

ALUSrc
RegWrite Comp
2
6 BranchCompType / Branch
Success
/

ALUResult[31]
•
Text C[25..21] rs
PC
Read Reg1
Read Data1
• . . Zero .

•
Read
Address
•
C[20..16] rt
Read Reg2 Read Data2
• .

••
0 32-Bit .
M Result Address
Instruction ALU .
C[31..0] •TText
•• Register
1 U
X Carry Read Data
2 File 4

Instruction
•ex 0
M 3
2
.
Memory t U Write Reg Write Data
X ZERO Data
RegID($ra) 1 Write Data 2M
Memory
7 1U
ALU
Control / 0X

16 Text C[15..0] 16 32
/ • /
16-32 Sign
Extension /

10
• C[9..0]
/ 32
/
6 6-32 32
C[15..10]
/ Pad Leading
Zeroes
/

21 C[20..0] 32
21-32 Sign
/ Extension /
 Datapath for Instructions in Pseudo-Direct Addressing Mode
( bl )
32
/32
/
BranchReg
32
/ 1
• BranchCarryType
M
U
• BranchCarryDep 32 0
X

/ 1
M
U
X
0

C[25..0] Text
28 32 • 1

• Left Shift 2 / Concatenate /

M
U
X
32-Bit
Adder • 21
/
C[20..0] Left Shift 2 +
23-32 1
0

4 SignExtd M
32-Bit
32 (PC+4)[31..28]
/ Adder
U
X
FOUR / •. •
Text 0

•
26 2
/ / RegDest BranchNoRegNoCond

BranchComp

2
Mem2RegData /3
32 / 32 / Control /
ALUOp
MemWrite 3
/
C[31..26]

ALUSrc
RegWrite Comp
2
6 BranchCompType / Branch
Success
/

ALUResult[31]
•
Text C[25..21] rs
PC
Read Reg1
Read Data1
• . . Zero .

•
Read
Address
•
C[20..16] rt
Read Reg2 Read Data2
• .
••
0 32-Bit .
M Result Address
Instruction ALU .
C[31..0] •TText
•• Register
1 U
X Carry Read Data
2 File 4

Instruction •x
e
0
M 3
2
.
Memory t U Write Reg Write Data
X ZERO Data
RegID($ra) 1 Write Data 2M
Memory
ALU 7 1U
Control / 0X

16 Text C[15..0] 16 32
/ • /
16-32 Sign
Extension /
10

• C[9..0]
/ 32
/
6 6-32 32
C[15..10]
/ Pad Leading
Zeroes
/

21 C[20..0] 32
21-32 Sign
/ Extension /
 Datapath for Instructions in Pseudo-Direct Addressing Mode
( bcy, bncy ) : Successful Branching
32
/32
/
BranchReg
32
/ 1
• BranchCarryType
M
U
• BranchCarryDep 32 0
X

/ 1
M
U
X
0

C[25..0] Text
28 32 • 1

• Left Shift 2 / Concatenate /

M
U
X
32-Bit
Adder • 21
/
C[20..0] Left Shift 2
+ 23-32 1
0

4 SignExtd M
32-Bit
32 (PC+4)[31..28]
/ Adder
U
X
FOUR / •. •
Text 0

•
26 2
/ / RegDest BranchNoRegNoCond

BranchComp

2
Mem2RegData /3
32 / 32 / Control /
ALUOp
MemWrite 3
/
C[31..26]

ALUSrc
RegWrite Comp
2
6 BranchCompType / Branch
Success
/

ALUResult[31]
•
Text C[25..21] rs
PC
Read Reg1
Read Data1
• . . Zero .

•
Read
Address
•
C[20..16] rt
Read Reg2 Read Data2
• .

••
0 32-Bit .
M Result Address
Instruction ALU .
C[31..0] •TText
•• Register
1 U
X Carry Read Data
2 File 4

Instruction
•ex 0
M 3
2
.
Memory t U Write Reg Write Data
X ZERO Data
RegID($ra) 1 Write Data 2M
Memory
ALU 7 1U
Control / 0X

16 Text C[15..0] 16 32
/ • /
16-32 Sign
Extension /

10
• C[9..0]
/ 32
/
6 6-32 32
C[15..10]
/ Pad Leading
Zeroes
/

21 C[20..0] 32
21-32 Sign
/ Extension /
 Datapath for Instructions in Pseudo-Direct Addressing Mode
( bcy, bncy ) : Unsuccessful Branching
32
/32
/
BranchReg
32
/ 1
• BranchCarryType
M
U
• BranchCarryDep 32 0
X

/ 1
M
U
X
0

C[25..0] Text
28 32 • 1

• Left Shift 2 / Concatenate /

M
U
X
32-Bit
Adder • 21
/
C[20..0] Left Shift 2 +
23-32 1
0

4 SignExtd M
32-Bit
(PC+4)[31..28] /
U
Adder
32 X
FOUR / •. •
Text 0

•
26 2
/ / RegDest BranchNoRegNoCond

BranchComp

2
Mem2RegData /3
32 / 32 / Control /
ALUOp
MemWrite 3
/
C[31..26]

ALUSrc
RegWrite Comp
2
6 BranchCompType / Branch
Success
/

•
C[25..21] rs

ALUResult[31]
Text
PC
Read Reg1
Read Data1
• . . Zero .

•
Read
Address
•
C[20..16] rt
Read Reg2 Read Data2
• .

••
0 32-Bit .
M Result Address
Instruction ALU .
C[31..0] •TText
•• Register
1 U
X Carry Read Data
2 File 4

Instruction
•ex 0
M 3
2
.
Memory t U Write Reg Write Data
X ZERO Data
RegID($ra) 1 Write Data 2M
Memory
7 1U
ALU
Control / 0X

16 Text C[15..0] 16 32
/ • /
16-32 Sign
Extension /

10
• C[9..0]
/ 32
/
6 6-32 32
C[15..10]
/ Pad Leading
Zeroes
/

21 C[20..0] 32
21-32 Sign
/ Extension /
 Datapath for Instructions in PC-Relative Addressing Mode
( br )
32
/32
/
BranchReg
32
/ 1
• BranchCarryType
M
U
• BranchCarryDep 32 0
X

/ 1
M
U
X
0

C[25..0] Text
28 32 • 1

• Left Shift 2 / Concatenate /

M
U
X
32-Bit
Adder • 21
/
C[20..0] Left Shift 2 +
23-32 1
0

4 SignExtd M
32-Bit
(PC+4)[31..28] /
U
Adder
32 X
FOUR / •
. •
Text 0

•
26 2
/ / RegDest BranchNoRegNoCond

BranchComp

2
Mem2RegData /3
32 / 32 / Control /
ALUOp
MemWrite 3
/
C[31..26]

ALUSrc
RegWrite Comp
2
6 BranchCompType / Branch
Success
/

ALUResult[31]
Text C[25..21] rs
PC
Read Reg1
Read Data1
• . . Zero .

•
Read
Address
•
C[20..16] rt
Read Reg2 Read Data2
• .

••
0 32-Bit .
M Result Address
Instruction ALU .
C[31..0] •TText
•• Register
1 U
X Carry Read Data
2 File 4

Instruction
•ex 0
M 3
2
.
Memory t U Write Reg Write Data
X ZERO Data
RegID($ra) 1 Write Data 2M
Memory
7 1U
ALU
Control / 0X

16 Text C[15..0] 16 32
/ • /
16-32 Sign
Extension /

10
• C[9..0]
/ 32
/
6 6-32 32
C[15..10]
/ Pad Leading
Zeroes
/

21 C[20..0] 32
21-32 Sign
/ Extension /
 Datapath for Instructions in PC-Relative Addressing Mode
( bltz, bz, bnz ) : Unsuccessful Branching
32
/32
/
BranchReg
32
/ 1
• BranchCarryType
M
U
• BranchCarryDep 32 0
X

/ 1
M
U
X
0

28 32 • 1

•
C[25..0] Text M
Left Shift 2 / Concatenate / U
X
32-Bit
Adder • 21
/
C[20..0] Left Shift 2 +
23-32 1
0

4 SignExtd M
32-Bit
(PC+4)[31..28] /
U
Adder
32 X
FOUR / •. •
Text 0

•
26 2
/ / RegDest BranchNoRegNoCond

BranchComp

2
Mem2RegData /3
32 / 32 / Control /
ALUOp
MemWrite 3
/
C[31..26]

ALUSrc
RegWrite Comp
2
6 BranchCompType / Branch
Success
/

ALUResult[31]
•
Text C[25..21] rs
PC
Read Reg1
Read Data1
• . . Zero .

•
Read
Address
•
C[20..16] rt
Read Reg2
Read Data2
• .

••
0 32-Bit .
M Result Address
Instruction ALU .
C[31..0] •TText
•• 2
Register
1 U
X Carry Read Data
File 4

Instruction •ex 0
M 3
2
.
Memory t U Write Reg Write Data
X ZERO Data
RegID($ra) 1 Write Data 2M
Memory
7 1U
ALU
Control / 0X

16 Text C[15..0] 16 32
/ • /
16-32 Sign
Extension /

10
• C[9..0]
/ 32
/
6 6-32 32
C[15..10]
/ Pad Leading
Zeroes
/

21 C[20..0] 32
21-32 Sign
/ Extension /
 Datapath for Instructions in PC-Relative Addressing Mode
( bltz, bz, bnz ) : Successful Branching
32
/32
/
BranchReg
32
/ 1
• BranchCarryType
M
U
• BranchCarryDep 32 0
X

/ 1
M
U
X
0

28 32 • 1

•
C[25..0] Text M
Left Shift 2 / Concatenate / U
X
32-Bit
Adder • 21
/
C[20..0] Left Shift 2
+ 23-32 1
0

4 SignExtd M
32-Bit
(PC+4)[31..28] /
U
Adder
32 X
FOUR / •. •
Text 0

•
26 2
/ / RegDest BranchNoRegNoCond

BranchComp

2
Mem2RegData /
32 / 32 / Control /
3
ALUOp
MemWrite 3
/
C[31..26]

ALUSrc
RegWrite Comp
2
6 BranchCompType / Branch
Success
/

ALUResult[31]
•
Text C[25..21] rs
PC
Read Reg1
Read Data1
• . . Zero .

•
Read
Address
•
C[20..16] rt
Read Reg2 Read Data2
• .
••
0 32-Bit .
M Result Address
Instruction ALU .
C[31..0] •TText
•• Register
1 U
X Carry Read Data
2 File 4

Instruction •x
e
0
M 3
2
.
Memory t U Write Reg Write Data
X ZERO Data
RegID($ra) 1 Write Data 2M
Memory
7 1U
ALU
Control / 0X

16 Text C[15..0] 16 32
/ • /
16-32 Sign
Extension /
10

• C[9..0]
/ 32
/
6 6-32 32
C[15..10]
/ Pad Leading
Zeroes
/

21 C[20..0] 32
21-32 Sign
/ Extension /
• Design of Arithmetic Logic Unit
Following is the design of the 32-bit ALU (control lines are shown in blue color). The adder used is
a 32-bit Carry Look Ahead Adder and the combinational circuit used for implementing the shift
instructions is a 32-bit Barrel Shifter. The AND and XOR instructions are trivial implementations
of bitwise-AND and bitwise-XOR using an array of AND and XOR gates.

• Design of Addition Circuit

The addition component of the ALU is implemented as a Carry Look-Ahead Adder (CLA) with
an augmented look-ahead carry unit. The adder shown below is a 16-bit Carry Look Ahead Adder,
we are simply extending this implementation to build the 32-bit Carry Look Ahead Adder.
• Design of Shift Circuit
The shift component of the ALU is implemented as a Barrel Shifter. The combinational shifter
shown below is an 8-bit Barrel Shifter with a 4-bit shift amount (shamt). In our design, we are
simply extending this implementation to build the 32-bit Barrel Shifter with a 6-bit shift amount.
• Design of Control Logic
There are two control logic units in our processor. One is the Main Controller that controls the
values of the selectors in all the multiplexers and enablers in all the modules. The other one is the
ALU Controller that determines the function that the ALU module has to operate.
Both the control units are implemented as purely combinational circuits with primitive logic gates.
The main controller signal has 13 output ports, emitting the control signals whose significance is
already clear with the datapath diagrams. The ALU control has one 7-bit output that determines
uniquely the ALU operation and some other determiners that are crucial for some specific
operations (refer to the diagram of the ALU design).
Main control signals are purely a function of 𝑜𝑝𝑐𝑜𝑑𝑒 and the ALU control signals are a function of
𝐴𝐿𝑈𝑂𝑝 (a main control signal emitted by the Main Controller) and the 𝑓𝑢𝑛𝑐𝑡 field for the R-Type
instructions.
Main Controller

OPCODE ALUOp MemWrite ALUSrc RegWrite BranchCompType RegDest

000 000 001 0 000 1 XX 00

000 001 010 0 010 1 XX 00
000 010 011 0 000 1 XX 00
000 011 100 0 100 1 XX 00
000 100 101 0 100 1 XX 00
000 101 110 0 001 1 XX 10
000 110 110 1 001 0 XX XX
000 111 000 0 XXX 0 XX XX
001 000 000 0 XXX 1 XX 01
001 001 000 0 XXX 0 XX XX
001 010 000 0 XXX 0 XX XX
001 011 000 0 XXX 0 XX XX
001 100 110 0 011 0 01 XX
001 101 110 0 011 0 00 XX
001 110 110 0 011 0 10 XX

Branch
OPCODE BranchReg BranchCarryType BranchCarryDep BranchComp Mem2RegData
NoRegNoCond

000 000 0 X 0 0 0 00
000 001 0 X 0 0 0 00
000 010 0 X 0 0 0 00
000 011 0 X 0 0 0 00
000 100 0 X 0 0 0 00
000 101 0 X 0 0 0 01
000 110 0 X 0 0 0 XX
000 111 0 X 0 1 0 XX
001 000 0 X 0 1 0 10
001 001 0 1 1 0 0 XX
001 010 0 0 1 0 0 XX
001 011 1 X 0 0 0 XX
001 100 0 X 0 0 1 XX
001 101 0 X 0 0 1 XX
001 110 0 X 0 0 1 XX

ALU Controller

Instruction ALU Op FUNCT ALU Operation ALU Operation Code

and 0000000000 Addition 1000000

add 0000000001 Logical AND 0000001

xor 001 0000000010 Logical XOR 0000010

comp 0000000011 2’s Complement 0001000

— XXXXXXXXXX — 0111111

shll 0000000000 Shift Left Logical 0010011

shrl 0000000001 Shift Right Logical 0000011

010
shra 0000000010 Shift Right Arithmetic 0100011

— XXXXXXXXXX — 0111111

shllv 0000000000 Shift Left Logical 0010011

shrlv 0000000001 Shift Right Logical 0000011

011
shrav 0000000010 Shift Right Arithmetic 0100011

— XXXXXXXXXX — 0111111

addi 100 XXXXXXXXXX Addition 1000000

compi 101 XXXXXXXXXX 2’s Complement 0001000

bnz, bz,
110 XXXXXXXXXX Addition 0000000
bltz, lw, sw

b, bl,
000 XXXXXXXXXX — 0111111
bcy, bncy
• Design of Memory Modules
The processor consists of two memory modules — Instruction Memory and Data Memory.
Since, the processor must not be permitted to overwrite the instruction memory, it is implemented
as a 32-bit enabled Single Port ROM (Read-Only Memory) (left hand side picture). The module
takes as input a 32-bit address and emits the 32-bit binary instruction stored at that address.

The processor must have both read and write access to the data memory and hence it is
implemented as a 32-bit enabled Single Port RAM (Random-Access Memory) (right hand side
picture). Note that though the processor has both read and write access to the data memory, this
access is moderated by the control signals to prevent unwanted write operations on the data
memory. Please refer to the truth-table to learn more about the instructions that allow the
respective access.
For reading, the module takes as input a 32-bit address and emits the 32-bit data that is stored at
that address in the memory. For writing, the write enabling port of the module should be active. It
takes as input a 32-bit address and 32-bit data and writes the data to that address in the memory.

• Design of Register File

This is another very important module in our processor. The 32x32 register file is implemented in
a hierarchical fashion using DFFs that are cascaded to build 32-bit registers that are further
cascaded to build a file of 32 32-bit registers.
The register file uses multiplexors to decode the 5-bit register ID to select exactly one of the 32
registers for read or write operation. There are in-fact 3 multiplexers, with bus width of 32, one for
enabling writing to the destination register (rd), and one for reading from each of the two source
registers (rs and rt).

Register File while Reading Register File while Writing

The 32 registers in the register file are as follows.

Register ID Register Name Purpose

0 $0 / $zero Stores constant value 0

1 – 30 $1 – $30 General purpose registers / temporaries

31 $31 / $ra Stores the linked return address of bl instruction

Unlike in MIPS32, we have not made any special distinction between callee-saved registers
($s<i>), argument registers ($a<i>) and temporaries ($t<i>). All registers can be used for all
purposes, except two special registers $zero and $ra.
$zero stores a constant value of 0. Therefore the register-write-enabled instructions with $zero as
the destination register (rd) may not give the desired result.
# Value of $0 – 0
addi $0, 100
# Value of $0 – 0
# Mem[4] – 123
lw $0, 4($0)
# Value of $0 – 0

Though these instructions are logically illegal because the destination register is read-only, since
we have not developed any interrupt or exception mechanism in our custom ISA, the programmer
might be unaware of this bug.
CAUTION: The programmer should never use $zero as the destination register in
register-write-enabled instructions.

Similarly the use of $ra should also be restricted to bl and br instructions only. If $ra is
overwritten explicitly (say addi $31, 100) and as opposed to only internally by the bl instruction,
the function call mechanism in the code might get disrupted, and that might become extremely
difficult to debug. But if the programmer still has to jump to some custom address using a br but
not the bl instruction, he can use any general purpose register ($1 – $30), copy the value of $ra to
that and can do whatever with that register.

# Value of $1 – 0
add $1, $31
addi $1, 1200 # addi $31, 1200 X
br $1 # br $31 X

CAUTION: The programmer should never use $ra as a destination register in

register-write-enabled instructions.