LVS Best Practice and
Debugging
颜全/Oliver
Sr. Calibre AE
June, 2020
Agenda
1. LVS Basic
What is LVS
ＬＶＳ Flow Chart
2. RVE Review
Multilayer highlights
Search
Short Isolation
3. LVS Case Study
Short
Open
Seed Promotion
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LVS BASIC
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What is LVS?
Layout vs. Schematic (Netlist)
Two Phases
— Extraction - Layout
— Compare
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Calibre nmLVS Execution Examples
“Normal” – Extraction & Compare in one step
○ > calibre –lvs –hier <command file>
Extraction Only (Hierarchical SPICE netlist from the layout)
○ > calibre –spice <layout spice file name> <command file>
Compare Only (Using an existing extracted SPICE netlist)
○ > calibre –lvs –hier –layout <layout spice file name> <command file>
Verify Source Netlist (Check for source netlist compile)
○ > calibre –lvs –cs <command file>
Useful Switches (Add before the command file name)
○ –turbo <no. of processors> Multi-threaded parallel processing
– No. of processors is a positive integer specifying the number of CPU’s needed for run
– No number will use all CPU’s on the machine
○ –hyper Enables the concurrent, parallel execution of SVRF operations
– Can only be used with –turbo
○ –hcell <cell list> Cell correspondence file for compare © Mentor Graphics Corp. Company Confidential
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Hierarchical Engine
The power behind Calibre
Very efficient and smart
> calibre –lvs –hier –hcell <cell list> –hyper <command_file>
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HCell List
List of cells to be used for compare in the hierarchical extraction
Option 1: Generated List (Text File) used with the –hcell switch in the Calibre execution
command line
— > calibre –lvs –hier –hcell <cell list> -hyper <command file>
— Example: <layout name> <source name>
Option 2: HCELL command file syntax
— HCELL <layout name> <source name>
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HCell List (Cont.)
What should be included?
○ User preference
○ Suggestions
– IP Blocks
– Memories
– Standard Cells (Anything with a transistor in it)
– IO Cells
Follow the hierarchy of the design.
○ Cells known to have equal parts
○ Layout and Netlist at the same hierarchy of the design
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When to Use Extraction only flow
Short Isolation
Check Floorplan stage data
○ IO Ring
– Diodes Placed correctly
– ESD Clamps placed correctly
– Power Breaks in the correct locations
○ Power / Ground Structure
○ Multi Rail P/G Structure
○ Special Nets
○ Hand Routed Nets
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Compare
> calibre –lvs –hier –hcell <cell list>
<command_file>
What is needed:
○ Command file
○ Extracted results
○ Verilog/Spice netlist
– Spice is created from Verilog using v2lvs
○ Hcell list
○ Do not need to re-run extraction if Netlist has changed and layout
has not
Know your design and what is expected
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LVS Flow Chart
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RVE REVIEW
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LVS CASE STUDY
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LVS Case Study
Case List:
#1 - Cell-Level Short
#2 - Combined Short and Open
2 Conn.
#3 – Seed Promotion with Bad
Devices
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Case #1 — Cell-level Short
Case #1 - Cell-Level Short
The Problem
A piece of metal in a cell is
shorting power and ground at
3 Shorts
the top level.
Return to Case List
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Case #1 — Cell-Level Short (Cont.)
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Case #1 — Run LVS Job
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Case #1 — Check Extraction Results
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Case #1 — Invoke Short Isolation
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Case #1 — Highlight the Short
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Case #1 — Invoke Short Isolation Options
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Case #1 — Examine Isolation Results
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Case #1 — Set Up Highlight Colors
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Case #1 — Highlight Metal2
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Case #1 — Highlight Metal1
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Case #1 — View Cell Detail
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Case #1 — Fix the Short
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Case #1 — LVS Is Correct
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Case #1 — Conclusion
Case #1 - Cell-Level Short
The Problem
A piece of metal in a cell is
shorting power and ground at
3 Shorts
the top level.
Lesson Learned
Use of the short isolation BY
LAYER feature can help locate
shorting geometries.
Return to Case List
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Case #2 — Combined Short and Open
Case #2 - Combined Short and
Open
The Problem
An incorrect metal connection
has shorted two nets and also
2 Conn.
created an open circuit.
Return to Case List
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Case #2 — Combined Short and Open (Cont.)
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Case #2 — Run Job
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Case #2 — Expand Analysis Results
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Case #2 — Highlight Shorted Net
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Case #2 — Highlight Instance
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Case #2 — Highlight Correct Net
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Case #2 — Highlight Devices
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Case #2 — Identify Fix
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Case #2 — Fix the Layout
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Case #2 — Re-Run Job
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Case #2 — Conclusion
Case #2 - Combined Short and
Open
The Problem
An incorrect metal connection
has shorted two nets and also
2 Conn.
created an open circuit.
Lesson Learned
Error analysis and the
schematic viewer can be used
to quickly identify incorrectly-
connected pins.
Return to Case List
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Case #3 — Seed Promotion With Bad Devices
Case #3 - Seed Promotion With
Bad Devices
The Problem
Even though LVS PUSH
DEVICES YES is specified, a
4 Device
promoted device is not pushed
back into its parent cell.
Return to Case List
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Case #3 — Seed Promotion With Bad Devices (Cont.)
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Case #3 — Run Extraction Job
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Case #3 — Examine Netlist
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Case #3 — Examine Transcript
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Case #3 — Examine Rule File
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Case #3 — Examine Extraction Report
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Case #3 — Examine the Layout
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Case #3 — Fix the Layout
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Case #3 — Re-Run Extraction
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Case #3 — Examine Netlist
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Case #3 — Conclusion
Case #4 - Seed Promotion With
Bad Devices
The Problem
Even though LVS PUSH
DEVICES YES is specified, a
4 Device
promoted device is not pushed
back into its parent cell.
Lesson Learned
A device recognition error
involving one placement of a
cell will prevent pushdown of
the device into that cell.
Return to Case List
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Calibre应用技巧系列讲座第六期
如何使用calibre PERC进行芯片可靠性相关检查
时间：6月16日下午16：30 -17：30
主讲人：吴文鑫
扫码报名
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