BEETC321 Manthan Choudhury

Pimpri Chinchwad Education Trust’s

Pimpri Chinchwad College of Engineering

Department of Electronics and Telecommunication Engineering

Experiment No.:1

Academic Year:2021- 2022 Year: BE (A,B, C) Semester:I Course: Lab practice II (VLSI
Design&Technology) Course Code: 404186

TITLE: Design of 4 bit ALU for add, subtract, AND, NAND, XOR, XNOR, OR & ALUpass.

OBJECTIVES OF THE EXPT.:

1. Write VHDL code for 4 bit ALU using Xilinx ISE Design Suite 14.4 andsynthesize
2. Simulate the design writing test bench using ISimSimulator
3. Implement design on Digilent ATLYS board with Spartan6FPGA

CO andPOMAPPED: CO1 PO-1,3,5 PSO-2

REQUIREMENTS:
1. Xilinx ISE Design Suite 14.7 EDA tool for coding andsynthesis
2. ISim Simulator inbuilt in Xilinx forsimulation
3. Digilent ATLYS board with Spartan6 FPGA forimplementation

BLOCK DIAGRAM:

4
A 4

4-BIT ALU Y

4
B

SELECT LINES

DESCRIPTION:

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 BEETC321 Manthan Choudhury

The 4-bit ALU is a combinational design used to perform various arithmetic and logical operations.
The ALU accepts 4 bit data (operands) through its two input ports (A and B) and performs the desired
arithmetic or logical operation as chosen by user. User decides the operation with the help of select
lines (SELECT). The designed ALU has 3 select lines, so it can perform any one out of total eight
operations depending on the status of select lines. The 4 bit output is taken out from the outputport(Y)
of ALU. The designed 4-bit ALU performs a number of basic arithmetic and bitwise logic functions
includingadd,subtract,AND,NAND,XOR,XNORandOR.IncaseofALUpassoperation(alsocalled
Passthroughoperation),allbitsofA(orB)appearunmodifiedatY.Thisoperationistypicallyusedto determine
the parity of the operand or whether it is zero or negative, or to load the operand into a processor
register. If user selects any undesired value of select line, then the output bus goes into high
impedancestate.

STEPS FOR IMPLEMENTATION:

1. Open ISE Design Suite 14.4 and ISE Project Navigator window would comeup.
2. Create a new Project, provide project name and select location for saving theproject.
3. In New Project Wizard Window, provide the followingdetails:
● Family- Spartan 6
● Device -XC6SLX45
● Package -CSG324
● Speed --3
● Synthesis Tool - XST(VHDL/Verilog)
● Simulator- ISim (VHDL/Verilog)
● Preferred Language - VHDL ClickFinish
4. Right Click on Project Name and select new source as VHDL module and write the VHDL
code for the intendeddesign.
5. Perform Check syntax operation under Synthesize process to verify that the code is
syntacticallycorrect.
6. View RTL schematic and observe the Block diagram and its detailedconnection.
7. Forperformingsimulation,writeclickonVHDLfileandselectnewsource.NowselectVHDL Test
Bench option, and in this window, write VHDL code for testbench.
8. Select Simulation Radio button at left hand top corner of Navigatorwindow.
9. In ISim simulator process, perform Behavioral Check Syntax followed by Simulate
Behavioral Model. Run the simulation and observe the output in ISimwindow.
10. Now for implementation, Select Implementation Radio button at left hand top corner of
Navigatorwindow.
11. Right click on VHDL file, go to New Source and select Implementation constraintfile.
12. In UCF file, assign pin numbers for inputs and outputs looking at the switches and LEDs on
Digilent ATLYS board. The template for the same is asunder:

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 BEETC321 Manthan Choudhury

Net "<Port Name>" LOC= "Switch/LED number"

13. Click on Implement design which includes Translate, Map, Place and Route
14. Now select Generate Programming File process to create the bitfile.
15. Next in Configure target device option, double click on Mange Configuration Project
(iMPACT)
16. In ISE iMPACT window, double click on Boundary Scan. Right Click on window andselect
Add Xilinx Device
17. Now select the appropriate bit file from Assign New Configuration Filewindow
18. Right click on Xilinx Icon and select ProgramOption.
19. ApplytheinputthroughonboardswitchesorinterfacedAdd-onModuleandobservetheoutput on
the intended output device which may be on board LED/LCD/SSD/Add-onModule

QUESTIONS:

1. In short, write about the Levels of Abstractions inVHDL.

2. List down few EDA tools for VLSIdesign.
3. List down few VLSI companies in India andabroad.
4. Draw the flowchart of Frontend design flow and Backend design flow.
5. Explain in short simulation andsynthesis.

PCCOE-E & TC - VLSI Design & Technology

 BEETC321 Manthan Choudhury

Pimpri Chinchwad Education Trust’s

Pimpri Chinchwad College of Engineering

Experiment No. 1 Experimentation

details
Department:E&TC Academic Year: 2021-22 Semester-
I
Class:BEE&TC Course: VLSI Design and Technology

Name of Student: Manthan Choudhury

Div C and Batch: C2

Roll No: BEETC321

Title of the Experiment:

To write VHDL code for 4-bit ALU for add, subtract, AND, NAND, XOR, XNOR, OR, & ALU
pass simulate with test bench, synthesis, implement on PLD.

Software Requirements:Xilinx 14.7 ISE Design Suite

Hardware Requirements:Xilinx Spartan-6 XC6SLX45 FPGA

VHDL Code for 4-bit ALU

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity alu_lab2is
Port (A,B : in STD_LOGIC_VECTOR (3 downto 0);
sel : in STD_LOGIC_VECTOR (2 downto 0);
Y : out STD_LOGIC_VECTOR (3 downto 0)); end
alu_lab2;

architecture Behavioral of alu_4bit is

begin process(A,B,sel)
begin case sel is when "000" => Y <=A+B; when
"001" => Y <=A-B; when "010" => Y <=A
ANDB;

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 BEETC321 Manthan Choudhury

when "011" => Y <=A NAND B; when "100"

=> Y <=A XOR B; when "101" => Y <=A XNOR B;
when "110" => Y <=A OR B; when "111"
=> Y <=A;
when others => Y <="ZZZZ"; end case;
end process;
endBehavioral;

RTL Schematic
Block Diagram of Design

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 BEETC321 Manthan Choudhury

Detailed Schematic

VHDL Test Bench

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY alu IS
END alu;

ARCHITECTURE behavior OF alu IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT alu_lab2
PORT(
A : IN std_logic_vector(3 downto 0);
B : IN std_logic_vector(3 downto 0);
sel : IN std_logic_vector(2 downto 0);
Y : OUT std_logic_vector(3 downto0)
);
END COMPONENT;
--Inputs signal A : std_logic_vector(3 downto 0) :=
(others => '0'); signal B : std_logic_vector(3 downto 0) :=
(others => '0'); signal sel : std_logic_vector(2 downto
0) := (others => '0'); --Outputs
signal Y : std_logic_vector(3 downto 0);
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 BEETC321 Manthan Choudhury

BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: alu_lab2 PORT MAP (
A => A,
B =>B,
sel => sel,
Y =>Y
);
PROCESS
BEGIN
A<="0011";
B<="0100";
sel<="000";
wait for 20ns;
A<="1011";
B<="0001";
sel<="001";
wait for 20ns;
sel<="010";
wait for 20ns;
sel<="011";
wait for
20ns;
sel<="100";
wait for 20ns;
sel<="101";
wait for 20ns;
sel<="110";
wait for 20ns;
sel<="111";
wait;
end process; END;

Simulation Results 4-bit

ALU

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 BEETC321 Manthan Choudhury

Implementation on Spartan 6
2-bit ALU
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Expt_1b is
Port ( A : in STD_LOGIC_VECTOR(1 downto 0);
B : in STD_LOGIC_VECTOR(1 downto 0);
sel : in STD_LOGIC_VECTOR(2 downto 0);
Y : out STD_LOGIC_VECTOR(1 downto0)); end
Expt_1b;

architecture Behavioral of Expt_1b is

begin process(A,B,sel)
begin
case sel is
when "000" => Y <=A+B; when "001" => Y
<=A-B; when "010" => Y <=A ANDB;
when "011" => Y <=A NAND B; when "100"
=> Y <=A XOR B; when "101" => Y <=A XNOR B;
when "110" => Y <=A OR B;
when "111" => Y <=A; when others
=> Y <="ZZ"; end case;
end process;
endBehavioral;

Device Specifications to be selected while implementing:

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 BEETC321 Manthan Choudhury

Implementation Constraint File

Net"A<0>"LOC="A10";
Net"A<1>"LOC="D14";
Net"B<0>"LOC="C14";
Net"B<1>"LOC="P15";
Net"SEL<0>"LOC="P12";
Net"SEL<1>"LOC="R5";
Net"SEL<2>"LOC="T5";
Net"Y<0>"LOC="U18"; Net"Y<1>"LOC="M14";

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 BEETC321 Manthan Choudhury

Implementation Successful

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 BEETC321 Manthan Choudhury

Hardware Snapshots Digilent ATLYS Spartan 6 FPGA Board

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