PRESIDENCY UNIVERISTY, BENGALURU, School of Engineering

Computer Organization and Architecture

CSE 2009

Module-2: Instruction Set Architecture and Memory Unit

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 Addressing modes
• The different ways in which the location of an operand is specified
in an instruction are referred to as addressing modes.
• We can access an operand by specifying the name of the register
or the address of the memory location where the operand is
located.
1. Register Mode:
The operand is the contents of a processor register, the
name(address) of the register is given in the instruction.
e.g. MOV R1,R2
The instruction copies the contents of register R1 to register R2.

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2. Absolute mode:
The operand is in a memory location; the address of
this location is given explicitly in the
instruction.(In some assembly languages, this mode
is called direct).
The instruction uses two modes.
E.g. MOV LOCA,R2
Processor registers are used as temporary storage
locations where the data in a register are
accessed using register mode.

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3. Immediate mode:

• The operand is given explicitly in the instruction.

e.g. MOV 200immediate,R0
• The instruction places the value 200 in the register R0.
• The immediate mode is only used to specify the value of a source
operand. Using a subscript to denote the immediate mode is not
appropriate in assembly languages.
• A common convention is to use the sharp sign (#) in front of the
value to indicate that this value is to be used as an immediate
operand.
Hence we write the instruction above in the form
MOV #200,R0

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4. Indirect mode:
• In this addressing mode, the instruction does not give the operand or its address
explicitly. instead it provides information from which the memory address of the
operand can be determined. we refer to this address as the effective address(EA) of
the operand.

• The effective address of an operand is the contents of register or memory location

whose address appears in the instruction.

• To execute the add instruction in the figure(A) the processor uses the value B, which is
in the register R1, as the effective address of the operand. the value read is desired
operand, which the processor adds to the contents or register R0.

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Tuesday, February 27, 2024
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• Indirect addressing through a memory location is also possible as
shown in the figure(b). In this case processor first reads the contents
of memory location A, then requests a second read operation using the
value B as an address to obtain the operand.

• The register or memory location that contains the address of an

operand is called a pointer.

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5. Index mode :
• The effective address of the operand is generated by
adding a constant value to the contents of a register.
• The register used may be either a special register
provided for this purpose, or more commonly, it may be any
one of a set of general-purpose registers in the processor.
• In either case, it is referred to as an index register.
• We indicate the index mode symbolically as
X(Ri)
X denotes the constant value in the instruction, Ri is name
of the register involved.
Effective address of the operand is given by
EA = X+[Ri]

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Tuesday, February 27, 2024 9
Tuesday, February 27, 2024 10
• Figure illustrates two ways of using the index mode.
• In figure A the index register R1, contains the address of a
memory location and the value X defines an offset(also
called displacement) from this address to the location
where the operand is found.
• An alternative use is illustrated in figure B. Here, the
constant X corresponds to a memory address, and the
contents of the index register define the offset to the
operand.
• In either case, the effective address is the sum of the two
values, one is given explicitly in instruction and the other is
stored in a register.

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 Base with Index Mode
• In this addressing mode Effective Address is the sum of two
registers.
Syntax:
(Ri,Rj)

Effective Address:

EA= [Ri]+[Rj]

The first register is called Index Register.

The second register is called Base Register.

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 Base with Index and Offset
• In this addressing mode effective address is the sum of
the constant(X) and the contents of the two registers.

Syntax:
X(Ri,Rj)

EA=[Ri]+[Rj]+X

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6. Relative Addressing:
• We have discussed the index mode using general-purpose register.
• A useful version of this obtained if program counter(PC) is used instead of a
general purpose register.
• Then X(PC) can be used to address a memory location that is X bytes away
from the location pointed by the program counter.
EA=[PC]+X
The effective address is determined by the index mode using the program
counter in the place of the general purpose register.
Its common use is to specify the target address in branch instructions. An
instruction such as
Branch>0 Loop
Causes program execution to go to the branch target location identified by the
name LOOP if the branch condition is satisfied. this location can be
computed by specifying it as an offset from the current value of the
program counter

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 Additional Modes
• So far we have discussed the six basic addressing modes- register, absolute,
immediate, index, indirect and relative.
• Many computers provide two additional modes:
1) Autoincrement Mode
2) Autodecrement Mode

Autoincrement mode:
• The effective address of an operand is contents of register specified in the
instruction. After accessing the operand, the contents of the register are
automatically incremented to point to the next item in the list.
• We denote autoincrement mode by putting the specified register in
parentheses, to show that contents of register are used as the effective
address.

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• The autoincrement mode is written as
(Ri)+
Autodecrement mode:

• The contents of a register specified in the instruction are first

automatically decremented and are then used as the effective
address of the operand.
• We denote the autodecrement mode by putting the specified register
in parentheses, preceded by a minus sign to indicate that the
contents of the register are to be decremented before being used as
the effective address. Thus we write
-(Ri)

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 STACK
• Data operated on by a program can be organized in a variety of
ways.
• Now, we consider the important data structure known as
STACK.
• A stack is a list of data elements usually words or bytes with
the accessing restriction that elements can be added or
removed at one end of the list only, this end is called TOP of
the STACK, and the other end is called the bottom.
• The structure sometimes referred to as a pushdown stack or
last –in first –out(LIFO). That is the last data item placed on
the stack is the first one removed when retrieval begins.

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PUSH:
• Placing a new item on the stack.
POP:
• Removing the top item from the stack.

• Assume that the first element is placed in location bottom, and when
new elements are pushed onto the stack, they are placed in
successively lower address locations. We use a stack that grows in
the direction of decreasing memory addresses in our discussion,
because this is common practice.
• The figure shows a stack of data items in the memory of a computer,
it contains numerical values, with 43 at the bottom and -28 at the top.
• A processor register is used to keep track of the address of the
element of the stack that is at the top at any given time. this register
is called the STACK POINTER(SP).

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• If we assume a byte addressable memory with 32-bit word length the push
operation can be implemented as

Subtract #4,SP
Move NEWITEM,(SP)

These two instructions move the word from location NEWITEM onto the top of the
STACK decrementing the stack pointer before the move.
The POP operation can be implemented as
Move (SP), ITEM
Add #4,SP
These two instructions move the top value from the stack into the location ITEM
and then increment the stack pointer by 4 so that it points to the new top
element. The figure shows the effect of the each of these operations on the
stack.

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Tuesday, February 27, 2024 21
• If the processor has the autoincrement and autodecrement addressing modes
the push operation can be performed by the single instruction
MOVE NEWITEM, -(SP)
And pop operation can be performed by
MOVE (SP)+, ITEM
• When a stack used in a program, it is usually allocated a fixed amount of space
in the memory .
• In this case we must avoid pushing an item onto the stack when the stack
has reached its maximum size.
• Also, we must avoid attempting to POP an item off an empty stack, which could
result from a programming error.

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• Suppose that a stack runs from location 2000(bottom) .

• The stack pointer is loaded initially with the address value 2004. recall
that SP is decremented by 4 before new item pushed on the stack.
Hence an initial value of 2004 means that the first item pushed onto the
stack will be at location 2000.

• To prevent either pushing an item on a full stack or popping an item

off an empty stack the single instruction push and pop operations can
be replaced by the instruction sequences shown in the figure.

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 SAFE PUSH

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 SAFEPOP

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 SUBROUTINES
• In a given program, it is often necessary to perform a particular subtask
many times.

• A subroutine is a group of instructions, performs a particular subtask

which is executed number of times. It is written separately.

• The processor executes this subroutine by transferring the program

control to the subroutine program.

• After completion of subroutine program execution, the program control is

returned back to the main program.

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Tuesday, February 27, 2024 27
CALL Instruction:

The call instruction performs the following operations

• Store the contents of the Program counter(PC) in the link register.

• Branch to the target address specified by the instruction.

RETURN Instruction:

• Loads the program counter(PC) with the contents of link register and
branch to that address.

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 Subroutine Nesting
• When one subroutine calls another subroutine to complete a particular
task, the operation is called NESTING.

Calling program SUB1 SUB2

1 1 1
2 2 2
3 3 3
CALL SUB1 CALL SUB2 4
5 5 5
6 RET
RET
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• In this case, the return address(RA) of the second call is also stored

in the link register, destroying its previous contents.

• Hence it is essential to save the contents of the link register in some

other location before calling another subroutine, otherwise the return

address of the first subroutine will be lost.

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 Parameter Passing
• When calling a subroutine, a program must provide to the subroutine the parameters ,
that is operands or their addresses, to be used in the computation.

• Later the subroutine returns other parameters, in this case the results of the
computation.

• This exchange of information between a calling program and a subroutine is referred to as

parameters passing.

• Parameters passing may be accomplished in several ways.

• The parameters may be placed in registers or in memory locations, where they can be
accessed by subroutine.

• Alternatively, the parameters may be placed on the processor stack.

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 Passing Parameters Through
Registers.
• Passing parameters through registers is straight forward and efficient.

• Figure shows how the program for adding a list of numbers can be

implemented as subroutine.

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• If many parameters are involved, there may not be

enough general-purpose registers available for passing

them to the subroutine.

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The Memory System
Fundamental Concepts
Some basic concepts
• Maximum size of the memory of a computer is
determined by the number of address lines of the
processor bus.
• For ex, computer having 16 address lines are capable of
addressing upto 216 = 64K memory locations.
• So, in general, if there are K bit address lines, then there
are 2K memory locations
• If the memory is byte addressable, each location of
memory can store 8 bit of information.
• So, memory capacity L=2K locations * 8 bits/location= 2K
bytes
Some basic concepts
• Maximum size of the Main Memory
• byte-addressable
• CPU-Main Memory Connection
Processor Memory
k-bit
address bus
MAR
n-bit
data bus Up to 2k addressable
MDR locations

Word length = n bits

Control lines
( R / W , MFC, etc.)
Some basic concepts
• Maximum size of the memory of a computer is
determined by the number of address lines of the
processor bus.
• For ex, computer having 16 address lines are capable of
addressing upto 216 = 64K memory locations.
• So, in general, if there are K bit address lines, then there
are 2K memory locations
• If the memory is byte addressable, each location of
memory can store 8 bit of information.
• So, memory capacity L=2K locations * 8 bits/location= 2K
bytes
Some basic concepts(Contd.,)
 Measures for the speed of a memory:
 memory access time.
 memory cycle time.
 An important design issue is to provide a
computer system with as large and fast a
memory as possible, within a given cost target.
 Several techniques to increase the effective size
and speed of the memory:
 Cache memory (to increase the effective speed).
 Virtual memory (to increase the effective size).
The Memory System
• Semiconductor RAM memories
Internal organization of memory
chips
• Each memory cell can hold one bit of information.
• Memory cells are organized in the form of an array.
• One row is one memory word.
• All cells of a row are connected to a common line, known as
the “word line”.
• Word line is connected to the address decoder.
• Sense/write circuits are connected to the data input/output
lines of the memory chip.
Internal organization of memory
chips (Contd.,)
7 7 1 1 0 0
W0

•
•
•
FF FF
A0 W1

•
•
•
A1
Address Memory
• • • • • • cells
decoder • • • • • •
A2
• • • • • •
A3

W15
•
•
•

Sense / Write Sense / Write Sense / Write R/W

circuit circuit circuit
CS

Data input /output lines: b7 b1 b0

 Internal organization of memory chips (Contd.,)
 The previous figure is an example of a very small memory circuit consisting of 16
words of 8 bits each. This is referred to as a 16 × 8 organization. The data input
and the data output of each Sense/Write circuit are connected to a single
bidirectional data line that can be connected to the data lines of a computer. Two
control lines, R/W and CS, are provided. The R/W Read/Write) input specifies the
required operation, and the CS (Chip Select) input selects a given chip in a
multichip memory system.

 The memory circuit stores 128 bits and requires 14 external connections for
address, data, and control lines. It also needs two lines for power supply and
ground connections. Consider now a slightly larger memory circuit, one that has
1K (1024) memory cells. This circuit can be organized as a 128 × 8 memory,
requiring a total of 19 external connections. Alternatively, the same number of
cells can be organized into a 1K×1 format. In this case, a 10-bit address is needed,
but there is only one data line, resulting in 15 external
 Read-Only Memories (ROMs)
 SRAM and SDRAM chips are volatile:
 Lose the contents when the power is turned off.
 Many applications need memory devices to retain contents after the power
is turned off.
 For example, computer is turned on, the operating system must be loaded from
the disk into the memory.
 Store instructions which would load the OS from the disk.
 Need to store these instructions so that they will not be lost after the power is
turned off.
 We need to store the instructions into a non-volatile memory.
 Non-volatile memory is read in the same manner as volatile memory.
 Separate writing process is needed to place information in this memory.
 Normal operation involves only reading of data, this type
of memory is called Read-Only memory (ROM).
Read-Only Memories (Contd.,)
 Read-Only Memory:
 Data are written into a ROM when it is manufactured.
 Programmable Read-Only Memory (PROM):
 Allow the data to be loaded by a user.
 Process of inserting the data is irreversible.
 Storing information specific to a user in a ROM is expensive.
 Providing programming capability to a user may be better.
 Erasable Programmable Read-Only Memory (EPROM):
 Stored data to be erased and new data to be loaded.
 Flexibility, useful during the development phase of digital systems.
 Erasable, reprogrammable ROM.
 Erasure requires exposing the ROM to UV light.
Read-Only Memories (Contd.,)
 Electrically Erasable Programmable Read-Only Memory (EEPROM):
 To erase the contents of EPROMs, they have to be exposed to ultraviolet light.
 Physically removed from the circuit.
 EEPROMs the contents can be stored and erased electrically.
 Flash memory:
 Has similar approach to EEPROM.
 Read the contents of a single cell, but write the contents of an entire block of
cells.
 Flash devices have greater density.
▪ Higher capacity and low storage cost per bit.
 Power consumption of flash memory is very low, making it attractive for use
in equipment that is battery-driven.
 Single flash chips are not sufficiently large, so
larger memory modules are implemented using
flash cards and flash drives.
Speed, Size, and Cost
 A big challenge in the design of a computer system is to
provide a sufficiently large memory, with a reasonable
speed at an affordable cost.
 Static RAM:
 Very fast, but expensive, because a basic SRAM cell has a complex
circuit making it impossible to pack a large number of cells onto a
single chip.
 Dynamic RAM:
 Simpler basic cell circuit, hence are much less expensive, but
significantly slower than SRAMs.
 Magnetic disks:
 Storage provided by DRAMs is higher than SRAMs, but is still less
than what is necessary.
 Secondary storage such as magnetic disks provide a large amount
of storage, but is much slower than DRAMs.
 Memory Hierarchy
Processor •Fastest access is to the data held in
processor registers. Registers are at
Registers the top of the memory hierarchy.
Increasing Increasing Increasing •Relatively small amount of memory that
size speed cost per bit can be implemented on the processor
Primary L1
cache chip. This is processor cache.
•Two levels of cache. Level 1 (L1) cache
is on the processor chip. Level 2 (L2)
cache is in between main memory and
SecondaryL2 processor.
cache
•Next level is main memory, implemented
as SIMMs. Much larger, but much slower
than cache memory.
Main •Next level is magnetic disks. Huge amount
memory of inexepensive storage.
•Speed of memory access is critical, the
idea is to bring instructions and data
Magnetic disk
that will be used in the near future as
secondary close to the processor as possible.
memory
Cache Memories
 Processor is much faster than the main memory.
 As a result, the processor has to spend much of its time waiting
while instructions and data are being fetched from the main
memory.
 Major obstacle towards achieving good performance.
 Speed of the main memory cannot be increased beyond
a certain point.
 Cache memory is an architectural arrangement which
makes the main memory appear faster to the processor
than it really is.
 Cache memory is based on the property of computer
programs known as “locality of reference”.
Locality of Reference
 Analysis of programs indicates that many instructions
in localized areas of a program are executed repeatedly
during some period of time, while the others are
accessed relatively less frequently.
 These instructions may be the ones in a loop, nested loop or few
procedures calling each other repeatedly.
 This is called “locality of reference”.
 Temporal locality of reference:
 Recently executed instruction is likely to be executed again very
soon.
 Spatial locality of reference:
 Instructions with addresses close to a recently instruction are
likely To be executed soon.
 Cache memories
Main
Processor Cache memory

• Processor issues a Read request, a block of words is transferred from the main
memory to the cache, one word at a time.
• Subsequent references to the data in this block of words are found in the cache.
• At any given time, only some blocks in the main memory are held in the cache.
Which blocks in the main memory are in the cache is determined by a
“mapping function”.
• When the cache is full, and a block of words needs to be transferred
from the main memory, some block of words in the cache must be
replaced. This is determined by a “replacement algorithm”.
Cache hit
• Existence of a cache is transparent to the processor. The processor
issues Read and
Write requests in the same manner.
• If the data is in the cache it is called a Read or Write hit.
• Read hit:
 The data is obtained from the cache.
• Write hit:
 Cache has a replica of the contents of the main memory.
 Contents of the cache and the main memory may be updated simultaneously.
This is the write-through protocol.
 Update the contents of the cache, and mark it as updated by setting a bit
known as the dirty bit or modified bit. The contents of the main memory
are updated when this block is replaced. This is write-back or copy-back
protocol.
 Cache miss
• If the data is not present in the cache, then a Read miss or Write miss occurs.

• Read miss:
 Block of words containing this requested word is transferred from the memory.
 After the block is transferred, the desired word is forwarded to the processor.
 The desired word may also be forwarded to the processor as soon as it is transferred
without waiting for the entire block to be transferred. This is called load-through or
early-restart.

• Write-miss:
 Write-through protocol is used, then the contents of the main memory are
updated directly.
 If write-back protocol is used, the block containing the
addressed word is first brought into the cache. The desired word
is overwritten with new information.
Cache Coherence Problem
• A bit called as “valid bit” is provided for each block.
• If the block contains valid data, then the bit is set to 1, else it is 0.
• Valid bits are set to 0, when the power is just turned on.
• When a block is loaded into the cache for the first time, the valid bit is set to
1.
• Data transfers between main memory and disk occur directly bypassing the
cache.
• When the data on a disk changes, the main memory block is also updated.
• However, if the data is also resident in the cache, then the valid bit is set to 0.
• What happens if the data in the disk and main memory changes and the
write-back protocol is being used?
• In this case, the data in the cache may also have changed and is indicated by
the dirty bit.
• The copies of the data in the cache, and the main memory are different. This
is called the cache coherence problem.
• One option is to force a write-back before the main memory is updated from
the disk.
Mapping functions
 Mapping functions determine how memory blocks are
placed in the cache.
 A simple processor example:
 Cache consisting of 128 blocks of 16 words each.
 Total size of cache is 2048 (2K) words.
 Main memory is addressable by a 16-bit address.
 Main memory has 64K words.
 Main memory has 4K blocks of 16 words each.
 Three mapping functions:
 Direct mapping
 Associative mapping
 Set-associative mapping.
Direct mapping
Main Block 0 •Block j of the main memory maps to j modulo 128 of
memory
the cache. 0 maps to 0, 129 maps to 1.
Cache Block 1
•More than one memory block is mapped onto the same
tag
Block 0 position in the cache.
tag •May lead to contention for cache blocks even if the
Block 1
cache is not full.
Block 127 •Resolve the contention by allowing new block to
Block 128 replace the old block, leading to a trivial replacement
tag
algorithm.
Block 127 Block 129
•Memory address is divided into three fields:
- Low order 4 bits determine one of the 16
words in a block.
- When a new block is brought into the cache,
Block 255 the the next 7 bits determine which cache
Tag Block Word
Block 256 block this new block is placed in.
5 7 4
- High order 5 bits determine which of the possible
Main memory address Block 257 32 blocks is currently present in the cache. These
are tag bits.
•Simple to implement but not very flexible.

Block 4095
Set-Associative mapping
Cache
Main Block 0 Blocks of cache are grouped into sets.
memory
tag Block 0 Mapping function allows a block of the main
Block 1
tag
memory to reside in any block of a specific set.
Block 1
Divide the cache into 64 sets, with two blocks per set.
tag Block 2 Memory block 0, 64, 128 etc. map to block 0, and they
tag Block 3 can occupy either of the two positions.
Block 63 Memory address is divided into three fields:
Block 64 - 6 bit field determines the set number.
tag - High order 6 bit fields are compared to the tag
Block 126 Block 65
fields of the two blocks in a set.
tag
Block 127 Set-associative mapping combination of direct and
associative mapping.
Number of blocks per set is a design parameter.
Tag Block Word
Block 127 - One extreme is to have all the blocks in one set,
Block 128 requiring no set bits (fully associative mapping).
5 7 4
- Other extreme is to have one block per set, is
Block 129
Main memory address the same as direct mapping.

Block 4095
Associative mapping
Main Block 0
memory

Block 1
•Main memory block can be placed into any cache
Cache
tag
position.
Block 0 •Memory address is divided into two fields:
tag
Block 1 - Low order 4 bits identify the word within a block.
- High order 12 bits or tag bits identify a memory
Block 127
block when it is resident in the cache.
Block 128 •Flexible, and uses cache space efficiently.
tag
Block 127 Block 129
•Replacement algorithms can be used to replace an
existing block in the cache when the cache is full.
•Cost is higher than direct-mapped cache because of
the need to search all 128 patterns to determine
whether a given block is in the cache.
Block 255
Tag Word
12 4 Block 256

Main memory address Block 257

Block 4095