College of Computers and Information ‫كلية الحاسبات وتقنية‬

Technology ‫المعلومات‬

THE MICROPROCESSOR AND

ITS ARCHITECTURE
 Inside the 8088/8086
 Introduction to Assembly Language
 Introduction to Program Segments
 More about Segments in the 80x86

Chapter 2
CLO1

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Technology ‫المعلومات‬

Objectives of Chapter 2
By the end of this chapter, the student will be able
to:
 Describe function and purpose of each program-
visible register in the 8086 microprocessors.
 Detail the flag register and the purpose of each
flag bit.
 Describe the different segments of the memory.

Chapter 2
CLO1

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The
The Programming
Programming Model
Model
 8086 through Core2 consider two types of registers:
 Program visible registers:
 registers are used during programming and are specified by
the instructions
 Program invisible registers:
 not addressable directly during applications programming

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Technology ‫المعلومات‬

The
The Programming
Programming Model
Model
 80286 and above contain program-invisible registers to
control and operate protected memory.
 and other features of the microprocessor
 80386 through Core2 microprocessors contain full 32-bit
internal architectures.
 8086 through the 80286 are fully upward-compatible to
the 80386 through Core2.
 The following figure illustrates the programming model
8086 through Core2 microprocessor including the 64-bit
extensions

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 College of Computers and Information ‫كلية الحاسبات وتقنية‬
Technology ‫المعلومات‬

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 College of Computers and Information ‫كلية الحاسبات وتقنية‬
Technology ‫المعلومات‬

The
The Programming
Programming Model
Model
Multipurpose Registers
o RAX - a 64-bit register (RAX), a 32-bit register (accumulator)
(EAX), a 16-bit register (AX), or as either of two 8-bit registers
(AH and AL).

 The accumulator is used for instructions such as multiplication, division,

and some of the adjustment instructions.
o RBX, addressable as RBX, EBX, BX, BH, BL.
 BX register (base index) sometimes holds offset address
of a location in the memory system in all versions of the
microprocessor
o RCX, as RCX, ECX, CX, CH, or CL.
 a (count) general-purpose register that also holds the
count for various instructions
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Technology ‫المعلومات‬

The
The Programming
Programming Model
Model
Multipurpose Registers
o RDX, as RDX, EDX, DX, DH, or DL.
 a (data) general-purpose register
 holds a part of the result from a multiplication or part of
dividend before a division.
o RBP, as RBP, EBP, or BP.
 points to a memory (base pointer) location for memory
data transfers
o RDI addressable as RDI, EDI, or DI.
 often addresses (destination index) string destination
data for the string instructions

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The
The Programming
Programming Model
Model
Multipurpose Registers
o RSI used as RSI, ESI, or SI.
 the (source index) register addresses source string data
for the string instructions
 like RDI, RSI also functions as a general-purpose register
o R8 - R15 found in the Pentium 4 and Core2 if 64-bit
extensions are enabled.
 data are addressed as 64-, 32-, 16-, or 8-bit sizes and are
of general purpose

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The
The Programming
Programming Model
Model
Special-Purpose Registers
o Include RIP, RSP, and RFLAGS
 segment registers include CS, DS, ES, SS, FS, and GS
o RIP addresses the next instruction in a section of memory.
 defined as (instruction pointer) a code segment
o RSP addresses an area of memory called the stack.
 the (stack pointer) stores data through this pointer
o RFLAGS indicate the condition of the microprocessor and control its
operation.
o Figure 2–2 shows the flag registers of all versions of the
microprocessor.
o Flags are upward-compatible from the 8086/8088 through Core2 .
o The rightmost five and the overflow flag are changed by most
arithmetic and logic operations.
 although data transfers do not affect them
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The
The Programming
Programming Model
Model
Figure 2–2 The EFLAG and FLAG register counts for the entire
8086 and Pentium microprocessor family.

• Flags never change for any data transfer or program control

operation.
• Some of the flags are also used to control features found in the
microprocessor.
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Inside
Inside the
the 8086
8086
 8086 considered program visible.
 registers are used during programming and are specified by
the instructions
 Other registers considered to be program invisible.
 not addressable directly during applications programming

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BIU
BIU and
and EU
EU
 The 8086 CPU logic has been partitioned into two
functional units namely Bus Interface Unit (BIU) and
Execution Unit (EU)
 The major reason for this separation is to increase the
processing speed of the processor
 The BIU has to interact with memory and input and
output devices in fetching the instructions and data
required by the EU
 EU is responsible for executing the instructions of the
programs and to carry out the required processing

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Technology ‫المعلومات‬

Inside
Inside the
the 8086
8086
Dedicated Adder to
generate 20 bit
address

Four 16-bit segment

registers
Code Segment (CS)
Data Segment (DS)
Stack Segment (SS)
Extra Segment (ES)

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Pipelining
Pipelining
 There are two ways to make the CPU process
information faster:
 increase the working frequency
 or change the internal architecture of the CPU. (Pipelining)
 Pipelining is allow the CPU to fetch and execute at
the same time.
 Pipelining in the 8088/86 by splitting the internal
structure of the microprocessor into two sections:
the bus interface unit (BIU) and the execution unit
(EU).

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Pipelining
Pipelining
 These two sections work simultaneously. The BIU accesses
memory and peripherals while the EU executes instructions
previously fetched.
 This works only if the BIU keeps ahead of the EU; thus the
BIU of the 8088/86 has a buffer, or queue.
 The buffer is 4 bytes long in the 8088 and 6 bytes in the
8086.
 If any instruction takes too long to execute, the queue is
filled to its maximum capacity and the buses will sit idle.
 The BIU fetches a new instruction whenever the queue has
room for 2 bytes in the 6-byte 8086 queue, and for 1 byte
in the 4-byte 8088 queue.
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PIPELINING
PIPELINING
 Start work ASAP!! Do not waste time!
6 PM 7 8 9 10 11 12 1 2 AM
Time
Task
order
A Not pipelined
B

 Assume 30 min. each task – wash, dry, fold, store – and that
separate tasks use separate hardware and so can be overlapped
6 PM 7 8 9 10 11 12 1 2 AM
Time

Task
order

A
Pipelined
B

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PIPELINING
PIPELINING
 In a Computer, a machine instruction is executed in the following
cycles:
1. Fetch an instruction from memory (Fetch)
2. Decode the instruction (Decode)
3. Execute the instruction (Execute)
Execution of instructions without a
pipeline
C9 C8 C7 C6 C5 C4 C3 C2 C1
Execute Decode Fetch Instruction 1

Execute Decode Fetch Instruction 2

Execute Decode Fetch Instruction 3

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PIPELINING
PIPELINING
 In a pipeline execution, overlapping the execution of several
instructions in a pipeline fashion.
Execution of instructions with a pipeline
C9 C8 C7 C6 C5 C4 C3 C2 C1

Execute Decode Fetch Instruction 1

Execute Decode Fetch Instruction 2

Execute Decode Fetch Instruction 3

Execute Decode Fetch Instruction 4

Execute Decode Fetch Instruction 5

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The
The 80868086 Programming
Programming
Model
Model
 The programming model for a microprocessor shows the various
internal registers that are accessible to the programmer. The
Following Figure is a model for the 8086. In general, each register has
a special function.

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Inside
Inside the
the 8086
8086
Multipurpose Registers
 AX - a 16-bit register (AX), or as either of two 8-bit
registers (AH and AL).
 The accumulator is used for instructions such as
multiplication, division, and some of the adjustment
instructions.
 BX, addressable as BH, BL.
 BX register (base index) sometimes holds offset address of a
location in the memory system in all versions of the
microprocessor.

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Inside
Inside the
the 8086
8086
Multipurpose Registers
 CX, addressable as CH, or CL.
 a (count) general-purpose register that also holds the count
for various instructions.
 DX, addressable as DH, or DL.
 a (data) general-purpose register holds a part of the result
from a multiplication or part of dividend before a division.

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Inside
Inside the
the 8086
8086
Multipurpose Registers
 BP Base Pointer
 points to a memory (base pointer) location for memory data
transfers.
 DI Destination Index.
 often addresses (destination index) string destination data
for the string instructions.
 SI Source Index
 the (source index) register addresses source string data for
the string instructions.

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Inside
Inside the
the 8086
8086
Special-Purpose Registers
 IP instruction pointer
 addresses the next instruction in a section of memory.

 SP stack pointer
 addresses an area of memory called the stack.
 the (stack pointer) stores data through this pointer.

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Inside
Inside the
the 8086
8086
Segment Registers
 Generate memory addresses when combined with
other registers in the microprocessor.
 Four segment registers in various versions of the
microprocessor.
 CS (Code Segment) holds code (programs and
procedures) used by the microprocessor.
 DS (Data Segment) contains most data used by a
program.
 Data are accessed by an contents of other registers that hold
the offset address offset address.
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Inside
Inside the
the 8086
8086
Segment Registers
 SS (Stack Segment) defines the area of memory used
for the stack.
 stack entry point is determined by the stack segment and stack
pointer registers.
 the BP register also addresses data within the stack segment

 ES (Extra Segment) an additional data segment used

by some instructions to hold destination data.

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Registers
Registers
 Registers are used to store information temporarily.
 That information could be one or two bytes of data
to be processed or the address of data.
 The general-purpose registers in 8088/86
microprocessors can be accessed as either 16-bit or
8-bit registers.
 All other registers can be accessed only as the full
16 bits.

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Registers
Registers
Category Registers 8-bit Name 16-bit Name
AX – Accumulator AH - AL AX
BX – Base BH – BL BX
General-Purpose (Data)
CX – Loop Counter CH – CL CX
DX – Data DH – DL DX
SP – Stack Pointer - SP
Pointer
BP – Base Pointer - BP
SI – Source Index - SI
Index
DI – Destination Index - DI
CS – Code Segment - CS
DS – Data Segment - DS
Segment
SS – Stack Segment - SS
ES – Extra Segment - ES
instruction IP – Instruction Pointer - IP
Flag Flags - FR

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Introduction
Introduction to
to Assembly
Assembly
Language
Language
MOV instruction
 MOV instruction copies data from one location to

another. It has the following format:

MOV destination, source
 copy source operand to destination
 This instruction tells the CPU to move (in reality, copy)

the source operand to the destination operand.

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Introduction
Introduction to
to Assembly
Assembly
Language
Language
MOV instruction
 For example,

MOV DX, CX
 copies the contents of register CX to register DX.
 After this instruction is executed, register DX will have

the same value as register CX.

 The MOV instruction does not affect the source

operand.

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Introduction
Introduction to
to Assembly
Assembly
Language
Language
MOV Examples
MOV CL, 55H ;move 55H into register CL
MOV DL, CL ;copy the contents of CL into DL (now DL=CL=55H)
MOV AH, DL ;copy the contents of DL into AH (now AH=DL=55H)
MOV AL, AH ;copy the contents of AH into AL (now AL=AH=55H)
MOV BH, CL ;copy the contents of CL into BH (now BH=CL=55H)
MOV CH, BH ;copy the contents of BH into CH (now CH=BH=55H)
;--------
MOV CX, 468FH ;move 468FH into CX (now CH = 46, CL = 8F)
MOV AX, CX ;copy contents of CX to AX (now AX = CX = 468FH)
MOV DX, AX ;copy contents of AX to DX (now DX = AX = 468FH)
MOV BX, DX ;copy contents of DX to BX (now BX = DX = 468FH)
MOV DI, BX ;now DI = BX = 468FH
MOV SI, DI ;now SI = DI = 468FH
MOV DS, SI ;now DS = SI = 468FH

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Introduction
Introduction to
to Assembly
Assembly
Language
Language
MOV instruction
 Data can be moved among all the register as long as

the source and destination registers match in size.

MOV AL, DX ; Error
MOV BX, AH ;Error
 Data can not be moved directly into segment

registers.
MOV DS, 2459H ; Error
 Values cannot be loaded directly into any segment

register (CS, DS, ES, or SS).

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Introduction
Introduction to
to Assembly
Assembly
Language
Language
MOV instruction
 To load a value into a segment register, first load it to a

nonsegment register and then move it to the segment

register.
MOV AX, 2345H ;load 2345H into AX
MOV DS, AX ;load the value of AX into DS
 If a value less than FFH is moved into a 16-bit register, the

rest of the bits are assumed to be all zeros.

MOV BX, 5 ;the result will be BX = 0005H;
MOV BL, 5 ;the result will be BL = 05H;

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Introduction
Introduction to
to Assembly
Assembly
Language
Language
MOV instruction
 Moving a value that is too large into a register will

cause an error.
MOV BL, 7F2H ;ILLEGAL: 7F2H is larger than 8 bits
MOV AX, 2FE456H ;ILLEGAL: the value is larger than AX

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Introduction
Introduction to
to Assembly
Assembly
Language
Language
ADD Instruction
 ADD instruction has the following format:

ADD destination, source

ADD AL, BL
 The ADD instruction adds the source and destination

operands and put the result in the destination.

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Introduction
Introduction to
to Assembly
Assembly
Language
Language
ADD Instruction
 To add two numbers such as 25H and 34H:
MOV AL, 25H ;move 25 into AL
MOV BL, 34H ;move 34 into BL
ADD AL, BL ;AL = AL + BL
 The program above can be written in many ways,
MOV DH, 25H ;move 25 into DH
MOV CL, 34H ;move 34 into CL
ADD DH, CL ;add CL to DH; DH = DH+CL
 Another way:
MOV DH, 25H ;load one operand into DH
ADD DH, 34H ;add the second operand to DH
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Program
Program Segments
Segments
A program consists of four
segments:
 The Code Segment contains the
Assembly language instructions.
 The Data Segment is used to store
information (data) that needs to
be processed by the instructions in
the code segment.
 The Stack Segment is used to store
information temporarily.
 The Extra Segment is used to
temporarily segment to the above
three segments.
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Program
Program Segments
Segments
Logical address and physical
address
 In Intel literature concerning the 8086, there are three types of

addresses mentioned frequently: the physical address, the offset

address, and the logical address.
 The physical address is the 20-bit address that is actually put on the

address pins of the 8086 microprocessor

 This address can have a range of 00000H to FFFFFH for the 8086 and

real-mode 286,386, and 486 CPUs. This is an actual physical location

in RAM or ROM within the 1 megabyte memory range.
 The offset address is a location within a 64K-byte segment range.

Therefore, an offset address can range from 0000H to FFFFH.

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Code
Code Segment
Segment
 To execute a program, the 8086 fetches the instructions

from the code segment.

 The logical address of an instruction always consists of

a CS (code segment) and an IP (instruction pointer),

shown in CS:IP format.
 The physical address for the location of the instruction

is generated by shifting the CS left one hex digit and

then adding it to the IP. IP contains the offset address.
 The resulting 20-bit address is called the physical

address.
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Code
Code Segment
Segment
 Assume values in CS

and IP as shown in the

diagram. The offset
address is contained in
IP; in this case it is
95F3H. The logical
address is CS:IP, or
2500:95F3H.
 The physical address

will be 25000 + 95F3 =

2E5F3H.
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Code
Code Segment
Segment
Example 1-1
If CS = 24F6H and IP = 634AH, show:
(a) The logical address
(b) The offset address
(c) The physical address
(d) The lower range
(e) The upper range of the code segment
Solution:
(a) The logical address = 24F6:634A
(b) The offset address = 634A
(c) The physical address = 24F60 + 634A = 2B2AA
(d) The lower range = 24F60 + 0000 = 24F60
(e) The upper range of the code segment = 24F60 + FFFF = 34F5F

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Data
Data Segment
Segment
Assume that a program is being written to add 5 bytes of data, such
as 25H, 12H, 15H, 1FH, and 2BH, where each byte represents a
person's daily overtime pay.
One way to add them is as follows:
MOV AL, 00H ;initialize AL
ADD AL, 25H ;add 25H to AL
ADD AL, 12H ;add 12H to AL
ADD AL, 15H ;add 1FH to AL
ADD AL, 1FH ;add 1FH to AL
ADD AL, 2BH ;add 2BH to AL
In this program, the data and code are mixed together in the
instructions.
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Data
Data Segment
Segment
 In 8086 microprocessors, the area of memory set aside for
data is called the data segment.
 Code segment is associated with CS and IP, the data
segment uses register DS and an offset value.
 Assume that the offset for the data segment begins at 200H.
The data is placed in memory locations:
DS:0200 = 25
DS:0201 = 12
DS:0202 = 15
DS:0203 = 1F
DS:0204 = 2B

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Data
Data Segment
Segment
 and the program can be rewritten as follows:
MOV AL, 0 ;clear AL
ADD AL, [0200] ;add the contents of DS:200 to AL
ADD AL, [0201] ;add the contents of DS:201 to AL
ADD AL, [0202] ;add the contents of DS:202 to AL
ADD AL, [0203] ;add the contents of DS:203 to AL
ADD AL, [0204] ;add the contents of DS:204 to AL

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Data
Data Segment
Segment
 This program will run with any set of data. Changing
the data has no effect on the code.
 If the data had to be stored at a different offset
address, say 450H, the program would have to be
rewritten.
 One way to solve this problem would be to use a
register to hold the offset address.
 The 8086/88 allows only the use of registers BX, SI,
and DI as offset registers for the data segment.

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Data
Data Segment
Segment
 In the following example, BX is used as a pointer:
MOV AL, 0 ;initialize AL
MOV BX, 0200H ;BX points to the offset address of first
byte
ADD AL, [BX] ;add the first byte to AL
INCBX ;increment BX to point to the next byte
ADD AL, [BX] ;add the next byte to AL
INCBX ;increment the pointer
ADD AL, [BX] :add the next byte to AL
INCBX ;increment the pointer

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Data
Data Segment
Segment
Example 1-2 DS : Offset
Assume that DS is 5000
and the offset is 1950.
5 0 0 0 : 1 9 5 0
Calculate the physical
Start with DS 5 0 0 0
address of the byte.
Solution:
The physical address will Shift DS left 5 0 0 0 0
be
50000 + 1950 = 51950.
Add offset 1 9 5 0

Physical Address 5 1 9 5 0

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Data
Data Segment
Segment
Example 1-3
If DS = 7FA2H and the offset is 438E,
(a) Calculate the physical address
(b) Calculate the lower range
(c) Calculate the upper range of the data segment
(d) Show the logical address
Solution:
(a) The physical address = 7FA20 + 438E = 83DAE
(b) The lower range = 7FA20 + 0000 = 7FA20
(c) The upper range of the code segment = 7FA20 + FFFF =
8FA1F
(d) The logical address = 7FA2 : 438E
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Data
Data Segment
Segment
Example 1-4
 Assume that the DS register is 578C. To access a
given byte of data at physical memory location
67F66. does the data segment cover the range
where the data is located? If not what changes
need to be made?
Solution:
 No, since the range is 578C0 to 678BF, location
67F66 is not included in this range.
 To access that byte, DS must be changed so that its
range will include that byte.

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Little
Little Endian
Endian Convention
Convention
 Previous examples used 8-bit or 1-byte data.
 What happens when 16-bit data is used?
 For example:
MOV AX, 35F3H ;load 35F3H into AX
MOV [1500], AX ;copy the contents of AX to offset 1500H
 In cases like this, the low byte goes to the low memory
location and the high byte goes to the high memory
address.
 In example above, memory location DS:1500 contains F3H
and memory location DS:1501 contains 35H.
DS:1500 = F3 DS:1501 = 35
 This convention is called little endian versus big endian.
 In the big endian method, the high byte goes to the low
address.
 In the little endian method, the high byte goes to the high
address and the low byte to the low address.
 All Intel microprocessors and many minicomputers, use
the little
Microprocessors endian convention.
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Little
Little Endian
Endian Convention
Convention
Example 1-5
Assume memory locations with the following contents:
DS:6826 = 48 and DS:6827 = 22.
Show the contents of register BX in the instruction
MOV BX, [6826]
Solution:
According to the little endian convention, register BL
contain the value from the low offset address 6826
and register BH the value from offset address 6827,
giving BL = 48H and BH = 22H.
DS:6826 = 48 BH BL
DS:6827 = 22 22 48

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Stack
Stack Segment
Segment
 The stack is a section of read/write memory (RAM) used
by the CPU to store information temporarily.
 If the stack is a section of RAM, there must be registers
inside the CPU to point to it.
 The two main registers used to access the stack are the
SS (stack segment) register and the SP (stack pointer)
register.
 These registers must be loaded before any instructions
accessing the stack are used.

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Stack
Stack Segment
Segment
 The storing of a CPU register in the stack is called a
push, and loading the contents of the stack into the CPU
register is called a pop.
 In other words, a register is pushed onto the stack to
store it and popped off the stack to retrieve it.
 In the 80x86, the stack pointer register (SP) points at
the current memory location used for the top of the
stack and as data is pushed onto the stack it is
decremented.
 It is incremented as data is popped off the stack into the
CPU.
 When an
Microprocessors instruction pushes
503431-3
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Stack
Stack Segment
Segment
 Pushing onto the stack
 Notice as each PUSH is executed, the contents of the register
are saved on the stack and SP is decremented by 2. For every
byte of data saved on the stack, SP is decremented once, and
since push is saving the contents of a 16-bit register, it is
decremented twice.

 popping from the stack

 Popping the contents of the stack back into the 80x86 CPU is the
opposite process of pushing.
 With every pop, the top 2 by1es of the stack are copied to the
register specified by the instruction and the stack pointer is
incremented twice.
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Flag
Flag Register
Register
 The flag register is a 16-bit register sometimes referred to
as the status register
 Although the register is 16 bits wide, only some of the bits
are used.
 The rest are either undefined or reserved by Intel.
 Six of the flags are called conditional flags, meaning that
they indicate some condition that resulted after an
instruction was executed.
 These six are CF, PF, AF, ZF, SF, and OF.
 The three remaining flags are sometimes called control
flags since they are used to control the operation of
instructions
503431-3before they are executed.
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Flag
Flag Register
Register
:The 16 bits of the flag register
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

D O
CF U PF U AF U ZF SF TF IF R R R R
F F

Sign Flag = SF Reserved R=

Zero Flag = ZF Undefined U=
Auxiliary carry = AF Overflow Flag = OF
Flag
Parity Flag = PF Direction Flag = DF
Carry Flag = CF Interrupt Flag = IF
Trap Flag = TF

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Flag
Flag Register
Register
 CF, the Carry Flag. This flag is set whenever there is a
carry out of the operation
 PF, the Parity Flag. If the result has an even number of
1s,
 AF, Auxiliary Carry Flag. If there is a carry from d3 to
d4 of an operation.
 ZF, the Zero Flag. The zero flag is set to 1 if the result
is zero; otherwise, it is cleared.
 SF, the Sign Flag. indicating the sign of the result.
 TF, the Trap Flag. Set to perform single-step execute
 IF, Interrupt Enable Flag. indicating the external
maskable interrupt requests.
 DF, the Direction Flag. This bit is used to control the
direction of string operations,
 OF, the Overflow Flag. This flag is set whenever the
result of a signed number overflow
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Flag
Flag Register
Register
Example 1-6
Show how the flag register is affected by the addition
of 38H and 2FH.
Solution
MOV BH, 38H ;BH= 38H
ADD BH, 2FH ;add 2F to BH, now BH=67H
1
38 0011 1000
+ 2F 0010 1111
67 0 0110 0111
 CF = 0 since there is no carry beyond d7
 PF = 0 since there is an odd number of 1s in the
result
 AF = 1 since there is a carry from d3 to d4
 ZF = 0 since the result is not zero
 SF = 0 since d7 of the result is zero
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Flag
Flag Register
Register
Example 1-7
Show how the flag register is affected by
MOV AL, 9CH ;AL = 9CH
MOV DH, 64H ;DH = 64H
ADD AL, DH ;now AL = 0
Solution
9C 1001 1100
+ 64 0110 0100
1 00 1 0000 0000
 CF = 1 since there is carry beyond d7
 PF = 1 since there is an even number of 1s in the
result
 AF = 1 since there is a carry from d3 to d4
 ZF = 1 since the result is zero
 SF = 0 since d7 of the result is zero
Microprocessors 503431-3
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Flag
Flag Register
Register
Example 1-8
Show how the flag register is affected by
MOV AX, 34F5H ;AX = 34F5H
ADD AX, 95EBH ;now AX = CAE0H

Solution
34F5 0011 0100 1111 0101
+ 95EB 1001 0101 1110 1011
CAE0 1100 1010 1110 0000
 CF = 0 since there is no carry beyond d15
 PF = 0 since there is an odd number of 1s in the
result
 AF = 1 since there is a carry from d3 to d4
 ZF = 0 since the result is zero
 SF = 1 since d15 of the result is 1
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Flag
Flag Register
Register
Example 1-9
Show how the flag register is affected by
MOV BX, AAAAH ;BX = AAAAH
ADD BX, 5556H ;now BX = 0000H

Solution
AAAA 1010 1010 1010 1010
+ 5556 0101 0101 0101 0110
10000 1 0000 0000 0000 0000
 CF = 1 since there is carry beyond d15
 PF = 1 since there is an even number of 1s in the
result
 AF = 1 since there is a carry from d3 to d4
 ZF = 1 since the result is zero
 SF = 0 since d15 of the result is 0
Microprocessors 503431-3
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