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Memory Locations and Addresses

Memory locations and address

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27 views3 pages

Memory Locations and Addresses

Memory locations and address

Uploaded by

aljufmuhammad
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Memory locations and addresses

The main memory consists of many millions of storage cells, each of which can store 1 bit
having value 0 or 1. Since a single bit represents only a very small amount of information,
they are handled in groups of fixed size to represent information. For this purpose, the main
memory is organized so that a group of ‘n’ bits can be stored or retrieved in a single basic
operation. Each group of ‘n’ bits is referred to as a word of information and the ‘n’ is called
the word length.

Figure: Memory words

Modern computers have word lengths that typically range from 16 to 64 bits. If the word
length of a computer is 32 bits, a single word can store a 32 bit 2’s complement number or
four ASCII characters, each occupying 8 bits. A unit of 8 bits is called a byte. Machine
instructions may require one or more words for their representation.

Figure: a) A signed integer b) Four characters

Accessing the memory to store or retrieve information from memory, either a word or one
byte (8-bit), requires distinct names or addresses for each item location. A k-bit address
memory has 2k memory locations, namely 0 through 2k-1, called address space. The
memory can have up to 2k addressable locations.

Example

A 24 bit address generate an address space of 224 locations.

• 24-bit memory: 224 = 16,777,216 = 16M (1M=220)

• 32-bit memory: 232 = 4G (1G=230)

• 1K(kilo)=210

• 1T(tera)=240

Byte addressability

We have three basic information quantities to deal with. They are

Bit
Byte

word

It is not practical to assign distinct addresses to individual bit locations in the memory. It is
impractical to assign distinct addresses to individual bit locations in the memory.The most
practical assignment is to have successive addresses refer to successive byte locations in
the memory – byte-addressable memory. Byte locations have addresses 0, 1, 2, … If word
length is 32 bits, they successive words are located at addresses 0, 4, 8,… with each word
consisting of four bytes.

Big-Endian and Little-Endian Assignments

There are two ways that the byte addresses can be assigned across words. They are

• Big-endian

• Little endian

Big-Endian: lower byte addresses are used for the most significant bytes of the word.

Little-Endian: opposite ordering. lower byte addresses are used for the less significant
bytes of the word. Both are used in commercial machines.

Figure: a) big endian assignment b) Little endian assignment

Instruction Execution and Straight-Line Sequencing

A possible program segment for performing C  [A] +[B] as it appears in the memory of a
computer is shown in the following figure.

Figure: A program for C  [A]+[B]

Here we assume that the word length is 32 bits and the memory is byte addressable. The
three instructions of the program are in successive word locations, starting at location i.
Since each instruction is 4 bytes long, the second and third instructions start at addresses
i+4 and i+8.
Consider the execution of the program. The processor contains a register called the program
counter(PC), which holds the address of the instruction to be executed next. To begin the execution,
the address of its first instruction must be placed into PC. Then the processor control circuits
use the information in the PC to fetch and execute instructions one at a time in the increasing
order of addresses. This is called straight line sequencing. During the execution of each
instruction, the PC is incremented by 4 to point to the next instruction. Thus, after the Move
instruction at location i+8 is executed, the PC contains the value i+12, which is address of
the first instruction of the next program segment.

Instruction execution is a two-phase procedure.

• Instruction fetch

• Instruction execute

In the first phase, the instruction is fetched from the memory location whose address is in
the PC. This instruction is placed in the IR in the processor. In the second phase, the
instruction in the IR is examined to determine which operation is to be performed. The
specified operation is then performed by the processor. This may involve fetching operands
from memory, or from processor registers, performing an arithmetic or logic operation and storing
the result in the destination location. When the execute phase is completed, the PC contains the
address of the next instruction, and a new instruction fetch phase can begin.

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