Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444

APPLICATION NOTES
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CONTENT

1. INTRODUCTION 7
1.1 Protection of overhead lines and cable circuits 7
1.2 MiCOM distance relay 7
1.2.1 Protection Features 8
1.2.2 Non-Protection Features 9
1.2.3 Additional Features for the P441 Relay Model 9
1.2.4 Additional Features for the P442 Relay Model 9
1.2.5 Additional Features for the P444 Relay Model 10
1.3 Remark 10

2. APPLICATION OF INDIVIDUAL PROTECTION FUNCTIONS 11

2.1 Configuration column 11
2.2 Phase fault distance protection 12
2.3 Earth fault distance protection 13
2.4 Consistency between zones 14
2.5 General Distance Trip logic 15
2.5.1 Equation 15
2.5.2 Inputs 15
2.5.3 Outputs 16
2.6 Type of trip 16
2.6.1 Inputs 16
2.6.2 Outputs 16
2.7 Distance zone settings 16
2.7.1 Settings table 17
2.7.2 Zone Logic Applied 19
2.7.3 Zone Reaches 22
2.7.4 Zone Time Delay Settings 24
2.7.5 Residual Compensation for Earth Fault Elements 24
2.7.6 Resistive Reach Calculation - Phase Fault Elements 25
2.7.7 Resistive Reach Calculation - Earth Fault Elements 27
2.7.8 Effects of Mutual Coupling on Distance Settings 27
2.7.9 Effect of Mutual Coupling on Zone 1 Setting 27
2.7.10 Effect of Mutual Coupling on Zone 2 Setting 28
2.8 Distance protection schemes 29
2.8.1 Settings 30
2.8.2 Carrier send & Trip logic 31
2.8.3 The Basic Scheme 33
2.8.4 Zone 1 Extension Scheme 36
2.8.5 Loss of Load Accelerated Tripping (LoL) 38
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2.9 Channel-aided distance schemes 41

2.9.1 Permissive Underreach Transfer Trip Schemes PUP Z2 and PUP Fwd 41
2.9.2 Permissive Overreach Transfer Trip Schemes POP Z2 and POP Z1 44
2.9.3 Permissive Overreach Schemes Weak Infeed Features 46
2.9.4 Permissive Scheme Unblocking Logic 49
2.9.5 Blocking Schemes BOP Z2 and BOP Z1 53
2.10 Distance schemes current reversal guard logic 56
2.10.1 Permissive Overreach Schemes Current Reversal Guard 56
2.10.2 Blocking Scheme Current Reversal Guard 56
2.11 Distance schemes in the “open” programming mode 57
2.12 Switch On To Fault and Trip On Reclose protection 57
2.12.1 Initiating TOR/SOTF Protection 59
2.12.2 TOR-SOTF Trip Logic 61
2.12.3 Switch on to Fault and Trip on Reclose by I>3 Overcurrent Element (not filtered for
inruch current): 63
2.12.4 Switch on to Fault and Trip on Reclose by Level Detectors 63
2.12.5 Setting Guidelines 65
2.12.6 Inputs /Outputs in SOTF-TOR DDB Logic 66
2.13 Power swing blocking (PSB) 67
2.13.1 The Power Swing Blocking Element 68
2.13.2 Unblocking of the Relay for Faults During Power Swings 69
2.13.3 Typical Current Settings 72
2.13.4 Removal of PSB to Allow Tripping for Prolonged Power Swings 72
2.14 Directional and non-directional overcurrent protection 72
2.14.1 Application of Timer Hold Facility 75
2.14.2 Directional Overcurrent Protection 75
2.14.3 Time Delay VTS 75
2.14.4 Setting Guidelines 75
2.15 Negative sequence overcurrent protection (NPS) 78
2.15.1 Setting Guidelines 78
2.15.2 Negative phase sequence current threshold, ‘I2> Current Set’ 79
2.15.3 Time Delay for the Negative Phase Sequence Overcurrent Element, ‘I2> Time Delay’ 79
2.15.4 Directionalising the Negative Phase Sequence Overcurrent Element 79
2.16 Broken conductor detection 80
2.16.1 Setting Guidelines 80
2.16.2 Example Setting 81
2.17 Directional and non-directional earth fault protection 82
2.17.1 Directional Earth Fault Protection (DEF) 84
2.17.2 Application of Zero Sequence Polarising 84
2.17.3 Application of Negative Sequence Polarising 85
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2.18 Aided DEF protection schemes 85

2.18.1 Polarising the Directional Decision 86
2.18.2 Aided DEF Permissive Overreach Scheme 87
2.18.3 Aided DEF Blocking Scheme 88
2.19 Undervoltage protection 90
2.19.1 Setting Guidelines 91
2.20 Overvoltage protection 91
2.20.1 Setting Guidelines 92
2.21 Circuit breaker fail protection (CBF) 92
2.21.1 Breaker Failure Protection Configurations 92
2.21.2 Reset Mechanisms for Breaker Fail Timers 94
2.21.3 Typical settings 98

3. OTHER PROTECTION CONSIDERATIONS-SETTINGS EXAMPLE 99

3.1 Distance Protection Setting Example 99
3.1.1 Objective 99
3.1.2 System Data 99
3.1.3 Relay Settings 99
3.1.4 Line Impedance 99
3.1.5 Zone 1 Phase Reach Settings 100
3.1.6 Zone 2 Phase Reach Settings 100
3.1.7 Zone 3 Phase Reach Settings 100
3.1.8 Zone 4 Reverse Settings with no Weak Infeed Logic Selected 100
3.1.9 Zone 4 Reverse Settings with Weak Infeed Logic Selected 100
3.1.10 Residual Compensation for Earth Fault Elements 101
3.1.11 Resistive Reach Calculations 101
3.1.12 Power Swing Band 102
3.1.13 Current Reversal Guard 102
3.1.14 Instantaneous Overcurrent Protection 102
3.2 Teed feeder protection 103
3.2.1 The Apparent Impedance Seen by the Distance Elements 103
3.2.2 Permissive Overreach Schemes 103
3.2.3 Permissive Underreach Schemes 104
3.2.4 Blocking Schemes 105
3.3 Alternative setting groups 105
3.3.1 Selection of Setting Groups 106

4. APPLICATION OF NON-PROTECTION FUNCTIONS 108

4.1 Fault locator 108
4.1.1 Mutual Coupling 109
4.1.2 Setting Guidelines 109
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4.2 Voltage transformer supervision (VTS) – Main VT for minZ measurement 110
4.2.1 VTS logic description 110
4.2.2 The internal detection FUSE Failure condition 112
4.2.3 Fuse Failure Alarm reset 112
4.2.4 Loss of One or Two Phase Voltages 113
4.2.5 Loss of All Three Phase Voltages Under Load Conditions 113
4.2.6 Absence of Three Phase Voltages Upon Line Energisation 113
4.2.7 Menu Settings 114
4.2.8 INPUT / OUTPUT used in VTS logic: 115
4.3 Current Transformer Supervision (CTS) 115
4.3.1 The CT Supervision Feature 115
4.3.2 Setting the CT Supervision Element 116
4.4 Check synchronisation 116
4.4.1 Dead Busbar and Dead Line 118
4.4.2 Live Busbar and Dead Line 118
4.4.3 Dead Busbar and Live Line 118
4.4.4 Check Synchronism Settings 119
4.4.5 Logic inputs / Outputs from synchrocheck function 123
4.5 Autorecloser 125
4.5.1 Autorecloser Functional Description 125
4.5.2 Benefits of Autoreclosure 127
4.5.3 Auto-reclose logic operating sequence 128
4.5.4 Scheme for Three Phase Trips 134
4.5.5 Scheme for Single Pole Trips 134
4.5.6 Logical Inputs used by the Autoreclose logic 136
4.5.7 Logical Outputs generated by the Autoreclose logic 142
4.5.8 Setting Guidelines 149
4.5.9 Choice of Protection Elements to Initiate Autoreclosure 149
4.5.10 Number of Shots 149
4.5.11 Dead Timer Setting 150
4.5.12 De-Ionising Time 150
4.5.13 Reclaim Timer Setting 151
4.6 Circuit breaker state monitoring 152
4.6.1 Circuit Breaker State Monitoring Features 152
4.6.2 Inputs / outputs DDB for CB logic: 156
4.7 Circuit breaker condition monitoring 157
4.7.1 Circuit Breaker Condition Monitoring Features 157
4.7.2 Setting guidelines 159
4.7.3 Setting the Number of Operations Thresholds 159
4.7.4 Setting the Operating Time Thresholds 160
4.7.5 Setting the Excessive Fault Frequency Thresholds 160
4.7.6 Inputs/Outputs for CB Monitoring logic 160
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4.8 Circuit Breaker Control 161

4.9 Event Recorder 165
4.9.1 Change of state of opto-isolated inputs. 167
4.9.2 Change of state of one or more output relay contacts. 167
4.9.3 Relay Alarm conditions. 168
4.9.4 Protection Element Starts and Trips 168
4.9.5 General Events 168
4.9.6 Fault Records 169
4.9.7 Maintenance Reports 169
4.9.8 Setting Changes 169
4.9.9 Resetting of Event / Fault Records 169
4.9.10 Viewing Event Records via MiCOM S1 Support Software 170
4.10 Disturbance recorder 171

5. NEW ADDITIONAL FUNCTIONS – VERSION C1.X 175

5.1 Maximum of Residual Power Protection – Zero Sequence Power Protection 175
5.1.1 Function description 175
5.1.2 Settings & DDB cells assigned to zero sequence power (ZSP) function 177
5.2 Capacitive Voltage Transformers Supervision (CVT) 178
5.2.1 Function description 178
5.2.2 Settings & DDB cells assigned to Capacitive Voltage Transformers Supervision
(CVT) function 179

6. PROGRAMMABLE SCHEME LOGIC DEFAULT SETTINGS 180

6.1 HOW TO USE PSL Editor? 180
6.2 Logic input mapping 182
6.3 Relay output contact mapping 185
6.4 Relay output conditioning 186
6.5 Programmable led output mapping 188
6.6 Fault recorder trigger 188

7. CURRENT TRANSFORMER REQUIREMENTS 189

7.1 CT Knee Point Voltage for Phase Fault Distance Protection 189
7.2 CT Knee Point Voltage for Earth Fault Distance Protection 189
7.3 Recommended CT classes (British and IEC) 189
7.4 Determining Vk for an IEEE “C" class CT 189

8. DDB DESCRIPTION FOR ALL TYPES P441/P442 & P444 MODELS 189
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1. INTRODUCTION
1.1 Protection of overhead lines and cable circuits
Overhead lines are amongst the most fault susceptible items of plant in a modern power
system. It is therefore essential that the protection associated with them provides secure
and reliable operation. For distribution systems, continuity of supply is of para mount
importance. The majority of faults on overhead lines are transient or semi-permanent in
nature, and multi-shot autoreclose cycles are commonly used in conjunction with
instantaneous tripping elements to increase system availability. Thus, high speed, fault
clearance is often a fundamental requirement of any protection scheme on a distribution
network. The protection requirements for sub-transmission and higher voltage systems must
also take into account system stability. Where systems are not highly interconnected the
use of single phase tripping and high speed autoreclosure is commonly used. This in turn
dictates the need for high speed protection to reduce overall fault clearance times.
Underground cables are vulnerable to mechanical damage, such as disturbance by
construction work or ground subsidence. Also, faults can be caused by ingress of ground
moisture into the cable insulation, or its buried joints. Fast fault clearance is essential to limit
extensive damage, and avoid the risk of fire, etc.
Many power systems use earthing arrangements designed to limit the passage of earth fault
current. Methods such as resistance earthing make the detection of earth faults difficult.
Special protection elements are often used to meet such onerous protection requirements.
Physical distance must also be taken into account. Overhead lines can be hundreds of
kilometres in length. If high speed, discriminative protection is to be applied it will be
necessary to transfer information between the line ends. This not only puts the onus on the
security of signalling equipment but also on the protection in the event of loss of this signal.
Thus, backup protection is an important feature of any protection scheme. In the event of
equipment failure, maybe of signalling equipment or switchgear, it is necessary to provide
alternative forms of fault clearance. It is desirable to provide backup protection which can
operate with minimum time delay and yet discriminate with the main protection and
protection elsewhere on the system.
1.2 MiCOM distance relay
MiCOM relays are a range of products from T&D EAI. Using advanced numerical
technology, MiCOM relays include devices designed for application to a wide range of power
system plant such as motors, generators, feeders, overhead lines and cables.
Each relay is designed around a common hardware and software platform in order to
achieve a high degree of commonality between products. One such product in the range is
the series of distance relays. The relay series has been designed to cater for the protection
of a wide range of overhead lines and underground cables from distribution to transmission
voltage levels.
The relay also includes a comprehensive range of non-protection features to aid with power
system diagnosis and fault analysis. All these features can be accessed remotely from one
of the relays remote serial communications options.
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1.2.1 Protection Features

The distance relays offer a comprehensive range of protection functions, for application to
many overhead line and underground cable circuits. There are 3 separate models available,
the P441, P442 and P444. The P442 and P444 models can provide single and three pole
tripping. The P441 model provides three pole tripping only. The protection features of each
model are summarised below:

• 21G/21P : Phase and earth fault distance protection, each with up to 5 independent
zones of protection. Standard and customised signalling schemes are available to
give fast fault clearance for the whole of the protected line or cable.
• 50/51 : Instantaneous and time delayed overcurrent protection - Four elements are
available, with independent directional control for the 1st and 2nd element. The fourth
element can be configured for stub bus protection in 1½ circuit breaker arrangements.
The 3rd element can be used for SOFT/TOR logic.

• 50N/51N : Instantaneous and time delayed neutral overcurrent protection. Two

element are available and four threshold from next version C1.0 (model 020G or
020H).
• 67N : Directional earth fault protection (DEF) - This can be configured for channel
aided protection, plus two elements are available for backup DEF.
• 32N : Maximum of Residual Power Protection - Zero sequence Power Protection
This element can provide protection element for high resistance fault, eliminated
without communication channel.
• 27 : Undervoltage Protection - Two stage, configurable to measure either phase to
phase or phase to neutral voltage. Stage 1 may be selected as either IDMT or DT and
stage 2 is DT only.
• 59 : Overvoltage Protection - Two stage, configurable to measure either phase to
phase or phase to neutral voltage. Stage 1 may be selected as either IDMT or DT and
stage 2 is DT only.
• 67/46 : Directional or non-directional negative sequence overcurrent protection - This
element can provide backup protection for many unbalanced fault conditions.
• 50/27 : Switch on to fault (SOTF) protection - These settings enhance the protection
applied for manual circuit breaker closure.
• 50/27 :Trip on reclose (TOR) protection - These settings enhance the protection
applied on autoreclosure of the circuit breaker.
• 78 : Power swing blocking - Selective blocking of distance protection zones ensures
stability during the power swings experienced on sub-transmission and transmission
systems. From version C1.0, the relay can differentiate between a stable power swing
and a loss of synchronism (out of steps).
• VTS : Voltage transformer supervision (VTS). To detect VT fuse failures. This
prevents maloperation of voltage dependent protection on AC voltage input failure.
• CTS : Current transformer supervision - To raise an alarm should one or more of the
connections from the phase CTs become faulty.
• 46 BC : Broken conductor detection - To detect network faults such as open circuits,
where a conductor may be broken but not in contact with another conductor or the
earth.
• 50 BF : Circuit breaker failure protection - Generally set to backtrip upstream circuit
breakers, should the circuit breaker at the protected terminal fail to trip. Two stages
are provided.
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1.2.2 Non-Protection Features

The P441, P442 and P444 relays have the following non-protection features:

• 79/25 : Autoreclosure with Check synchronism - This permits up to 4 reclose shots,

with voltage synchronism, differential voltage, live line/dead bus, and dead bus/live
line interlocking available. Check synchronism is optional.

• Measurements - Selected measurement values polled at the line/cable terminal,

available for display on the relay or accessed from the serial communications facility.

• Fault/Event/Disturbance Records - Available from the serial communications or on

the relay display (fault and event records only).

• Distance to fault locator - Reading in km, miles or % of line length.

• Four Setting Groups - Independent setting groups to cater for alternative power
system arrangements or customer specific applications.

• Remote Serial Communications - To allow remote access to the relays. The following
communications protocols are supported: Courier, MODBUS, IEC60870-5/103 and
DNP3 (UCA2 soon available).

• Continuous Self Monitoring - Power on diagnostics and self checking routines to

provide maximum relay reliability and availability.

• Circuit Breaker State Monitoring - Provides indication of any discrepancy between

circuit breaker auxiliary contacts.

• Circuit Breaker Control - Opening and closing of the circuit breaker can be achieved
either locally via the user interface / opto inputs, or remotely via serial
communications.

• Circuit Breaker Condition Monitoring - Provides records / alarm outputs regarding the
number of CB operations, sum of the interrupted current and the breaker operating
time.

• Commissioning Test Facilities.

1.2.3 Additional Features for the P441 Relay Model

• 8 Logic Inputs - For monitoring of the circuit breaker and other plant status.

• 14 Output relay contacts - For tripping, alarming, status indication and remote
control.
1.2.4 Additional Features for the P442 Relay Model

• Single pole tripping and autoreclose.

• Real Time Clock Synchronisation - Time synchronisation is possible from the relay
IRIG-B input. (IRIG-B must be specified as an option at time of order).

• Fibre optic converter for IEC60870-5/103 communication (optional).

• Second rear port in COURIER Protocol (KBus/RS232/RS485)

• 16 Logic Inputs - For monitoring of the circuit breaker and other plant status.

• 21 Output relay contacts - For tripping, alarming, status indication and remote
control.
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1.2.5 Additional Features for the P444 Relay Model

• Single pole tripping and autoreclose.

• Real Time Clock Synchronisation - Time synchronisation is possible from the relay
IRIG-B input. (IRIG-B must be specified as an option at time of order).

• Fibre optic converter for IEC60870-5/103 communication (optional).

• Second rear port in COURIER Protocol (KBus/RS232/RS485)

• 24 Logic Inputs - For monitoring of the circuit breaker and other plant status.

• 32 Output relay contacts - For tripping, alarming, status indication and remote
control.
1.3 Remark
The PSL screen copy extracted from S1, uses the different types of model P44x (07, 09…).
(See the DDB equivalent table with the different model number).
Example : check synch OK (model 07) = DDB204
check synch OK (model 09) = DDB236
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2. APPLICATION OF INDIVIDUAL PROTECTION FUNCTIONS

The following sections detail the individual protection functions in addition to where and how
they may be applied. Each section also gives an extract from the respective menu columns
to demonstrate how the settings are applied to the relay.
The P441, P442 and P444 relays each include a column in the menu called the
‘CONFIGURATION’ column. As this affects the operation of each of the individual protection
functions, it is described in the following section.
2.1 Configuration column
The following table shows the Configuration column:-

Menu text Default setting Available settings

CONFIGURATION
Restore Defaults No Operation No Operation
All Settings
Setting Group 1
Setting Group 2
Setting Group 3
Setting Group 4
Setting Group Select via Menu Select via Menu
Select via Optos
Active Settings Group 1 Group1
Group 2
Group 3
Group 4
Save Changes No Operation No Operation
Save
Abort
Copy From Group 1 Group1,2,3 or 4
Copy To No Operation No Operation
Group1,2,3 or 4
Setting Group 1 Enabled Enabled or Disabled
Setting Group 2 Disabled Enabled or Disabled
Setting Group 3 Disabled Enabled or Disabled
Setting Group 4 Disabled Enabled or Disabled
Distance Enabled Enabled or Disabled
Power Swing Enabled Enabled or Disabled
Back-up I> Disabled Enabled or Disabled
Neg Sequence O/C Disabled Enabled or Disabled
Broken Conductor Disabled Enabled or Disabled
Earth Fault O/C Disabled Enabled or Disabled
Aided DEF Enabled Enabled or Disabled
Zero Seq. power (*) Disabled Enabled or Disabled
Volt Protection Disabled Enabled or Disabled
CB Fail & I< Enabled Enabled or Disabled
Supervision Enabled Enabled or Disabled
System Checks Disabled Enabled or Disabled
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Menu text Default setting Available settings

Internal A/R Disabled Enabled or Disabled
Input Labels Visible Invisible or Visible
Output Labels Visible Invisible or Visible
CT & VT Ratios Visible Invisible or Visible
Event Recorder Invisible Invisible or Visible
Disturb Recorder Invisible Invisible or Visible
Measure’t Setup Invisible Invisible or Visible
Comms Settings Visible Invisible or Visible
Commission Tests Visible Invisible or Visible
Setting Values Primary Primary or Secondary

(*) from B1.0

The aim of the Configuration column is to allow general configuration of the relay from a
single point in the menu. Any of the functions that are disabled or made invisible from this
column do not then appear within the main relay menu.
2.2 Phase fault distance protection
The P441, P442 and P444 relays have 5 zones of phase fault protection, as shown in the
impedance plot Figure 1 below.

X( /phase)

ZONE 3

ZONE P

ZONE 2

ZONE 1X

ZONE 1

R1Ph/2 R2Ph/2 RpPh/2 R3Ph/2 = R4Ph/2 R ( /phase)

ZONE 4

P0470ENa

FIGURE 1 – PHASE/PHASE FAULT QUADRILATERAL CHARACTERISTICS ( /PHASE SCHEME)

Remarks: 1. R limit value in MiCOM S1, are in ohms loop.
2. In a Ω/phase scheme the R value must be divided by 2 (for
phase/phase diagram).
3. The angle of the start element (Quad) is the angle of the
positive impedance of the line (value adjusted in the settings)
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All phase fault protection elements are quadrilateral shaped, and are directionalied as
follows:

• Zones 1, 2 and 3 - Directional forward zones, as used in conventional three zone

distance schemes. Note that Zone 1 can be extended to Zone 1X when required in
zone 1 extension schemes (see page 17 §2.5.2).

• Zone P - Programmable. Selectable in MiCOM S1 (Distance scheme\Fault type) as

a directional forward or reverse zone.

• Zone 4 - Directional reverse zone. Note that zone 3 and zone 4 can be set with
same Rloop value to provide a general start of the relay.
Remark: If any zone i presents a Rloop i bigger than R3=R4, the limit of the
start is always given by R3. See also the "Commissioning Test"
chapter.
2.3 Earth fault distance protection
The P441, P442 and P444 relays have 5 zones of earth (ground) fault protection, as shown
in the earth loop impedance plot Figure 2 below.
Type of fault can be selected in MiCOM S1 (only Phase/Phase or P/P & P/Ground)

X( /phase)

ZONE 3

ZONE P (Programmable)

ZONE 2

ZONE 1X

ZONE 1

R1G R2G RpG R3G = R4G

1+KZ 1+KZ 1+KZ 1+KZ 1+KZ
1 2 p 3/4 3/4 R( /phase)

ZONE P Reverse

ZONE 4

P0471ENa

FIGURE 2 – PHASE/GROUND FAULT QUADRILATERAL CHARACTERISTICS ( /PHASE SCHEME)

Remarks: 1. In a Ω/phase scheme the R value must be divided by 1+KZ (for

phase/ground diagram)
2. The angle of the start element (Quad) is the angle of the
2Z1+Z0 (Z1: positive sequence Z, Z0: zero sequence Z)
3. See calculation of KZ in section 2.6.5.
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All earth fault protection elements are quadrilateral shaped, and are directionalised as per
the phase fault elements. The reaches of the earth fault elements use residual
compensation of the corresponding phase fault reach. The residual compensation factors
are as follows:

• kZ1 - For zone 1 (and zone 1X);

• kZ2 - For zone 2;

• kZ3/4 - Shared by zones 3 and 4;

• kZp - For zone P.

2.4 Consistency between zones
In order to understand how the different distance zones interact the parameters below
should be considered:

• If Zp is a forward zone

− Z1 ! Z2 < Zp < Z3
− tZ1 < tZ2 < tZp < tZ3
− R1G < R2G < RpG < R3G = R4G
− R1Ph < R1extPh < R2Ph < RpPh < R3Ph

• If Zp is a reverse zone

− Z1 < Z2 < Z3
− Zp > Z4
− tZ1 < tZ2 < tZ3
− tZp < tZ4
− R1G < R2G < R3G
− RpG < R3G = R4G
− R1Ph < R2Ph < R3Ph
− RpPh < R3Ph = R4Ph
− R3G < UN / (1.2 X √3 IN)
− R3Ph < UN / (1.2 X √3 IN)
Remarks: 1. If Z3 is disabled, the forward limit element becomes the
smaller zone Z2- (or Zp if selected forward)
2. If Z4 is disabled, the directional limit for the forward zone is: 30°
(since version A4.0)
3. For older version than A4.0, the directional limit is: 0° (when Z4
is selected: disable).
Conventional rules are used as follows:

− Distance Timers are initiated as soon as the relay has picked up – CVMR pickup
distance
(CVMR = Start & Convergence)
− The minimum tripping time even with Carrier received is T1
− Zone 4 is always Reverse
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2.5 General Distance Trip logic

2.5.1 Equation

Z1'.T1. BZ1 . PZ1

+ Z1x'.(None + Z1xSiAnomTac.UNB_Alarm).[ T1. INP_Z1EXT]
+ UNB_CR.T1.[ PZ1.Z1'+PZ2.Z2'+PFwd.Aval’]
+ UNB_CR .T1.(Tp +INP_COS(*)).[ Z1'.BZ1 + (Z2'.BZ2. INP_COS (*)])
+ T2 [ Z2' + PZ1.Z1' + BZ1.Z1']
+ Z3'.T3
+ Zp' .Tzp
+ Z4'.T4
[(*) from version A2.10 & A3.1]
(See Figure 3 in section 2.7.2.1- Z’ logic description)
Remarks: 4. In case of COS (carrier out of service), the logic swap back to a
basic scheme.
5. In the column Data Type:"Configuration" means MiCOM S1 Setting
(the parameter is present in the settings).
With the inputs/outputs described above:
2.5.2 Inputs

Data Type Description

T1 to T4 Internal logic Elapse of Distance Timer 1 to 4 (T1/T2/T3/TZp/T4)
Tp Internal logic Elapse of transmission time in blocking scheme
Z1' to Z4' (*) Internal logic Detection of fault in zones 1 to 4
(lock out by PSWing or Rev Guard) – See figure 3 section
2.7.21
Forward’ Internal logic Fwd Fault Detection l (lockout by reversal guard)
UNB_CR Internal logic Carrier Received
INP_COS TS Opto Carrier Out of Service
CSZ1 Configuration Carrier send in case of zone 1 decision
CSZ2 Configuration Carrier send in case of zone 2 decision
CSZ4 Configuration Carrier send in case of zone 4 decision (Reverse)
None Configuration Scheme without carrier
PZ1 Configuration Permissive scheme Z1
PZ2 Configuration Permissive scheme Z2
PFwd Configuration Permissive Scheme with directional Fwd
BZ1 Configuration Blocking scheme Z1
BZ2 Configuration Blocking scheme Z2
INP_Z1EXT Internal logic Zone extension (digital input assigned to an opto by
dedicated PSL)
Z1xChannel Fail Configuration Z1x logic enabled if channel fail detected (Carrier out of
service = COS)
UNBAlarm Internal logic Carrier Out Of Service

(*) the use of an apostrophe in the above logic (Z'1) is explained in section 2.7.2.1 Figure 3
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2.5.3 Outputs

Data Type Description

PDist_Dec Internal logic Distance protection Trip

2.6 Type of trip

Single Pole Z1 Single pole Z2 T1 T2 Tzp T3 T4

0 1 1 1 3 3 3
1 0 1 3 3 3 3
0 0 3 3 3 3 3

1 : Trip 1P if selected in MiCOM S1 otherwise trip 3P

3 : Trip 3P
2.6.1 Inputs

Data Type Description

INP_Dist_Timer_Block TS opto Input for blocking the distance function
Single Pole T1 Configuration Trip 1pole at T1 – 3P in other cases
Single Pole T1 & T2 Configuration Trip 1pole at T1 /T2 – 3P in other cases
PDist_Trip Internal Logic Trip by Distance protection
T1 to T4 Internal Logic End of distance timer by Zone
Fault A Internal Logic Phase A selection
Fault B Internal Logic Phase B selection
Fault C Internal Logic Phase C selection

2.6.2 Outputs

Data Type Description

PDist_Trip A Internal Logic Trip Order phase A
PDist_Trip B Internal Logic Trip Order phase B
PDist_Trip C Internal Logic Trip Order phase C

2.7 Distance zone settings

NOTE: Individual distance protection zones can be enabled or disabled by
means of the Zone Status function links. Setting the relevant bit to 1
will enable that zone, setting bits to 0 will disable that distance
zones. Note that zone 1 is always enabled, and that zones 2 and 4
will need to be enabled if required for use in channel aided schemes.
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 17/220

Remarks: 1. .Z3 disable means Fwd start becomes Zp

.Z3 & Zp Fwd disable means Fwd start becomes Z2
.Z3 & Zp Fwd & Z2 disable means Fwd start becomes Z1
2. Z4 disable (see remark 1/2/3 in section 2.4)
2.7.1 Settings table

Menu text Default setting Setting range Step size

Min Max
GROUP 1
DISTANCE ELEMENTS
LINE SETTING
Line Length 1000 km 0.3 km 1000 km 0.010 km
(625 miles) (0.2 mile) (625 miles) (0.005 mile)
Line Impedance 12/In Ω 0.001/In Ω 500/In Ω 0.001/In Ω
Line Angle 70° –90° +90° 0.1°
Zone Setting
Zone Status 00011111 Bit 0: Z1X Enable, Bit 1: Z2 Enable,
Bit 2: Zone P Enable, Bit 3: Z3 Enable,
Bit 4: Z4 Enable.
KZ1 Res Comp 1 0 7 0.001
KZ1 Angle 0° 0° 360° 0.1°
Z1 10/In Ω 0.001/In Ω 500/In Ω 0.001/In Ω
Z1X 15/In Ω 0.001/In Ω 500/In Ω 0.001/In Ω
R1G 10/In Ω 0 400/In Ω 0.01/In Ω
R1Ph 10/In Ω 0 400/In Ω 0.01/In Ω
tZ1 0 0 10s 0.002s
KZ2 Res Comp 1 0 7 0.001
KZ2 Angle 0° 0° 360° 0.1°
Z2 20/In Ω 0.001/In Ω 500/In Ω 0.001/In Ω
R2G 20/In Ω 0 400/In Ω 0.01/In Ω
R2Ph 20/In Ω 0 400/In Ω 0.01/In Ω
tZ2 0.2s 0 10s 0.01s
KZ3/4 Res Comp 1 0 7 0.01
P44x/EN AP/E33 Application Notes

Page 18/220 MiCOM P441/P442 & P444

Menu text Default setting Setting range Step size

Min Max
KZ3/4 Angle 0° 0° 360° 0.1°
Z3 30/In Ω 0.001/In Ω 500/In Ω 0.001/In Ω
R3G - R4G 30/In Ω 0 400/In Ω 0.01/In Ω
R3Ph - R4Ph 30/In Ω 0 400/In Ω 0.01/In Ω
tZ3 0.6s 0 10s 0.01s
Z4 40/In Ω 0.001/In Ω 500/In Ω 0.01/In Ω
tZ4 1s 0 10s 0.01s
Zone P - Direct. Directional Fwd Directional Fwd or Directional Rev
KZp Res Comp 1 0 7 0.001
KZp Angle 0° 0° 360° 0.1°
Zp 25/In Ω 0.001/In Ω 500/In Ω 0.001/In Ω
RpG 25/In Ω 0 400/In Ω 0.01/In Ω
RpPh 25/In Ω 0 400/In Ω 0.01/In Ω
tZp 0.4s 0 10s 0.01s
Serial Cmp.line (*) Disable Enable Disable
Overlap Z Mode (*) Disable Enable Disable
Fault Locator
KZm Mutual Comp 0 0 7 0.001
KZm Angle 0° 0° 360° 0.1°

(*) Serial Cmp. Line Enabled

(*) Overlap Z Mode Enabled

(*) These parameters are available from version A4.0 onwards

• Serial Compensated Line : If enabled, the Directional used in the Deltas Algorithms is
set at 90°
(Fwd = Quad1&4 / Rev = Quad 2&3)

REV FWD

REV FWD

P0472ENa
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 19/220

• If disable, the Directional of the Deltas algorithms is set at -30° like conventional
algorithms

FWD FWD

R
REV FWD

REV -30˚

P0473ENa

• Overlap Z Mode: If enable, for a fault in Zp (fwd), then Z1 & Z2 will be displayed in
LCD/Events/Drec – The internal logic is not modified
2.7.2 Zone Logic Applied
Normally the zone logic used by the distance algorithm is as below:

Z1'
Z2'

Z4'

P0462XXa

(with overlap logic the Z2 will cover also the Z1)

2.7.2.1 Zone Logic
The relay internal logic will modify the zones & directionality under the following conditions:

• Power swing detection

• Settings about blocking logic during Power swing

• Reversal Guard Timer

• Type of Logical transmission scheme

For Power swing, two signals are considered:

• Presence of Power swing

• Unblocking during power swing

During Power swing the zones are blocked; but can be unblocked with:

• Start of unblocking logic

• Unblocking logic enable in MiCOM S1 on the concerned zone or all zones

During the Reversal guard logic (in case of parallel lines), the reverse directional decision is
latched (until that timer is issued) from the switch from Reverse to Forward (for distance
scheme with Z1>ZL).
P44x/EN AP/E33 Application Notes

Page 20/220 MiCOM P441/P442 & P444

Z1x
& Z1x'

unblock PS ≥1
in Z1

Z1<ZL &
≥1
1

& Z1'
Z1

Reversal
Guard
&
PermZ2
≥1
Power
Swing
≥1 & Z2'
Unblock PS
≥1 unblock PS
in Z2

Z2

&

PermFwd
≥1 Forward'
&
Forward

unblock PS ≥1
in Z3
& Z3'
Z3 Z2'

unblock PS
in Z4 ≥1

Z4 & Z4'

Zp_Fwd
&
unblock PS
in Zp
≥1
Zp'
Zp &

Reverse
Reverse'
≥1

P0474ENa

FIGURE 3 - ZONES UNBLOCKING/BLOCKING LOGIC WITH POWER SWING OR REVERSAL GUARD

Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 21/220

2.7.2.2 Inputs

Data Type Description

Z1 Internal Logic Fault detected in zone 1
Z1x Internal Logic Fault detected in zone 1 extended
Z2 Internal Logic Fault detected in zone 2
Z3 Internal Logic Fault detected in zone 3
Zp Internal Logic Fault detected in zone p
Z4 Internal Logic Fault detected in zone 4
Forward Internal Logic FWD Fault Detected
Reverse Internal Logic REV Fault Detected
Reversal Guard Internal Logic Reversal guard
Unblock PS Internal Logic Unblocking Power Swing
Power Swing Internal Logic Power Swing Detected
INP_Distance_Timer_block TS opto Zones blocked by external input (*)
Unblock Z1 Configuration Unblocking Pswing with Z1
Unblock Z2 Configuration Unblocking Pswing with Z2
Unblock Zp Configuration Unblocking Pswing with Zp
Unblock Z3 Configuration Unblocking Pswing with Z3
Unblock Z4 Configuration Unblocking Pswing with Z4
Zp_Fwd Configuration Directional Zp set Forward
Z1<ZL Configuration Internal Configuration which determine that Z1
is lower than the length of the line ZL
Perm Z2 Configuration Type of logical distance scheme
(PUP Z2– POP Z2) (**)
Perm Fwd Configuration Type of logical distance scheme
(PUP Fwd)
Block Z1 Configuration Type of logical distance scheme
(BOP Z1)
Block Z2 Configuration Type of logical distance scheme
(BOP Z2)

Remarks: *. Usefull for dedicated logic designed in PSL

Facility in Commissioning Test
**. For Aided Distace Scheme – See description in the TRIP
LOGIC Table (section 2.8.2.4)
P44x/EN AP/E33 Application Notes

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2.7.2.3 Outputs

Data Type Description

Z1x’ Internal Logic Fault detected in zone 1 extended
Z1’ Internal Logic Fault detected in zone 1
Z2’ Internal Logic Fault detected in zone 2
Z3’ Internal Logic Fault detected in zone 3
Zp’ Internal Logic Fault detected in zone p
Z4’ Internal Logic Fault detected in zone 4
Forward’ Internal Logic Fault Detected in Forward Direction
Reverse’ Internal Logic Fault Detected in Reverse Direction

For guidance on Line Length, Line Impedance, kZm Mutual Compensation and kZm mutual
compensation Angle settings, refer to section 4.1.
2.7.3 Zone Reaches

All impedance reaches for phase fault protection are calculated in polar form: Z ∠θ, where Z
is the reach in ohms, and θ is the line angle setting in degrees, common to all zones.
The line parameters can be adjusted in polar or rectangular mode to give the total positive
impedance of the protected line:

Remark: Z limit in MiCOM S1 are adjusted for Ω/phase

Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 23/220

• The zone 1 elements of a distance relay should be set to cover as much of the
protected line as possible, allowing instantaneous tripping for as many faults as
possible. In most applications the zone 1 reach (Z1) should not be able to respond to
faults beyond the protected line. For an underreaching application the zone 1 reach
must therefore be set to account for any possible overreaching errors. These errors
come from the relay, the VTs and CTs and inaccurate line impedance data. It is
therefore recommended that the reach of the zone 1 distance elements is restricted to
80 - 85% of the protected line impedance (positive phase sequence line impedance),
with zone 2 elements set to cover the final 20% of the line. (Note: Two of the channel
aided distance schemes described later, schemes POP Z1 and BOP Z1 use
overreaching zone 1 elements, and the previous setting recommendation does not
apply).

• The zone 2 elements should be set to cover the 20% of the line not covered by zone
1. Allowing for underreaching errors, the zone 2 reach (Z2) should be set in excess of
120% of the protected line impedance for all fault conditions. Where aided tripping
schemes are used, fast operation of the zone 2 elements is required. It is therefore
beneficial to set zone 2 to reach as far as possible, such that faults on the protected
line are well within reach. A constraining requirement is that, where possible, zone 2
does not reach beyond the zone 1 reach of adjacent line protection. Where this is not
possible, it is necessary to time grade zone 2 elements of relays on adjacent lines.
For this reason the zone 2 reach should be set to cover ≤50% of the shortest adjacent
line impedance, if possible. When setting zone 2 earth fault elements on parallel
circuits, the effects of zero sequence mutual coupling will need to be accounted for.
The mutual coupling will result in the Zone 2 ground fault elements underreaching. To
ensure adequate coverage an extended reach setting may be required, this is covered
in Section 2.7.7.

• The zone 3 elements would usually be used to provide overall back-up protection for
adjacent circuits. The zone 3 reach (Z3) is therefore set to approximately 120% of the
combined impedance of the protected line plus the longest adjacent line. A higher
apparent impedance of the adjacent line may need to be allowed where fault current
can be fed from multiple sources or flow via parallel paths.

• Zone P is a reversible directional zone. The setting chosen for zone P, if used at all,
will depend upon its application. Typical applications include its use as an additional
time delayed zone or as a reverse back-up protection zone for busbars and
transformers. Use of zone P as an additional forward zone of protection may be
required by some users to line up with any existing practice of using more than three
forward zones of distance protection. Zone P may also be useful for dealing with some
mutual coupling effects when protecting a double circuit line, which will be discussed
in section 2.7.7.

• The zone 4 elements would typically provide back-up protection for the local busbar,
where the offset reach is set to 25% of the zone 1 reach of the relay for short lines
(<30km) or 10% of the zone 1 reach for long lines. Setting zone 4 in this way would
also satisfy the requirements for Switch on to Fault, and Trip on Reclose protection, as
described in later sections. Where zone 4 is used to provide reverse directional
decisions for Blocking or Permissive Overreach schemes, zone 4 must reach further
behind the relay than zone 2 for the remote relay. This can be achieved by setting:
Z4 ≥ ((Remote zone 2 reach) x 120%) minus the protected line impedance.
P44x/EN AP/E33 Application Notes

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2.7.4 Zone Time Delay Settings

(initiated with CVMR (General start convergency))

• The zone 1 time delay (tZ1) is generally set to zero, giving instantaneous operation.
However, a time delay might be employed in cases where a large transient DC
component is expected in the fault current, and older circuit breakers may be unable
to break the current until zero crossings appear.

• The zone 2 time delay (tZ2) is set to co-ordinate with zone 1 fault clearance time for
adjacent lines. The total fault clearance time will consist of the downstream zone 1
operating time plus the associated breaker operating time. Allowance must also be
made for the zone 2 elements to reset following clearance of an adjacent line fault and
also for a safety margin. A typical minimum zone 2 time delay is of the order of
200ms. This time may have to be adjusted where the relay is required to grade with
other zone 2 protection or slower forms of back-up protection for adjacent circuits.

• The zone 3 time delay (tZ3) is typically set with the same considerations made for the
zone 2 time delay, except that the delay needs to co-ordinate with the downstream
zone 2 fault clearance. A typical minimum zone 3 operating time would be in the
region of 400ms. Again, this may need to be modified to co-ordinate with slower forms
of back-up protection for adjacent circuits.

• The zone 4 time delay (tZ4) needs to co-ordinate with any protection for adjacent lines
in the relay’s reverse direction. If zone 4 is required merely for use in a Blocking
scheme, tZ4 may be set high.
Remark: In MiCOM S1, timers settable are: tZi but in the DDB corresponding
cells are: Ti
2.7.5 Residual Compensation for Earth Fault Elements
For earth faults, residual current (derived as the vector sum of phase current inputs
(Ia + Ib + Ic) is assumed to flow in the residual path of the earth loop circuit. Thus, the earth
loop reach of any zone must generally be extended by a multiplication factor of (1 + kZ0)
compared to the positive sequence reach for the corresponding phase fault element. kZ0 is
designated as the residual compensation factor, and is calculated as:

kZ0 Res. Comp, kZ0 = (Z0 – Z1) / 3.Z1 Ie: As a ratio.

kZ0 Angle, ∠kZ0 = ∠ (Z0 – Z1) / 3.Z1 Set in degrees.

Where:
Z1 = Positive sequence impedance for the line or cable;
Z0 = Zero sequence impedance for the line or cable.
kZ0 CALCULATION DESCRIPTION
If we consider a phase to ground fault AN with analog values VA and IA.
Using symetrical components, VA is described as above:
(1) VA = V1 + V2 + V0 = Z1I1 + Z2I2 + Z0I0
Z2 = Z1 (for a line or a cable)
(2) VA = Z1 (I1 + I2) + Z0I0
we can write also: IA = I1 + I2 +I0
(3) (I1 + I2) = IA – I0
with (3) in (2) we obtain:
(4) VA = Z1 (IA – I0) + Z0I0
The physical fault current is IR = 3I0 – if put in (4) – we obtain:
VA = Z1 [IA – IR/3 + Z0IR/3Z1] = Z1 [IA + IR (Z0–Z1)/3Z1]
but: (Z0 – Z1)/3Z1 = kZ0
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 25/220

(5) VA = Z1 [IA + kZ0 IR]

(6) Z1 = VA/(IA + kZ0 IR)
Particular case
Resistive fault
(7) VA = Z1 [IA + kZ0 IR] + Rdef. Idef (Rdef = Rloop)
To determine the distance, Z1 term is extracted.
(8) Z1 = (VA – Rdef. Idef)/(IA + kZ0 IR)
with
Rdef: fault resistance (loop)
Idef: current crossing the fault resistance
Open line:
Ifault = IR = IA
(9) VA = Z1 IA (1 + kZ0) + Rfault IA
(10) Z1 = (VA/IA – Rfault)/(1 + kZ0)
The impedance detected will be:
Z = Z1 (1 + kZ0) + Rfault

That is the form used for the result of Z measured with injector providing U, I, ϕ
Separate compensation for each zone (KZ1, KZ2, KZ3/4 and KZp) allows more accurate
earth fault reach control for elements which are set to overreach the protected line, such that
they cover other circuits which may have different zero sequence to positive sequence
impedance ratios (Example: underground cable & overhead line in the protected line).
2.7.6 Resistive Reach Calculation - Phase Fault Elements
In MiCOM S1 all resistances are set per loop
The P441, P442 and P444 relays have quadrilateral distance elements, thus the resistive
reach (RPh) is set independently of the impedance reach along the protected line/cable.
RPh defines the maximum amount of fault resistance additional to the line impedance for
which a distance zone will trip, regardless of the location of the fault within the zone. Thus,
the right hand and left hand resistive reach constraints of each zone are displaced by +RPh
and -RPh either side of the characteristic impedance of the line, respectively. RPh is
generally set on a per zone basis, using R1Ph, R2Ph and RpPh. Note that zones 3 and 4
share the resistive reach R3Ph-R4Ph.
When the relay is set in primary impedance terms, RPh must be set to cover the maximum
expected phase-to-phase fault resistance. In general, RPh must be set greater than the
maximum fault arc resistance for a phase-phase fault, calculated as follows:
Ra = (28710 x L) / If1.4

RPh ≥ Ra
Where:
If = Minimum expected phase-phase fault current (A);
L = Maximum phase conductor separation (m);

Ra = Arc resistance, calculated from the van Warrington formula (Ω).

P44x/EN AP/E33 Application Notes

Page 26/220 MiCOM P441/P442 & P444

Typical figures for Ra are given in Table 1 below, for different values of minimum expected
phase fault current.

Conductor Typical system If = 1kA If = 5kA If = 10kA

spacing (m) voltage (kV)
2 33 3.6Ω 0.4Ω 0.2Ω
5 110 9.1Ω 1.0Ω 0.4Ω
8 220 14.5Ω 1.5Ω 0.6Ω

TABLE 1 - TYPICAL ARC RESISTANCES CALCULATED USING THE VAN WARRINGTON FORMULA
The maximum phase fault resistive reach must be limited to avoid load encroachment trips.
Thus, R3Ph and other phase fault resistive reach settings must be set to avoid the heaviest
allowable loading on the feeder. An example is shown in Figure 3 below, where the worst
case loading has been determined as point “Z”, calculated from:

Impedance magnitude, Z = kV2 / MVA

Leading phase angle, ∠Z = cos–1 (PF)

Where:
kV = Rated line voltage (kV);
MVA = Maximum loading, taking the short term overloading during out ages of
parallel circuits (MVA);
PF = Worst case lagging power factor.

Zone 3

∆R

R3PG-R4PG
Z

LOAD

Zone 4

P0475ENa

FIGURE 4 - RESISTIVE REACHES FOR LOAD AVOIDANCE

As shown in the Figure, R3Ph-R4Ph is set such as to avoid point Z by a suitable margin.
Zone 3 must never reach more than 80% of the distance from the line characteristic
impedance (shown dotted), towards Z. However, where power swing blocking is used, a
larger impedance (including ∆R) characteristic surrounds zones 3 and 4, and it is essential
also that load does not encroach upon this characteristic. For this reason, R3Ph would be
set ≤ 60% of the distance from the line characteristic impedance towards Z. A setting
between the calculated minimum and maximum should be applied.
R/Z ratio: For best zone reach accuracy, the resistive reach of each zone would not normally
be set greater than 10 times the corresponding zone reach. This avoids relay overreach or
underreach where the protected line is exporting or importing power at the instant of fault
inception. The resistive reach of any other zone cannot be set greater than R3Ph, and
where zone 4 is used to provide reverse directional decisions for Blocking or Permissive
Overreach schemes, the zone 2 elements used in the scheme must satisfy R2Ph ≤ (R3Ph-
R4Ph) x 80%.
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 27/220

2.7.7 Resistive Reach Calculation - Earth Fault Elements

The resistive reach setting of the relay earth fault elements (RG) should be set to cover the
desired level of earth fault resistance, but to avoid operation with minimum load impedance.
Fault resistance would comprise arc-resistance and tower footing resistance. In addition, for
best reach accuracy, the resistive reach of any zone of the relay would not normally be
greater than 10 times the corresponding earth loop reach.
EXPERT SECTION
As shown in Figure 4 (section 2.7.6), R3G – R4G is set such as to avoid point Z (minimum
load impedance) by a suitable margin.

R3G – R4G ≤ 80% Z minimum load impedance

Umin/√3
≤ 80%
1,2 x Imax

• Umin: minimum phase/phase voltage in normal condition without fault

• Imax: maximum load current in normal condition without fault

However, where Power Swing blocking is used, a larger impedance surrounds zone 3 and
zone 4, and it is essential also, that load does not encroach upon the characteristic.

[(R3G – R4G) – ∆R] ≤ 80% Z min load

With ∆R = 0,032 x ∆f x R load min

∆f: power swing frequency
R load min: minimum load resistance

A typical resistive reach coverage would be 40Ω on the primary system. The same load
impedance as in section 2.4.4 must be avoided. Thus R3G is set such as to avoid point Z by
a suitable margin. Zone 3 must never reach more than 80% of the distance from the line
characteristic impedance (shown dotted in Figure 3), towards Z.
For high resistance earth faults, the situation may arise where no distance elements could
operate. In this case it will be necessary to provide supplementary earth fault protection, for
example using the relay Channel Aided DEF protection.
2.7.8 Effects of Mutual Coupling on Distance Settings
Where overhead lines are connected in parallel or run in close proximity for the whole or part
of their length, mutual coupling exists between the two circuits. The positive and negative
sequence coupling is small and can be neglected. The zero sequence coupling is more
significant and will affect relay measurement during earth faults with parallel line operation.
Zero sequence mutual coupling will cause a distance relay to underreach or overreach,
depending on the direction of zero sequence current flow in the parallel line. However, it can
be shown that this underreach or overreach will not affect relay discrimination during parallel
line operation (ie. it is not be possible to overreach for faults beyond the protected line and
neither will it be possible to underreach to such a degree that no zone 1 overlap exists). A
channel-aided scheme will therefore still respond to faults within the protected line and
remain secure during external faults. Some applications exist, however, where the effects of
mutual coupling should be addressed.
2.7.9 Effect of Mutual Coupling on Zone 1 Setting
For the case shown in Figure 5, where one circuit of a parallel line is out of service and
earthed at both ends, an earth fault at the remote bus may result in incorrect operation of the
zone 1 earth fault elements. It may be desirable to reduce the zone 1 earth loop reach for
this application. This can be achieved using an alternative setting group within the relay, in
which the residual compensation factor kZ1 is set at a lower value than normal (typically ≤
80% of normal kZ1).
P44x/EN AP/E33 Application Notes

Page 28/220 MiCOM P441/P442 & P444

Z1 G/F (Optional)

Z1 G/F (Normal)

ZMO

P3048ENa

FIGURE 5 - ZONE 1 REACH CONSIDERATIONS

2.7.10 Effect of Mutual Coupling on Zone 2 Setting
If the double circuit line to be protected is long and there is a relatively short adjacent line, it
is difficult to set the reach of the zone 2 elements to cover 120% of the protected line
impedance for all faults, but not more than 50% of the adjacent line. This problem can be
exacerbated when a significant additional allowance has to be made for the zero-sequence
mutual impedance in the case of earth faults (see Section 2.4.6). For parallel circuit
operation the relay Zone 2 earth fault elements will tend to underreach. Therefore, it is
desirable to boost the setting of the earth fault elements such that they will have a
comparable reach to the phase fault elements. Increasing the residual compensation factor
kZ2 for zone 2 will ensure adequate fault coverage.
Under single circuit operation, no mutual coupling exists, and the zone 2 earth fault elements
may overreach beyond 50% of the adjacent line, necessitating time discrimination with other
Zone 2 elements. Therefore, it is desirable to reduce the earth fault settings to that of the
phase fault elements for single circuit operation, as shown in Figure 5. Changing between
appropriate settings can be achieved by using the alternative setting groups available in the
relay series relays.

Z2 ' Boost ' G/F

Z2 PH

ZMO

(i) Group 1

Z2 ' Reduced ' G/F

Z2 PH

(ii) Group 2 P3049ENa

FIGURE 6 - MUTUAL COUPLING EXAMPLE - ZONE 2 REACH CONSIDERATIONS

Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 29/220

2.8 Distance protection schemes

The option of using separate channels for DEF aided tripping, and distance protection
schemes, is offered in the P441, P442 and P444 relays. Alternatively, the aided DEF
protection can share the distance protection signalling channel, and the same scheme logic.
In this case a permissive overreach or blocking distance scheme must be used. The aided
tripping schemes can perform single pole tripping. The relays include basic five-zone
distance scheme logic for stand-alone operation (where no signalling channel is available)
and logic for a number of optional additional schemes. The features of the basic scheme will
be available whether or not an additional scheme has been selected.
P44x/EN AP/E33 Application Notes

Page 30/220 MiCOM P441/P442 & P444

2.8.1 Settings

Menu text Default setting Setting range Step size

Min Max
Group 1
Distance schemes
Program Mode Standard Scheme Standard Scheme
Open Scheme
Standard Mode Basic + Z1X Basic + Z1X, POP Z1,
POP Z2, PUP Z2, PUP Fwd, BOP Z1,
BOP Z2.
Fault Type Both Enabled Phase to Ground Fault Enabled,
Phase to Phase Fault Enabled,
Both Enabled.
Trip Mode Force 3 Poles Force 3 Poles,
1 Pole Z1 & CR,
1 Pole Z1 Z2 & CR.
Sig. Send Zone None None, CsZ1, CsZ2, CsZ4.
Dist CR None None, PermZ1, PermZ2, PermFwd, BlkZ1,
BlkZ2.
Tp 0.02s 0 1s 0.002s
tReversal Guard 0.02s 0 0.15s 0.002s
Unblocking Logic None None, Loss of Guard, Loss of Carrier.
TOR-SOTF Mode 00000000110000 Bit 0: TOR Z1
Bit 1: TOR Z2
Bit 2: TOR Z3
Bit 3: TOR All Zones
Bit 4: TOR Dist. Scheme
Bit 5: SOFT All Zones
Bit 6: SOFT Lev. Det.
Bit 7: SOFT Z1
Bit 8: SOFT Z2
Bit 9: SOFT Z3
Bit 0A: SOFT Z1 + Rev
Bit 0B: SOFT Z2 + Rev
Bit 0C: SOFT Dist. Scheme
Bit 0D: SOFT Disable
Z1 Ext. on Chan. Fail Disabled Disabled or Enabled
Weak Infeed
WI: Mode Status Disabled Disabled, Echo, WI Trip & Echo.
WI: Single Pole Trip Disabled Disabled or Enabled
WI: V< Thres. 45V 10V 70V 5V
WI: Trip Time Delay 0.06s 0 1s 0.002s
Loss of Load
LoL: Mode Status Disabled Disabled or Enabled
LoL: Chan. Fail Disabled Disabled or Enabled
LoL: I< 0.5 x In 0.05 x In 1 x In 0.05 x In
LoL: Window 0.04s 0.01s 0.1s 0.01s
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 31/220

2.8.2 Carrier send & Trip logic

2.8.2.1 Carrier send can be triggered by

• Zone1 (CSZ1)

• Zone2 (CSZ2)

• Zone4 Reverse (CSZ4)

Remarks: 1. CSZ1 means: "carrier send if Z1 detected"
2. The carrier send in Z4 is managed by "Reverse", instead of Z4
(because Reverse decision starts quicker than Z4).
The zones decision logic is described as below:

Z1'
Z2'

Z4' Z2'(*)

P0476XXa

Remark: Z2'(*) if overlapping zone enabled in MiCOM S1

PDist-CS = (Z1' + Z2').CSZ2 + Z1'.CSZ1 + Reverse.CSZ4 + WI_CS
The complete logic – with DEF integrated is:

CS = PDist_CS + ( Share_Logic Share_Logic_DEF. DEF_CS) → logic with canal shared

CS_DEF = Not Share_Logic_DEF. DEF_CS → logic with canal independent

(There is a 10ms delay in drop of on the carried send to avoid a logic race between this
signal and the zone pick up.)
2.8.2.2 Inputs

Data Type Description

CSZ1 Configuration Carrier send for zone 1
CSZ2 Configuration Carrier send for zone 2
CSZ4 Configuration Carrier send for zone 4 (reverse)
Not Share_Logic_DEF Configuration DEF channel independent
Reverse' Internal Logic Fault detected Reverse
Z1' to Z4' Internal Logic Zone 1 to 4 decision
(blocked by Pswing or Rguard)
WI_CS Internal Logic Winfeed carrier send (Echo)
DEF_CS Internal Logic DEF carrier send
P44x/EN AP/E33 Application Notes

Page 32/220 MiCOM P441/P442 & P444

2.8.2.3 Outputs

Data Type Description

CS Internal Logic Main channel Carrier send
CS_DEF Internal Logic DEF channel Carrier send

2.8.2.4 Trip logic

IEC Standard Carrier Trip Logic Application Setting

Send MiCOM
448.15.13 PUR Z1 Z2.CR.T1 + Z1T1 + Z2.T2 + Z3T3... Z1 = 80% ZL PUP Z2
(LFZR)
or AUP
PUR2 Z2 Z2.CR.T1 + Z1.T1 + Z2.T2 + Z3T3... Z1 = 80% ZL POP Z2
POR2
(LFZR)
448.15.14 BOR1 or Z4 Z1. CR .T1.Tp + Z1.T2 + Z2T2 + Z3T3... Z1 > ZL BOP Z1
BOP
BOR2 Z4 Z2. CR .T1.Tp + Z1.T1 + Z2.T2 + Z3.T3... Z1 = 80% ZL BOP Z2
BLOCK2
(LFZR)
448.15.11 PUP or Z1 Fwd.CR.T1 + Z1.T1 + Z2.T2 +... Z1 = 80% ZL PUP Fwd
PUTT
448.15.16 POR1 or Z1 Z1.CR.T1 + Z1.T2 Z1 > ZL POP Z1
POP or Z2.T2 + Z3.T3...
POTT

2.8.2.5 Tripping modes

The tripping mode is settable (Distance scheme\Trip mode):

− Force 3P : Trip 3P in all cases

− 1PZ1 & CR : Trip 1Pole in T1 for fault in Z1 and also in case of Carrier Received
(aided Trip)

− 1PZ1, Z2 & CR : Trip 1Pole for T1 & T2 in T1 for fault in Z1 and CR (aided Trip) and
also in Z2 with CR

Several defined aided trip logic can be selected or an open logic can be designed by user
(see also section 4.5 from chapter P44x/EN HW).
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 33/220

Unblocking Basic
+
Aided
Schemes
+
Weak-Infeed
Trip
Distance
Protection

PSB
TOR
+ SOTF
RVG
LOL

PSB: Power swing blocking

RVG: Reversal guard
LOL: Loss of load
P0477ENa

FIGURE 7 - MIMIC DIAGRAM

The zones unblocking/blocking logic with Power swing or Reversal guard is managed as
explained in the scheme: Figure 3 (section 2.7)

• The unblocking function if enabled, carries out a function similar to Carrier receive
logic. (see explanations in section 2.9.4)

• Weak infeed allows for the case where there may be no zone pick up from local end.

• TOR & SOTF applies specific logic in case of manual closing or AR closing logic.

• Trip Distance Protection manages the Trip order regarding the distance algorithm
outputs, the type of trip1P or 3P, the distance timers, and the logic datas such as
power swing blocking.

• Loss of Load manages a specific logic for tripping 3P in Z2 accelerated without carrier.
2.8.3 The Basic Scheme
The Basic distance scheme is suitable for applications where no signalling channel is
available. Zones 1, 2 and 3 are set as described in Sections 2.7.3 to 2.7.10. In general
zones 1 and 2 provide main protection for the line or cable as shown in Figure 9 below, with
zone 3 reaching further to provide back up protection for faults on adjacent circuits.
P44x/EN AP/E33 Application Notes

Page 34/220 MiCOM P441/P442 & P444

FIGURE 8 - SETTINGS IN MiCOM S1(GROUP1\DISTANCE SCHEME\STANDARD MODE)

– 6 DIFFERENTS SETTABLE SCHEMES –

Z2A
ZL
A Z1A B

Z1B
Z2B
P3050XXa

FIGURE 9 - MAIN PROTECTION IN THE BASIC SCHEME (NO REQUIREMENT FOR SIGNALLING
CHANNEL)
Key:
A, B = Relay locations;
ZL = Impedance of the protected line.
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 35/220

Protection A Protection B
Z1' Z1'
& &
T1
tZ1 T1
tZ1

Z2' Z2'
& &
T2
tZ2 T2
tZ2
Trip Trip
Z3' Z3'

T3
tZ3
& ≥1 ≥1 &
T3
tZ3

Zp' Zp'
& &
Tzp
tZp Tzp
tZp

Z4' Z4'
& &
T4
tZ4 T4
tZ4

P0543ENa

FIGURE 10 - LOGIC DIAGRAM FOR THE BASIC SCHEME

Figure 10 shows the tripping logic for the Basic scheme. Note that for the P441, P442 and
P444 relays, zone timers tZ1 to tZ4 are started at the instant of fault detection, which is why
they are shown as a parallel process to the distance zones. The use of an apostrophe in the
logic (eg. the ‘ in Z1’) indicates that protection zones are stabilised to avoid maloperation for
transformer magnetising inrush current. The method used to achieve stability is based on
second harmonic current detection.
The Basic scheme incorporates the following features :
Instantaneous zone 1 tripping. Alternatively, zone 1 can have an optional time delay of 0 to
10s.
Time delayed tripping by zones 2, 3, 4 and P. Each with a time delay set between 0 and
10s.
The Basic scheme is suitable for single or double circuit lines fed from one or both ends.
The limitation of the Basic scheme is that faults in the end 20% sections of the line will be
cleared after the zone 2 time delay. Where no signalling channel is available, then improved
fault clearance times can be achieved through the use of a zone 1 extension scheme or by
using loss of load logic, as described below. Under certain conditions however, these two
schemes will still result in time delayed tripping. Where high speed protection is required
over the entire line, then a channel aided scheme will have to be employed.
P44x/EN AP/E33 Application Notes

Page 36/220 MiCOM P441/P442 & P444

2.8.4 Zone 1 Extension Scheme

Auto-reclosure is widely used on radial overhead line circuits to re-establish supply following
a transient fault. A Zone 1 extension scheme may therefore be applied to a radial overhead
feeder to provide high speed protection for transient faults along the whole of the protected
line. Figure 11 shows the alternative reach selections for zone 1: Z1 or the extended reach
Z1X.

Z1 Extension (A)

ZL
A Z1A B

Z1B
Z1 Extension (B)

P3052ENa

FIGURE 11 - ZONE 1 EXTENSION SCHEME DEFINIED AS DESCRIBED ABOVE:

Z1 < Z1X < Z2 or Z1 < Z2 < Z1X
(with Z1 < ZL < Z1X)
In this scheme, zone 1X is enabled and set to overreach the protected line. A fault on the
line, including one in the end 20% not covered by zone 1, will now result in instantaneous
tripping followed by autoreclosure. Zone 1X has resistive reaches and residual
compensation similar to zone 1. The autorecloser in the relay is used to inhibit tripping from
zone 1X such that upon reclosure the relay will operate with Basic scheme logic only, to co-
ordinate with downstream protection for permanent faults. Thus, transient faults on the line
will be cleared instantaneously, which will reduce the probability of a transient fault becoming
permanent. The scheme can, however, operate for some faults on an adjacent line,
although this will be followed by autoreclosure with correct protection discrimination.
Increased circuit breaker operations would occur, together with transient loss of supply to a
substation.
The time delays associated with extended zone Z1X are shown in Table 2 below:

Scenario Z1X Time Delay

First fault trip = tZ1
Fault trip for persistent fault on autoreclose = tZ2

TABLE 2 - TRIP TIME DELAYS ASSOCIATED WITH ZONE 1X

The Zone 1 Extension scheme is selected by setting the Z1X Enable bit in the Zone Status
function links to 1.

FIGURE 12 – SETTINGS IN MiCOM S1 (GROUP1\DISTANCE SCHEME\ZONE STATUS)

Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 37/220

Remark: To enable the Z1X logic, the DDB "Z1X extension" cell must be linked
in the PSL (opto/reclaim time…)

FIGURE 13 - DISTANCE SCHEME WITHOUT CARRIER & Z1 EXTENDED

Z1'
&
T1

INP_Z1EXT &

None
& >1

Z1x'
T2
Z1X channel fail & & PDist_Trip
Z2'
UNB_Alarm ≥1
Z3'
&
T3

Zp'
&
Tzp

Z4'
&
T4

P0478ENa

FIGURE 14 – Z1X TRIP LOGIC

(Z1X can be used as well as the default scheme logic in case of UNB _Alarm-carrier out of
service (See unblocking logic – section 2.9.4))
2.8.4.1 Inputs

Data Type Description

None Configuration No distance scheme (basic scheme)
INP_Z1EXT Digital input Input for Z1 extended
Z1x channel fail Configuration Z1X extension enabled on channel fail (UNB-CR.
see Mode loss of guard or Loss of carrier)
UNB_Alarm Internal logic (See Unblocking logic)
Z1x’ Internal logic Z1X Decision (lock out by Power Swing)
Z1’ Internal logic Z1 Decision (lock out by Power Swing)
Z2’ Internal logic Z2 Decision (lock out by Power Swing)
Z3’ Internal logic Z3 Decision (lock out by Power Swing)
P44x/EN AP/E33 Application Notes

Page 38/220 MiCOM P441/P442 & P444

Data Type Description

Zp’ Internal logic Zp Decision (lock out by Power Swing)
Z4’ Internal logic Z4 Decision (lock out by Power Swing)
T1 Internal logic Elapse of distance timer 1
T2 Internal logic Elapse of distance timer 2
T3 Internal logic Elapse of distance timer 3
Tzp Internal logic Elapse of distance timer p
T4 Internal logic Elapse of distance timer 4

2.8.4.2 Outputs

Data Type Description

PDist_Dec Internal logic Trip order by Distance Protection

2.8.5 Loss of Load Accelerated Tripping (LoL)

The loss of load accelerated trip logic is shown in Figure 15. The loss of load logic provides
fast fault clearance for faults over the whole of a double end fed protected circuit for all types
of fault, except three phase. The scheme has the advantage of not requiring a signalling
channel. Alternatively, the logic can be chosen to be enabled when the channel associated
with an aided scheme has failed. This failure is detected by permissive scheme unblocking
logic, or a Channel Out of Service (COS) opto input.
Any fault located within the reach of Zone 1 will result in fast tripping of the local circuit
breaker. For an end zone fault with remote infeed, the remote breaker will be tripped in
Zone 1 by the remote relay and the local relay can recognise this by detecting the loss of
load current in the healthy phases. This, coupled with operation of a Zone 2 comparator
causes tripping of the local circuit breaker.
Before an accelerated trip can occur, load current must have been detected prior to the fault.
The loss of load current opens a window during which time a trip will occur if a Zone 2
comparator operates. A typical setting for this window is 40ms as shown in Figure 15,
although this can be altered in the menu LoL: Window cell. The accelerated trip is delayed
by 18ms to prevent initiation of a loss of load trip due to circuit breaker pole discrepancy
occurring for clearance of an external fault. The local fault clearance time can be deduced
as follows :
t = Z1d + 2CB + LDr + 18ms
Where:
Z1d = maximum downstream zone 1 trip time
CB = Breaker operating time
LDr = Upstream level detector (LoL: I<) reset time
For circuits with load tapped off the protected line, care must be taken in setting the loss of
load feature to ensure that the I< level detector setting is above the tapped load current.
When selected, the loss of load feature operates in conjunction with the main distance
scheme that is selected. In this way it provides high speed clearance for end zone faults
when the Basic scheme is selected or, with permissive signal aided tripping schemes, it
provides high speed back-up clearance for end zone faults if the channel fails.
Note that loss of load tripping is only available where 3 pole tripping is used.
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 39/220

Z2
Z1

Z1 Z1
Z1
Z2

LOL-A
LOL-B
&
LOL-C

18ms
0 & Trip
40ms 0
&
Z2
1

P3053ENa

FIGURE 15 - LOSS-OF-LOAD ACCELERATED TRIP SCHEME

2.8.5.1 Inputs

Data Type Description

Activ_LOL Configuration Loss of Load activated (LOL)
TRIP_Any Internal Logic Any trip (internal or external)
LOL. channel fail Configuration LOL enabled on channel fail (alarm carrier)
Force_3P_Dist Internal Logic Force Trip 3P in Distance Logic
Force_3P_DEF Configuration Force Trip 3P in DEF Logic
Activ_WI Configuration Weak-infeed activated (Trip & Echo)
WI_1pTrip Configuration WI 1Pole trip
PZ1, PZ2, PFwd, None Configuration Underreach scheme : Z1 < ZL
PZ1: permissive underreach Z1
PZ2: permissive underreach Z2
PFwd: permissive underreach forward
None: no distance scheme (basic scheme)
Z1<ZL Configuration Underreach scheme in Z1
UNB_CR_Alarm Internal Logic Carrier out of service Alarm
LOL Wind Configuration Activated time window for Loss Of Load logic
IA_LOL< Internal Logic Threshold I< for phase A in LOL logic
IB_LOL< Internal Logic Threshold I< for phase B in LOL logic
IC_LOL< Internal Logic Threshold I< for phase C in LOL logic
Flt A Internal Logic Faulty Phase A
Flt B Internal Logic Faulty Phase B
Flt C Internal Logic Faulty Phase C
Flt AB Internal Logic Faulty Phase AB
Flt BC Internal Logic Faulty Phase BC
Flt AC Internal Logic Faulty Phase AC
Z2' Internal Logic Fault in Z2 (lockout by Pswing or RGuard)
P44x/EN AP/E33 Application Notes

Page 40/220 MiCOM P441/P442 & P444

2.8.5.2 Outputs

Data Type Description

LOL_Trip3p Internal Logic 3P Trip by LOL logic

Activ_LOL

TRIP _Any

Force_3P_Dist Yes

Force3P_DEF 3p &
Activ WI = WI/echo &
WI_1pTrip = No

LOL. channel fail

UNB_CR_Alarm
&
&
PZ1, PZ2, PFwd ≥1
Z1<ZL

None

S
&
0 Q
R
T
LOL Wind
&
IA_LOL<

&
IB_LOL<

IC_LOL< &

≥1 T
Flt A & 0 S
LOL_Trip3P
Q
18 ms R
Flt B &

Flt C

Flt AB
&
Flt BC

Flt AC
&

Z2'
P0479ENa

FIGURE 16 – LOSS OF LOAD TRIP LOGIC

Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 41/220

2.9 Channel-aided distance schemes

The following channel aided distance tripping schemes are available when the Standard
program mode is selected:

• Permissive Underreach Transfer Trip Schemes PUP Z2 and PUP Fwd;

• Permissive Overreach Transfer Trip Schemes POP Z2 and POP Z1;

• Weak infeed logic to supplement permissive overreach schemes;

• Unblocking logic to supplement permissive schemes;

• Blocking Schemes BOP Z2 and BOP Z1;

• Current reversal guard logic to prevent maloperation of any overreaching zone used in
a channel aided scheme, when fault clearance is in progress on the parallel circuit of a
double circuit line.
2.9.1 Permissive Underreach Transfer Trip Schemes PUP Z2 and PUP Fwd
To provide fast fault clearance for all faults, both transient and permanent, along the length
of the protected circuit, it is necessary to use a signal aided tripping scheme. The simplest
of these is the permissive underreach protection scheme (PUP), of which two variants are
offered in the P441, P442 and P444 relays. The channel for a PUP scheme is keyed by
operation of the underreaching zone 1 elements of the relay. If the remote relay has
detected a forward fault upon receipt of this signal, the relay will operate with no additional
delay. Faults in the last 20% of the protected line are therefore cleared with no intentional
time delay.
Listed below are some of the main features/requirements for a permissive underreaching
scheme:

• Only a simplex signalling channel is required.

• The scheme has a high degree of security since the signalling channel is only keyed
for faults within the protected line.

• If the remote terminal of a line is open then faults in the remote 20% of the line will be
cleared via the zone 2 time delay of the local relay.

• If there is a weak or zero infeed from the remote line end, (ie. current below the relay
sensitivity), then faults in the remote 20% of the line will be cleared via the zone 2 time
delay of the local relay.

• If the signalling channel fails, Basic distance scheme tripping will be available.

Z2A
ZL
A Z1A B

Z1B
Z2B

P3054XXa

FIGURE 17 - ZONE 1 AND 2 REACHES FOR PERMISSIVE UNDERREACH SCHEMES

P44x/EN AP/E33 Application Notes

Page 42/220 MiCOM P441/P442 & P444

2.9.1.1 Permissive Underreach Protection, Accelerating Zone 2 (PUP Z2)

This scheme is similar to that used in the other AREVA distance relays, allowing an
instantaneous Z2 trip on receipt of the signal from the remote end protection. Figure 11
shows the simplified scheme logic.

Send logic: Zone 1

Permissive trip logic: Zone 2 plus Channel Received.

Protection A Protection B
Signal Signal
Send Z1' Send Z1'

Z1' Z1'
tZ1 & & tZ1

Z3' Z3'
& &
tZ3 tZ3

Zp' Zp'
& &
tZp tZp

Z4'
≥1 Trip Trip
≥1 Z4'
& &
tZ4 tZ4

tZ2 tZ2
& &

Z2' Z2'

&
&

P3055ENa

FIGURE 18 - THE PUP Z2 PERMISSIVE UNDERREACH SCHEME

(SEE TRIP LOGIC TABLE IN SECTION 2.8.2.4)
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 43/220

2.9.1.2 Permissive Underreach Protection Tripping via Forward Start (PUP Fwd)
This scheme is similar to that used in the AREVA EPAC and PXLN relays, allowing an
instantaneous Z2 or Z3 trip on receipt of the signal from the remote end protection. Figure
19 shows the simplified scheme logic.

Send logic: Zone 1

Permissive trip logic: Underimpedance Start within any Forward Distance Zone, plus
Channel Received.

Signal Protection A Protection B Signal

Send Z1' Send Z1'

Z1' Z1'

tZ1 & & tZ1

Z3' Z3'
& &
tZ3 tZ3

Zp' Zp'
tZp & &
tZp
Trip
Z4' ≥1
Trip
≥1
Z4'
&
tZ4 & tZ4
tZ2
tZ2
&
Z2' & Z2'

Fwd' Fwd'

<Z & & <Z

P3056ENa

FIGURE 19 - THE PUP FWD PERMISSIVE UNDERREACH SCHEME

(SEE TRIP LOGIC TABLE IN SECTION 2.8.2.4)
Key:
Fwd = Forward fault detection;
<Z = Underimpedance start by Z2 or Z3.
P44x/EN AP/E33 Application Notes

Page 44/220 MiCOM P441/P442 & P444

2.9.2 Permissive Overreach Transfer Trip Schemes POP Z2 and POP Z1

The P441, P442 and P444 relays offer two variants of permissive overreach protection
schemes (POP), having the following common features/requirements:

• The scheme requires a duplex signalling channel to prevent possible relay

maloperation due to spurious keying of the signalling equipment. This is necessary
due to the fact that the signalling channel is keyed for faults external to the protected
line.

• The POP Z2 scheme may be more advantageous than permissive underreach

schemes for the protection of short transmission lines, since the resistive coverage of
the Zone 2 elements may be greater than that of the Zone 1 elements.

• Current reversal guard logic is used to prevent healthy line protection maloperation for
the high speed current reversals experienced in double circuit lines, caused by
sequential opening of circuit breakers.

• If the signalling channel fails, Basic distance scheme tripping will be available.
2.9.2.1 Permissive Overreach Protection with Overreaching Zone 2 (POP Z2)
This scheme is similar to that used in the AREVA LFZP and LFZR relays. Figure 20 shows
the zone reaches, and Figure 21 the simplified scheme logic. The signalling channel is
keyed from operation of the overreaching zone 2 elements of the relay. If the remote relay
has picked up in zone 2, then it will operate with no additional delay upon receipt of this
signal. The POP Z2 scheme also uses the reverse looking zone 4 of the relay as a reverse
fault detector. This is used in the current reversal logic and in the optional weak infeed echo
feature.

Send logic: Zone 2

Permissive trip logic: Zone 2 plus Channel Received.

Z2A
ZL
A Z1A B

Z1B
Z2B

P3054XXa

FIGURE 20 - MAIN PROTECTION IN THE POP Z2 SCHEME

Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 45/220

Protection A Protection B Signal

Signal
Send Z2' Send Z2'

Z1' Z1'
tZ1 tZ1
& &

Z3' Z3'

tZ3 & & tZ3

Zp' Zp'

tZp & & tZp

Trip Trip
Z4'
≥1 ≥1
Z4'
tZ4 & & tZ4

tZ2 tZ2
& &
Z2' Z2'

& &

P3058ENa

FIGURE 21 - LOGIC DIAGRAM FOR THE POP Z2 SCHEME

(SEE TRIP LOGIC TABLE IN SECTION 2.8.2.4)
2.9.2.2 Permissive Overreach Protection with Overreaching Zone 1 (POP Z1)
This scheme is similar to that used in the AREVA EPAC and PXLN relays. Figure 22 shows
the zone reaches, and Figure 23 the simplified scheme logic. The signalling channel is
keyed from operation of zone 1 elements set to overreach the protected line. If the remote
relay has picked up in zone 1, then it will operate with no additional delay upon receipt of this
signal. The POP Z1 scheme also uses the reverse looking zone 4 of the relay as a reverse
fault detector. This is used in the current reversal logic and in the optional weak infeed echo
feature.
NOTE: Should the signalling channel fail, the fastest tripping in the Basic
scheme will be subject to the tZ2 time delay.

Send logic: Zone 1

Permissive trip logic: Zone 1 plus Channel Received.

Z2A
Z1A
A ZL B

Z1B
Z2B

P3059XXa

FIGURE 22 - MAIN PROTECTION IN THE POP Z1 SCHEME

P44x/EN AP/E33 Application Notes

Page 46/220 MiCOM P441/P442 & P444

Signal Protection A Protection B Signal

Send Z1' Send Z1'

Z2' Z2'

& & tZ2

tZ2

Z3' Z3'
& &
tZ3 tZ3

Zp' Zp'

tZp & &

tZp

Z4' ≥1 Trip Trip ≥1

Z4'
&
tZ4 & tZ4

&
&

Z1' Z1'

& &
tZ1 tZ1

P3060ENa

FIGURE 23 - LOGIC DIAGRAM FOR THE POP Z1 SCHEME

(SEE TRIP LOGIC TABLE IN SECTION 2.8.2.4)
2.9.3 Permissive Overreach Schemes Weak Infeed Features
Weak infeed logic can be enabled to run in parallel with all the permissive schemes. Two
options are available: WI Echo, and WI Tripping.
NOTE: The 2 modes are blocked during Fuse failure conditions.

Power swing detection

Def_Reverse

Reverse

0 &
Distance start
T
FFUS_Confirmed 150 ms
WI Logic confirmed
0
UNB_CR T
60 ms &

Pulse
Timer
200 ms
Activ_WI Echo or WI/echo

P0480ENa

FIGURE 24 - WEAK INFEED MODE ACTIVATION LOGIC

Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 47/220

• Weak Infeed Echo

For permissive schemes, a signal would only be sent if the required signal send zone were
to detect a fault. However, the fault current infeed at one line end may be so low as to be
insufficient to operate any distance zones, and risks a failure to send the signal. Also, if one
circuit breaker had already been left open, the current infeed would be zero. These are
termed weak infeed conditions, and may result in slow fault clearance at the strong infeed
line end (tripping after time tZ2). To avoid this slow tripping, the weak infeed relay can be
set to “echo” back any channel received to the strong infeed relay (ie. to immediately send a
signal once a signal has been received). This allows the strong infeed relay to trip
instantaneously in its permissive trip zone. The additional signal send logic is:

WI logic

& WI_CS
UNB_CR
Echo send:
(NB: For UNB_CR explanation see Unblocking logic in next section 2.9.4)

• Weak Infeed Tripping

Weak infeed echo logic ensures an aided trip at the strong infeed terminal but not at the
weak infeed. The P441, P442 and P444 relays also have a setting option to allow tripping of
the weak infeed circuit breaker of a faulted line.
Three undervoltage elements, Va<, Vb< and Vc< are used to detect the line fault at the weak
infeed terminal, with a common setting typically 70% of rated phase-neutral voltage. This
voltage check prevents tripping during spurious operations of the channel or during channel
testing.

VA<_WI
& WI_A
CB 52a_phA
& FLT_A
VB<_WI
& WI_B
CB 52a_phB
& FLT_B
VC<_WI
& WI_C
CB 52a_phC

UNB_CR & FLT_B

P0481ENa

FIGURE 25 - WEAK INFEED PHASE SELECTION LOGIC

UNB_CR is used as a filter to avoid a permanent phase selection which could be maintained
if Cbaux signals are not mapped in the PSL (when line is opened).
P44x/EN AP/E33 Application Notes

Page 48/220 MiCOM P441/P442 & P444

The additional weak infeed trip logic is:

Weak infeed trip: No Distance Zone Operation, plus reverse directional decision, plus
V<, plus Channel Received.
Weak infeed tripping is time delayed according to the WI:
Trip Time Delay value, usually set at 60ms. Due to the use of phase segregated
undervoltage elements, single pole tripping can be enabled for WI trips if required. If single
pole tripping is disabled a three pole trip will result after the time delay.

WI_A

WI_B ≥1
≥1 WI_PhaseA
WI_C &
WI/echo

Activ_WI

Trip1P_WI Yes
≥1 WI_PhaseB
&

&

≥1 WI_PhaseC

&

P0482ENa

FIGURE 26 – WEAK INFEED TRIP DECISION LOGIC

WI_Phase A

T
WI_Phase B ≥1 0

TtripWI
WI_Phase C

& WI_TripA

& WI_TripB

& WI_TripC

Autor_WI
P0531ENa

FIGURE 27 - WEAK INFEED TRIP LOGIC

Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 49/220

2.9.3.1 Inputs

Data Type Description

Activ_WI Configuration Weak infeed mode selection (Disable, Echo,
WI/echo)
Trip1P_WI Configuration Trip 1P in Weak infeed mode
Any Pole Dead Internal Logical Minimum 1 pole is open
Distance start Internal Logical Convergency of any impedance Loop – start of
distance
Reverse Internal Logical Fault detected in Reverse direction
FFUS_Confirmed Internal Logical Fuse Failure confirmed
Power swing Internal Logical Power swing detection
UNB_CR Internal Logical Carrier Received
VA<_WI Internal Logical Phase A selection by WI
VB<_WI Internal Logical Phase B selection by WI
VC<_WI Internal Logical Phase C selection by WI
CB52a_A, CB52a_B, Internal Logical Dead Pole by phase A/B/C
CB52a_C (detected by interlocking contacts 52a/52b)
TtripWI Configuration Weak-Infeed Trip Timer

2.9.3.2 Outputs

Data Type Description

WI_CS Internal Logical Carrier Send (echo)
WI_TripA Internal Logical Trip Phase A by WI logic
WI_TripB Internal Logical Trip Phase A by WI logic
WI_TripC Internal Logical Trip Phase A by WI logic

2.9.4 Permissive Scheme Unblocking Logic

Two modes of unblocking logic are available for use with permissive schemes, (Blocking
schemes are excluded).
The unblocking logic creates the : "UNB_Alarm" and the : "UNB_CR" signals, which depend
upon:

• Inputs signals [binary inputs: CR (Carrier Receive) COS (Carrier Out of Service)]

• Settings used for the distance channel & DEF aided trip channel

• Shared or independent logic between DEF & Distance

• Carrier Out of Service detected

Different modes are selectable :

• None (basic mode)

• Loss of Guard mode

• Loss of Carrier mode

P44x/EN AP/E33 Application Notes

Page 50/220 MiCOM P441/P442 & P444

Two types of carrier received signals are used:

• Carrier received (INP_CR - binary input)

• Carrier Out of Service (INP_COS - binary input for distance logic) and
(INP_COS_DEF - binary input for DEF logic)
2.9.4.1 None

The status of opto is copied directly :

UNB_ALARM = INP_COS + INP_COS_DEF

UNB_CR = INP_CR
UNB_CR_DEF = INP_CR_DEF

2.9.4.2 Loss of Guard Mode

This mode is designed for use with frequency shift keyed (FSK) power line carrier
communications. When the protected line is healthy a guard frequency is sent between line
ends, to verify that the channel is in service. However, when a line fault occurs and a
permissive trip signal must be sent over the line, the power line carrier frequency is shifted to
a new (trip) frequency. Thus, distance relays should receive either the guard, or trip
frequency, but not both together. With any permissive scheme, the PLC communications
are transmitted over the power line which may contain a fault. So, for certain fault types the
line fault can attenuate the PLC signals, so that the permissive signal is lost and not received
at the other line end. To overcome this problem, when the guard is lost and no “trip”
frequency is received, the relay opens a window of time during which the permissive scheme
logic acts as though a “trip” signal had been received. Two opto inputs to the relay need to
be assigned, one is the Channel Receive opto, the second is designated Loss of Guard (the
inverse function to guard received). The function logic is summarised in Table 3.
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 51/220

System Permissive Loss of Permissive Trip Alarm

Condition Channel Guard Allowed Generated
Received
Healthy Line No No No No
Internal Line Fault Yes Yes Yes No
Unblock No Yes Yes, during a Yes, delayed on
150ms window pickup by 150ms
Signalling Yes No No Yes, delayed on
Anomaly pickup by 150ms

TABLE 3 - LOGIC FOR THE LOSS OF GUARD FUNCTION

The window of time during which the unblocking logic is enabled starts 10ms after the guard
signal is lost, and continues for 150ms. The 10ms delay gives time for the signalling
equipment to change frequency as in normal operation.
For the duration of any alarm condition, zone 1 extension logic will be invoked if the option
Z1 Ext on Chan. Fail has been Enabled.

150 ms

0
S
=1 Q UNB Alarm
R
Pulse Timer
Indicates by digital input
200 ms
the Loss of guard

INP COS

&
INP CR
≥1 UNB CR

10 ms

0
S
&
Q
R
Pulse Timer
150 ms

P3061ENa

FIGURE 28 - LOSS OF GUARD LOGIC

INP_CR INP_COS UNB_CR UNB_Alarm

0 0 0 0
1 1 1 0
0 1 1 (Window) 1 (delayed)
1 0 0 1 (delayed)
P44x/EN AP/E33 Application Notes

Page 52/220 MiCOM P441/P442 & P444

2.9.4.3 Loss of Carrier

In this mode the signalling equipment used is such that a carrier/data messages are
continuously transmitted across the channel, when in service. For a permissive trip signal to
be sent, additional information is contained in the carrier (eg. a trip bit is set), such that both
the carrier and permissive trip are normally received together. Should the carrier be lost at
any time, the relay must open the unblocking window, in case a line fault has also affected
the signalling channel. Two opto inputs to the relay need to be assigned, one is the Channel
Receive opto, the second is designated Loss of Carrier (the inverse function to carrier
received). The function logic is summarised in Table 4.

System Permissive Loss of Permissive Trip Alarm

Condition Channel Guard Allowed Generated
Received
Healthy Line No No No No
Internal Line Fault Yes No Yes No
Unblock No Yes Yes, during a Yes, delayed on
150ms window pickup by 150ms
Signalling No Yes No Yes, delayed on
Anomaly pickup by 150ms

TABLE 4 - LOGIC FOR THE LOSS OF CARRIER FUNCTION

The window of time during which the unblocking logic is enabled starts 10ms after the guard
signal is lost, and continues for 150ms.
For the duration of any alarm condition, zone 1 extension logic will be invoked if the option
Z1 Ext on Chan. Fail has been Enabled.

150 ms

0 S
Q UNB Alarm
R
Pulse Timer

Indicates by digital input 200 ms

the Loss of Carrier

INP COS
&
UNB CR
INP CR ≥1

10 ms

0
S
&
Q
R
Pulse Timer
150 ms

P3062ENa

FIGURE 29 - LOSS OF CARRIER

Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 53/220

INP_CR INP_COS UNB_CR UNB_Alarm

0 0 0 0
0 1 1 (Window) 1 (delayed)
1 0 1 0
1 1 0 1 (delayed)

NOTE: For DEF the logic will used depende upon which settings are enabled:

• Same channel (shared)

In this case, the DEF channel is the Main Distance channel signal (the scheme & contacts of
carrier received will be identical)

• Independent channel (2 Different channels) – (2 independent contacts)

2.9.4.4 Inputs

Data Type Description

INP_CR Digital input Distance channel carrier received
INP_CR_DEF Digital input DEF channel carrier received
INP_COS Digital input Carrier Out of Service - Distance channel
INP_COS_DEF Digital input Carrier Out of Service – DEF channel

2.9.4.5 Outputs

Data Type Description

UNB_CR internal logic Internal carrier received – Distance channel
UNB_CR _DEF internal logic Internal carrier received – DEF channel
UNB_Alarm internal logic Alarm channel Main & DEF

2.9.5 Blocking Schemes BOP Z2 and BOP Z1

The P441, P442 and P444 relays offer two variants of blocking overreach protection
schemes (BOP). With a blocking scheme, the signalling channel is keyed from the reverse
looking zone 4 element, which is used to block fast tripping at the remote line end. Features
are as follows:

• BOP schemes require only a simplex signalling channel.

• Reverse looking Zone 4 is used to send a blocking signal to the remote end to prevent
unwanted tripping.

• When a simplex channel is used, a BOP scheme can easily be applied to a multi-
terminal line provided that outfeed does not occur for any internal faults.

• The blocking signal is transmitted over a healthy line, and so there are no problems
associated with power line carrier signalling equipment.

• BOP schemes provides similar resistive coverage to the permissive overreach

schemes.

• Fast tripping will occur at a strong source line end, for faults along the protected line
section, even if there is weak or zero infeed at the other end of the protected line.

• If a line terminal is open, fast tripping will still occur for faults along the whole of the
protected line length.

• If the signalling channel fails to send a blocking signal during a fault, fast tripping will
occur for faults along the whole of the protected line, but also for some faults within
the next line section.
P44x/EN AP/E33 Application Notes

Page 54/220 MiCOM P441/P442 & P444

• If the signalling channel is taken out of service, the relay will operate in the
conventional Basic mode.

• A current reversal guard timer is included in the signal send logic to prevent unwanted
trips of the relay on the healthy circuit, during current reversal situations on a parallel
circuit.

• To allow time for a blocking signal to arrive, a short time delay on aided tripping, Tp,
must be used, as follows:
Recommended Tp setting = Max. signalling channel operating time + 14ms
2.9.5.1 Blocking Overreach Protection with Overreaching Zone 2 (BOP Z2)
This scheme is similar to that used in the other ALSTOM distance relays. Figure 30 shows
the zone reaches, and Figure 31 the simplified scheme logic. The signalling channel is
keyed from operation of the reverse zone 4 elements of the relay. If the remote relay has
picked up in zone 2, then it will operate after the Tp delay if no block is received.

Send logic: Reverse Zone 4

Trip logic: Zone 2, plus Channel NOT Received, delayed by Tp.

Z4A Z2A
ZL
A Z1A B

Z1B Z4B
Z2B

P3063XXa

FIGURE 30 - MAIN PROTECTION IN THE BOP Z2 SCHEME

Protection A Protection B
Signal
Emission Signal
Emission
Send Z4'
Téléac Send Z4'
Téléac

Z1' Z1'

tZ1 & & tZ1

T1 T1

Z3' Z3'
& &
tZ3
T3 tZ3
T3

Zp' Zp'
& &
tZp
Tzp tZp
Trip Tzp
≥1 Trip ≥1
Z4' Z4'
& &
tZ4
T4 tZ4
T4

Tp Tp
& &

Z2' Z2'
tZ2
T2 & & tZ2
T2

P0533ENa

FIGURE 31 - LOGIC DIAGRAM FOR THE BOP Z2 SCHEME

(SEE TRIP LOGIC TABLE IN SECTION 2.8.2.4)
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 55/220

2.9.5.2 Blocking Overreach Protection with Overreaching Zone 1 (BOP Z1)

This scheme is similar to that used in the AREVA EPAC and PXLN relays. Figure 32 shows
the zone reaches, and Figure 33 the simplified scheme logic. The signalling channel is
keyed from operation of the reverse zone 4 elements of the relay. If the remote relay has
picked up in overreaching zone 1, then it will operate after the Tp delay if no block is
received.
NOTE: The fastest tripping is always subject to the Tp delay.

Send logic: Reverse Zone 4

Trip logic: Zone 1, plus Channel NOT Received, delayed by Tp.

Z4A Z2A
Z1A
A ZL B

Z1B
Z4B
Z2B

P3065XXa

FIGURE 32 - MAIN PROTECTION IN THE BOP Z1 SCHEME

Signal Protection A Protection B Signal

Send Z4' Send Z4'

Z2' Z2'
tZ2 & & tZ2

Z3' Z3'
& &
tZ3 tZ3

Zp' Zp'
& &
tZp tZp

≥1 Trip Trip ≥1
Z4' Z4'
& &
tZ4 tZ4

&
&

Z1' Z1'
tZ1 tZ1
& &
Tp Tp

P3066ENa

FIGURE 33 - LOGIC DIAGRAM FOR THE BOP Z1 SCHEME

(SEE TRIP LOGIC TABLE IN SECTION 2.8.2.4)
P44x/EN AP/E33 Application Notes

Page 56/220 MiCOM P441/P442 & P444

2.10 Distance schemes current reversal guard logic

For double circuit lines, the fault current direction can change in one circuit when circuit
breakers open sequentially to clear the fault on the parallel circuit. The change in current
direction causes the overreaching distance elements to see the fault in the opposite direction
to the direction in which the fault was initially detected (settings of these elements exceed
150% of the line impedance at each terminal). The race between operation and resetting of
the overreaching distance elements at each line terminal can cause the Permissive
Overreach, and Blocking schemes to trip the healthy line. A system configuration that could
result in current reversals is shown in Figure 34. For a fault on line L1 close to circuit
breaker B, as circuit breaker B trips it causes the direction of current flow in line L2 to
reverse.

t2(C) t2(D)
Fault Fault
A L1 B A L1 B

Strong Weak
source C L2 D source C L2 D

Note how after circuit breaker B on line L1 opens

the direction of current flow in line L2 is reversed.
P3067ENa

FIGURE 34 - CURRENT REVERSAL IN DOUBLE CIRCUIT LINES

(See the zone’ description in section 2.4 – unblock/blocking logical scheme)
2.10.1 Permissive Overreach Schemes Current Reversal Guard
The current reversal guard incorporated in the POP scheme logic is initiated when the
reverse looking Zone 4 elements operate on a healthy line. Once the reverse looking Zone 4
elements have operated, the relay’s permissive trip logic and signal send logic are inhibited
at substation D (Figure 34). The reset of the current reversal guard timer is initiated when
the reverse looking Zone 4 resets. A time delay tREVERSAL GUARD is required in case the
overreaching trip element at end D operates before the signal send from the relay at end C
has reset. Otherwise this would cause the relay at D to over trip. Permissive tripping for the
relays at D and C substations is enabled again, once the faulted line is isolated and the
current reversal guard time has expired. The recommended setting is:
tREVERSAL GUARD = Maximum signalling channel reset time + 35ms.
2.10.2 Blocking Scheme Current Reversal Guard
The current reversal guard incorporated in the BOP scheme logic is initiated when a blocking
signal is received to inhibit the channel-aided trip. When the current reverses and the
reverse looking Zone 4 elements reset, the blocking signal is maintained by the timer
tREVERSAL GUARD. Thus referring to Figure 34, the relays in the healthy line are
prevented from over tripping due to the sequential opening of the circuit breakers in the
faulted line. After the faulty line is isolated, the reverse-looking Zone 4 elements at
substation C and the forward looking elements at substation D will reset. The recommended
setting is:
Where Duplex signalling channels are used:
tREVERSAL GUARD = Maximum signalling channel operating time + 14ms.
Where Simplex signalling channels are used:
tREVERSAL GUARD = Maximum signalling channel operating time -
minimum signalling channel reset time + 14ms.
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 57/220

2.11 Distance schemes in the “open” programming mode

When a scheme is required which is not covered in the Standard modes above, the Open
programming mode can be selected. The user then has the facility to decide which distance
relay zone is to be used to key the signalling channel, and what type of aided scheme runs
when the channel is received. The signal send zone options are shown in Table 5, and the
aided scheme options on channel receipt are shown in Table 6.

Setting Signal Send Zone Function

None No Signal Send To configure a Basic scheme.
CsZ1 Zone 1 To configure a Permissive scheme.
CsZ2 Zone 2 To configure a Permissive scheme.
CsZ4 Zone 4 To configure a Blocking scheme.

TABLE 5 - SIGNAL SEND ZONES IN OPEN SCHEMES

Setting Aided Scheme Function

None None To configure a Basic scheme.
PermZ1 To configure a Permissive scheme where Zone 1 can only trip if a
channel is received.
PermZ2 To configure a Permissive scheme where Zone 2 can trip without
waiting for tZ2 timeout if a channel is received.
PermFwd To configure a Permissive scheme where any forward distance zone
start will cause an aided trip if a channel is received.
BlkZ1 To configure a Blocking scheme where Zone 1 can only trip if a
channel is NOT received.
BlkZ2 To configure a Blocking scheme where Zone 2 can trip without waiting
for tZ2 timeout if a channel is NOT received.

TABLE 6 - AIDED SCHEME OPTIONS ON CHANNEL RECEIPT

Where appropriate, the tREVERSAL GUARD and Tp timer (in case of blocking scheme for
covering the time transmission) settings will appear in the relay menu. Further customising
of distance schemes can be achieved using the Programmable Scheme Logic to condition
send and receive logic.
2.12 Switch On To Fault and Trip On Reclose protection
Switch on to fault protection (SOTF) is provided for high speed clearance of any detected
fault immediately following manual closure of the circuit breaker. SOTF protection remains
enabled for 500ms following circuit breaker closure, detected via the CB Man Close input or
CB close with CB control or Internal detection with all pole dead (see Figure 37), or for the
duration of the close pulse on internal detection.
[Instantaneous three pole tripping (and auto-reclose blocking) can be also selected (AR lock
out by BAR Figure 80 in AR section)– See BAR logic in Figure 80 AR description section].
Trip on reclose protection (TOR) is provided for high speed clearance of any detected fault
immediately following autoreclosure of the circuit breaker.
Instantaneous three pole tripping (TOR logic) can be selected for faults detected by various
elements, (See MiCOM S1 settings description above). TOR protection remains enabled for
500ms following circuit breaker closure. The use of a TOR scheme is usually advantageous
for most distance schemes, since a persistent fault at the remote end of the line can be
cleared instantaneously after reclosure of the breaker, rather than after the zone 2 time
delay.
The options for SOTF and TOR are found in the “Distance Schemes” menu.
P44x/EN AP/E33 Application Notes

Page 58/220 MiCOM P441/P442 & P444

(7 additional settable bits are available from version A3.1)

and are as shown below:

Menu text Default setting Setting range Step size

Min Max
GROUP 1
DISTANCE SCHEMES
TOR-SOTF Mode Bit 0: TOR Z1 Enabled,
Bit 1:TOR Z2 Enabled,
Bit 2: TOR Z3 Enabled,
Bit 3:TOR All Zones,
TOR
Bit 4:TOR Dist. Scheme .
Dist scheme
14 bits
Bit 0 to 4 Bit 5 : SOTF All Zones
Default: bit 4 Bit 6 : SOTF Lev. Detect.

From version A3.1:

Bit 7 : SOTF Z1 Enabled
Bit 8 : SOTF Z2 Enabled
SOTF all Zones Bit 9 : SOTF Z3 Enabled
Bit 5 to D
Bit A: SOTF Z1+Rev
Default: bit 5
Bit B: SOTF Z2+Rev
Bit C: SOTF Dist. Scheme
Bit D: SOTF Disable
SOTF Delay 110sec 10sec 3600sec 1 sec
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 59/220

2.12.1 Initiating TOR/SOTF Protection

SOTF/TOR Activated
2 signals are issued from the logic: TOR Enable - SOTF Enable (See DDB description in
appendix from that chapter). There is a difference between them due to the AR (internal or
external) which must be blocked in SOTF logic.
The detection of open pole is based on the activation of : Any Pole Dead (at least one pole
opened). It is a OR logic between the internal analog detection (level detectors) or the
external detection (given by CB status : 52A/52B, which is requested in case of VT Bus
side).
The Dead pole Level Detectors V< and I< per phase are settable as described belows:

− V< is either a fixed threshold 20% Vn or equal to V Dead Line threshold of the check
synchro function if enabled, (default value for V< dead line = 20% VN)

− I< is either a fixed threshold of 5% In or equal to the I< threshold of the Breaker
Failure protection (default value for I< CB fail = 5% IN).
TOR Enable logic is activated in 2 cases :
1. When internal AR is activated or when the reclaim signal from an external AR is
connected to a digital input (opto):
As soon as the reclaim time starts, the « TOR Enable » is activated . It will be reset at the
end of the internal or external reclaim time.
2. Without any reclaim time (internal AR disabled or external opto input Reclaim Time not
assigned in the PSL):
TOR Enable will be activated during a 200 ms time window, following the detection of pole
dead detection. The TOR logic will be reset (TOR Enable) ONLY 500 ms after the drop off of
any pole dead detection.
This behaviour has been designed to avoid any maloperation on a parallel line, in case of an
incorrect Any Pole Dead detection performed by the internal level detectors (Ex: Fault front
of Busbar on a parallel line and weak source on the other end of the line)
A delay of 200ms will allow the adjacent line to be tripped and the level detectors will then
reset the timer :

• TOR protection logic is enabled any time that any circuit breaker pole has been open
longer than 200ms but not longer than 110s default value (ie. First shot autoreclosure
is in progress)- the timer is configurable from version A3.0 /allows variation of the
duration when dead pole is detected before the internal logic detects line dead and
activates the SOTF logic and also where the relay logic detects that further delayed
autoreclose shots are in progress.

Trip

Reclosing

Any Pole Dead

200 ms 500 ms
TOR Enable

P0532ENa

• SOTF protection is enabled any time that the circuit breaker has been open 3 pole for
longer than 110s, that timer is configurable from version A3.0 /allows variation of the
duration when dead pole is detected before the internal logic detects line dead and
activates the SOTF logic and autoreclosure is not in progress. Thus, SOTF protection
is enabled for manual reclosures, not for autoreclosure.
P44x/EN AP/E33 Application Notes

Page 60/220 MiCOM P441/P442 & P444

SOTF Enable logic is activated in 2 cases:

1. If no external closing command (manual or by remote communication via control

system) is present :
When the internal levels detectors have detected a three pole open for more than 110 s
(settable from A3.0); as soon as all poles are closed, then SOTF is enabled for 500 ms and
then reset,

2. When an external closing command (manual or by remote communication via control

system) is present:
The SOTF logic is activated immediately. As soon as all the poles are closed (after the
external closing order if a synchro condition is used in the PSL); SOTF is enable for
500msec and then is reset.

AR_RECLAIM
Pulse
>1
T
INP_RECLAIM >1 TOR Enable
500 ms
1P or 3P AR

INP_RECLAIM >1
Assigned
T
& 0
200 ms S
Q
>1
>1 R
Any Pole Dead 0
T
500 ms
>1
R
T Q SOTF Enable
All Pole Dead
0 S
>1
TSOTF Enable &
(by default:110 s)
SOTF HS

CBC_Closing Order

CB_Control &
activated

&
INP_CB_Man_Close
P0485ENa

FIGURE 35 – SOTF/TOR LOGIC - START

Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 61/220

2.12.2 TOR-SOTF Trip Logic

During the TOR/SOTF 500ms window, individual distance protection zones can be enabled
or disabled by means of the TOR-SOTF Mode function links. Setting the relevant bit to 1 will
enable that zone, setting bits to 0 will disable distance zones. When enabled (Bit = 1), the
zones will trip without waiting for their usual time delays. Thus tripping can even occur for
close-up three phase short circuits where line connected VTs are used, and memory voltage
for a directional decision is unavailable. Setting “All Zones Enabled” allows instantaneous
tripping to occur for all faults within the trip characteristic shown in Figure 36 below. Note,
the TOR/SOTF element has second harmonic current detection, to avoid maloperation
where power transformers are connected in-zone, and inrush current would otherwise cause
problems. Harmonic blocking of distance zones occurs when the magnitude of the second
harmonic current exceeds 25% of the fundamental.

Zone 4

Zone 3
Directional
line (not used)
P0535ENa

FIGURE 36 - “ALL ZONES” DISTANCE CHARACTERISTIC AVAILABLE FOR SOTF/TOR TRIPPING

Test results from different settings selected in MiCOM S1.
WARNING: MiCOM S1 DOES NOT DYNAMICALLY CHANGE THE SETTINGS, AND
ONE SETTING MAY AFFECT ANOTHER.
SOTF Z2: means that an instantaneous 3 poles trip will occur for fault in Z1 or Z2 without
waiting for the issue of the distance timer T1 or T2 only in case Z2 or Z1 are detected by the
logic.
T0 = instantaneous Trip
Ts = Trip at the end of SOTF time window (500ms)
T1 = 0, T2=200ms, Tzp=400ms, T3=600ms, T4=1s (Distance timer).
The fault is maintained with a duration bigger than the 500msec SOTF time, until a trip
occurs.
P44x/EN AP/E33 Application Notes

Page 62/220 MiCOM P441/P442 & P444

SOTF Trip logic results

Type of Fault Fault in Z1 Fault in Z2 Fault in Zp Fault in Zp Fault in Z3 Fault in Z4

Fwd Rev
SOTF selected Logic
SOTF All Zone SOTF trip SOTF trip SOTF trip Same result SOTF trip SOTF trip
(Zp Fwd) T0 T0 T0 if Zp Rev T0 T0
T0

SOTF Z1 SOTF trip DIST trip DIST trip x DIST trip DIST trip
(Zp Fwd) T0 T2 TZp T3 T4

SOTF Z2 SOTF trip SOTF trip DIST trip x DIST trip DIST trip
(Zp Fwd) T0 T0 TZp T3 T4
SOTF Z3 SOTF trip SOTF trip SOTF trip x SOTF trip DIST trip
(Zp Fwd) T0 T0 T0 T0 T4
SOTF Z1+Rev (Zp Fwd) SOTF trip DIST trip DIST trip x DIST trip SOTF trip
T0 T2 TZp T3 T0
SOTF Z2+Rev (Zp Fwd) SOTF trip SOTF trip DIST trip x DIST trip SOTF trip
T0 T0 TZp T3 T0
SOTF Z1+Rev (Zp Rev) SOTF trip DIST trip x SOTF trip DIST trip DIST trip
T0 T2 T0 T3 T4
SOTF Z2+Rev (Zp Rev) SOTF trip SOTF trip x SOTF trip DIST trip DIST trip
T0 T0 T0 T3 T4
SOTF Dist. Sch. (Zp fwd) SOTF trip SOTF trip SOTF trip x SOTF trip SOTF trip
(With a 3Plogic) T1 T2 TZp T3 T4
SOTF Disable DIST trip DIST trip DIST trip x DIST trip DIST trip
(Distance scheme & 1P) T1* T2 TZp* T3 T4
No setting in SOTF DIST trip DIST trip DIST trip x DIST trip DIST trip
(All Bits at 0) & No I>3 T1* T2 TZp T3 T4
Level detectors SOTF trip SOTF trip SOTF trip x SOTF trip SOTF trip
T0 T0 T0 T0 T0

*No Ban Tri: Distance trip logic is applied without any 3P trip logic forced by SOTF.
TOR Trip logic results

Type of Fault Fault in Z1 Fault in Z2 Fault in Zp Fault in Zp Fault in Z3 Fault in Z4

Fwd Rev
TOR selected Logic
TOR All Zone TOR trip TOR trip TOR trip TOR trip TOR trip TOR trip
(Zp Fwd) T0 T0 T0 T0 T0 T0
TOR Z1 Enabled TOR trip Dist trip Dist trip Dist trip Dist trip Dist trip
(Zp Fwd) T0 T2 Tp Tp T3 T4
TOR Z2 Enabled TOR trip TOR trip Dist trip Dist trip Dist trip Dist trip
(Zp Fwd) T0 T0 Tp Tp T3 T4
TOR Z3 Enabled TOR trip TOR trip TOR trip Dist trip TOR trip Dist trip
(Zp Fwd) T0 T0 T0 Tp T0 T4
TOR Dist.Scheme Dist trip Dist trip Dist trip Dist trip Dist trip Dist trip
(logic POP/PUP) T1 T2 Tp Tp T3 T4
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 63/220

2.12.3 Switch on to Fault and Trip on Reclose by I>3 Overcurrent Element (not filtered for inruch
current):
Inside the 500 ms time window initiated by SOTF/TOR logic, an instantaneous 3 phases trip
logic will be issued, if a faulty current is measured over the I>3 threshold value (adjusted in
MiCOM S1).

After the 500 ms TOR/SOTF time windows has ended, the I>3 overcurrent element remains
in service with a trip time delay equal to the setting I>3 Time Delay. This element would trip
for close-up high current faults, such as those where maintenance earth clamps are
inadvertently left in position on line energisation.
2.12.4 Switch on to Fault and Trip on Reclose by Level Detectors
TOR/SOTF level detectors (Bit6 in SOTF logic), allows an instantaneous 3 phases tripping
from any low set I< level detector, provided that its corresponding Live Line level detector
has not picked up within 20ms. When closing a circuit breaker to energize a healthy line,
current would normally be detected above setting, but no trip results as the system voltage
rapidly recovers to near nominal. Only when a line fault is present will the voltage fail to
recover, resulting in a trip.

• SOTF/TOR trip by level detectors per phase: If Vphase< 70% Vn AND if Iphase> 5% In
during 20 ms (to avoid any maloperation due to unstable contact during reclosing
order), an instantaneous trip order is issued.
P44x/EN AP/E33 Application Notes

Page 64/220 MiCOM P441/P442 & P444

The logic diagram for this, and other modes of TOR/SOTF protection is shown in Figure 37:

T
Va > & 0 & TOC A

Ia < 20 ms

Vb >
T
& 0 & TOC B

Ib <
20 ms
Vc > T
& 0 & TOC C
Ic <
20 ms

SOTF LD Enable LD Enable

SOTF All Zones Enable

&
All Zones

SOTF Z1 Enable
&
≥1
Z1 &

SOTF Z1 + rev Enable &

Zp
&
Z4
1
Zp Reverse &

SOTF Z2 + rev Enable &

Z1+Z2

&
SOTF Z2 Enable
≥1 SOTF/TOR trip
SOTF Z3 Enable
&
Z1+Z2+Z3

PHOC_Start_3Ph_I>3

SOTF Enable

TOR Z1 Enable
&
Z1

TOR Z2 Enable

Z1+Z2 &

TOR Z3 Enable
& ≥1
Z1+Z2+Z3
&
TOR All Zones Enable
&
All Zones

Dist. Scheme Enable

&
Dist Trip

TOR Enable
P0486ENa

FIGURE 37 - SWITCH ON TO FAULT AND TRIP ON RECLOSE LOGIC DIAGRAM

Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 65/220

2.12.5 Setting Guidelines

• When the overcurrent option is enabled, the I>3 current setting applied should be
above load current, and > 35% of peak magnetising inrush current for any connected
transformers as this element has no second harmonic blocking. Setting guidelines for
the I>3 element are shown in more detail in Table below.

• When a Zone 1 Extension scheme is used along with autoreclosure, it must be

ensured that only Zone 1 distance protection can trip instantaneously for TOR.
Typically, TOR-SOTF Mode bit 0 only would be set to “1”. Also the I>3 element must
be disabled to avoid overreaching trips by level detectors.
2.12.5.1 Inputs

Data Type Description

Ia<, Ib<, Ic< Internal Logic No current detected (I< threshold, by default 5% In
or I< CB fail)
Dist Trip Internal Logic Trip by Distance logic
AR_RECLAIM Internal Logic Internal AR reclaim in progress
INP_RECLAIM Digital Input External AR in progress (by opto)
CBC_closing order Internal Logic Closing order in progress by CB Control
INP_CB_Man_Close Digital Input CB Closing order (by opto)
CB Control activated Configuration CB control activated
1P or 3 P AR Configuration 1P or 3P AR enabled
TOR Zi Enable Configuration TOR logic enabled in case of fault in Zi
TOR All Zones Enable Configuration TOR logic enabled in case for all zones (Distance
Start)
Dist. Scheme Enable Configuration Distance scheme aided Trip logic applied
SOTF LD Enable Configuration Levels detectors in SOTF activated
SOTF All Zones Enable Configuration SOTF logic enabled for all zones (Distance Start)
Va>, Vb>, Vc> Internal Logic Live Voltage detected ( V Live Line threshold, fixed
at 70% Vn)
Valid_stx_PHOC Configuration Threshold I>3 must be activated
PHOC_Start_3Ph_I>3 Internal Logic Detection by I>3 overcurrents (not filtered by
INRUSH.)
Z1, Z2, Z3, all zones Internal Logic Zones Detected

2.12.5.2 Outputs

Data Type Description

TOC_A Internal Logic Trip phase A by TOR /SOTF
TOC_B Internal Logic Trip phase B by TOR /SOTF
TOC_C Internal Logic Trip phase C by TOR /SOTF
SOTF/TOR trip Internal Logic Trip by SOTF (manual close) or TOR (AR close)
logic
P44x/EN AP/E33 Application Notes

Page 66/220 MiCOM P441/P442 & P444

2.12.6 Inputs /Outputs in SOTF-TOR DDB Logic

See also, DDB description in appendix of the same section.
2.12.6.1 Inputs

Man Close CB
Digital input (opto) 6 is assigned by default PSL to "Man Close CB"
The DDB Man Close CB if assigned to an opto input in PSL and when energized, will initiate
the internal SOTF logic enable (see Figure 35) without CB control.
If CB control is activated SOTF will be enable by internal detection (CB closing order
managed by CB control)

AR Reclaim
The DDB AR Reclaim if assigned to an opto input in PSL and when energized, will start the
internal logic TOR enable (see Figure 35).- (External AR logic applied).

CB aux A
CB aux B
CB aux C
The DDB CB Aux if assigned to an opto input in PSL and when energized, will be used for
Any pole dead & All pole dead internal detection
2.12.6.2 Outputs

SOTF Enable
The DDB SOTF Enable if assigned in PSL, indicates that SOTF logic is enabled in the relay
– see logic description in Figure 37

TOR Enable
The DDB TOR Enable if assigned in PSL, indicates that TOR logic is activated in the relay -
see logic description in Figure 37

TOC Start A
The DDB TOC Start A if assigned in PSL, indicates a Tripping order on phase A issued by
the SOTF levels detectors - see Figure 37

TOC Start B
The DDB TOC Start B if assigned in PSL, indicates a Tripping order on phase B issued by
the SOTF levels detectors - see Figure 37

TOC Start C
The DDB TOC Start C if assigned in PSL, indicates a Tripping order on phase C issued by
the SOTF levels detectors - see Figure 37

Any Pole Dead

The DDB Any Pole Dead if assigned in PSL, indicates that at least one pole is opened
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 67/220

All Pole Dead

The DDB All Pole Dead if assigned in PSL, indicates all pole are dead (All 3 poles are
opened)

SOTF/TOR Trip
The DDB SOTF/TOR Trip if assigned in PSL, indicates a 3poles trip by TOR or SOTF logic -
see Figure 37
2.13 Power swing blocking (PSB)
Power swings are oscillations in power flow which can follow a power system disturbance.
They can be caused by sudden removal of faults, loss of synchronism across a power
system or changes in direction of power flow as a result of switching. Such disturbances can
cause generators on the system to accelerate or decelerate to adapt to new power flow
conditions, which in turn leads to power swinging. A power swing may cause the impedance
presented to a distance relay to move away from the normal load area and into one or more
of its tripping characteristics. In the case of a stable power swing it is important that the relay
should not trip. The relay should also not trip during loss of stability since there may be a
utility strategy for controlled system break up during such an event.

Menu text Default setting Setting range Step size

Min Max
GROUP 1
POWER SWING
Delta R 0.5/In Ω 0 400/In Ω 0.01/In Ω
Delta X 0.5/In Ω 0 400/In Ω 0.01/In Ω
IN > Status Enabled Disabled or Enabled
IN > (% Imax) 40% 10% 100% 1%
I2 > Status Enabled Disabled or Enabled
I2 > (% Imax) 30% 10% 100% 1%
Imax line > Status Enabled Disabled or Enabled
Imax line > 3 x In 1 x In 20 x In 0.01 x In
Unblocking Time delay 30s 0 30s 0.1s
Blocking Zones 00000000 Bit 0: Z1/Z1X Block, Bit 1: Z2 Block,
Bit 2: Z3 Block, Bit 3: Zp Block.
P44x/EN AP/E33 Application Notes

Page 68/220 MiCOM P441/P442 & P444

2.13.1 The Power Swing Blocking Element

PSB can be disabled on distribution systems, where power swings would not normally be
experienced.
Operation of the PSB element is menu selectable to block the operation of any or all of the
distance zones (including aided trip logic) or to provide indication of the swing only. The
Blocked Zones function links are set to 1 to block zone tripping, or set to 0 to allow tripping
as normal. Power swing detection uses a ∆R (resistive) and ∆X (reactive) impedance band
which surrounds the entire phase fault trip characteristic. This band is shown in Figure 38
below:

∆X

Zone 3

Power
swing
∆R ∆R bundary

Zone 4

∆X

P3068ENa

FIGURE 38 - POWER SWING DETECTION CHARACTERISTICS

FIGURE 39 - POWER SWING SETTINGS (SET HIGHZONE IS LOCKED OUT)

Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 69/220

A fault on the system results in the measured impedance rapidly crossing the ∆R band, en
route to a tripping zone. Power swings follow a much slower impedance locus. A power
swing is detected where all three phase-phase measured impedances have remained within
the ∆R band for at least 5ms, and have taken longer than 5ms to reach the trip characteristic
(the trip characteristic boundary is defined by zones 3 and 4). PSB is indicated on reaching
zone 3 or zone 4. Typically, the ∆R and ∆X band settings are both set with: 0.032 x ∆f x
Rmin load.

NOTE: ∆f = Power swing frequency

2.13.2 Unblocking of the Relay for Faults During Power Swings
The relay can operate normally for any fault occurring during a power swing, as there are
three selectable conditions which can unblock the relay:
A biased residual current threshold is exceeded - this allows tripping for earth faults
occurring during a power swing. The bias is set as: Ir> (as a percentage of the highest
measured current on any phase), with the threshold always subject to a minimum of 0.1 x In.
Thus the residual current threshold is:
IN > 0.1 In + ( (IN> / 100) . (I maximum) ).
A biased negative sequence current threshold is exceeded - this allows tripping for phase-
phase faults occurring during a power swing. The bias is set as: I2> (as a percentage of the
highest measured current on any phase), with the threshold always subject to a minimum of
0.1 x In. Thus the negative sequence current threshold is:
I2 > 0.1 In + ( (I2> / 100) . (I maximum) ).
A phase current threshold is exceeded - this allows tripping for three-phase faults occurring
during a power swing. The threshold is set as: Imax line> (in A).
P44x/EN AP/E33 Application Notes

Page 70/220 MiCOM P441/P442 & P444

AnyPoleDead

Loop AN detected
≥1 &
S ≥2
in PS bundary ∆t
Q S
≥1 R Q PS loop AN

≥1
Tunb &

Loop BN detected ≥1
in PS bundary S
∆t
Q S
≥1 R Q PS loop BN

Tunb

≥1
Loop CN detected
in PS bundary S
Q
∆t
S ≥1 & S
≥1 R Q PS loop CN Q
Power Swing Detection
R
R

Tunb

Inrush AN

Inrush BN

Inrush CN

Fault clear ≥1
Healthy Network

All Pole Dead

& /Fuse Failure confirmed

PS disabled

Iphase>(Imax line>) S
Q
Unblocking Imax disabled R

∆ Tunblk
IN> threshold S
≥1 S
Q
R
Unblocking IN disabled Q
Power Swing unblocking

∆Tunblk ≥1 R
I2> threshold S
Q
R
Unblocking I2> disabled
P0488ENa

FIGURE 40 – POWER SWING DETECTION & UNBLOCKING LOGIC

Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 71/220

Z1x
& Z1x'

Unblock Z1
≥1
Z1'
Z1 &

Power Swing Detection Unblock Z2

≥1 ≥1
Unblocking Power Swing Z2'
&
Z2

Unblock Z3
≥1
Z3'
&
Z3

≥1
Zp_Fwd Zp'
& &
Unblock Zp
Zp
P0489ENa

FIGURE 41 - DISTANCE PROTECTION BLOCK/UNBLOCKING LOGIC

Data Type Description

∆R Configuration 0.1/In to 250/In by step 0.01/In
∆X Configuration 0.1/In to 250/In by step de 0.01/In
∆Tunbk Configuration 0 to 60 s by step de 1 s.
Imax> Configuration 1 to 20 In by step de 0.01
IN> Configuration 0.1In + 10 to 100 % of Imax>
I2> Configuration 0.1In + 10 to 100 % of Imax>
Unblock Z1 Configuration 0 => Z1 blocked during PSwing
1 => Z1 unblocked during PSwing
Unblock Z2 Configuration 0 => Z2 blocked during PSwing
1 => Z2 unblocked during PSwing
Unblock Z3 Configuration 0 => Z3 blocked during PSwing
1 => Z3 unblocked during PSwing
Unblock Zp Configuration 0 => Zp blocked during PSwing
1 => Zp unblocked during PSwing
P44x/EN AP/E33 Application Notes

Page 72/220 MiCOM P441/P442 & P444

2.13.3 Typical Current Settings

The three current thresholds must be set above the maximum expected residual current
unbalance, the maximum negative sequence unbalance, and the maximum expected power
swing current. Generally, the power swing current will not exceed 2.In. Typical setting limits
are given in Table 7 and Table 8 below:

Parameter Minimum Setting (to avoid Maximum Setting (to ensure Typical
maloperation for asymmetry unblocking for line faults) Setting
in power swing currents)
IN> > 30% < 100% 40%
I2> > 10% < 50% 30%

TABLE 7 - BIAS THRESHOLDS TO UNBLOCK PSB FOR LINE FAULTS

Parameter Minimum Setting Maximum Setting

Imax line> 1.2 x (maximum power swing 0.8 x (minimum phase fault current level)
current)

TABLE 8 - PHASE CURRENT THRESHOLD TO UNBLOCK PSB FOR LINE FAULTS

2.13.4 Removal of PSB to Allow Tripping for Prolonged Power Swings
It is possible to limit the time for which blocking of any distance protection zones is applied.
Thus, certain locations on the power system can be designated as split points, where circuit
breakers will trip three pole should a power swing fail to stabilise. Power swing blocking is
automatically removed after the Unblocking Delay with typical settings:

− 30s if a near permanent block is required;

− 2s if unblocking is required to split the system.

2.14 Directional and non-directional overcurrent protection
The overcurrent protection included in the P441, P442 and P444 relays provides two stage
non-directional / directional three phase overcurrent protection and two non directional
stages (I>3 and I>4), with independent time delay characteristics. One or more stages may
be enabled, in order to complement the relay distance protection. All overcurrent and
directional settings apply to all three phases but are independent for each of the four stages.
The first two stages of overcurrent protection, I>1 and I>2 have time delayed characteristics
which are selectable between inverse definite minimum time (IDMT), or definite time (DT).
The third and fourth overcurrent stages can be set as follows:
I>3 - The third element is fixed as non-directional, for instantaneous or definite time delayed
tripping. This element can be permanently enabled, or enabled only for Switch on to Fault
(SOTF) or Trip on Reclose (TOR). It is also used to detect close-up faults (in SOTF/TOR
tripping logic no timer is applied).
I>4 - The fourth element is only used for stub bus protection, where it is fixed as non-
directional, and only enabled when the opto-input Stub Bus Isolator Open (Stub Bus
Enable) is energised.
All the stages trip three-phase only. (Could be used for back up protection during a VTS
logic)
The following Table shows the relay menu for overcurrent protection, including the available
setting ranges and factory defaults. Note that all tripping via overcurrent protection is three
pole.
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 73/220

Menu text Default setting Setting range Step size

Min Max
GROUP 1
BACK-UP I>
I>1 Function DT Disabled, DT, IEC S Inverse, IEC V
Inverse, IEC E Inverse, UK LT Inverse,
IEEE M Inverse, IEEE V Inverse, IEEE E
Inverse, US Inverse, US ST Inverse
I>1 Direction Directional Fwd Non-Directional, Directional Fwd,
Directional Rev
I>1 VTS Block Non-Directional Block, Non-Directional
I>1 Current Set 1.5 x In 0.08 x In 4.0 x In 0.01 x In
I>1 Time Delay 1s 0 100s 0.01s
I>1 Time Delay VTS 0.2s 0 100s 0.01s
I>1 TMS 1 0.025 1.2 0.025
I>1 Time Dial 7 0.5 15 0.1
I>1 Reset Char DT DT or Inverse
I>1 tRESET 0 0 100s 0.01s
I>2 Function DT Disabled, DT, IEC S Inverse, IEC V
Inverse, IEC E Inverse, UK LT Inverse,
IEEE M Inverse, IEEE V Inverse, IEEE E
Inverse, US Inverse, US ST Inverse
I>2 Direction Non Directional Non-Directional, Directional Fwd,
Directional Rev
I>2 VTS Block Non-Directional Block, Non-Directional
I>2 Current Set 2 x In 0.08 x In 4.0 x In 0.01 x In
I>2 Time Delay 2s 0 100s 0.01s
I>2 Time Delay VTS 2s 0 100s 0.01s
I>2 TMS 1 0.025 1.2 0.025
I>2 Time Dial 7 0.5 15 0.1
I>2 Reset Char DT DT or Inverse
I>2 tRESET 0 0 100s 0.01s
I>3 Status Enabled Disabled or Enabled
I>3 Current Set 3 x In 0.08 x In 32 x In 0.01xIn
I>3 Time Delay 3s 0s 100s 0.01s
I>4 Status Disabled Disabled or Enabled
I>4 Current Set 4 x In 0.08 x In 32 x In 0.01xIn
I>4 Time Delay 4s 0s 100s 0.01s
P44x/EN AP/E33 Application Notes

Page 74/220 MiCOM P441/P442 & P444

The inverse time delayed characteristics listed above, comply with the following formula:

t=T× + L
K
(I/Is) α
–1 
Where:
t = operation time
K = constant
I = measured current
Is = current threshold setting

α = constant
L = ANSI/IEEE constant (zero for IEC curves)
T = Time multiplier Setting

Curve description Standard K constant α constant L constant

Standard Inverse IEC 0.14 0.02 0
Very Inverse IEC 13.5 1 0
Extremely Inverse IEC 80 2 0
Long Time Inverse UK 120 1 0
Moderately Inverse IEEE 0.0515 0.02 0.0114
Very Inverse IEEE 19.61 2 0.491
Extremely Inverse IEEE 28.2 2 0.1217
Inverse US 5.95 2 0.18
Short Time Inverse US 0.02394 0.02 0.1694

Note that the IEEE and US curves are set differently to the IEC/UK curves, with regard to the
time setting. A time multiplier setting (TMS) is used to adjust the operating time of the IEC
curves, whereas a time dial setting is employed for the IEEE/US curves. Both the TMS and
Time Dial settings act as multipliers on the basic characteristics but the scaling of the time
dial is 10 times that of the TMS, as shown in the previous menu. The menu is arranged such
that if an IEC/UK curve is selected, the I> Time Dial cell is not visible and vice versa for the
TMS setting.
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 75/220

2.14.1 Application of Timer Hold Facility

The first two stages of overcurrent protection in the P441, P442 and P444 relays are
provided with a timer hold facility, which may either be set to zero or to a definite time value.
(Note that if an IEEE/US operate curve is selected, the reset characteristic may be set to
either definite or inverse time in cell I>1 Reset Char; otherwise this setting cell is not visible
in the menu). Setting of the timer to zero means that the overcurrent timer for that stage will
reset instantaneously once the current falls below 95% of the current setting. Setting of the
hold timer to a value other than zero, delays the resetting of the protection element timers for
this period. This may be useful in certain applications, for example when grading with
upstream electromechanical overcurrent relays which have inherent reset time delays.
Another possible situation where the timer hold facility may be used to reduce fault clearance
times is where intermittent faults may be experienced. An example of this may occur in a
plastic insulated cable. In this application it is possible that the fault energy melts and reseals
the cable insulation, thereby extinguishing the fault. This process repeats to give a
succession of fault current pulses, each of increasing duration with reducing intervals
between the pulses, until the fault becomes permanent.
When the reset time of the overcurrent relay is instantaneous the relay may not trip until the
fault becomes permanent. By using the timer hold facility the relay will integrate the fault
current pulses, thereby reducing fault clearance time.
Note that the timer hold facility should not be used where high speed autoreclose with short
dead times are set.
The timer hold facility can be found for the first and second overcurrent stages as settings
I>1 tRESET and I>2 tRESET. Note that this cell is not visible if an inverse time reset
characteristic has been selected, as the reset time is then determined by the programmed
time dial setting.
2.14.2 Directional Overcurrent Protection
If fault current can flow in both directions through a relay location, it is necessary to add
directional control to the overcurrent relays in order to obtain correct discrimination. Typical
systems which require such protection are parallel feeders and ring main systems. Where
I>1 or I>2 stages are directionalised, no characteristic angle needs to be set as the relay
uses the same directionalising technique as for the distance zones (fixed superimposed
power technique).
2.14.3 Time Delay VTS
Should the Voltage Transformer Supervision function detect an ac voltage input failure to the
relay, such as due to a VT fuse blow, this will affect operation of voltage dependent
protection elements. Distance protection will not be able to make a forward or reverse
decision, and so will be blocked. As the I>1 and I>2 overcurrent elements in the relay use
the same directionalising technique as for the distance zones, any directional zones would
be unable to trip.
To maintain protection during periods of VTS detected failure, the relay allows an I> Time
Delay VTS to be applied to the I>1 and I>2 elements. On VTS pickup, both elements are
forced to have non-directional operation, and are subject to their revised definite time delay.
2.14.4 Setting Guidelines
I>1 and I>2 Overcurrent Protection
When applying the overcurrent or directional overcurrent protection provided in the P441,
P442 and P444 relays, standard principles should be applied in calculating the necessary
current and time settings for co-ordination. For more detailed information regarding
overcurrent relay co-ordination, reference should be made to AREVA’s ‘Protective relay
Application Guide’ - Chapter 9. In general, where overcurrent elements are set, these
should also be set to time discriminate with downstream and reverse distance protection.
The I>1 and I>2 elements are continuously active. However tripping is blocked if the
distance protection function starts. An example is shown in Figure 42.
P44x/EN AP/E33 Application Notes

Page 76/220 MiCOM P441/P442 & P444

Time
I>1
I>2
Z3,tZ3
Z4, tZ4
Zp,tZp
Z2,tZ2
Reverse Z1,tZ1 Forward

P3069ENa

FIGURE 42 - TIME GRADING OVERCURRENT PROTECTION WITH DISTANCE PROTECTION (DT

EXAMPLE)
I>1 and I>2 Time Delay VTS
The I>1 and I>2 overcurrent elements should be set to mimic operation of distance
protection during VTS pickup. This requires I>1 and I>2 current settings to be calculated to
approximate to distance zone reaches, although operating non-directional. If fast protection
is the main priority then a time delay of zero or equal to tZ2 could be used. If parallel
current-based main protection is used alongside the relay, and protection discrimination
remains the priority, then a DT setting greater than that for the distance zones should be
used. An example is shown in Figure 43.

I phase

I 1>

Trip

I 2>

No trip

t
tI1> tI2> P0483ENa

FIGURE 43 - TRIPPING LOGIC FOR PHASE OVERCURRENT PROTECTION

I>3 Highset Overcurrent and Switch on to Fault Protection
The I>3 overcurrent element of the P441, P442 and P444 relays can be Enabled as an
instantaneous highset just during the TOR/SOTF period. After this period has ended, the
element remains in service with a trip time delay setting I>3 Time Delay. This element
would trip for close-up high current faults, such as those where maintenance earth clamps
are inadvertently left in position on line energisation.
The I>3 current setting applied should be above load current, and > 35% of peak
magnetising inrush current for any connected transformers as this element has no second
harmonic blocking. If a high current setting is chosen, such that the I>3 element will not
overreach the protected line, then the I>3 Time Delay can be set to zero. It should also be
verified that the remote source is not sufficiently strong to cause element pickup for a close-
up reverse fault.
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 77/220

If a low current setting is chosen, I>3 will need to discriminate with local and remote distance
protection. This principle is shown in Table 9.

I>3 Current Setting Instantaneous Function After Time Delay Required

TOR/SOTF Function TOR/SOTF Period
Above load and inrush Yes - sensitive. Time delayed backup Longer than tZ3 to
current but LOW protection. grade with distance
protection.
HIGH, ≥ 120% of max. Yes - may detect Instantaneous I>3 Time Delay = 0.
fault current for a fault at high current close- highset to detect (Note #.)
the remote line terminal up faults. close-up faults.
and max. reverse fault
current

TABLE 9 - CURRENT AND TIME DELAY SETTINGS FOR THE I>3 ELEMENT
Key:
As the instantaneous highset trips three pole it is recommended that the I>3 Time
Delay is set ≥ tZ2 in single pole tripping schemes, to allow operation of the correct
single pole autoreclose cycle.
I>4 Stub Bus Protection
When the protected line is switched from a breaker and a half arrangement it is possible to
use the I>4 overcurrent element to provide stub bus protection. When stub bus protection is
selected in the relay menu, the element is only enabled when the opto-input Stub Bus
Isolator Open (Stub Bus Enable) is energised. Thus, a set of 52b auxiliary contacts (closed
when the isolator is open) are required.

I>4 Element: Stub Bus Protection

Busbar 1
VT

V=0

Protection's blocking using VTs

I>0
Open isolator

Stub Bus Protection : I >4

Busbar 2
P0536ENa

Although this element would not need to discriminate with load current, it is still common
practice to apply a high current setting. This avoids maloperation for heavy through fault
currents, where mismatched CT saturation could present a spill current to the relay. The I>4
element would normally be set instantaneous, t>4 = 0s.
P44x/EN AP/E33 Application Notes

Page 78/220 MiCOM P441/P442 & P444

2.15 Negative sequence overcurrent protection (NPS)

When applying traditional phase overcurrent protection, the overcurrent elements must be
set higher than maximum load current, thereby limiting the element’s sensitivity. Most
protection schemes also use an earth fault element operating from residual current, which
improves sensitivity for earth faults. However, certain faults may arise which can remain
undetected by such schemes.
Any unbalanced fault condition will produce negative sequence current of some magnitude.
Thus, a negative phase sequence overcurrent element can operate for both phase-to-phase
and phase to earth faults.
The following section describes how negative phase sequence overcurrent protection may
be applied in conjunction with standard overcurrent and earth fault protection in order to
alleviate some less common application difficulties.

• Negative phase sequence overcurrent elements give greater sensitivity to resistive

phase-to-phase faults, where phase overcurrent elements may not operate.

• In certain applications, residual current may not be detected by an earth fault relay
due to the system configuration. For example, an earth fault relay applied on the delta
side of a delta-star transformer is unable to detect earth faults on the star side.
However, negative sequence current will be present on both sides of the transformer
for any fault condition, irrespective of the transformer configuration. Therefore, an
negative phase sequence overcurrent element may be employed to provide time-
delayed back-up protection for any uncleared asymmetrical faults downstream.

• Where rotating machines are protected by fuses, loss of a fuse produces a large
amount of negative sequence current. This is a dangerous condition for the machine
due to the heating effects of negative phase sequence current and hence an upstream
negative phase sequence overcurrent element may be applied to provide back-up
protection for dedicated motor protection relays.

• It may be required to simply alarm for the presence of negative phase sequence
currents on the system. Operators may then investigate the cause of the unbalance.
The negative phase sequence overcurrent element has a current pick up setting ‘I2> Current
Set’, and is time delayed in operation by the adjustable timer ‘I2> Time Delay’. The user
may choose to directionalise operation of the element, for either forward or reverse fault
protection for which a suitable relay characteristic angle may be set. Alternatively, the
element may be set as non-directional.
2.15.1 Setting Guidelines
The relay menu for the negative sequence overcurrent element is shown below:

NEG SEQ O/C Default Min Max Step

I2> Status Enabled Disabled, Enabled
I2> Directional Non-Directional Non-Directional, Directional Fwd, Directional Rev
I2> VTS Non-Directionel Block, Non-Directional
I2> Current Set 0.2In 0.08In 4In 0.01In
I2> Time Delay 10s 0s 100s 0.01s
I2> Char Angle –45° –95° +95° 1°
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 79/220

2.15.2 Negative phase sequence current threshold, ‘I2> Current Set’

The current pick-up threshold must be set higher than the negative phase sequence current
due to the maximum normal load unbalance on the system. This can be set practically at the
commissioning stage, making use of the relay measurement function to display the standing
negative phase sequence current, and setting at least 20% above this figure.
Where the negative phase sequence element is required to operate for specific uncleared
asymmetric faults, a precise threshold setting would have to be based upon an individual
fault analysis for that particular system due to the complexities involved. However, to ensure
operation of the protection, the current pick-up setting must be set approximately 20% below
the lowest calculated negative phase sequence fault current contribution to a specific remote
fault condition.
Note that in practice, if the required fault study information is unavailable, the setting must
adhere to the minimum threshold previously outlined, employing a suitable time delay for co-
ordination with downstream devices. This is vital to prevent unnecessary interruption of the
supply resulting from inadvertent operation of this element.
2.15.3 Time Delay for the Negative Phase Sequence Overcurrent Element, ‘I2> Time Delay’
As stated above, correct setting of the time delay for this function is vital. It should also be
noted that this element is applied primarily to provide back-up protection to other protective
devices or to provide an alarm. Hence, in practice, it would be associated with a long time
delay.
It must be ensured that the time delay is set greater than the operating time of any other
protective device (at minimum fault level) on the system which may respond to unbalanced
faults, such as:

• Phase overcurrent elements

• Earth fault elements

• Broken conductor elements

• Negative phase sequence influenced thermal elements

2.15.4 Directionalising the Negative Phase Sequence Overcurrent Element
Where negative phase sequence current may flow in either direction through a relay location,
such as parallel lines or ring main systems, directional control of the element should be
employed.
Directionality is achieved by comparison of the angle between the negative phase sequence
voltage and the negative phase sequence current and the element may be selected to
operate in either the forward or reverse direction. A suitable relay characteristic angle setting
(I2> Char Angle) is chosen to provide optimum performance. This setting should be set
equal to the phase angle of the negative sequence current with respect to the inverted
negative sequence voltage (- V2), in order to be at the centre of the directional characteristic.
The angle that occurs between V2 and I2 under fault conditions is directly dependent upon
the negative sequence source impedance of the system. However, typical settings for the
element are as follows:

• For a transmission system the RCA should be set equal to -60°

• For a distribution system the RCA should be set equal to -45°

P44x/EN AP/E33 Application Notes

Page 80/220 MiCOM P441/P442 & P444

2.16 Broken conductor detection

The majority of faults on a power system occur between one phase and ground or two
phases and ground. These are known as shunt faults and arise from lightning discharges
and other overvoltages which initiate flashovers. Alternatively, they may arise from other
causes such as birds on overhead lines or mechanical damage to cables etc. Such faults
result in an appreciable increase in current and hence in the majority of applications are
easily detectable.
Another type of unbalanced fault which can occur on the system is the series or open circuit
fault. These can arise from broken conductors, maloperation of single phase switchgear, or
the operation of fuses. Series faults will not cause an increase in phase current on the
system and hence are not readily detectable by standard overcurrent relays. However, they
will produce an unbalance and a resultant level of negative phase sequence current, which
can be detected.
It is possible to apply a negative phase sequence overcurrent relay to detect the above
condition. However, on a lightly loaded line, the negative sequence current resulting from a
series fault condition may be very close to, or less than, the full load steady state unbalance
arising from CT errors, load unbalance etc. A negative sequence element therefore would
not operate at low load levels.
The relay incorporates an element which measures the ratio of negative to positive phase
sequence current (I2/I1). This will be affected to a lesser extent than the measurement of
negative sequence current alone, since the ratio is approximately constant with variations in
load current. Hence, a more sensitive setting may be achieved.
2.16.1 Setting Guidelines
The sequence network connection diagram for an open circuit fault is detailed in Figure 1.
From this, it can be seen that when a conductor open circuit occurs, current from the positive
sequence network will be series injected into the negative and zero sequence networks
across the break.
In the case of a single point earthed power system, there will be little zero sequence current
flow and the ratio of I2/I1 that flows in the protected circuit will approach 100%. In the case of
a multiple earthed power system (assuming equal impedances in each sequence network),
the ratio I2/I1 will be 50%.
It is possible to calculate the ratio of I2/I1 that will occur for varying system impedances, by
referring to the following equations:-
E (Z + Z )
I1F = Z Z +g Z 2Z + 0Z Z
1 2 1 0 2 0

–E Z
I2F = Z Z + Z Zg 0+ Z Z
1 2 1 0 2 0

Where:
Eg = System Voltage
Z0 = Zero sequence impedance
Z1 = Positive sequence impedance
Z2 = Negative sequence impedance
Therefore:

I2F Z0
=
I1F Z0 + Z2
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 81/220

It follows that, for an open circuit in a particular part of the system, I2/I1 can be determined
from the ratio of zero sequence to negative sequence impedance. It must be noted however,
that this ratio may vary depending upon the fault location. It is desirable therefore to apply as
sensitive a setting as possible. In practice, this minimum setting is governed by the levels of
standing negative phase sequence current present on the system. This can be determined
from a system study, or by making use of the relay measurement facilities at the
commissioning stage. If the latter method is adopted, it is important to take the
measurements during maximum system load conditions, to ensure that all single phase
loads are accounted for.
Note that a minimum value of 8% negative phase sequence current is required for
successful relay operation.
Since sensitive settings have been employed, it can be expected that the element will
operate for any unbalance condition occurring on the system (for example, during a single
pole autoreclose cycle). Hence, a long time delay is necessary to ensure co-ordination with
other protective devices. A 60 second time delay setting may be typical.
The following table shows the relay menu for the Broken Conductor protection, including the
available setting ranges and factory defaults:-

Menu text Default setting Setting range Step size

Min Max
GROUP 1
BROKEN CONDUCTOR
Broken Conductor Enabled Enabled/Disabled N/A
I2/I1 0.2 0.2 1 0.01
I2/I1 Time Delay 60 0s 100s 1s
I2/I1 Trip Disabled* Enabled Disabled N/A

* If disabled, only a Broken Conductor Alarm is possible.

2.16.2 Example Setting
The following information was recorded by the relay during commissioning;
Ifull load = 1000A
I2 = 100A
therefore the quiescent I2/I1 ratio is given by;
I2/I1 = 100/1000 = 0.05
To allow for tolerances and load variations a setting of 200% of this value may be typical:
Therefore set I2/I1 = 0.2
Set I2/I1 Time Delay = 60s to allow adequate time for short circuit fault clearance by time
delayed protections.
P44x/EN AP/E33 Application Notes

Page 82/220 MiCOM P441/P442 & P444

2.17 Directional and non-directional earth fault protection

Three elements of earth fault protection are available, as follows:

• IN> element - Channel aided directional earth fault protection;

• IN>1 element - Directional or non-directional protection, definite time

(DT) or IDMT time-delayed.

• IN>2 element - Directional or non-directional, DT delayed.

The IN> element may only be used as part of a channel-aided scheme, and is fully described
in the Aided DEF section of the Application Notes which follow.
The IN>1 and IN>2 backup elements always trip three pole, and have an optional timer hold
facility on reset, as per the phase fault elements. (The IN> element can be selected to trip
single and/or three pole). All Earth Fault overcurrent elements operate from a residual
current quantity which is derived internally from the summation of the three phase currents.
The following table shows the relay menu for the Earth Fault protection, including the
available setting ranges and factory defaults.

Menu text Default setting Setting range Step size

Min Max
GROUP 1
EARTH FAULT O/C
IN>1 Function DT Disabled, DT, IEC S Inverse, IEC V
Inverse, IEC E Inverse, UK LT Inverse,
IEEE M Inverse, IEEE V Inverse, IEEE E
Inverse, US Inverse, US ST Inverse
IN>1 Directional Directional Fwd Non-Directional, Directional Fwd,
Directional Rev
IN>1 VTS Block Non directional Block or Non directional
IN>1 Current Set 0.2 x In 0.08 x In 4.0 x In 0.01 x In
IN>1 Time Delay 1s 0 200s 0.01s
IN>1 Time Delay VTS 0.2s 0 200s 0.01s
IN>1 TMS 1 0.025 1.2 0.025
IN>1 Time Dial 7 0.5 15 0.1
IN>1 Reset Char DT DT or Inverse
IN>1 tRESET 0 0 100s 0.01s
IN>2 Status Enabled Disabled or Enabled
IN>2 Directional Non Directional Non-Directional, Directional Fwd,
Directional Rev
IN>2 VTS Block Non directional Block or Non directional
IN>2 Current Set 0.3 x In 0.08 x In 32 x In 0.01 x In
IN>2 Time Delay 2s 0 200s 0.01s
IN>2 Time Delay VTS 2s 0 200s 0.01s
IN> DIRECTIONAL
IN> Char Angle –45° –95° 95° 1°
Polarisation Zero Sequence Zero Sequence or Negative Sequence
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 83/220

Note that the elements are set in terms of residual current, which is three times the
magnitude of zero sequence current (Ires = 3I0). The IDMT time delay characteristics
available for the IN>1 element, and the grading principles used will be as per the phase fault
overcurrent elements.
To maintain protection during periods of VTS detected failure, the relay allows an IN> Time
Delay VTS to be applied to the IN>1 and IN>2 elements. On VTS pickup, both elements are
forced to have non-directional operation, and are subject to their revised definite time delay.

V2

I2
Negative sequence
Polarisation Directional SBEF Fwd
VN Residual zero
Calculation SBEF Rev
sequence Polarisation

IN

IN IN> IN> Pick-up

IN> Pick-up

CTS Blocking IDMT/DT IN> Trip

Any Pole Dead &
IN> Timer Block

IN> Pick-up

CTS Blocking

Any Pole Dead

&
IN> Timer Block & IDMT/DT

SBEF Fwd Directionnal

Check
SBEF Rev
& >1 IN> Trip
MCB/VTS Line
IN> TD VTS

&
0
P0490ENa

FIGURE 44 - SBEF CALCULATION & LOGIC

P44x/EN AP/E33 Application Notes

Page 84/220 MiCOM P441/P442 & P444

CTS Block
SBEF Start
SBEF
Overcurrent
SBEF
IDMT/DT
Trip SBEF Trip
SBEF Timer Block
P0484ENa

FIGURE 45 - LOGIC WITHOUT DIRECTIONALITY

CTS Block

SBEF
Overcurrent SBEF Start

Slow VTS
Block Directional
Check
Vx > Vs
Ix > Is
IDMT/DT
SBEF Trip
SBEF Timer Block
P0533ENa

FIGURE 46 - LOGIC WITH DIRECTIONALITY

2.17.1 Directional Earth Fault Protection (DEF)
The method of directional polarising selected is common to all directional earth fault
elements, including the channel-aided element. There are two options available in the relay
menu:
• Zero sequence polarising - The relay performs a directional decision by comparing
the phase angle of the residual current with respect to the inverted residual voltage:
(–Vres = –(Va + Vb + Vc)) derived by the relay.

• Negative sequence polarising - The relay performs a directional decision by

comparing the phase angle of the derived negative sequence current with respect to
the derived negative sequence voltage.
NOTE: Even though the directional decision is based on the phase
relationship of I2 with respect to V2, the operating current quantity for
DEF elements remains the derived residual current.
2.17.2 Application of Zero Sequence Polarising
This is the conventional option, applied where there is not significant mutual coupling with a
parallel line, and where the power system is not solidly earthed close to the relay location.
As residual voltage is generated during earth fault conditions, this quantity is commonly used
to polarise DEF elements. The relay internally derives this voltage from the 3 phase voltage
input which must be supplied from either a 5-limb or three single phase VT’s. These types of
VT design allow the passage of residual flux and consequently permit the relay to derive the
required residual voltage. In addition, the primary star point of the VT must be earthed. A
three limb VT has no path for residual flux and is therefore incompatible with the use of zero
sequence polarising.
The required characteristic angle settings for DEF will differ depending on the application.
Typical characteristic angle settings are as follows:
• Resistance earthed systems generally use a 0° RCA setting. This means that for a
forward earth fault, the residual current is expected to be approximately in phase with
the inverted residual voltage (-Vres).
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 85/220

• When protecting solidly-earthed distribution systems or cable feeders, a -45° RCA

setting should be set.

• When protecting solidly-earthed transmission systems, a -60° RCA setting should be

set.
2.17.3 Application of Negative Sequence Polarising
In certain applications, the use of residual voltage polarisation of DEF may either be not
possible to achieve, or problematic. An example of the former case would be where a
suitable type of VT was unavailable, for example if only a three limb VT were fitted. An
example of the latter case would be an HV/EHV parallel line application where problems with
zero sequence mutual coupling may exist. In either of these situations, the problem may be
solved by the use of negative phase sequence (nps) quantities for polarisation. This method
determines the fault direction by comparison of nps voltage with nps current. The operate
quantity, however, is still residual current.
When negative sequence polarising is used, the relay requires that the Characteristic Angle
is set. The Application Notes section for the Negative Sequence Overcurrent Protection
better describes how the angle is calculated - typically set at - 45° (I2 lags (-V2)).
2.18 Aided DEF protection schemes
The option of using separate channels for DEF aided tripping, and distance protection
schemes, is offered in the P441, P442 and P444 relays. When a separate channel for DEF
is used, the above DEF schemes are independently selectable. When a common signalling
channel is employed, the distance and DEF must Share a common scheme. In this case a
permissive overreach or blocking distance scheme must be used. The aided tripping
schemes can perform single pole tripping. The relay has aided scheme settings as shown in
the following table:

Menu text Default setting Setting range Step size

Min Max
GROUP 1
AIDED D.E.F.
Aided DEF Status Enabled Disabled or Enabled
Polarisation Zero Sequence Zero Sequence or Negative Sequence
V> Voltage Set 1V 0.5V 20V 0.01V
IN Forward 0.1 x In 0.05 x In 4 x In 0.01 x In
Time Delay 0 0 10s 0.1s
Scheme Logic Shared Shared, Blocking or Permissive
Tripping Three Phase Three Phase or Single Phase

FIGURE 47 - MiCOM S1 SETTINGS

P44x/EN AP/E33 Application Notes

Page 86/220 MiCOM P441/P442 & P444

Opto label 01 DIST. CR DIST CS Relay Label 01

Opto Label 02 DEF. CR DEF CS Relay Label 02

P0534ENa

FIGURE 48 - PSL REQUIRED TO ACTIVATE DEF LOGIC WITH AN INDEPENDANT CHANNEL

Opto label 01 DIST. CR DIST CS

>1 Relay label 01
DEF. CR DEF CS
P0544ENa

FIGURE 49 - PSL REQUIRED TO ACTIVATE DEF LOGIC WITH SHARED CHANNEL

V2
Negative
I2 Polarisation Directionnal DEF Fwd
VN Residual
Calculation DEF Rev
Polarisation
IN

Negative
V2 Polarisation
V> DEF V>
Residual
VN Polarisation

INRev>
IN IN>
INRev = 0.6*INFwd
INFwd>
P0545ENa

FIGURE 50 - DEF CALCULATION

NOTE: The DEF is blocked in case of VTS or CTS
2.18.1 Polarising the Directional Decision
The relative advantages of zero sequence and negative sequence polarising are outlined on
the previous page. Note how the polarising chosen for aided DEF is independent of that
chosen for backup earth fault elements.
The relay has a V> threshold which defines the minimum residual voltage required to enable
an aided DEF directional decision to be made. A residual voltage measured below this
setting would block the directional decision, and hence there would be no tripping from the
scheme. The V> threshold is set above the standing residual voltage on the protected
system, to avoid operation for typical power system imbalance and voltage transformer
errors. In practice, the typical zero sequence voltage on a healthy system can be as high as
1% (ie: 3% residual), and the VT error could be 1% per phase. This could equate to an
overall error of up to 5% of phase-neutral voltage, although a setting between 2% and 4% is
typical. On high resistance earthed and insulated neutral systems the settings might need to
be as high as 10% or 20% of phase-neutral voltage, respectively.
When negative sequence polarising is set, the V> threshold becomes a V2> negative
sequence voltage detector.
The characteristic angle for aided DEF protection is fixed at –14°, suitable for protecting all
solidly-earthed and resistance earthed systems.
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 87/220

FWD FWD

R
-14˚
REV REV

P0491ENa

2.18.2 Aided DEF Permissive Overreach Scheme

DEF Fwd

IN Fwd>

DEF V>

DEF Timer Block

Reversal Guard & DEF CS

0
Any Pole Dead
150 ms

T
& DEF Trip
IN Rev>
0

t_delay
UNB CR DEF
P0546ENa

FIGURE 51 - INDEPENDANT CHANNEL – PERMISSIVE SCHEME

DEF Fwd

IN Fwd>

DEF V>

DEF Timer Block

Reversal Guard & DEF CS

Any Pole Dead 0

>1
Any DIST Start 150 ms
& DEF Trip
T
IN Rev>
0

t_delay
UNB CR DEF
P0547ENa

FIGURE 52 - SHARED CHANNEL – PERMISSIVE SCHEME

This scheme is similar to that used in the AREVA LFZP, LFZR, EPAC and PXLN relays.
Figure 53 shows the element reaches, and Figure 54 the simplified scheme logic. The
signalling channel is keyed from operation of the forward IN> DEF element of the relay. If
the remote relay has also detected a forward fault, then it will operate with no additional
delay upon receipt of this signal.
Send logic: IN> Forward pickup
Permissive trip logic: IN> Forward plus Channel Received.
P44x/EN AP/E33 Application Notes

Page 88/220 MiCOM P441/P442 & P444

IN> Fwd (A)

ZL
A B

IN> Fwd (B)

P3070ENa

FIGURE 53 - THE DEF PERMISSIVE SCHEME

FIGURE 54 - LOGIC DIAGRAM FOR THE DEF PERMISSIVE SCHEME

The scheme has the same features/requirements as the corresponding distance scheme
and provides sensitive protection for high resistance earth faults.
Where “t” is shown in the diagram this signifies the time delay associated with an element,
noting that the Time Delay for a permissive scheme aided trip would normally be set to zero.
2.18.3 Aided DEF Blocking Scheme
This scheme is similar to that used in the AREVA LFZP, LFZR, EPAC and PXLN relays.
Figure 57 shows the element reaches, and Figure 58 the simplified scheme logic. The
signalling channel is keyed from operation of the reverse DEF element of the relay. If the
remote relay forward IN> element has picked up, then it will operate after the set Time Delay
if no block is received.

DEF Fwd

IN Fwd>
Tp

DEF V> 0

Reversal Guard

IN Rev>
T
& & DEF Trip
0

0 t_delay
Any Pole Dead
150 ms

DEF Timer Block

UNB CR DEF

DEF Rev
& DEF CS
IN Rev>

DEF V>
P0548ENa

FIGURE 55 - INDEPENDANT CHANNEL – BLOCKING SCHEME

Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 89/220

DEF Fwd

IN Fwd>

DEF V>

Reversal Guard 0

IN Rev>
T
& Tp
0

Any Pole Dead t_delay

0

Any DIST Start

>1 150 ms

DEF Timer Block

& DEF Trip
UNB CR DEF

DEF Rev

IN Rev>
& DEF CS

DEF V>
P0549ENa

FIGURE 56 - SHARED CHANNEL – BLOCKING SCHEME

Send logic: DEF Reverse
Trip logic: IN> Forward, plus Channel NOT Received, with small set delay.

IN> Fwd (A)

IN> Rev (A)
ZL
A B

IN> Fwd (B)

IN> Rev (B)

P0550ENa

FIGURE 57 - THE DEF BLOCKING SCHEME

Signal Protection A Protection B Signal

Send IN> Send IN>
Reverse Reverse

IN>1 t t IN>1
0 0

Trip Trip
IN>2 t
0 >1 >1 0
t IN>2

IN > & t t IN>

Forward 0 0 &
Forward

P0551ENa

FIGURE 58 - LOGIC DIAGRAM FOR THE DEF BLOCKING SCHEME

The scheme has the same features/requirements as the corresponding distance scheme
and provides sensitive protection for high resistance earth faults.
Where “t” is shown in the diagram this signifies the time delay associated with an element.
To allow time for a blocking signal to arrive, a short time delay on aided tripping must be
used. The recommended Time Delay setting = max. signalling channel operating time +
14ms.
P44x/EN AP/E33 Application Notes

Page 90/220 MiCOM P441/P442 & P444

2.19 Undervoltage protection

Undervoltage conditions may occur on a power system for a variety of reasons, some of
which are outlined below:-

• Increased system loading. Generally, some corrective action would be taken by

voltage regulating equipment such as AVR’s or On Load Tap Changers, in order to
bring the system voltage back to it’s nominal value. If the regulating equipment is
unsuccessful in restoring healthy system voltage, then tripping by means of an
undervoltage relay will be required following a suitable time delay.

• Faults occurring on the power system result in a reduction in voltage of the phases
involved in the fault. The proportion by which the voltage decreases is directly
dependent upon the type of fault, method of system earthing and its location with
respect to the relaying point. Consequently, co-ordination with other voltage and
current-based protection devices is essential in order to achieve correct discrimination.
This function will be blocked with VTS logic or could be disabled if CB open.
Both the under and overvoltage protection functions can be found in the relay menu “Volt
Protection”. The following table shows the undervoltage section of this menu along with the
available setting ranges and factory defaults.

Menu text Default setting Setting range Step size

Min Max
GROUP 1
VOLT Protection
V< & V> MODE 0 V<1 Trip, V<2 Trip, V>1 Trip, V>2 Trip
UNDER VOLTAGE
V< Measur't Mode Phase-Neutral Phase-phase or Phase-neutral
V<1 Function DT Disabled, DT pr IDMT
V<1 Voltage Set 50V 10V 120V 1V
V<1 Time Delay 10s 0s 100s 0.01s
V<1 TMS 1 0.5 100 0.5
V<2 Status Disabled Disabled or Enabled
V<2 Voltage Set 38V 10V 120V 1V
V<2 Time Delay 5s 0s 100s 0.01s

As can be seen from the menu, the undervoltage protection included within the P441, P442
and P444 relays consists of two independent stages. These are configurable as either
phase to phase or phase to neutral measuring within the V< Measur’t Mode cell.
Stage 1 may be selected as either IDMT, DT or disabled, within the V<1 Function cell.
Stage 2 is DT only and is enabled/disabled in the V<2 Status cell.
Two stages are included to provide both alarm and trip stages, where required.
Alternatively, different time settings may be required depending upon the severity of the
voltage dip.
The IDMT characteristic available on the first stage is defined by the following formula:
K
t=
1–M

Where:
K = Time Multiplier Setting (TMS)
T = Operating Time in Seconds
M = Measured Voltage / relay Setting Voltage (V<)
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 91/220

2.19.1 Setting Guidelines

In the majority of applications, undervoltage protection is not required to operate during
system earth fault conditions. If this is the case, the element should be selected in the menu
to operate from a phase to phase voltage measurement, as this quantity is less affected by
single phase voltage depressions due to earth faults.
The voltage threshold setting for the undervoltage protection should be set at some value
below the voltage excursions which may be expected under normal system operating
conditions. This threshold is dependent upon the system in question but typical healthy
system voltage excursions may be in the order of -10% of nominal value.
Similar comments apply with regard to a time setting for this element, i.e. the required time
delay is dependent upon the time for which the system is able to withstand a depressed
voltage.
2.20 Overvoltage protection
Undervoltage conditions may occur on a power system for a variety of reasons, some of
which are outlined below:-
• Under conditions of load rejection, the supply voltage will increase in magnitude. This
situation would normally be rectified by voltage regulating equipment such as AVRs or
on-load tap changers. However, failure of this equipment to bring the system voltage
back within prescribed limits leaves the system with an overvoltage condition which
must be cleared in order to preserve the life of the system insulation. Hence,
overvoltage protection which is suitably time delayed to allow for normal regulator
action, may be applied.

• During earth fault conditions on a power system there may be an increase in the
healthy phase voltages. Ideally, the system should be designed to withstand such
overvoltages for a defined period of time.
As previously stated, both the over and undervoltage protection functions can be found in the
relay menu “Volt Protection”. The following table shows the overvoltage section of this menu
along with the available setting ranges and factory defaults.

Menu text Default setting Setting range Step size

Min Max
Group 1
Volt protection
V> Measur't Mode Phase-Neutral Phase-phase or Phase-neutral
V>1 Function DT Disabled, DT pr IDMT
V>1 Voltage Set 75V 60V 185V 1V
V>1 Time Delay 10s 0s 100s 0.01s
V>1 TMS 1 0.5 100 0.5
V>2 Status Enabled Disabled or Enabled
V>2 Voltage Set 90V 60V 185V 1V
V>2 Time Delay 0.5s 0s 100s 0.01s

As can be seen, the setting cells for the overvoltage protection are identical to those
previously described for the undervoltage protection. The IDMT characteristic available on
the first stage is defined by the following formula:
t = K / (M - 1)
Where:
K = Time Multiplier Setting
T = Operating Time in Seconds
M = Measured Voltage / relay Setting Voltage (V>)
P44x/EN AP/E33 Application Notes

Page 92/220 MiCOM P441/P442 & P444

2.20.1 Setting Guidelines

The inclusion of the two stages and their respective operating characteristics allows for a
number of possible applications;

• Use of the IDMT characteristic gives the option of a longer time delay if the
overvoltage condition is only slight but results in a fast trip for a severe overvoltage. As
the voltage settings for both of the stages are independent, the second stage could
then be set lower than the first to provide a time delayed alarm stage if required.

• Alternatively, if preferred, both stages could be set to definite time and configured to
provide the required alarm and trip stages.

• If only one stage of overvoltage protection is required, or if the element is required to

provide an alarm only, the remaining stage may be disabled within the relay menu.
This type of protection must be co-ordinated with any other overvoltage relays at other
locations on the system. This should be carried out in a similar manner to that used for
grading current operated devices.
2.21 Circuit breaker fail protection (CBF)
Following inception of a fault one or more main protection devices will operate and issue a
trip output to the circuit breaker(s) associated with the faulted circuit. Operation of the circuit
breaker is essential to isolate the fault, and prevent damage / further damage to the power
system. For transmission/sub-transmission systems, slow fault clearance can also threaten
system stability. It is therefore common practice to install circuit breaker failure protection,
which monitors that the circuit breaker has opened within a reasonable time. If the fault
current has not been interrupted following a set time delay from circuit breaker trip initiation,
breaker failure protection (CBF) will operate.
CBF operation can be used to backtrip upstream circuit breakers to ensure that the fault is
isolated correctly. CBF operation can also reset all start output contacts, ensuring that any
blocks asserted on upstream protection are removed.
2.21.1 Breaker Failure Protection Configurations
The phase selection must be performed by creating dedicated PSL.
The circuit breaker failure protection incorporates two timers, ‘CB Fail 1 Timer’ and ‘CB Fail 2
Timer’, allowing configuration for the following scenarios:
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 93/220

Enable tBF1
CBF1_Status
& 0
tBF1 Trip 3Ph
Pulsed output latched in UI

>1
tBF1
Breaker
Any Internal Trip A
0
& 0
>1 Fail
1
Alarm
2
3 4 tBF2 - tBF1

S
Ia<
0
Q
tBF1 & 0
tBF2 Trip 3Ph

&
1
R
2 0
4
>1
3

0
1

2 S CBF2_Status Enable

Q
>1
3 4
Any Internal Trip A
& 0 R
Non Current Prot Trip 1

2
3 4
CBA_A
Setting:
Non I Trip
Reset:
0) I< Only
1) /Trip & I<
2) CB & I<
3) Disable
4) /Trip or I<

External Trip A 1

2
S
3 4 Q
R

Ia< 1
0
>1
&
2
3 4

Setting:
Ext. Trip
>1 Reset:
0) I< Only
1) /Trip & I<
2) CB & I<

CBA_A
& 3) Disable
4) /Trip or I<

Any Internal Trip B

Ib<
PHASE B
Non Current Prot Trip Same logic as A
CBA_B
phase
WI Trip A
External Trip B
WI Trip B

WI Trip C

V<1 Trip >1 Non Current Prot Trip

V<2 Trip
Any Internal Trip C
V>1 Trip
Ic< PHASE C
V>2 Trip
Non Current Prot Trip Same logic as A
phase
CBA_C

External Trip C P0552ENa

FIGURE 59 - CB FAIL GENERAL LOGIC

• Simple CBF, where only ‘CB Fail 1 Timer’ is enabled. For any protection trip, the ‘CB
Fail 1 Timer’ is started, and normally reset when the circuit breaker opens to isolate
the fault. If breaker opening is not detected, ‘CB Fail 1 Timer’ times out and closes an
output contact assigned to breaker fail (using the programmable scheme logic). This
contact is used to backtrip upstream switchgear, generally tripping all infeeds
connected to the same busbar section.

• A re-tripping scheme, plus delayed backtripping. Here, ‘CB Fail 1 Timer’ is used to
route a trip to a second trip circuit of the same circuit breaker. This requires
duplicated circuit breaker trip coils, and is known as re-tripping. Should re-tripping fail
to open the circuit breaker, a backtrip may be issued following an additional time
delay. The backtrip uses ‘CB Fail 2 Timer’, which is also started at the instant of the
initial protection element trip.
P44x/EN AP/E33 Application Notes

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CBF elements ‘CB Fail 1 Timer’ and ‘CB Fail 2 Timer’ can be configured to operate for trips
triggered by protection elements within the relay or via an external protection trip. The latter
is achieved by allocating one of the relay opto-isolated inputs to ‘External Trip’ using the
programmable scheme logic.
2.21.2 Reset Mechanisms for Breaker Fail Timers
It is common practice to use low set undercurrent elements in protection relays to indicate
that circuit breaker poles have interrupted the fault or load current, as required. This covers
the following situations:

• Where circuit breaker auxiliary contacts are defective, or cannot be relied upon to
definitely indicate that the breaker has tripped.

• Where a circuit breaker has started to open but has become jammed. This may result
in continued arcing at the primary contacts, with an additional arcing resistance in the
fault current path. Should this resistance severely limit fault current, the initiating
protection element may reset. Thus, reset of the element may not give a reliable
indication that the circuit breaker has opened fully.
For any protection function requiring current to operate, the relay uses operation of
undercurrent elements (I<) to detect that the necessary circuit breaker poles have tripped
and reset the CB fail timers. However, the undercurrent elements may not be reliable
methods of resetting circuit breaker fail in all applications. For example:

• Where non-current operated protection, such as under/overvoltage or

under/overfrequency, derives measurements from a line connected voltage
transformer. Here, I< only gives a reliable reset method if the protected circuit would
always have load current flowing. Detecting drop-off of the initiating protection
element might be a more reliable method. (in that case setting will be : "Prot. Reset or
I<")

• Where non-current operated protection, such as under/overvoltage or

under/overfrequency, derives measurements from a busbar connected voltage
transformer. Again using I< would rely upon the feeder normally being loaded. Also,
tripping the circuit breaker may not remove the initiating condition from the busbar,
and hence drop-off of the protection element may not occur. In such cases, the
position of the circuit breaker auxiliary contacts may give the best reset method.
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 95/220

Pole Live Pole Dead

+ + +
I< T
T

- - -

Pole Live Pole Dead

+ + +
I< T

- - -

P0553ENa

FIGURE 60 - ALGORITHM FOR POLE DEAD DETECTION

Description of open pole detection algorithm :
Each half period after zero crossing of current, the algorithm detects if the current is bigger
than the I< threshold. If yes, then the detection timer is restarted, if it is lower than the
adjusted value nothing is done.
At the end of the detection timer, open pole decision is given by the algorithm.
Timer value given by: (Number of Samples/2 + 2) * ((1/Freq)/Number of Samples)
With:
T = 13,3 ms (50 Hz) T = 11,1 ms (60 Hz)
The current used is the unfiltered current (only the analog lowPass )
Example:
In the first example, the current line is interrupted by the CB opening.
The detection is confirmed 3 ms after the pole is opened.
In the second example, some residual current remains due to the CT; The detection is
confirmed 12 / 15 msec after the pole is opened.
P44x/EN AP/E33 Application Notes

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2.21.2.1 Inputs

Data Type Description

CBF1_Status Configuration Breaker Failure 1 activated
CBF2_Status Configuration Breaker Failure 2 activated
CBF1_Timer Configuration Timer Breaker Failure 1
CBF2_Timer Configuration Timer Breaker Failure 2
CBF1_Reset Configuration Type of reset (current, CB status, interlocks).
CBF2_Reset Configuration Type of reset (current, CB Status, interlocks).
CBF_I< Configuration Dead Pole threshold detection
Any Trip A Internal Logic Trip phase A by internal or external protection
function
Any Trip B Internal Logic Trip phase B by internal or external protection
function
Any Trip C Internal Logic Trip phase C by internal or external protection
function
CB 52a_A Internal Logic CB Pole A opened
CB 52a_B Internal Logic CB Pole B opened
CB 52a_C Internal Logic CB Pole C opened
Ia<, Ib<, Ic< Internal Logic Under-current detection for dead pole

2.21.2.2 Outputs

Data Type Description

CBF1_Trip_3p Internal Logic Trip 3P CB fail by TBF1
CBF2_Trip_3p Internal Logic Trip 3P CB fail by TBF2
CB Fail Alarm Internal Logic CB Fail alarm

Resetting of the CBF is possible from a breaker open indication (from the relay’s pole dead
logic) or from a protection reset. In these cases resetting is only allowed provided the
undercurrent elements have also reset. The resetting options are summarised in the
following table.
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 97/220

Initiation CB fail timer reset mechanism

(Menu selectable)
Current based protection - The resetting mechanism is fixed.
(eg. 50/51/46/21/87..) [IA< operates] &
[IB< operates] &
[IC< operates] &
[IN< operates]
Non-current based protection Three options are available. The user can select from
(eg. 27/59/81/32L..) the following options.
[All I< and IN< elements operate]
[Protection element reset] AND [All I< and IN<
elements operate]
CB open (all 3 poles) AND [All I< and IN< elements
operate]
External protection - Three options are available. The user can select any or
all of the options.
[All I< and IN< elements operate]
[External trip reset] AND [All I< and IN< elements
operate]
CB open (all 3 poles) AND [All I< and IN< elements
operate]

The selection in the relay menu is grouped as follows:

Menu text Default setting Setting range Step size

Min Max
CB FAIL & I<
BREAKER FAIL
CB Fail 1 Status Enabled Enabled, Disabled
CB Fail 1 Timer 0.2s 0s 10s 0.01s
CB Fail 2 Status Disabled Enabled, Disabled
CB Fail 2 Timer 0.4s 0s 10s 0.01s
CBF Non I Reset CB Open & I< I< Only, CB Open & I<, Prot Reset & I<,
Prot Reset or I<, Disable
CBF Ext Reset CB Open & I< I< Only, CB Open & I<, Prot Reset & I<,
Prot Reset or I<, Disable
UNDER CURRENT
I< Current Set 0.05In 0.05In 3.2In 0.01In

The ‘CBF Blocks I>‘ and ‘CBF Blocks IN>‘ settings are used to remove starts issued from the
overcurrent and earth elements respectively following a breaker fail time out. The start is
removed when the cell is set to Enabled.
P44x/EN AP/E33 Application Notes

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2.21.3 Typical settings

2.21.3.1 Breaker Fail Timer Settings
Typical timer settings to use are as follows:

CB Fail Reset Mechanism tBF time delay Typical delay for 2½ cycle
circuit breaker
Initiating element reset CB interrupting time + element 50 + 50 + 10 + 50
reset time (max.) + error in tBF = 160 ms
timer + safety margin
CB open CB auxiliary contacts 50 + 10 + 50
opening/closing time (max.) + = 110 ms
error in tBF timer + safety
margin
Undercurrent elements CB interrupting time + 50 + 25 + 50
undercurrent element operating = 125 ms
time (max.) + safety margin

Note that all CB Fail resetting involves the operation of the undercurrent elements. Where
element reset or CB open resetting is used the undercurrent time setting should still be used
if this proves to be the worst case.
The examples above consider direct tripping of a 2½ cycle circuit breaker. Note that where
auxiliary tripping relays are used, an additional 10-15 ms must be added to allow for trip
relay operation.
2.21.3.2 Breaker Fail Undercurrent Settings
The phase undercurrent settings (I<) must be set less than load current, to ensure that I<
operation indicates that the circuit breaker pole is open. A typical setting for overhead line or
cable circuits is 20% In, with 5% In common for generator circuit breaker CBF.
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 99/220

3. OTHER PROTECTION CONSIDERATIONS-SETTINGS EXAMPLE

3.1 Distance Protection Setting Example
3.1.1 Objective
To protect the 100Km double circuit line between Green Valley and Blue River substations
using relay protection in the POP Z2 Permissive Overreach mode and to set the relay at
Green Valley substation, shown in Figure 61.

Tiger Bay Green valley

Blue River Rocky bay

80 Km
100 Km 60 Km

System Data
Green Valley - Blue River transmission line 21 21
System voltage 230kv
System grounding solid
CT ratio 1200/5
VT ratio 230000/115
Line length 100km
Line impedance
Z1 = 0.089 + J0.476 OHM/km
Z0 = 0.426 + J1.576 OHM/km
Faults levels
Green Valley substation busbars maximum 5000MVA, minimum 2000MVA
Blue River substation busbars maximum 3000MVA, minimum 1000MVA P3074ENa

FIGURE 61 - SYSTEM ASSUMED FOR WORKED EXAMPLE

3.1.2 System Data
Line length: 100Km

Line impedances: Z = 0.089 + j0.476 = 0.484 / 79.4° Ω/km

1

Z = 0.426 + j1.576 = 1.632 / 74.8° Ω/km

0

Z /Z1 = 3.372 / -4.6°

0
CT ratio: 1 200 / 5
VT ratio: 230 000 / 115
3.1.3 Relay Settings
It is assumed that Zone 1 Extension is not used and that only three forward zones are
required. Settings on the relay can be performed in primary or secondary quantities and
impedances can be expressed as either polar or rectangular quantities (menu selectable).
For the purposes of this example, secondary quantities are used.
3.1.4 Line Impedance
1200 / 5
Ratio of secondary to primary impedance = = 0.12
230000 / 115

Line impedance secondary = ratio CT/VT x line impedance primary.

Line Impedance = 100 x 0.484 / 79.4° (primary) x 0.12

= 5.81 / 79.4° Ω secondary.

Relay Line Angle settings -90° to 90° in 1° steps. Therefore, select Line Angle = 80° for
convenience.

Therefore set Line Impedance and Line Angle: = 5.81 / 80° Ω secondary.
P44x/EN AP/E33 Application Notes

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3.1.5 Zone 1 Phase Reach Settings

Required Zone 1 reach is to be 80% of the line impedance between Green Valley and Blue
River substations.

Required Zone 1 reach = 0.8 x 100 x 0.484 / 79.4° x 0.12

Z1 = 4.64 / 79.4° Ω secondary.

Z2 = 100 x 0.484 / 79.4° + 50% x 60 x 0.484 / 79.4°

The Line Angle = 80°.

Therefore actual Zone 1 reach, Z1 = 4.64 / 80° Ω secondary.

3.1.6 Zone 2 Phase Reach Settings
Required Zone 2 impedance =
(Green Valley-Blue River) line impedance + 50% (Blue River-Rocky Bay) line impedance

Z2 = (100+30) x 0.484 / 79.4° x 0.12

= 7.56 / 79.4° Ω secondary.

The Line Angle = 80°.

Actual Zone 2 reach setting = 7.56 / 80° Ω secondary

3.1.7 Zone 3 Phase Reach Settings
Required Zone 3 forward reach =
(Green Valley-Blue River + Blue River-Rocky Bay) x 1.2

= (100+60) x 1.2 x 0.484 / 79.4° x 0.12

Z3 = 11.15 / 79.4° ohms secondary

Actual Zone 3 forward reach setting = 11.16 / 80° ohms secondary

3.1.8 Zone 4 Reverse Settings with no Weak Infeed Logic Selected
Required Zone 4 reverse reach impedance = Typically 10% Zone 1 reach

= 0.1 x 4.64 / 79.4°

Z4 = 0.464 / 79.4°

Actual Zone 4 reverse reach setting = 0.46 / 80° ohms secondary

3.1.9 Zone 4 Reverse Settings with Weak Infeed Logic Selected
Where zone 4 is used to provide reverse directional decisions for Blocking or Permissive
Overreach schemes, zone 4 must reach further behind the relay than zone 2 for the remote
relay. This can be achieved by setting: Z4 ≥ ((Remote zone 2 reach) x 120%) minus the
protected line impedance:
Remote Zone 2 reach =
(Blue River-Green Valley) line impedance + 50% (Green Valley-Tiger Bay) line impedance

= (100+40) x 0.484 / 79.4° x 0.12

= 8.13 / 79.4° Ω secondary.

Z4 ≥ ((8.13 / 79.4°) x 120%) - (5.81 / 79.4°)

= 3.95 / 79.4°

Minimum zone 4 reverse reach setting = 3.96 / 80° ohms secondary

Application Notes P44x/EN AP/E33

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3.1.10 Residual Compensation for Earth Fault Elements

The residual compensation factor can be applied independently to certain zones if required.
This feature is useful where line impedance characteristics change between sections or
where hybrid circuits are used. In this example, the line impedance characteristics do not
change and as such a common KZ0 factor can be applied to each zone. This is set as a
ratio “kZ0 Res. Comp”, and an angle “kZ0 Angle”:

kZ0 Res. Comp, kZ0 = (Z0 - Z1) / 3.Z1 Ie: As a ratio.

kZ0 Angle, ∠kZ0 = ∠ (Z0 - Z1) / 3.Z1 Set in degrees.

Z -Z = (0.426 + j1.576) - (0.089 + j0.476)
L0 L1
= 0.337 + j1.1

= 1.15 / 72.9°
1.15 / 72.9°
kZ0 = = 0.79 / –6.5°
3 × 0.484 / 79.4°

Therefore, select:
kZ0 Res. Comp = 0.79 (Set for kZ1, kZ2, kZp, kZ4).
kZ0 Angle = –6.5° (Set for kZ1, kZ2, kZp, kZ4).
3.1.11 Resistive Reach Calculations
All distance elements must avoid the heaviest system loading. Taking the 5A CT secondary
rating as a guide to the maximum load current, the minimum load impedance presented to
the relay would be:

Vn (phase-neutral) / In = (115 / √3) / 5 = 13.3 Ω (secondary)

Typically, phase fault distance zones would avoid the minimum load impedance by a margin
of ≥40% if possible (bearing in mind that the power swing characteristic surrounds the
tripping zones), earth fault zones would use a ≥20% margin. This allows maximum resistive
reaches of 7.9Ω, and 10.6Ω, respectively.

From Table 1 (see §2.4.4), taking a required primary resistive coverage of 14.5Ω for phase
faults, and assuming a typical earth fault coverage of 40Ω, the minimum secondary reaches
become:

RPh (min) = 14.5 x 0.12 = 1.74Ω (secondary);

RG (min) = 40 x 0.12 = 4.8Ω (secondary).

Resistive reaches could be chosen between the calculated values as shown in Table 10.
The zone 2 elements satisfy R2Ph ≤ (R3Ph x 80%), and R2G ≤ (R3G x 80%).

Minimum Maximum Zone 1 Zone 2 Zones 3 & 4

Phase (RPh) Ω 1.74 7.9 R1Ph = 3 R1Ph = 4 R3Ph-4Ph = 8
Earth (RG) Ω 4.8 10.6 R1G = 5 R1G = 6 R3G-4G = 10

TABLE 10 - SELECTION OF RESISTIVE REACHES

R3Ph-R4Ph should be set ≤ 80% Z minimum load – ∆R.

P44x/EN AP/E33 Application Notes

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3.1.12 Power Swing Band

Typically, the ∆R and ∆X band settings are both set between 10 - 30% of R3Ph. This gives
a secondary impedance between 0.6 and 1.8Ω. For convenience, 1.0Ω could be set.
The width of the power swing band is calculated as follows:

∆R = 1.3 × tan(π × ∆f × ∆t) × RLOAD

Assuming that the load corresponds to 60° angles between sources and if the resistive reach
is set so that Rlim = RLOAD/2, the following is obtained:

∆R = 0.032 × ∆f × RLOAD
To ensure that a power swing frequency of 5 Hz is detected, the following is obtained:

∆R = 0.16 × RLOAD
Where:

∆R width of the power swing detection band

∆f power swing frequency (fA – fB)

Rlim resistive reach of the starting characteristic (=R3ph-R4ph)
Z network impedance corresponding to the sum of the reverse (Z4) and
forward (Z3) impedances
RLOAD load resistance
3.1.13 Current Reversal Guard
The current reversal guard timer available with POP schemes needs a non-zero setting
when the reach of the zone 2 elements is greater than 1.5 times the impedance of the
protected line. In this example, their reach is only 1.3 times the protected line impedance.
Therefore, current reversal guard logic does not need to be used and the recommended
settings for scheme timers are:
tREVERSAL GUARD = 0
Tp = 98ms (typical).
3.1.14 Instantaneous Overcurrent Protection
To provide parallel high-speed fault clearance to the distance protection, it is possible to use
the I>3 element as an instantaneous highset. It must be ensured that the element will only
respond to faults on the protected line. The worst case scenario for this is when only one of
the parallel lines is in service.
Two cases must be considered. The first case is a fault at Blue River substation with the
relay seeing fault current contribution via Green Valley. The second case is a fault at Green
Valley with the relay seeing fault current contribution via Blue River.
Case 1:

Source Impedance = 2302 / 5000 = 10.58Ω

Line Impedance = 48.4Ω

Fault current seen by relay = (230000 / √3) / (10.58 + 48.4)

= 2251A
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 103/220

Case 2:

Source Impedance = 2302 / 3000 = 17.63Ω

Line Impedance = 48.4Ω

Fault current seen by relay = (230000 / √3) / (17.63 + 48.4)

= 2011A
The overcurrent setting must be in excess of 2251A. To provide an adequate safety margin
a setting ≥120% the minimum calculated should be chosen, say 2800A.
3.2 Teed feeder protection
The application of distance relays to three terminal lines is fairly common. However, several
problems arise when applying distance protection to three terminal lines.
3.2.1 The Apparent Impedance Seen by the Distance Elements
Figure 62 shows a typical three terminal line arrangement. For a fault at the busbars of
terminal B the impedance seen by a relay at terminal A will be equal to :
Za = Zat + Zbt + [ Zbt.(Ic/Ia) ]
Relay A will underreach for faults beyond the tee-point with infeed from terminal C. When
terminal C is a relatively strong source, the underreaching effect can be substantial. For a
zone 2 element set to 120% of the protected line, this effect may result in non-operation of
the element for internal faults. This not only effects time delayed zone 2 tripping but also
channel-aided schemes. Where infeed is present, it will be necessary for Zone 2 elements
at all line terminals to overreach both remote terminals with allowance for the effect of tee-
point infeed. Zone 1 elements must be set to underreach the true impedance to the nearest
terminal without infeed. Both these requirements can be met through use of the alternative
setting groups in the P441, P442 and P444 relays.

A Ia Ib B

Zat Zbt

Ic

Zct

C
Va = Ia Zat + Ib Zbt Impedance seen by relay A = Va
Ia
Ib = Ia + Ic Za = Zat + Zbt + Ic Zbt
Ia
Va = Ia Zat + Ia Zbt + Ic Zbt
P3075ENa

FIGURE 62 - TEED FEEDER APPLICATION - APPARENT IMPEDANCES SEEN BY RELAY

3.2.2 Permissive Overreach Schemes
To ensure operation for internal faults in a POP scheme, the relays at the three terminals
should be able to see a fault at any point within the protected feeder. This may demand very
large zone 2 reach settings to deal with the apparent impedances seen by the relays.
A POP scheme requires the use of two signalling channels. A permissive trip can only be
issued upon operation of zone 2 and receipt of a signal from both remote line ends. The
requirement for an 'AND' function of received signals must be realised through use of contact
logic external to the relay, or the internal Programmable Scheme Logic. Although a POP
scheme can be applied to a three terminal line, the signalling requirements make its use
unattractive.
P44x/EN AP/E33 Application Notes

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3.2.3 Permissive Underreach Schemes

For a PUP scheme, the signalling channel is only keyed for internal faults. Permissive
tripping is allowed for operation of zone 2 plus receipt of a signal from either remote line end.
This makes the signalling channel requirements for a PUP scheme less demanding than for
a POP scheme. A common power line carrier (PLC) signalling channel or a triangulated
signalling arrangement can be used. This makes the use of a PUP scheme for a teed feeder
a more attractive alternative than use of a POP scheme.
The channel is keyed from operation of zone 1 tripping elements. Provided at least one
zone 1 element can see an internal fault then aided tripping will occur at the other terminals if
the overreaching zone 2 setting requirement has been met. There are however two cases
where this is not possible:
Figure 63 (i) shows the case where a short tee is connected close to another terminal. In
this case, zone 1 elements set to 80% of the shortest relative feeder length do not overlap.
This leaves a section not covered by any zone 1 element. Any fault in this section would
result in zone 2 time delayed tripping.
Figure 63 (ii) shows an example where terminal 'C' has no infeed. Faults close to this
terminal will not operate the relay at 'C' and hence the fault will be cleared by the zone 2
time-delayed elements of the relays at 'A' and 'B'.
Figure 63 (iii) illustrates a further difficulty for a PUP scheme. In this example current is
outfeed from terminal 'C' for an internal fault. The relay at 'C' will therefore see the fault as
reverse and not operate until the breaker at 'B' has opened; i.e. sequential tripping will occur.

(i) A B

Z1A Z1C
= area where no zone 1 overlap exists

C
(ii) A B

Z1A Z1B

Fault Fault seen by A & B in zone 2

C
No infeed

(iii) A B

Relay at C sees reverse fault until B opens

P3076ENa

FIGURE 63 - TEED FEEDER APPLICATIONS

Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 105/220

3.2.4 Blocking Schemes

Blocking schemes are particularly suited to the protection of teed feeders, since high speed
operation can be achieved where there is no current infeed from one or more terminals. The
scheme also has the advantage that only a common simplex channel or a triangulated
simplex channel is required.
The major disadvantage of blocking schemes is highlighted in Figure 63 (iii) where fault
current is outfeed from a terminal for an internal fault condition. relay 'C' sees a reverse fault
condition. This results in a blocking signal being sent to the two remote line ends, preventing
tripping until the normal zone 2 time delay has expired.
3.3 Alternative setting groups
The P441, P442 and P444 relays can store up to four independent groups of settings. The
active group is selected either locally via the menu or remotely via the serial
communications. The ability to quickly reconfigure the relay to a new setting group may be
desirable if changes to the system configuration demand new protection settings. Typical
examples where this feature can be used include:
Single bus installations with a transfer bus;
Double bus installations, with or without a separate transfer bus, where the transfer circuit
breaker or bus coupler might be used to take up the duties of any feeder circuit breaker
when both the feeder circuit breaker and the current transformers are by-passed.
In the case of a double bus installation, it is usual for bus 1 to be referred to as the main bus
and bus 2 as the reserve bus, and for any bypass circuit isolator to be connected to bus 2 as
shown in Figure 64. This arrangement avoids the need for a current polarity reversing switch
that would be required if both buses were to be used for by-pass purposes. The standby
relay, associated with the transfer circuit breaker or the bus coupler, can be programmed
with the individual setting required for each of the outgoing feeders. For bypass operation
the appropriate setting group can be selected as required. This facility is extremely useful in
the case of unattended substations where all of the switching can be controlled remotely.

Main bus (1)

Reserve bus (2)

21

P440
21 21

Feeder 1 Feeder 2
P3077ENa

FIGURE 64 - TYPICAL DOUBLE BUS INSTALLATION WITH BYPASS FACILITIES

A further use for this feature is the ability to provide alternative settings for teed feeders or
double circuit lines with mutual coupling. Similar alternative settings could be required to
cover different operating criteria in the event of the channel failing, or an alternative system
configuration (ie. lines being switched in or out).
P44x/EN AP/E33 Application Notes

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3.3.1 Selection of Setting Groups

Setting groups can be changed by one of two methods selectable by MiCOM S1:

• Automatic group selection by changes in state of two opto-isolated inputs, assigned as

Setting Group Change bit 0 (opto 1), and Setting Group Change bit 1 (opto 2), as
shown in Table 11 below. The new setting group binary code must be maintained for
2 seconds before a group change is implemented, thus rejecting spurious induced
interference.(See also hysteresis value for level logic 0 & level logic 1 in section 6.1 of
this chapter).
When this selection is chosen, the two opto-isolated inputs assigned to this function
will be opto inputs 1 and 2 and they must not be connected to any output signal
in the PSL. Special care should be take into account to avoid use them for another
purpose (i.e in the default PSL they have been used for another functions: DIST/DEF
Chan. Recv. For opto 1 and DIST/DEF carrier out of service).

• Default PSL: To enable the setting group via binary inpputs, the opto input 1 and 2
must be removed from the PSL.
(If assigned in the PSL, instead of Dist DEF Carrier Receive Logic Start, a setting
group change will occur)

Note that each setting group has its own dedicated PSL, which should be configured and
sent to the relay independently)
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 107/220

• Or using the relay operator interface / remote communications. Should the user issue
a menu command to change group, the relay will transfer to that settings group, and
then ignore future changes in state of the bit 0 and bit 1 opto-inputs. Thus, the user is
given greater priority than automatic setting group selection.

Binary State of SG Change bit 1 Binary State of SG Change bit 0 Setting Group
Activated
Opto 2 Opto 1
0 0 1
0 1 2
1 0 3
1 1 4

TABLE 11 - SETTING GROUP SELECTION

REMINDER : IF SELECTED IN THE MENU (CHANGEMENT GROUPS BY OPTOS),
OPTO 1 & 2 MUST BE REMOVED FROM THE PSL (THEY ARE
DEDICATED FOR GROUPS SELECTION ONLY)
P44x/EN AP/E33 Application Notes

Page 108/220 MiCOM P441/P442 & P444

4. APPLICATION OF NON-PROTECTION FUNCTIONS

4.1 Fault locator
The relay has an integral fault locator that uses information from the current and voltage
inputs to provide a distance to fault measurement. The sampled data from the analogue
input circuits is written to a cyclic buffer until a fault condition is detected. The data in the
input buffer is then held to allow the fault calculation to be made. When the fault calculation
is complete the fault location information is available in the relay fault record.
When calculated the fault location can be found in the fault record under the
VIEW RECORDS column in the Fault Location cells. Distance to fault is available in km,
miles, impedance or percentage of line length. The fault locator can store data for up to five
faults. This ensures that fault location can be calculated for all shots on a typical multiple
reclose sequence, whilst also retaining data for at least the previous fault.

FIGURE 65 - FAULT LOCATION INFORMATION INCLUDED IN AN EVENT:

Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 109/220

The following table shows the relay menu for the fault locator, including the available setting
ranges and factory defaults:-

Menu text Default setting Setting range Step size

Min Max
GROUP 1
DISTANCE ELEMENTS
LINE SETTING
Line Length 1000 km 0.3 km 1000 km 0.015 km
(625 miles) (0.2 mile) (625 miles) (0.005 mile)
Line Impedance 12 / In Ω 0.001 / In Ω 500 / In Ω 0.001 / In Ω
Line Angle 70° –90° +90° 0.1°

FAULT LOCATOR
kZm Mutual Comp 0 0 7 0.01
kZm Angle 0° 0° +360° 1°

4.1.1 Mutual Coupling

When applied to parallel circuits mutual flux coupling can alter the impedance seen by the
fault locator. The coupling will contain positive, negative and zero sequence components. In
practice the positive and negative sequence coupling is insignificant. The effect on the fault
locator of the zero sequence mutual coupling can be eliminated by using the mutual
compensation feature provided. This requires that the residual current on the parallel line is
measured, as shown in Appendix B. It is extremely important that the polarity of connection
for the mutual CT input is correct, as shown.
4.1.2 Setting Guidelines
The system assumed for the distance protection worked example will be used here, refer to
section 3.1. The Green Valley – Blue River line is considered.
Line length: 100Km
CT ratio: 1 200 / 5
VT ratio: 230 000 / 115

Line impedances: Z = 0.089 + j0.476 = 0.484 / 79.4° Ω/km

1

ZM = 0.107 + j0.571 = 0.581 / 79.4° Ω/km (Mutual)

0
1200 / 5
Ratio of secondary to primary impedance = = 0.12
230000 / 115

Line Impedance = 100 x 0.484 / 79.4° x 0.12

= 5.81 / 79.4° Ω secondary.

Relay Line Angle settings 0° to 360° in 1° steps. Therefore, select Line Angle = 80° for
convenience.
P44x/EN AP/E33 Application Notes

Page 110/220 MiCOM P441/P442 & P444

Therefore set Line Impedance and Line Angle: = 5.81 / 80° Ω (secondary).
No residual compensation needs to be set for the fault locator, as the relay automatically
uses the kZ0 factor applicable to the distance zone which tripped.
Should a CT residual input be available for the parallel line, mutual compensation could be
set as follows:

kZm Mutual Comp, kZm = ZM0 / 3.Z1 Ie: As a ratio.

kZm Angle, ∠kZm = ∠ ZM0 / 3.Z1 Set in degrees.

The CT ratio for the mutual compensation may be different from the Line CT ratio. However,
for this example we will assume that they are identical.

kZm = ZM0 / 3.Z1 = 0.581 / 79.4° / (3 x 0.484 / 79.4°)

= 0.40 / 0°
Therefore set kZm Mutual Comp = 0.40

kZm Angle = 0°
4.2 Voltage transformer supervision (VTS) – Main VT for minZ measurement
4.2.1 VTS logic description
The voltage transformer supervision (VTS) feature is used to detect failure of the analog ac
voltage inputs to the relay. This may be caused by internal voltage transformer faults,
overloading, or faults on the interconnecting wiring to relays. This usually results in one or
more VT fuses blowing. Following a failure of the ac voltage input there would be a
misrepresentation of the phase voltages on the power system, as measured by the relay,
which may result in maloperation of the distance element.
The VTS logic in the relay is designed to detect the voltage failure (with internal thresholds or
external opto input), and automatically adjust the configuration of protection elements
(Distance element is blocked but may be unblocked on I1,I2 or I0 conditions in case of fault
during VTS conditions) whose stability would otherwise be compromised (Distance, DEF,
Weak infeed, Directionnal phase current& all directional elements used in the internal logic).
A settable time-delayed alarm output is also available (min1sec to Max 20sec).
The condition of this alarm is given by:

FFUS_Confirmed = (Fuse_Failure And VTS Timer) Or INP_FFUS_Line

INP_F.Failure_Line
VN >F.Failure

I2 >F.Failure
&
≥1
VTS Time
I0 >F.Failure ≥1 delay

S
I >F.Failure Q FFUS_Confirmed
R

∆I>F.Failure Fuse_Failure

Any_pole_dead S
& R
Q
Healthy network
V<F.Failure
≥1
All Pole Dead

P0530ENa

FIGURE 66 - VTS LOGIC

(SEE ALSO DDB DESCRIPTION IN THE END OF THAT SECTION)
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 111/220

FIGURE 67 - VT SUPERVISION: VTS SETTINGS IN MiCOM S1

• VTS Timer: A settable alarm from 1 to 20s by step of 1s gives the possibility to signal
by an alarm the Failure. This alarm is instantaneous in case of opto energized by
external INP FFU signal (issued from contact of MCB). During no load, the timer
covers the duration of Dead time1 HSAR cycle (Vo&/IO in case of no load) which
could be detected as VT failure 1 pole.

• INP_FFUS Line :The external information given by the MCB to the opto input is
secure and will block instantaneously the distance function and the functions which
are use directional element.

FIGURE 68 - DEFAULT PSL EXTRACTED

Where a miniature circuit breaker (MCB) is used to protect the voltage transformer ac output
circuits, it is common to use MCB auxiliary contacts to indicate a three phase output
disconnection. As previously described, it is possible for the VTS logic to operate correctly
without this input. However, this facility has been provided for compatibility with various
utilities current practices. Energising an opto-isolated input assigned to “MCB Open” on the
relay will therefore provide the necessary block.
Fuse failure conditions are confirmed instantaneously if the opto input "INP_FFus line" is
energised and assigned in PSL, or after elapse of the VTS Time delay in case of 1, 2 or 3
phases Fuse Failure.
The confirmed Fuse Failure blocks all protection functions which use the voltage
measurement (Distance, Weak infeed, Directional overcurrent,…). The directional
overcurrent element may be blocked or set to become non directional with dedicated timer
(Time VTS in MiCOM S1)- I>1 or IN>1.
A non confirmed Fuse Failure will be a detection of an internal fuse failure before the timer is
issued. In that case a fault can be detected by the I2>,I0>,I1>, ∆I> criteria and will force the
unblocking functions:
Distance Protection
DEF Protection
Weak-infeed Protection
I> Directional
U>, U<
P44x/EN AP/E33 Application Notes

Page 112/220 MiCOM P441/P442 & P444

4.2.2 The internal detection FUSE Failure condition

Is verified by follows (Fuse Failure not confirmed logic)

(Vr AND /I0 AND /l2 Et /I>) OR (FusFus_tri AND /Any_pole_dead AND V< AND /∆Ι )
Vr>_FFUS : The residual voltage is bigger than a fixed threshold := 0,75Vn
I0>_FFUS : The zero sequence current is bigger than a settable threshold :
From 0.01 to 1.00 In by step of 0.01
I2>_FFUS : The negative sequence current is bigger than a settable threshold
identical to the I0 threshold.
I>_FFUS : The direct current is bigger than a fixed threshold equal to 2,5IN.
V<_FFUS : All the voltages are lower than a settable threshold from 0.05 à 1
Un by step of 0.1

∆Ι>_FFUS : The line currents have a variation bigger than a settable value from
0.01 to 0.5 In by step of 0.01 In
FuseFailure_3P : Parameter in MiCOM S1 which allows the FFU tri pole detection
Any pole dead : Cycle in progress.

• The I0 criteria (zero sequence current threshold) gives the possibility to UNBLOCK the
distance protection in case of phase to ground fault (if the fuse failure has not been yet
confirmed).

• The I2 criteria (negative sequence current threshold) gives the possibility to

UNBLOCK the distance protection in case of insulated phase to phase fault (if the fuse
failure has not been yet confirmed).

• The criteria (V< AND /∆Ι) gives the possibility to detect the 3Poles Fuse Failure(No
more phase voltage and no variation of current) (no specific logic about line
energisation).
4.2.3 Fuse Failure Alarm reset
In case of Fuse Failure confirmed, the condition which manages the Reset are given by :

Fusion_Fusible = 0
And
INP_FFUS_Line = 0
And
/All Pole Dead Or Healthy Network

• All Pole Dead: No current AND no voltage OR CB Opened ((52a) if assigned in PSL)

UN . V0 . I0 . CVMR (convergence) . PSWING

• Healthy Network:
Rated Line voltage AND
No V0 and No I0 AND
No start element AND
No Power Swing
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 113/220

There are three main aspects to consider regarding the failure of the VT supply. These are
defined below:
1. Loss of one or two phase voltages
2. Loss of all three phase voltages under load conditions
3. Absence of three phase voltages upon line energisation
4.2.4 Loss of One or Two Phase Voltages
The VTS feature within the relay operates on detection of residual voltage without the
presence of zero and negative phase sequence current, and earth fault current (ΣIph). This
gives operation for the loss of one or two phase voltages. Stability of the VTS function is
assured during system fault conditions, by the presence of I0 and/or I2 current. Also, VTS
operation is blocked (and distance element unblocked) when any phase current exceeds 2.5
x In.
Zero Sequence VTS Element:
The thresholds used by the element are:

• Fixed operate threshold: VN ≥ 0.75 x Vn;

• Blocking current thresholds, I0 = I2 = 0 to 1 x In; settable (defaulted to

0.05In),
and Iph = 2.5 x In.
4.2.5 Loss of All Three Phase Voltages Under Load Conditions
Under the loss of all three phase voltages to the relay, there will be no zero phase sequence
quantities present to operate the VTS function. However, under such circumstances, a
collapse of the three phase voltages will occur. If this is detected without a corresponding
change in any of the phase current signals (which would be indicative of a fault), then a VTS
condition will be raised. In practice, the relay detects the presence of superimposed current
signals, which are changes in the current applied to the relay. These signals are generated
by comparison of the present value of the current with that exactly one cycle previously.
Under normal load conditions, the value of superimposed current should therefore be zero.
Under a fault condition a superimposed current signal will be generated which will prevent
operation of the VTS.
The phase voltage level detectors is settable (default value is adjusted at 30V / setting
range : min:10V to Max:70V).
The sensitivity of the superimposed current elements is settable and default value is
adjusted at 0.1In (setting range : 0,01In to 5In).

4.2.6 Absence of Three Phase Voltages Upon Line Energisation

If a VT were inadvertently left isolated prior to line energisation, incorrect operation of voltage
dependent elements could result. The previous VTS element detected three phase VT
failure by absence of all 3 phase voltages with no corresponding change in current. On line
energisation there will, however, be a change in current (as a result of load or line charging
current for example). An alternative method of detecting 3 phase VT failure is therefore
required on line energisation: in that case the SOTF logic is applied.
P44x/EN AP/E33 Application Notes

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4.2.7 Menu Settings

The VTS settings are found in the ‘SUPERVISION’ column of the relay menu. The relevant
settings are detailed below.

Menu text Default setting Setting range Step size

Min Max
GROUP 1
SUPERVISION
VT Supervision
VTS Time Delay 5s 1s 20s 1s
VTS I2> & I0> Inhibit 0.05 x In 0 1 x In 0.01 x In
Detect 3P Disabled Enabled
Disabled
Threshold 3P 30V 10V 70V 1V
Delta I> 0.1×In 0.01×In 5×In 0.01×In

The relay responds as follows, on operation of any VTS element:

• VTS alarm indication (delayed by the set Time Delay);

• Instantaneous blocking of distance protection elements (if opto used); and others
protection functions using voltage measurement

• Dedirectionalising of directionalised overcurrent elements with new time delays “I>

VTS”.(if selected)
The VTS block is latched after a user settable time delay ‘VTS Time Delay’. Once the signal
has latched then two methods of resetting are available. (See Reset logic description in
section 4.2.3).
If not blocked the time delay associated can be modified as well (Time VTS):
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 115/220

4.2.8 INPUT / OUTPUT used in VTS logic:

4.2.8.1 Inputs

MCB/VTS Line
The DDB:MCB/VTS Line if linked to an opto in the PSL and when energized, informs the
P44X about an internal maloperation from the VT used for the impedance measurement
reference. (Line in this case means Main VT ref measurement / even if the main VT is on the
bus side and the Synchro VT is on the line side).

MCB/VTS Bus
The DDB:MCB/VTS Bus if linked to an opto in the PSL and when energized, informs the
P44X about an internal maloperation from the VT used for synchrocheck control (See
CheckSync logic in section 4.4).
4.2.8.2 Outputs

VTS Fast
Set high for internal FFAilure detection made with internal logic.

VTS Fail Alarm

Set high Set highwhen Opto energised (copy of MCB) OR internal FFAilure confirmed at the
end of VTS timer.

Any Pole Dead

The DDB Any Pole Dead if linked in the PSL, indicates that one or more poles is opened.

All Pole Dead

The DDB All Pole Dead if linked in the PSL, indicates all pole are dead (The 3 poles are
open).
4.3 Current Transformer Supervision (CTS)
The current transformer supervision feature is used to detect failure of one or more of the ac
phase current inputs to the relay. Failure of a phase CT or an open circuit of the
interconnecting wiring can result in incorrect operation of any current operated element.
Additionally, interruption in the ac current circuits risks dangerous CT secondary voltages
being generated.
4.3.1 The CT Supervision Feature
The CT supervision feature operates on detection of derived zero sequence current, in the
absence of corresponding derived zero sequence voltage that would normally accompany it.
The voltage transformer connection used must be able to refer zero sequence voltages from
the primary to the secondary side. Thus, this element should only be enabled where the VT
is of five limb construction, or comprises three single phase units, and has the primary star
point earthed.
Operation of the element will produce a time-delayed alarm visible on the LCD and event
record (plus DDB 125: CT Fail Alarm), with an instantaneous block for inhibition of protection
elements. Protection elements operating from derived quantities (Broken Conductor, Earth
Fault, Neg Seq O/C) are always blocked on operation of the CT supervision element.
The following table shows the relay menu for the CT Supervision element, including the
available setting ranges and factory defaults:-
P44x/EN AP/E33 Application Notes

Page 116/220 MiCOM P441/P442 & P444

Menu text Default setting Setting range step size

Min max
GROUP 1
SUPERVISION
CT SUPERVISION
CTS Status Disabled Enabled/Disabled N/A
CTS VN< Inhibit 1 0.5 / 2V 22 / 88V 0.5 / 2V
CTS IN> Set 0.1 0.08 x In 4 x In 0.01 x In
CTS Time Delay 5 0s 10s 1s

4.3.2 Setting the CT Supervision Element

Ir>

Temporisation
& 0<->10sec

Vr<

Calulation Part Logical Part

P0554ENa

The residual voltage setting, CTS VN< Inhibit and the residual current setting, CTS IN> set,
should be set to avoid unwanted operation during healthy system conditions. For example
CTS VN< Inhibit should be set to 120% of the maximum steady state residual voltage. The
CTS IN> set will typically be set below minimum load current. The time-delayed alarm,
CTS Time Delay, is generally set to 5 seconds.
Where the magnitude of residual voltage during an earth fault is unpredictable, the element
be disabled to prevent a protection elements being blocked during fault conditions.
4.3.2.1 Inputs/outputs in CTS logic:

CT Fail Alarm
The DDB cell indicates a CT Fail detected after timer is issued
4.4 Check synchronisation
The check synchronism option is used to qualify reclosure of the circuit breaker so that it can
only occur when the network conditions on the busbar and line side of the open circuit
breaker are acceptable. If a circuit breaker were closed when the two system voltages were
out of synchronism with one another, i.e. a difference in voltage magnitudes or phase angles
existed, the system would be subjected to an unacceptable ‘shock’, resulting in loss of
stability and possible damage to connected machines.
Check synchronising therefore involves monitoring the voltage on both sides of a circuit
breaker and, if both sides are ‘live’, the relative synchronism between the two supplies. Such
checking may be required to be applied for both automatic and manual reclosing of the
circuit breaker and the system conditions which are acceptable may be different in each
case. For this reason, separate check synchronism settings are included within the relay for
both manual and automatic reclosure of the circuit breaker. With manual closure, the CB
close signal is applied into the logic as a pulse to ensure that an operator cannot simply keep
the close signal applied and wait for the system to come into synchronism. This is often
referred to as guard logic and requires the close signal to be released and then re-applied if
the closure is unsuccessful.
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 117/220

The check synchronising element provides two ‘output’ signals which feed into the manual
CB control and the auto reclose logic respectively. These signals allow reclosure provided
that the relevant check-synch criteria are fulfilled.

Note that if check-synchronising is disabled, the DDB: signal is

automatically asserted and becomes invariant (logical status always forced at 1).
For an interconnected power system, tripping of one line should not cause a significant shift
in the phase relationship of the busbar and line side voltages. Parallel interconnections will
ensure that the two sides remain in synchronism, and that autoreclosure can proceed safely.
However, if the parallel interconnection(s) is/are lost, the frequencies of the two sections of
the split system will begin to slip with respect to each other during the time that the systems
are disconnected. Hence, a live busbar / live line synchronism check prior to reclosing the
breaker ensures that the resulting phase angle displacement, slip frequency and voltage
difference between the busbar and line voltages are all within acceptable limits for the
system. If they are not, closure of the breaker can be inhibited.
The SYSTEM CHECKS menu contains all of the check synchronism settings for auto (“A/R”)
and manual (“Man”) reclosure and is shown in the table below along with the relevant default
settings:-

Menu text Default setting Setting range Step size

Min Max
GROUP 1
SYSTEM CHECKS
C/S Check Scheme for A/R 111 Bit 0: Live Bus / Dead Line,
Bit 1: Dead Bus / Live Line,
Bit 2: Live Bus / Live Line.
Dead / Dead made by PSL only (from
version A3.0 model 05)
C/S Check Scheme for Man 111 Bit 0: Live Bus / Dead Line,
CB Bit 1: Dead Bus / Live Line,
Bit 2: Live Bus / Live Line.
Dead / Dead made by PSL only (from
version A3.0 model 05)
V< Dead Line 13V 5V 30V 1V
V> Live Line 32V 30V 120V 1V
V< Dead Bus 13V 5V 30V 1V
V> Live Bus 32V 30V 120V 1V
Diff Voltage 6.5V 0.5V 40V 0.1V
Diff Frequency 0.05Hz 0.02Hz 1Hz 0.01Hz
Diff Phase 20° 5° 90° 2.5°
Bus-Line Delay 0.2s 0.1s 2s 0.1s

KEY: “Diff” denotes the differential between Line VT and Busbar VT measurements.

− At least one condition of c/s scheme must be selected in the 3 bits, to activate the c/s
check logic.

− Man CB, check sync condition is tallen in account, only if a logic of STF has been
enabled by S1.

− If SOTF is disabled in S1, a dedicated PSL must be created using Deb B (live L or live
B/Dead L) – live/live could not be managed – in that case.
P44x/EN AP/E33 Application Notes

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Note that the combination of the Diff Phase and Bus-Line Delay settings can also be equated
to a differential frequency, as shown below:

• Diff Phase angle set to +/-20°, Bus-Line Delay set to 0.2s.

• The phase angle ‘window’ is therefore 40°, which corresponds to 40/360ths of a

cycle = 0.111 cycle. This equates to a differential frequency of:
0.111 / 0.2 = 0.55 Hz
Thus it is essential that the time delay chosen before an “in synchronism” output can be
given is not too long, otherwise the synchronising conditions will appear more restrictive than
the actual Diff Frequency setting.
The Live Line and Dead Line settings define the thresholds which dictate whether or not the
line or bus is determined as being live or dead by the relay logic. Under conditions where
either the line or bus are dead, check synchronism is not applicable and closure of the
breaker may or may not be acceptable. Hence, setting options are provided which allow for
both manual and auto-reclosure under a variety of live/dead conditions. The following
paragraphs describe where these may be used.
WARNING: THE SETTINGS VOLTAGE IN MiCOM S1 IS ALLWAYS CALCULATED IN
PHASE TO GROUND – EVEN IF PHASE/PHASE REF HAS BEEN
SELECTED.
If the threshold : live line has been set too high – the relay will never detect a healthy
network (as the line voltage is always measured below the voltage threshold). Without live
line condition, the distance protection cannot use the delta algorithms as no prefault
detection has been previously detected.
4.4.1 Dead Busbar and Dead Line
This mode is not integrated in the internal logic, however can be created using a dedicated
PSL:

(This facility with cells (Dead Line/Dead Bus) is available since version A3.0 model 05)
This setting might also be used to allow manual close with specific test conditions on the CB.
4.4.2 Live Busbar and Dead Line
Where a radial feeder is protected, tripping the circuit breaker will isolate the infeed, and the
feeder will be dead. Provided that there is no local generation which can backfeed to
energise the feeder, reclosure for live busbar / dead line conditions is acceptable. This
setting might also be used to allow re-energisation of a faulted feeder in an interconnected
power system, which had been isolated at both line ends. Live busbar / dead line reclosing
allows energising from one end first, which can then be followed by live line / live busbar
reclosure with voltages in synchronism at the remote end.
4.4.3 Dead Busbar and Live Line
If there was a circuit breaker and busbar at the remote end of the radial feeder mentioned
above, the remote breaker might be reclosed for a dead busbar / live line condition.
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 119/220

4.4.4 Check Synchronism Settings

Depending on the particular system arrangement, the main three phase VT for the relay may
be located on either the busbar or the line. Hence, the relay needs to be programmed with
the location of the main voltage transformer. This is done under the ‘CT & VT RATIOS’
column in the ‘Main VT Location’ cell, which should be programmed as either ‘Line’ or ‘Bus’
to allow the previously described logic to operate correctly. (See DDB description bellow)
Note that the check synch VT input may be driven from either a phase to phase or phase to
neutral voltage. The ‘C/S Input’ cell in the ‘CT & VT RATIOS’ column has the options of A-N,
B-N, C-N, A-B, B-C or C-A, which should therefore be set according to the actual VT
arrangement.
If the VTS feature internal to the relay operates, the check synchronising element is inhibited
from giving an ‘Allow Reclosure’ output. This avoids allowing reclosure in instances where
voltage checks are selected and a VT fuse failure has made voltage checks unreliable.
Measurements of the magnitude angle and delta frequency (slip frequency - since version
A4.0 with model 07) – the rated frequency of network is displayed by default in case of
problem with the delta f calculation : No line voltage or no bus voltage or both of the check-
synch voltage are displayed in the ‘MEASUREMENTS 1’ column.
Individual System Check logic features can be enabled or disabled by means of the C/S
Check Scheme function links. Setting the relevant bit to 1 will enable the logic, setting bits
to 0 will disable that part of the logic. Voltage, frequency, angle and timer thresholds are
shared for both manual and autoreclosure, it is the live/dead line/bus logic which can differ.
P44x/EN AP/E33 Application Notes

Page 120/220 MiCOM P441/P442 & P444

Enable_SYNC

VTS_Slow

1
INP_Fuse Failure Bus

AR_Force_Sync

INP_AR_Cycle_1P S
Q
INP_AR_Reclaim R

INP_AR_Cycle_Conf
1 CHECK
SYNC
INP_AR_Reclaim_Conf 1
Conditions
0 & verified
Any_Pole_Dead &
t 1
&
All_Pole_Dead 200ms

Dead L/Live B

t
V< Dead Line &
0

V> Live Bus 100ms

Live L/Dead B

t
V> Live L &
0

V< Dead B 100ms

Live L/Live B

V> Live B t
0
&
V> Live L
Bus Line Delay
Diff voltage

Diff frequency

Diff phase
P0492ENa

FIGURE 69 – CHECK SYNC LOGIC DESCRIPTION

Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 121/220

X1 X2

b0 i0

b1 i1

sample

T sample

P0493ENa

FIGURE 70 – CALCUL OF FREQUENCY

Frequency tracking is calculated by: freq=1/((X2-X1+ Nbsamples)* Tsamples)
With X1 = b0 /(b0 – b1) et X2 = I0 /(I0 – I1).
Tsamples is the sampling period.
Nbsamples is the number of samples per period (between b1 & i1 (b1 being excluded))
The Line & Bus frequencies are calculated with the same principle (described here after).
P44x/EN AP/E33 Application Notes

Page 122/220 MiCOM P441/P442 & P444

Trailing VLine phase

VLine
VBus
x1 x2

Ta

∆T

y1 y2

Leading VLine phase

VBus
VLine

y2 y3

Ta

∆T

x1 x2

P0494ENa

FIGURE 71 - CALCULATION OF DIFF. PHASE

Phase shift = (∆T/ T) *360

∆T = Ta + (x1-y2)
A phase shift calculation requests a change of sign from both signals.
All the angles will be between 0° and 180°. For a phase shift of 245°,
(360 –245) = 115° will be displayed
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 123/220

4.4.5 Logic inputs / Outputs from synchrocheck function

4.4.5.1 Logic DDB input from the check sync logic

MCB/VTS Bus
The DDB:MCB/VTS Bus if assigned to an opto input in PSL and when energized, will inform
the P44X about an internal maloperation from the VT used for synchrocheck ref. (BUS in
that case means Checksync ref measurement / even if the main VT is on the bus side and
the Synchro VT is on the line side)
When this opto picks up it will block the internal logic of Synchrocheck.

MCB/VTS Line
The DDB:MCB/VTS Line if assigned to an opto input in PSL and when energized, will inform
the P44X about an internal maloperation from the VT used for impedance measurement ref.
(Line in that case means Main VT ref measurement / even if the main VT are bus side and
the Synchro VT is line side)
When that opto picks up it will block the internal logic of Synchrocheck.
4.4.5.2 Logic DDB outputs issued by the check sync logic

Check Sync OK
Set high when Check Synchro conditions are verified
[Used with AR close in dedicated PSL – "AND" gate : [(AR Close) & (CheckSync OK)]

A/R Force Sync

Simulates the CheckSync control and force the logical DDB output "CheckSync OK" at 1
during a 1 pole or 3 poles high speed AR cycle. Without CheckSync control (See the
explanation in AR description Figure 76 and Figure 106)

V<Dead Line
Set high when the Dead line condition is verified (voltage below the V<Dead Line threshold
value (settable in MiCOM S1) – The measured voltage is always calculated as a single
phase voltage

V>Live Line
Set high when the Live line condition is verified (voltage above the V>Live Line threshold
value (settable in MiCOM S1) - always calculated as a single phase voltage ref

V<Dead Bus
Set high when the Dead Bus condition is verified (voltage below the V<Dead Bus threshold
value (settable in MiCOM S1) - always calculated as a single phase voltage ref

V>Live Bus
Set high when the Live Bus condition is verified (voltage above the V>Live Bus threshold
value (settable in MiCOM S1) - always calculated as a single phase voltage ref

Control No C/S
Set high when the internal Check Sync conditions are not verified

Ext Chk Synch OK

The DDB Ext Chk Synch OK if assigned to an opto input in PSL and when energized,
indicates that Check Sync conditions are verified by an external device – The DDB cell
should be assigned afterwards with an internal AR logic (See also AR description in section
4.5.1).
P44x/EN AP/E33 Application Notes

Page 124/220 MiCOM P441/P442 & P444

WARNING: TO ENSURE THAT THE AR CLOSING COMMAND IS CONTROLED BY

THE CHECK SYNC CONDITIONS, THE ABOVE PSL SHOULD BE SET.
(Different schemes can be created with internal AR & external CSync or internal Csync &
external AR)

Synchro Check : Dead Bus / Dead Line

P0537ENa

FIGURE 72 – CHECK SYNC PSL LOGIC

PSL Output
assigned

Check Sync 1 SYNC

AR_Force_Sync

AR_Fail

AReclose AR_Close

AR_Cycle_1P

AR_Cycle_3P

Closing command
& with check sync
1 conditions verified
CB Control CBC_Recl_3P

CBC_No_Check_Sync

P0495ENa

FIGURE 73 – INTERNAL CHECK SYNC AND INTERNAL AR LOGIC

Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 125/220

External Check Sync 1

Closing command
& with external C. Sync
conditions verified

Output_AR_force_Sync

Output_closing order
P0496ENa

FIGURE 74 - LOGIC WITH EXTERNAL SYNCHRO CHECK

Output_Sync

1
Output_AR_force_Sync External closing order
External with internal C. Sync
AR close order &
conditions verified
Output_AR_Close
1

Output_closing order
P0497ENa

FIGURE 75 - LOGIC WITH EXTERNAL AR

4.5 Autorecloser
4.5.1 Autorecloser Functional Description
The relay autorecloser provides selectable multishot reclosure of the line circuit breaker.
The standard scheme logic is configured to permit control of one circuit breaker.
Autoreclosure of two circuit breakers in a 1½ circuit breaker or mesh corner scheme is not
supported by the standard logic (Dedicated PSL must be created & tested by user). The
autorecloser can be adjusted to perform a single shot, two shot, three shot or four shot cycle.
Dead times for all shots (reclose attempts) are independently adjustable (in MiCOM S1).
Where the relay is configured for single and three pole tripping, the recloser can perform a
high speed (HSAR) single pole reclose shot, for a single phase to earth fault. This single
pole shot may be followed by up to three delayed (DAR) autoreclose shots, each with three
phase tripping and reclosure. For a three pole trip, up to four reclose shots are available in
the same scheme. Where the relay is configured for three pole tripping only, up to four
reclose shots are available, each performing three phase reclosure.
P44x/EN AP/E33 Application Notes

Page 126/220 MiCOM P441/P442 & P444

Menu text Default setting Setting range Step size

Min Max
GROUP 1
AUTORECLOSE
AUTORECLOSE MODE
1P Trip Mode Single Single
Single/Three
Single/Three/Three
Single/Three/Three/Three
3P Trip Mode Three Three
Three/Three
Three/Three/Three
Three/Three/Three/Three
1P - Dead Time 1(HSAR) 1s 0.1s 5s 0.01s
3P - Dead Time 1(HSAR) 1s 0.1s 60s 0.01s
Dead Time 2 (DAR) 60s 1s 3600s 1s
Dead Time 3 (DAR) 180s 1s 3600s 1s
Dead Time 4 (DAR) 180s 1s 3600s 1s
Reclaim Time 180s 1s 600s 1s
Close Pulse Time 0.1s 0.1s 10s 0.1s
A/R Inhibit Wind 5s 1s 3600s 1s
(CB healthy application)
C/S on 3P Rcl DT1 Enabled Enabled, Disabled
(Check Sync with HSAR)
AUTORECLOSE
LOCKOUT
Block A/R 11111111 Bit 0: Block at tZ2, Bit 1: Block at tZ3,
11111111 Bit 2: Block at tZp, Bit 3: Block for LoL Trip,
Bit 4: Block for I2> Trip,
Bit 5: Block for I>1 Trip,
Bit 6: Block for I>2 Trip,
(Bit = 1 means AR blocked)
Bit 7: Block for V<1 Trip,
Bit 8: Block for V<2 Trip,
Bit 9: Block for V>1 Trip,
Bit 10: Block for V>2 Trip,
Bit 11: Block for IN>2 Trip,
Bit 12: Block for IN>2 Trip,
Bit 13: Block for Aided DEF Trip.
Discrim. Time 5s 0.1s 5s 0.01s

Remark: 1 PAR or/and 3 PAR logic must be enable in CB control:

Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 127/220

4.5.2 Benefits of Autoreclosure

An analysis of faults on any overhead line network has shown that 80-90% are transient in
nature. Lightning is the most common cause, other possibilities being clashing conductors
and wind blown debris. Such faults can be cleared by the immediate tripping of one or more
circuit breakers to isolate the fault, followed by a reclose cycle for the circuit breakers. As
the faults are generally self clearing ‘non-damage’ faults, a healthy restoration of supply will
result.
The remaining 10 - 20% of faults are either semi-permanent or permanent. A semi-
permanent fault could be caused by a small tree branch falling on the line. The cause of the
fault may not be removed by the immediate tripping of the circuit, but could be burnt
away/thrown clear after several further reclose attempts or “shots”. Thus several time
delayed shots may be required in forest areas.
Permanent faults could be broken conductors, transformer faults or cable faults which must
be located and repaired before the supply can be restored.
In the majority of fault incidents, if the faulty line is immediately tripped out, and time is
allowed for the fault arc to de-ionise, reclosure of the circuit breakers will result in the line
being successfully re-energised, with obvious benefits. The main advantages to be derived
from using autoreclose can be summarised as follows:

• Minimises interruptions in supply to the consumer;

• A high speed trip and reclose cycle clears the fault without threatening system
stability.
When considering feeders which are partly overhead line and partly underground cable, any
decision to install auto-reclosing would be influenced by any data known on the frequency of
transient faults. When a significant proportion of the faults are permanent, the advantages of
auto-reclosing are small, particularly since reclosing on to a faulty cable is likely to aggravate
the damage.
At subtransmission and transmission voltages, utilities often employ single pole tripping for
earth faults, leaving circuit breaker poles on the two unfaulted phases closed. High speed
single phase autoreclosure then follows. The advantages and disadvantages of such single
pole trip/reclose cycles are:

• Synchronising power flows on the unfaulted phases, using the line to maintain
synchronism between remote regions of a relatively weakly interconnected system.

• However, the capacitive current induced from the healthy phases can increase the
time taken to de-ionise fault arcs.
P44x/EN AP/E33 Application Notes

Page 128/220 MiCOM P441/P442 & P444

4.5.3 Auto-reclose logic operating sequence

An autoreclose cycle is internally initiated by operation of a protective element (could be
started by an internal trip or external trip), provided the circuit breaker is closed at the instant
of protection operation. The appropriate dead timer for the shot is started (Dead Time 1, 2, 3
or 4; noting that separate dead times are provided for the first high speed shot of single pole
(1P), and three pole (3P), reclosure). At the end of the dead time, a CB close command of
set duration = Close Pulse is given, (See Figure 76 with AR Close logic) provided system
conditions are suitable. The conditions to be met for closing are that the system voltages
satisfy the internal check synchronism criteria (set in the System Checks section of the relay
menu – and in a dedicated PSL (needs to be created by user – see section 4.2.8), and that
the circuit breaker closing spring, or other energy source, is fully charged indicated from the
DDB: CB Healthy input (Optional application / See Figure 78 and Figure 82 AR inputs).
When the CB has closed the reclaim time (Reclaim Time) starts (See Figure 76 with AR
Close logic). If the circuit breaker has been not retrip, the autoreclose logic is reset at the
end of the reclaim time. The autorecloser is ready again to restart from the first shot a new
cycle again (for future faults). If the protection retrips during the reclaim time, the relay either
advances to the next shot in the programmed autoreclose cycle, or, if all programmed
reclose attempts have been made, goes to lockout.

Trip_1P or Trip_3P
Dead Time_1P or
Dead Time_3P
Close Pulse

AR_Trip_3ph
Reclaim Time
P0555ENa

FIGURE 76 - AR CYCLE – GENERAL DESCRIPTION

AR_Trip_3ph and Reclaim

Time stop with next Trip

Trip_1P or Trip_3P
Dead Time_1P
Dead Time_3P
Close Pulse

AR_Trip_3ph
Reclaim Time
P0556ENa

FIGURE 77 - SUCCESSIVE AR CYCLE – SECOND TRIP ORDER BEFORE RECLAIM TIME IS ISSUED
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 129/220

(The reclaim time is reset when the reclaim timer adjusted in MiCOM S1 Timer is issued or if
a new trip order 1P or 3P occurs – see Figure 78)

Any Pole Dead

CHECK SYNC OK
R
Q
End of Dead Time 2 AR_Fail
& S

CHECK SYNC 3P HSAR

1
&
End of 3P Dead Time 1

S
& Q AR_Force_Sync
1 R
End of 1P Dead Time 1

1
& S
Q AR_RECLAIM
R
AR_Enable 0
& t
1 Reclaim Time
Block AR
1

INP_CBHealthy
1 S
Q AR_Close
TRIP_1P
R
1 0
1
t
TRIP_3P
Close pulse Time

P0498ENa

FIGURE 78 - LOGIC FOR RECLAIM TIME /AR CLOSE / AR FAIL AND AR FORCE_SYNC
(AR FAIL is reseted with 3 pole closed)
P44x/EN AP/E33 Application Notes

Page 130/220 MiCOM P441/P442 & P444

AR_Enable

Block AR
1

AR lock out

inhibit

CBA_Discrepency
& S & AR_lock out
Q
1
R
0
t
End of 1P Dead Time 1 Reclaim
Time
1
End of 3P Dead Time 1

S
&
Q
TRIP_1P
1 R

TRIP_3P

Reset TRIP 1P
1
Reset TRIP 3P

TPAR enable

AR_Cycle_1P & S
Q
AR_Discrimination R

TRIP_3P

Reset TRIP 3P 1

& S
Q
R

P0499ENa

FIGURE 79 - INTERNAL LOGIC OF AR LOCK OUT

AR lockout logic picks up by: Block AR (see Figure 80) or AR BAR Shots (see Figure 81)
or Inhibit (see Figure 82) or No pole discrepancy detected at the end of dead time1 (see
Figure 83) or Trip order still present at the end of Dead time or Trip3P issued during 1P cycle
after Discrimination Timer or Trip3P issued during 1P cycle with no 3PAR enable.
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 131/220

S
Q >1
AR 1P in Prog
>1 &
AR 3P in Prog

BAR_Block_T2 Enable
&
T2

BAR_Block_T3 Enable
&
T3

BAR_Block_Tzp Enable
&
Tzp

T4

BAR_Block_LOL Enable
&
LOL_Trip_3P

BAR_Block_I2 > Enable

&
Trip_I2>

BAR_Block_I> Enable
&
TRIP 3P_I>1

BAR_Block_I>2 Enable
&
TRIP 3P_I>2

BAR_Block_V<1 Enable
&
TRIP 3P_V<1
&
BAR_Block_V<2 Enable
&
>1
TRIP 3P_V<2 >1 Block AR

BAR_Block_V>1 Enable
&
TRIP 3P_V>1

BAR_Block_V>2 Enable
&
TRIP 3P_V>2

BAR_Block_IN>1 Enable
&
SBEF_TRIP 3P_IN>1

BAR_Block_IN>2 Enable
&
SBEF_TRIP 3P_IN>2

BAR_Block_DEF Enable
&
DEF_TripA

DEF_TripB >1
DEF_TripC

BRK_Trip 3P

SOTF_Enable
&
SOTF/TOR trip

PHOC_Trip_3P_I>4

CBF1_Trip_3P

CBF2_Trip_3P

INP_BAR
P0500ENa

FIGURE 80 – BLOCK AR LOGIC

− With AR Lock out (Block AR) activated, the AR does not initiate any additional AR
cycle. If AR lock out picks up during a cycle, the AR close is blocked.

− A dedicated PSL can be created, for performing an AR lock out in case of Fuse
Failure confirmed.
P44x/EN AP/E33 Application Notes

Page 132/220 MiCOM P441/P442 & P444

AR_Enable

SPAR enable
& & S
1 AR lockout_Shots>
Q
R

TRIP_1P
1

Trip counter = &

setting

TRIP_3P

&
TPAR enable

Reset TRIP_1P
1
Reset TRIP_3P
P0501ENa

FIGURE 81 - AR LOCK OUT BY NUMBER OF SHOTS

AR_Enable

End of 1P_Dead Time

1
& S
End of 3P_Dead Time Q t
0 inhibit
R
&
INP_CBHealthy Inhibit Window

P0502ENa

FIGURE 82 - LOGIC OF INHIBIT WINDOW

The inhibit timer is started at the end of dead time if CB healthy is absent

Trip1P
Dead time(1P)

AR_BAR

AR_Trip_3ph
CBA_Discrepency
P0503ENa

FIGURE 83 - POLES DISCREPENCY (CBA-DISC)

Trip1P or Trip 3P
Dead time1 or
Dead time 3P
AR_Close

AR_BAR
P0557ENa

FIGURE 84 - TRIP ORDER STILL PRESENT AT THE END OF DEAD TIME WILL FORCE AR LOCK OUT
(AR _BAR)
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 133/220

CNF_52b

CNF_52a

&
INP_52a_A &
S
Q
& R
INP_52b_A &
1 CBA_A
&

& & CBA_3P_C

xor

&
INP_52a_B &
S
Q 1 CBA_ANY
& R
INP_52b_B &
1 CBA_B
&

& & CBA_3P

xor

&
INP_52a_C & &
S
Q
& R
INP_52b_C &
1 CBA_C
&

& t
1 0 CBA_Status_Alarm
xor
CBA_Time_Alarm

CBA_Time_Disc

1 t
INP_DISCREPENCY CBA_Disc
0

P0504ENa

FIGURE 85 - LOGICAL CBAUX SCHEME

(CBA_DISC LOGIC FOR AR_BAR (AR LOCK OUT))
CBA TIME DISC=150MSEC FIXED VALUE

Logic of pole dead :

− CBA_A = Pole Dead A

− CBA_3P = All pole Dead

− CBA_3P_C = All pole Live

− CBA_Any = Minimum 1Pole dead

The total number of autoreclosures is shown in the “CB Condition” menu from LCD under
Total Reclosures. Separate counters for single pole and three pole reclosures are available
(See HMI description chapter P44x/EN HI). The counters can be reset to zero with the
Reset Total A/R command; by LCD HMI
P44x/EN AP/E33 Application Notes

Page 134/220 MiCOM P441/P442 & P444

4.5.4 Scheme for Three Phase Trips

The relay allows up to four reclose shots. The scheme is selected in the relay menu as
shown in Table 12:

(The first 3P_HSAR cycle can be controlled by the check Sync logic)

Reclosing Mode Number of Three Phase Shots

3 1
3/3 2
3/3/3 3
3/3/3/3 4

TABLE 12 - RECLOSING SCHEME FOR 3 PHASE TRIPS

4.5.5 Scheme for Single Pole Trips
The relay allows up to four reclose shots, ie. one high speed single pole AR shot (HSAR),
plus up to three delayed (DAR) shots. All DAR shots have three pole operation. The
scheme is selected in the relay menu as follows:

Scheme Number of Single Pole HSAR Shots Number of Three Pole DAR Shots
1 1 None
1/3 1 1
1/3/3 1 2
1/3/3/3 1 3

TABLE 13 - RECLOSING SCHEME FOR SINGLE PHASE TRIPS

Should a single phase fault evolve to affect other phases during the single pole dead time,
the recloser will then move to the appropriate three phase cycle.
When a single pole trip is issued by the relay, a 1 pole AR cycle is initiated. The Dead time1
and Discrimination timer (from version A3.0) are started. If the AR logic detects a single pole
or three poles trip (internal or external) during the discrimination timer, the 1P HSAR cycle is
disabled and replaced by a 3P HSAR cycle, if enable. If no AR 3P is enable in MiCOM S1,
the relay trip 3 poles and AR is blocked. (see Figure 86)
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 135/220

Trip 1P Trip 3P during Discrimination Timer

Trip_1P or Trip_3P

1P_Dead Time

AR_Discrimination Timer
3P_Dead Time

AR_Trip_3ph

AR_BAR
P0505ENa

FIGURE 86 - FAULT DURING A HSAR 1P CYCLE DURING DISCRIMINATION TIMER

If the AR logic detect a 3 poles trip (internal or external) when the Discrimination Timer is
issued, and during the 1P dead time; the single pole AR cycle is stopped and the relay trip 3
phases and block the AR. (see Figure 87)

Trip 1P Trip 3P after Discrim Timer

Trip_1P or Trip_3P

1P_Dead Time

AR_Discrimination Timer

3P_Dead Time

AR_Trip_3ph

AR_BAR
P0506ENa

FIGURE 87 - FAULT DURING A HSAR 1P CYCLE WHEN DISCRIMINATION TIMER IS ISSUED

- Figure 86 - Figure 87: Evolving fault during AR 1P cycle -
P44x/EN AP/E33 Application Notes

Page 136/220 MiCOM P441/P442 & P444

4.5.6 Logical Inputs used by the Autoreclose logic

Contacts from external equipment (External protection or external synchrocheck or external
AR) may be used to influence the auto-recloser via opto-isolated inputs. Such functions can
be allocated to any of the opto-isolated inputs on the relay via the programmable scheme
logic (Ensure that optos1&2 are not set for setting group change- Otherwise, these optos
cannot be mapped to functions in the PSL). The inputs can be selected to accept either a
normally open or a normally closed contact, programmable via the PSL editor.

SPAR Enable
The DDB SPAR Enable if assigned to an opto input in the PSL (in default PSL is inverted
and recorded to opto8) and when energized, will enable the 1P AR logic (The priority of that
input is higher than the settings done via MiCOM S1 or by front panel - that means the 1P
AR can be disabled even if activated in MiCOM S1; as the opto input is not energized.
(to be valid opto must be energized >1,2 sec).

SPAR
1 AR SPAR enable
INP_SPAR
P0507ENa

FIGURE 88

TPAR Enable
The DDB TPAR Enable if assigned to an opto input in the PSL (in default PSL is inverted
and recorded to opto8) and when energized, will enable the 3P AR logic (The priority is
higher than the settings done via MiCOM S1 or by front panel - that means the 3P AR can be
disabled even if activated in MiCOM S1; as that opto is not energized.
(to be valid opto must be energized >1,2 sec).

TPAR
1 AR TPAR enable
INP_TPAR
P0508ENa

FIGURE 89
NOTE: After a new PSL loaded in the relay (which includes "TPAR" or
"SPAR" cells); it is necessary to transfer again the settings
configuration (from PC to relay) for adjusting the datas in RAM and
EEPROM (otherwise discrepency could appear in the logic status of
AR enable).

A/R Internal
The DDB A/R Internal if assigned to an opto input in the PSL and when energized, will
enable the internal AR logic. This opto input could be connected to an external condition like
the Wdog of protection Main1 – which activates the internal AR of Main 2 (P44x) in case of
internal failure of the Main1.

AR_Internal

SPAR enable & AR_Enable

1

TPAR enable
P0509ENa

FIGURE 90 - AR ACTIVATED CONDITIONS

Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 137/220

A/R 1p in Prog
The DDB A/R 1P in Prog if assigned to an opto input in the PSL and when energized, will
block the internal DEF as an external single pole AR cycle is in progress.

A/R 3p in Prog
The DDB A/R 3P in Prog if assigned to an opto input in the PSL and when energized, will
inform the P44X about the presence of an external 3P cycle.That data could be used in case
of evolving fault

A/R Close
The DDB A/R Close if assigned to an opto input in the PSL and when energized, could be
linked with the internal check sync condition to control the external CB closing command.

A/R Reclaim
The DDB A/R Reclaim if assigned to an opto input in the PSL and when energized, will
inform the protection about an external reclaim time in progress; and will initiate the internal
TOR logic. (That information extension logic, by using a dedicated PSL could be used also
in Z1x.

BAR
Block Autoreclose (via Opto Input or PSL) – see Figure 80.
The DDB: BAR input will block the autoreclose and lockout the AR if in progress. If a single
pole cycle is in progress a three pole trip and lockout will be issued. It can be used when
protection operation without autoreclose is required. A typical example is on a transformer
feeder, where autoreclosing may be initiated from the feeder protection but blocked from the
transformer protection. Similarly, where a circuit breaker low gas pressure or loss of vacuum
alarm occurs during the dead time, autoreclosure, should be blocked – and BAR can be
used to realise that blocking logic.

Ext Chk Synch OK

External Check Synchroniser Used (via Opto Input) – Dedicated PSL required to be
configured.
If an opto input is assigned in the PSL (DDB: Ext Chk Synch OK), the AR close command
will be controlled by an external check synchronism device. The input is energised when the
Check Sync conditions are verified.

CB Healthy
(via Opto Input)
The majority of circuit breakers are only capable of providing one trip-close-trip cycle. It is
necessary to re-establish sufficient energy in the circuit breaker before the CB can be
reclosed. The DDB: CB Healthy input is used to ensure that there is sufficient energy
available to close and trip the CB before initiating a CB close command. If on completion of
the dead time, sufficient energy is not detected by the relay within a period given by the AR
Inhibit Wind window, lockout will result and the CB will remain open (AR BAR Picks up –
see Figure 79) If the CB energy becomes healthy during the time window, autoreclosure will
occur. This check can be disabled by not allocating an opto input. In this case, the DDB cell
“CB Healthy” is considered invariant for the logic of the relay. This will mean that the signal
is always high within the relay (when the logic required a high level) and at 0, if low level is
requested. It is an invariant status for the firmware (Same logic is applied for every optional
opto – if not linked in the PSL these cells are managed as invariant data for internal logic).
P44x/EN AP/E33 Application Notes

Page 138/220 MiCOM P441/P442 & P444

Start of INP_CB_Healthy picks up,

INhWind before issued of INhWind

INhWind
1P Dead Time or
3P Dead Time
INP_CB_Healthly
Close pulse

AR_Trip_3ph

AR_RECLAIM
P0510ENa

FIGURE 91 - CB_HEALTHY IS PRESENT BEFORE INHWIND IS ISSUED

Start of INhWind is
INhWind issued

INhWind
1P_Dead Time or
3P_Dead Time

INP_CB_Healthy

AR_Close

AR_Trip_3ph

AR_BAR
P0511ENa

FIGURE 92 - CB_HEALTHY DID NOT PICKS UP WHEN INHWIND IS ISSUED (AR BAR PICKS UP)
The CB healthy logic is used as a negative logic (due to an inverter in the scheme – see
Figure 82 (logic of inhibit window) but the DDB takes into account the CB healthy as a
positive logic [1=opto energised during inhwind (MiCOM S1 setting) =AR close pulse]

Force 3P Trip
The DDB Force 3P Trip if assigned to an opto input in the PSL and when energized, will
force the internal single phase protection to trip three phases. (external order from Main1 to
Main2 (P44x)) – next Trip will be 3P (Figure 92 & Figure 93)

INP_Trp_3P
1 BAN3
AR_Trip_3Ph

SPAR enable &

AR_internal
P0512ENa

FIGURE 93 – 3P TRIP LOGIC

Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 139/220

Trip_3P_SBEF_IN>1
Trip_3P_SBEF_IN>2
Trip_3P_I2>

TOR_Trip_3P

LOL_Trip_3P

BRK_Trip_3P
Trip_3P_I>1
Trip_3P_I>2 1

Trip_3P_I>3

Trip_3P_I>4
Trip_3P_V<1
Trip_3P_V<2 1
Trip_3P_V>1
Trip_3P_V>2 1 1 TRIP_Any Pole
PW_trip
R
Q
& S Dwell
1 Timer
BAN3
Trip_timer
PDist_Trip_A
Dwell
Weak_Trip_A 1 Trip_A
1
Timer
DEF_Trip_A
80 ms
User_Trip_A

1 TRIP_Any_A
INP_EXTERNAL_ProtA 1

& &
1 TRIP_3Poles

Trip_timer
PDist_Trip_B
Dwell 1
Weak_Trip_B Trip_B
1
Timer
DEF_Trip_B 80 ms
User_Trip_B

1 TRIP_Any_B
1
INP_EXTERNAL_ProtB

& TRIP_1Pole
xor
xor

Trip_timer
PDist_Trip_C
Dwell 1 Trip_C
Weak_Trip_C 1
Timer
DEF_Trip_C
80 ms
User_Trip_C

1 TRIP_Any_C
1
INP_EXTERNAL_ProtC
P0513ENa

FIGURE 94 - GENERAL TRIP LOGIC

Manual Close CB
(via Opto Input, Local or Remote Control)
Manual closure of the circuit breaker will force the autorecloser in a lockout logic, if selected
in the menu (see SOTF logic Figure 35).
P44x/EN AP/E33 Application Notes

Page 140/220 MiCOM P441/P442 & P444

Any fault detected within 500ms of a manual closure will cause an instantaneous three pole
tripping, without autoreclosure (See next Figure 80 BAR logic)
With AR Lock out (AR_BAR) activated, the AR does not initiate any additional AR cycle. If
AR lock out picks up during a cycle, the AR close is blocked.
This prevents excessive circuit breaker operations, which could result in increased circuit
breaker and system damage, when closing onto a fault.

Manual Trip CB
The DDB Force Manual Trip CB if assigned to an opto input in the PSL and when
energized, will inform the protection about an external trip command on the CB by the CB
control function (if activated).
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 141/220

SUP_Trip_Loc
& Manual/Remote/Local Trip
1
CBC_Local_Control
&
SUP_Close_Loc

SUP_Trip_Rem
&

CBC_Remote_Control
&
SUP_Close_Rem

INP_CB_Trip_Man
&

CBC_Input_Control Manual/Remote/Local Close

1
&
INP_CB_Man_Close

TRIP

& S CBC_Trip_Pulse
CBA_3P_C
Q CBC_Trip_3P
1
R
t
Pulsed output latched in UI
0 &
CBC_Failed_To_Trip

CBA_3P

CLOSE
CBA_Status_Alarm
& S
Q CBC_Close_In_Progress
AR_Cycle_1P R
1
INP_AR_Cycle_1P t
0
1
AR_Cycle_3P 1 CBC_Delay_Close

INP_AR_Cycle_3P & S
Q
CBA_3P R

CBA_Disc

TRIP_Any
1

INP_AR_Close
Pulsed output latched in UI

AR_Close 1 & CBC_ Fail_To_Close

t
0
R
Q CBC_Recl_3P
S CBC_Close_Pulse

CBA_Any

&
INP_CB_Healthy

CBC_Healthy_Window

t
0 & CBC_UnHeathly

CBC_CS_Window

t
0 & CBC_No_Check_Syn
SYNC
P0514ENa

FIGURE 95 - GENERAL CB CONTROL LOGIC

P44x/EN AP/E33 Application Notes

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CB Discrepancy
The DDB CB Discrepancy if assigned to an opto input in the PSL and when energized, will
inform the protection about a pole Discrepancy status. 1 pole opened and two other poles
closed. Must be Set to high logical level before Dead time 1 is issued (see Figure 83) -can
be generated also internally (see Figure 85 and Figure 109 Cbaux logic).

External TripA
External TripB
External TripC

From External Protection Devices (via Opto Inputs)- see General trip logic Figure 94.
Opto inputs are assigned as External Trip A, External Trip B and External Trip C (external
Trip Order issued by main 2 or in order to initiate the internal AR backup protection).
External trip is integrated in the DDB: Any Trip. No Dwell timer is associated as for an
internal trip (see Figure 94: trip logic).
4.5.7 Logical Outputs generated by the Autoreclose logic
The following DDB signals can be masked to a relay contact in the PSL or assigned to a
Monitor Bit in Commissioning Tests, to provide information about the status of the
autoreclose cycle. These are described below, identified by their DDB signal text.

AR Lockout Shot>
Indicates an unsuccessful autoreclose (definitive trip following the last AR shot). The relay
will be driven to lockout and the autoreclose function will be disabled until the lockout
condition has been reset. An alarm, "AR Lockout Shots>" (along with AR Lockout) will be
raised. – (see Figure 79 and Figure 81)

AR Fail
If the check sync conditions are not meet prior to reclose within the time window, an alarm
"AR Fail" will be raised. (see Figure 78)

AR Close
Initiates the reclosing command pulse for the circuit breaker. This output feeds a signal to
the Reclose Time Delay timer, which maintains the assigned reclose contact closed for a
sufficient time period to ensure reliable CB mechanism operation. This DDB signal may also
be useful during relay commissioning to check the operation of the autoreclose cycle.
Where three single pole circuit breakers are used, the AR Close contact will need to
energise the closing circuits for all three breaker poles (or alternatively assign three CB
Close contacts). (See Figure 78)

AR 1P In Prog.
A single pole autoreclose cycle is in progress. This output will remain activated from the
initiating protection trip, until the circuit breaker is closed successfully, or the AR function is
Locked Out, thus indicating that dead time timeout is in progress. This signal may be useful
during relay commissioning to check the operation of the autoreclose cycle.
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 143/220

SPAR enable
&

TRIP_1P

AR_Cycle_3P S
& Q AR__1P in prog
CBA_Discrepency
R

BAR t
1
0

TRIP_3P 1P Dead Time 1

S
Q AR_Discrimination
R

1 t
0
Discrimination Time

P0515ENa

FIGURE 96 – AR 1 POLE IN PROGRESS LOGIC

AR 3P In Prog.
A three phase autoreclose cycle is in progress. This output will remain activated from the
initiating protection trip, until the circuit breaker is closed successfully, or the AR function is
Locked Out, thus indicating that dead time timeout is in progress. This signal may be useful
during relay commissioning to check the operation of the autoreclose cycle.

HS_AR_3P

1 AR_3P in prog
DAR_3P
P0516ENa

FIGURE 97 - OUTPUT AR 3 POLES IN PROGRESS

AR_1P in prog

Trip counter = 0 &

TPAR enable
&
1 S
TRIP_3P Q HSAR_3P
R
&
AR_discrimination t
0

Block AR Dead Time1

1

P0517ENa

FIGURE 98 - HSAR 3 POLES (HIGH SPEED AR CYCLE 3 POLES)

3Par
&
& S
TRIP_3P
Q DAR_3P
0 < Trip counter < setting R

Block AR t
1
0
Dead Time 2
P0518ENa

FIGURE 99 - DAR 3 POLES (DELAYED AR CYCLE 3 POLES)

P44x/EN AP/E33 Application Notes

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AR 1st in Prog.
DDB: AR 1st in Prog. is used to indicate that the autorecloser is timing out its first dead
time, whether a high speed single pole or three pole shot.

HSAR_3P

1 AR_1st_Cycle
AR_1P in prog
P0519ENa

FIGURE 100 - OUTPUT HSAR (FOR DEAD TIME1)

AR 234 in Prog.
DDB: AR 234 in Prog. is used to indicate that the autorecloser is timing out delayed
autoreclose dead times for shots 2, 3 or 4. Where certain protection elements should not
initiate autoreclosure for DAR shots, the protection element operation is combined with AR
234 in Prog. as a logical AND operation in the Programmable Scheme Logic, and then set to
assert the DDB: BAR input, forcing lockout.

DAR_3P 1 AR_234th_Cycle

P0520ENa

FIGURE 101 - OUTPUT DAR (FOR DEAD TIME2,3,4)

AR Trip 3 Ph
This is an internal logic signal used to condition any protection trip command to the circuit
breaker(s). Where single pole tripping is enabled, fixed logic converts single phase trips for
faults on autoreclosure to three pole trips.

AR_1P in prog
1
AR_3P in prog

&
TRIP_1P

Block AR 1

AR_RECLAIM

&
inhibit 1 AR_Trip_3Ph

AR_Internal
&

SPAR enable
P0521ENa

FIGURE 102 - -AR LOGIC FOR 3P TRIP DECISION

AR Reclaim
Indicates that the reclaim timer following a particular autoreclose shot is timing out. The
DDB: AR Reclaim output would be energised at the same instant as resetting of any Cycle
outputs. AR Reclaim could be used to block low-set instantaneous protection on
autoreclosure, which had not been time-graded with downstream protection. This technique
is commonly used when the downstream devices are fuses, and fuse saving is implemented.
This avoids fuse blows for transient faults. See Figure 78.
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 145/220

AR Discrim
Start with the trip order.
When a single pole trip is issued by the relay, a 1 pole AR cycle is initiated. The Dead time1
and Discrimination timer (from version A3.0) are started. If the AR logic detects a single pole
or three poles trip (internal or external) during the discrimination timer, the 1P HSAR cycle is
disabled and replaced by a 3P HSAR cycle, if enable. If no AR 3P is enable in MiCOM S1,
the relay trip 3 poles and AR is blocked. (see Figure 86)
If the AR logic detect a 3 poles trip (internal or external) when the Discrimination Timer is
issued, and during the 1P dead time; the single pole AR cycle is stopped and the relay trip 3
phases and block the AR. (see Figure 87 and Figure 96)

SPAR enable
&

TRIP_1P

AR_3P in prog S
& Q AR_1P in prog
CBA_Discrepency
R

Block AR t
1
0

TRIP_3P 1P Dead Time 1

S
Q AR_Discrimination
R

1 t
0
Discrimination Time

P0522ENa

FIGURE 103 – AR DISCRIMINATION LOGIC

See also Figure 86 & Figure 87
The discrimination timer is used to differentiate an evolving fault to a second fault in the
power system or a long operation of the circuit breaker.
P44x/EN AP/E33 Application Notes

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If an evolving occurs during the discrimination timer, the first single pole high speed
AR cycle (1P HSAR) is stopped and removed by a 3 pole high speed AR cycle (3P HSAR)

P0523ENa

FIGURE 104 - DEAD TIME 1P=500MSEC / T DISCRIM=100MSEC

If the evolving fault occurs after the discrimination timer, it is considered like a new fault. The
1P cycle is blocked and the CB is kept opened. (No 3P AR cycle is started) (definitive trip –
3 poles are kept opened) – see Figure 105.
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 147/220

FIGURE 105
To inhibit the discrimination timer logic (fixed logic) ; the value should be equal to the 1P
cycle dead time. (1P Dead Time 1).

AR Enable
Indicates that the autoreclose function is in service. (See Figure 90)

AR SPAR Enable
Single pole AR is enabled. (See Figure 88)

AR TPAR Enable
Three poles AR is enabled. (See Figure 89)

AR Lockout
If protection operates during the reclaim time, following the final reclose attempt, the relay
will be driven to lockout and the autoreclose function will be disabled until the lockout
condition is reset. This will produce an alarm, AR Lockout. Secondly, the DDB: BAR input
will block autoreclose and cause a lockout if autoreclose is in progress. Lockout will also
occur if the CB energy is low and the CB fails to close. Once the autorecloser is locked out,
it will not function until a Reset Lockout or CB Manual Close command is received
(depending on the Reset Lockout method chosen in CB Monitor Setup).

NOTE: Lockout can also be caused by the CB condition monitoring functions

maintenance lockout, excessive fault frequency lockout, broken
current lockout, CB failed to trip and CB failed to close, manual close
no check synchronism and CB unhealthy. (See Figure 79 & Figure
80)
P44x/EN AP/E33 Application Notes

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A/R Force Sync

Force the Check Sync conditions to high logical level – used for SPAR or TPAR with SYNC
AR3 fast (Enable by MiCOM S1) - signal is reset with AR reclaim

DEC_3P

AR_Cycle_3P

SYNC

AR_Close

AR_Trip_3ph

RECLAIM
AR_Force_Sync
P0558ENa

FIGURE 106 – CHECK SYNC SIGNAL PICK-UP AT THE END OF THE DEAD TIME (AR CYCLE)

DEC_3P

AR_Cycle_3P

SYNC

AR_Close

AR_Trip_3ph

AR_RECLAIM

AR_Fail

AR_Force_Sync
P0559ENa

FIGURE 107 - THE CHECK SYNC SIGNAL IS FORCED AT THE END OF DEAD TIME
(SEE FIGURE 78)

Ext Chk Synch OK

The DDB Ext Chk Synch OK if linked to an opto in a dedicated PSL and when energized,
indicates that external conditions of Synchro are fullfiled – This can be linked afterwards with
an internal AR logic (See also AR description in Figure 76).

Check Sync;OK
(See Checksync logic description – section 4.4.5.2)

V<Dead Line
(See Checksync logic description – section 4.4.5.2)

V>Live Line
(See Checksync logic description – section 4.4.5.2)

V<Dead Bus
(See Checksync logic description – section 4.4.5.2)
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 149/220

V>Live Bus
(See Checksync logic description – section 4.4.5.2)

Ctrl Cls In Prog

Manual close in progress-using CB control (timer manual closing delay in progress)

Control Trip
CB Trip command by internal CB control

Control Close
CB close command by internal CB control

4.5.8 Setting Guidelines

Should autoreclosure not be required, the function may be Disabled in the relay
Configuration menu. Disabling the autorecloser does not prevent the use of the internal
check synchronism element to supervise manual circuit breaker closing. If the autoreclose
function is Enabled, the setting guidelines now outlined should be read:
4.5.9 Choice of Protection Elements to Initiate Autoreclosure
In most applications, there will be a requirement to reclose for certain types of faults but not
for others. The logic is partly fixed so that autoreclosure is always blocked for any Switch on
to Fault, Stub Bus Protection, Broken Conductor or Zone 4 trip. Autoreclosure will also be
blocked when relay supervision functions detect a Circuit Breaker Failure or Voltage
Transformer/Fuse Failure. All other protection trips will initiate autoreclosure unless blocking
bits are set in the A/R Block function links. Setting the relevant bit to 1 will block
autoreclose initiation (forcing a three pole lockout), setting bits to zero will allow the set
autoreclose cycle to proceed.
When autoreclosure is not required for multiphase faults, DDB signals 2Ph Fault and 3Ph
Fault can be mapped via the PSL in a logical OR combination onto input DDB: BAR. When
blocking is only required for a three phase fault, the DDB signal 3Ph Fault is mapped to BAR
alone. Three phase faults are more likely to be persistent, so many utilities may not wish to
initiate autoreclose in such instances.
4.5.10 Number of Shots
There are no clear-cut rules for defining the number of shots for any particular application. In
order to determine the required number of shots the following factors must be taken into
account:
An important consideration is the ability of the circuit breaker to perform several trip close
operations in quick succession and the effect of these operations on the maintenance period.
The fact that 80 - 90% of faults are transient highlights the advantage of single shot
schemes. If statistical information for the power system shows that a moderate percentage
of faults are semi-permanent, further DAR shots may be used provided that system stability
is not threatened. Note that DAR shots will always be three pole.
P44x/EN AP/E33 Application Notes

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4.5.11 Dead Timer Setting

High speed autoreclose may be required to maintain stability on a network with two or more
power sources. For high speed autoreclose the system disturbance time should be
minimised by using fast protection, <50 ms, such as distance or feeder differential protection
and fast circuit breakers <100 ms. For stability between two sources a system dead time of
<300 ms may typically be required. The minimum system dead time considering just the CB
is the trip mechanism reset time plus the CB closing time.
Minimum relay dead time settings are governed primarily by two factors:

• Time taken for de-ionisation of the fault path;

• Circuit breaker characteristics.

Also it is essential that the protection fully resets during the dead time, so that correct time
discrimination will be maintained after reclosure onto a fault. For high speed autoreclose
instantaneous reset of protection is required.
For highly interconnected systems synchronism is unlikely to be lost by the tripping out of a
single line. Here the best policy may be to adopt longer dead times, to allow time for power
swings on the system resulting from the fault to settle.
4.5.12 De-Ionising Time
The de-ionisation time of a fault arc depends on circuit voltage, conductor spacing, fault
current and duration, wind speed and capacitive coupling from adjacent conductors. As
circuit voltage is generally the most significant, minimum de-ionising times can be specified
as in the Table below.
NOTE: For single pole HSAR, the capacitive current induced from the healthy
phases can increase the time taken to de-ionise fault arcs.

Line Voltage (kV) Minimum De-Energisation Time (s)

66 0.1
110 0.15
132 0.17
220 0.28
275 0.3
400 0.5

TABLE 14 - MINIMUM FAULT ARC DE-IONISING TIME (THREE POLE TRIPPING)

Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 151/220

Example Minimum Dead Time Calculation

The following circuit breaker and system characteristics are to be used:

• CB Operating time (Trip coil energised → Arc interruption): 50ms (a);

• CB Opening + Reset time (Trip coil energised → Trip mechanism reset): 200ms (b);

• Protection reset time: < 80ms (c);

• CB Closing time (Close command → Contacts make): 85ms (d).

De-ionising time for 220kV line:

• 280ms (e) for a three phase trip. (560ms for a single pole trip).
The minimum relay dead time setting is the greater of:
(a) + (c) = 50 + 80 = 130ms, to allow protection reset;
(a) + (e) - (d) = 50 + 280 - 85 = 245ms, to allow de-ionising (three pole);
= 50 + 560 - 85 = 525ms, to allow de-ionising (single pole).
In practice a few additional cycles would be added to allow for tolerances, so 3P Rcl - Dead
Time 1 could be chosen as ≥ 300ms, and 1P Rcl - Dead Time 1 could be chosen as ≥
600ms. The overall system dead time is found by adding (d) to the chosen settings, and
then subtracting (a). (This gives 335ms and 635ms respectively here).
4.5.13 Reclaim Timer Setting
A number of factors influence the choice of the reclaim timer, such as;

• Fault incidence/Past experience - Small reclaim times may be required where there
is a high incidence of recurrent lightning strikes to prevent unnecessary lockout for
transient faults.

• Spring charging time - For high speed autoreclose the reclaim time may be set
longer than the spring charging time. A minimum reclaim time of >5s may be needed
to allow the CB time to recover after a trip and close before it can perform another trip-
close-trip cycle. This time will depend on the duty (rating) of the CB. For delayed
autoreclose there is no need as the dead time can be extended by an extra CB
healthy check AR Inhibit Wind window time if there is insufficient energy in the CB.

• Switchgear Maintenance - Excessive operation resulting from short reclaim times can
mean shorter maintenance intervals.

• The Reclaim Time setting is always set greater than the tZ2 distance zone delay.
P44x/EN AP/E33 Application Notes

Page 152/220 MiCOM P441/P442 & P444

4.6 Circuit breaker state monitoring

An operator at a remote location requires a reliable indication of the state of the switchgear.
Without an indication that each circuit breaker is either open or closed, the operator has
insufficient information to decide on switching operations. The relay incorporates circuit
breaker state monitoring, giving an indication of the position of the circuit breaker, or, if the
state is unknown, an alarm is raised.
4.6.1 Circuit Breaker State Monitoring Features
MiCOM relays can be set to monitor normally open (52a) and normally closed (52b) auxiliary
contacts of the circuit breaker. Under healthy conditions, these contacts will be in opposite
states. Should both sets of contacts be open, this would indicate one of the following
conditions:

• Auxiliary contacts / wiring defective

• Circuit Breaker (CB) is defective

• CB is in isolated position
Should both sets of contacts be closed, only one of the following two conditions would apply:

• Auxiliary contacts / wiring defective

• Circuit Breaker (CB) is defective

If any of the above conditions exist, an alarm will be issued after a 5s time delay. A normally
open / normally closed output contact can be assigned to this function via the programmable
scheme logic (PSL). The time delay is set to avoid unwanted operation during normal
switching duties.
In the PSL CB AUX could be used or not, following the four options:
None
52A (1 or 3 optos if it is a single pole logic)
52B (1 or 3 optos)
Both 52A and 52B (2 optos or 6 optos)
Sol1: One opto used for 52a (3 poles breaker)

Sol2: One opto used for 52b (3 poles breaker)

Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 153/220

Sol3: Two optos used for 52a & 52b (3 poles breaker)

Sol4: Three optos used for 52a (1 pole breaker)

Sol5: Three optos used for 52b (1 pole breaker)

Sol6: Six optos used for 52a &52b (1 pole breaker)

FIGURE 108 – DIFFERENTS OPTOS/CB AUX SCHEMES

P44x/EN AP/E33 Application Notes

Page 154/220 MiCOM P441/P442 & P444

Where ‘None’ is selected no CB status will be available. This will directly affect any function
within the relay that requires this signal, for example CB control, auto-reclose, etc. Where
only 52a is used on its own then the relay will assume a 52b signal from the absence of the
52a signal. Circuit breaker status information will be available in this case but no discrepancy
alarm will be available. The above is also true where only a 52b is used. If both 52a and 52b
are used then status information will be available and in addition a discrepancy alarm will be
possible, according to the following table. 52a and 52b inputs are assigned to relay opto-
isolated inputs via the PSL.

Auxiliary Contact Position CB State Detected Action

52a 52b
Open Closed Breaker Open Circuit breaker healthy
Closed Open Breaker Closed Circuit breaker healthy
Closed Closed CB Failure Alarm raised if the condition
persists for greater than 5s
Open Open State Unknown Alarm raised if the condition
persists for greater than 5s

Where single pole tripping is used (available on P442 and P444) then an open breaker
condition will only be given if all three phases indicate and open condition. Similarly for a
closed breaker condition indication that all three phases are closed must be given. For single
pole tripping applications 52a-A, 52a-B and 52a-C and/or 52b-A, 52b-B and 52b-C inputs
should be used.
With 52a&52b both present, the relay memorizes the last valid status of the 2 inputs
(52a=/52b). If no valid status is present (52a=52b) when the Alarm timer is issued
(value=150 msec), CBA_Status Alarm is activated. See Figure 109.
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 155/220

CNF_52b

CNF_52a

&
INP_52a_A &
S
Q
& R
INP_52b_A &
1 CBA_A
&

& & CBA_3P_C

xor

&
INP_52a_B &
S
Q 1 CBA_ANY
& R
INP_52b_B &
1 CBA_B
&

& & CBA_3P

xor

&
INP_52a_C & &
S
Q
& R
INP_52b_C &
1 CBA_C
&

CBA_Time_Alarm
& t
1 CBA_Status_Alarm
0
xor
150 ms

CBA_Time_Disc

1 t
INP_DISC CBA_Discrepancy
0
150 ms P0524ENa

FIGURE 109 - LOGICAL SCHEME OF CBAUX

CBA_A = Dead PoleA
CBA_B = Dead PoleB
CBA_C = Dead PoleC
CBA_3P_C = All Pole live
CBA_3P = All Pole Dead
CBA_ANY = Any Pole dead
CBA_Disc = Pole Discrepancy detection

INP_52a_A

INP_52a_A

CBA_A

CBA_STATUS_ALARM
P0525ENa

FIGURE 110 - NON COMPLEMENTARY OF 52a/52b NOT LONG ENOUGH FOR GETTING THE ALARM
P44x/EN AP/E33 Application Notes

Page 156/220 MiCOM P441/P442 & P444

INP_52a_A

INP_52b_A

CBA_A

CBA_STATUS_ALARM
P0526ENa

FIGURE 111 - COMPLEMENTARY OF 52a/52b IS LONG ENOUGH FOR GETTING THE ALARM

INP_52a_A

CBA_A

CBA_STATUS_ALARM
P0527ENa

FIGURE 112 - WITH ONE OPTO 52a- POLE DEAD LOGIC

INP_52b_A

CBA_A

CBA_STATUS_ALARM
P0528ENa

FIGURE 113 - WITH ONE OPTO 52b – POLE DEAD LOGIC

4.6.2 Inputs / outputs DDB for CB logic:
4.6.2.1 Inputs

External TripA
External TripB
External TripC
From External Protection Devices (via Opto Inputs)- see General trip logic Figure 94.
If these optos inputs are assigned as External Trip A, External Trip B and External Trip C
– their change will update the CB Operation counter.
(External trip is integrated in the DDB: Any Trip.No Dwell timer is associated as for an
internal trip. (see Figure 94: trip logic)

CB aux A(52a)
CB aux B(52a)
CB aux C(52a)
CB aux A(52b)
CB aux B(52b)
CB aux C(52b)
The DDB CB Aux if assigned to an opto input in the PSL and when energized, will be used
for Any pole dead & All pole dead internal logic & Discrepency logic

CB Discrepancy
Used for internal CBA_Disc issued by external (opto) or internal detection (CB Aux)
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 157/220

4.6.2.2 Outputs

CB Status Alarm
Picks up when CB Discrepancy status is detected after CBA timer issued externally by opto
or internally by CB Aux

CB aux A
CB aux B
CB aux C
Pole A+B+C detected Dead pole by internal logic or CB status

Any Pole Dead

The DDB Any Pole Dead if assigned in the PSL, indicates that one or more poles is open

All Pole Dead

The DDB All Pole Dead if assigned in the PSL, indicates that all pole are dead (All 3 poles
are open)
4.7 Circuit breaker condition monitoring
Periodic maintenance of circuit breakers is necessary to ensure that the trip circuit and
mechanism operate correctly, and also that the interrupting capability has not been
compromised due to previous fault interruptions. Generally, such maintenance is based on a
fixed time interval, or a fixed number of fault current interruptions. These methods of
monitoring circuit breaker condition give a rough guide only and can lead to excessive
maintenance.
The relays record various statistics related to each circuit breaker trip operation, allowing a
more accurate assessment of the circuit breaker condition to be determined. These
monitoring features are discussed in the following section.
4.7.1 Circuit Breaker Condition Monitoring Features
For each circuit breaker trip operation the relay records statistics as shown in the following
table taken from the relay menu. The menu cells shown are counter values only. The
Min/Max values in this case show the range of the counter values. These cells can not be
set:

Menu text Default setting Setting range Step size

Min Max
CB CONDITION
CB Operations 0 0 10000 1
{3 pole tripping}
CB A Operations 0 0 10000 1
{1 & 3 pole tripping}
CB B Operations 0 0 10000 1
{1 & 3 pole tripping}
CB C Operations 0 0 10000 1
{1 & 3 pole tripping}
Total IA Broken 0 0 25000In^ 1
Total IB Broken 0 0 25000In^ 1
Total IC Broken 0 0 25000In^ 1In^
CB Operate Time 0 0 0.5s 0.001
Reset All Values No Yes, No
P44x/EN AP/E33 Application Notes

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The above counters may be reset to zero, for example, following a maintenance inspection
and overhaul.
The following table, detailing the options available for the CB condition monitoring, is taken
from the relay menu. It includes the setup of the current broken facility and those features
which can be set to raise an alarm or CB lockout.

Menu text Default setting Setting range Step size

Min Max
CB MONITOR SETUP Default Min Max Step
Broken I^ 2 1 2 0.1
I^ Maintenance Alarm Disabled Alarm Disabled, Alarm Enabled
I^ Maintenance 1000In^ 1In^ 25000In^ 1In^
I^ Lockout Alarm Disabled Alarm Disabled, Alarm Enabled
I^ Lockout 2000In^ 1In^ 25000In^ 1In^
N° CB Ops Maint Alarm Disabled Alarm Disabled, Alarm Enabled
N° CB Ops Maint 10 1 10000 1
N° CB Ops Lock Alarm Disabled Alarm Disabled, Alarm Enabled
N° CB Ops Lock 20 1 10000 1
CB Time Maint Alarm Disabled Alarm Disabled, Alarm Enabled
CB Time Maint 0.1s 0.005s 0.5s 0.001s
CB Time Lockout Alarm Disabled Alarm Disabled, Alarm Enabled
CB Time Lockout 0.2s 0.005s 0.5s 0.001s
Fault Freq Lock Alarm Disabled Alarm Disabled, Alarm Enabled
Fault Freq Count 10 0 9999 1
Fault Freq Time 3600s 0 9999s 1s

The circuit breaker condition monitoring counters will be updated every time the relay issues
a trip command.One counter is incremented by phase,.the highest counter value is
compared to two thresholds values settable (value n):
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 159/220

Maintenance Alarm or Lock Out Alarm can be generated.

A pre-lock out Alarm is generated at value n-1.
All counters can be re-initiated with the command Reset all values (by HMI)
In cases where the breaker is tripped by an external protection device it is also possible to
update the CB condition monitoring. This is achieved by allocating one of the relays opto-
isolated inputs (via the programmable scheme logic) to accept a trigger from an external
device. The signal that is mapped to the opto is called ‘External TripA or B or C’.

Note that when in Commissioning test mode the CB condition monitoring counters will not be
updated.
4.7.2 Setting guidelines

Setting the Σ I^ Thresholds

Where overhead lines are prone to frequent faults and are protected by oil circuit breakers
(OCB’s), oil changes account for a large proportion of the life cycle cost of the switchgear.
Generally, oil changes are performed at a fixed interval of circuit breaker fault operations.
However, this may result in premature maintenance where fault currents tend to be low, and
hence oil degradation is slower than expected. The Σ I^ counter monitors the cumulative
severity of the duty placed on the interrupter allowing a more accurate assessment of the
circuit breaker condition to be made.

For OCB’s, the dielectric withstand of the oil generally decreases as a function of Σ I2t. This
is where ‘I’ is the fault current broken, and ‘t’ is the arcing time within the interrupter tank (not
the interrupting time). As the arcing time cannot be determined accurately, the relay would
normally be set to monitor the sum of the broken current squared, by setting ‘Broken I^’ = 2.
For other types of circuit breaker, especially those operating on higher voltage systems,
practical evidence suggests that the value of ‘Broken I^’ = 2 may be inappropriate. In such
applications ‘Broken I^’ may be set lower, typically 1.4 or 1.5. An alarm in this instance may
be indicative of the need for gas/vacuum interrupter HV pressure testing, for example.
The setting range for ‘Broken I^’ is variable between 1.0 and 2.0 in 0.1 steps. It is
imperative that any maintenance programme must be fully compliant with the switchgear
manufacturer’s instructions.
4.7.3 Setting the Number of Operations Thresholds
Every operation of a circuit breaker results in some degree of wear for its components.
Thus, routine maintenance, such as oiling of mechanisms, may be based upon the number
of operations. Suitable setting of the maintenance threshold will allow an alarm to be raised,
indicating when preventative maintenance is due. Should maintenance not be carried out,
the relay can be set to lockout the autoreclose function on reaching a second operations
threshold. This prevents further reclosure when the circuit breaker has not been maintained
to the standard demanded by the switchgear manufacturer’s maintenance instructions.
P44x/EN AP/E33 Application Notes

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Certain circuit breakers, such as oil circuit breakers (OCB’s) can only perform a certain
number of fault interruptions before requiring maintenance attention. This is because each
fault interruption causes carbonising of the oil, degrading its dielectric properties. The
maintenance alarm threshold (N° CB Ops Maint) may be set to indicate the requirement for
oil sampling for dielectric testing, or for more comprehensive maintenance. Again, the
lockout threshold (N° CB Ops Lock) may be set to disable autoreclosure when repeated
further fault interruptions could not be guaranteed. This minimises the risk of oil fires or
explosion.
4.7.4 Setting the Operating Time Thresholds
Slow CB operation is also indicative of the need for mechanism maintenance. Therefore,
alarm and lockout thresholds (CB Time Maint / CB Time Lockout) are provided and are
settable in the range of 5 to 500ms. This time is set in relation to the specified interrupting
time of the circuit breaker.
4.7.5 Setting the Excessive Fault Frequency Thresholds
A circuit breaker may be rated to break fault current a set number of times before
maintenance is required. However, successive circuit breaker operations in a short period of
time may result in the need for increased maintenance. For this reason it is possible to set a
frequent operations counter on the relay which allows the number of operations (Fault Freq
Count) over a set time period (Fault Freq Time) to be monitored. A separate alarm and
lockout threshold can be set.
4.7.6 Inputs/Outputs for CB Monitoring logic
4.7.6.1 Inputs

Reset Lock Out

Provides a reset of the CB monitoring lock out (all counters & values are reset)

Reset All Values

Provides a reset of the CB monitoring (all counters & values are reset)
4.7.6.2 Outputs

I^Maint Alarm
An alarm maintenance is issued when the maximum broken current (1st level) calculated by
the CB monitoring function is reached

I^Lock Out Alarm

An alarm Lock Out is issued when the maximum broken current (2nd level) calculated by the
monitoring function is reached

CB Ops Maint
An alarm is issued when the maximum of CB operations is reached [initiated by internal (any
protection function) or external trip (via opto)] (1st level:CB Ops Maint)

CB Ops Lockout
An alarm is issued when the maximum of CB operations is reached [initiated by internal or
external trip] (2nd level:CB Ops Lock)

CB Op Time Maint
An alarm is issued when the operating tripping time on any phase pass over the CB Time
Maint adjusted in MiCOM S1 (slowest pole detection calculated by I< from CB Fail logic)

CB Op Time Lock
An alarm is issued when the operating tripping time on any phase pass over the CB Time
Lockout adjusted in MiCOM S1 (slowest pole detection calculated by I< from CB Fail logic)
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 161/220

FF Pre Lockout
An alarm is issued at (n-1) value in the counters of Main lock out or Fault frequency

FF Lock
An alarm is issued at (n) value in the counters of Main lock out or Fault frequency

Lockout Alarm
An alarm is issued with: CBC Unhealthy or CBC No check sync or CBC Fail to close or CBC
fail to trip or FF Lock or CB Op Time Lock or CB Ops Lock
4.8 Circuit Breaker Control
The relay includes the following options for control of a single circuit breaker:

• Local tripping and closing, via the relay menu

• Local tripping and closing, via relay opto-isolated inputs

• Remote tripping and closing, using the relay communications

It is recommended that separate relay output contacts are allocated for remote circuit
breaker control and protection tripping. This enables the control outputs to be selected via a
local/remote selector switch as shown in Figure 114. Where this feature is not required the
same output contact(s) can be used for both protection and remote tripping.

Protection + ve
trip
Remote
control
trip Trip
0
Remote close
control
close

Local
Remote

Trip Close
ve
P3078ENa

FIGURE 114 - REMOTE CONTROL OF CIRCUIT BREAKER

The following table is taken from the relay menu and shows the available settings and
commands associated with circuit breaker control. Depending on the relay model some of
the cells may not be visible:
P44x/EN AP/E33 Application Notes

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Menu text Default setting Setting range Step size

Min Max
CB CONTROL
CB Control by Disabled Disabled, Local, Remote, Local+Remote,
Opto, Opto+local, Opto+Remote,
Opto+Rem+local
Close Pulse Time 0.5s 0.1s 10s 0.01s
Trip Pulse Time 0.5s 0.1s 5s 0.01s
Man Close Delay 10s 0.01s 600s 0.01s
Healthy Window 5s 0.01s 9999s 0.01s
C/S Window 5s 0.01s 9999s 0.01s
A/R Single Pole Disabled Disabled, Enabled
{1&3 pole A/R only} {Refer to Autoreclose notes for further
information}
A/R Three Pole Disabled Disabled, Enabled
{Refer to Autoreclose notes for further
information}

If AR Enable in MiCOM S1 (2 additive lines):

(*) For P442 – P444 only

WARNING: Must be enabled for validating the AR function (if TPAR/SPAR optos are
assigned in the PSL, these inputs have a higher priority from the MiCOM S1
settings).
The AR single and three poles mode could be enabled in the menu "CB
control" via MiCOM S1 or by the front panel.
However, if the DDB signals TPAR/SPAR have been assigned in the PSL,
these both inputs have a higher priority and depending of their status, will
enable/disable the single or three poles AR function independing of the
MiCOM S1 or front LCD settings.
Remark: If TPAR is disable, the Dead Time 2 is not used when SPAR logic
manages only 1PAR.
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 163/220

SUP_Trip_Loc
&
1
CBC_Local_Control
&
SUP_Close_Loc

SUP_Trip_Rem
&

CBC_Remote_Control
&
SUP_Close_Rem

INP_CB_Trip_Man
&

CBC_Input_Control
1
&
INP_CB_Man

& S CBC_Trip_Pulse
CBA_3P_C
Q CBC_Trip_3P
1
R
t
Pulsed output latched in UI
0 &
CBC_Failed_To_Trip

CBA_3P

CBA_Status_Alarm
& S
Q CBC_Close_In_Progress
AR_Cycle_1P R
1
INP_AR_Cycle_1P t
0
1
AR_Cycle_3P 1 CBC_Delay_Close

INP_AR_Cycle_3P & S
Q
CBA_3P R

CBA_Disc

TRIP_Any
1

INP_AR_Close
Pulsed output latched in UI

AR_Close 1 & CBC_ Fail_To_Close

t
0
R
Q CBC_Recl_3P
S CBC_Close_Pulse

CBA_Any

&
INP_CB_Healthy

CBC_Healthy_Window

t
0 & CBC_UnHeathly

CBC_CS_Window

t
0 & CBC_No_Check_Syn
SYNC

P0529ENa

FIGURE 115 - CB CONTROL LOGIC

A manual trip will be authorised if the circuit breaker has been initially closed. Likewise, a
close command can only be issued if the CB is initially open.
Therefor it will be necessary to use the breaker positions 52a and/or 52b contacts via PSL. If
no CB auxiliary contacts are available no CB control (manual or auto) will be possible. (See
the different solutions proposed in the CBAux logic section 4.6.1)
Once a CB Close command is initiated the output contact can be set to operate following a
user defined time delay (‘Man Close Delay’). This would give personnel time to move away
from the circuit breaker following the close command. This time delay will apply to all manual
CB Close commands.
P44x/EN AP/E33 Application Notes

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The length of the trip or close control pulse can be set via the ‘ManualTrip Pulse Time’ and
‘Close Pulse Time’ settings respectively. These should be set long enough to ensure the
breaker has completed its open or close cycle before the pulse has elapsed.
NOTE : The manual close commands for each user interface are found in the
System Data column of the menu.

If an attempt to close the breaker is being made, and a protection trip signal is generated,
the protection trip command overrides the close command.
Where the check synchronism function is set, this can be enabled to supervise manual
circuit breaker close commands. A circuit breaker close output will only be issued if the
check synchronism criteria are satisfied. A user settable time delay is included (‘C/S
Window’) for manual closure with check synchronising. If the checksynch criteria are not
satisfied in this time period following a close command the relay will lockout and alarm.
In addition to a synchronism check before manual reclosure there is also a CB Healthy
check if required. This facility accepts an input to one of the relays opto-isolators to indicate
that the breaker is capable of closing (circuit breaker energy for example). A user settable
time delay is included (‘Healthy Window’) for manual closure with this check. If the CB does
not indicate a healthy condition in this time period following a close command then the relay
will lockout and alarm.
Where auto-reclose is used it may be desirable to block its operation when performing a
manual close. In general, the majority of faults following a manual closure will be permanent
faults and it will be undesirable to auto-reclose. The "man close" input without CB Control
selected OR the "CBClose in progress" with CB control enabled: will initiate the SOTF logic
for which auto-reclose will be disabled following a manual closure of the breaker during
500msec (see SOTF logic in section 2.12.1, Figure 35).
If the CB fails to respond to the control command (indicated by no change in the state of CB
Status inputs) a ‘CB Fail Trip Control’ or ‘CB Fail Close Control’ alarm will be generated
after the relevant trip or close pulses have expired. These alarms can be viewed on the relay
LCD display, remotely via the relay communications, or can be assigned to operate output
contacts for annunciation using the relays programmable scheme logic (PSL).

CBA_3P_C

SUP_Trip OR
INP_CB_Trip_Man
0.1 to 5 Sec
CBC_Trip_3P

CBC_Failed_To_Trip
P0560ENa

FIGURE 116 - STATUS OF CB IS INCORRECT CBA3P C (3POLES ARE CLOSED) STAYS – AN ALARM
IS GENERATED “CB FAIL TO TRIP” (SEE ALSO FIGURE 109 & FIGURE 115)
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 165/220

CBA_3P

SUP_Close OR
INP_CB_Man

CBC_Close_In_Progress

0 to 60 Sec
0.1 to 10 Sec
CBC_Recl_3P

CBC_ Fail_To_Close

P0561ENa

FIGURE 117 - STATUS OF CB IS INCORRECT CBA3P (3POLES ARE OPENED) STAYS – AN ALARM IS
GENERATED “CB FAIL TO CLOSE” (SEE ALSO FIGURE 109 & FIGURE 115)
Note that the ‘Healthy Window’ timer and ‘C/S Window’ timer set under this menu section are
applicable to manual circuit breaker operations only. These settings are duplicated in the
Auto-reclose menu for Auto-reclose applications.
The ‘Lockout Reset’ and ‘Reset Lockout by’ setting cells in the menu are applicable to CB
Lockouts associated with manual circuit breaker closure, CB Condition monitoring (Number
of circuit breaker operations, for example) and auto-reclose lockouts.
4.9 Event Recorder
The relay records and time tags up to 250 events and stores them in non-volatile (battery
backed up – installed behind the plastic cover in front panel of the relay)) memory. This
enables the system operator to establish the sequence of events that occurred within the
relay following a particular power system condition, switching sequence etc. When the
available space is exhausted, the oldest event is automatically overwritten by the new one
(First in first out).
The real time clock within the relay provides the time tag to each event, to a resolution of
1ms.
The event records are available for viewing either via the frontplate LCD or remotely, via the
communications ports or via MiCOM S1 with a PC. connected to the relay (event extracted
from relay & loaded in PC):
1. Established the communication [ Device\open connection\address (always1 by serial
front port\Password (AAAA) ]

FIGURE 118
2. Select the extraction of events:
P44x/EN AP/E33 Application Notes

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3. Events must be listed, identified (file named) & Stored

Local viewing on the LCD is achieved in the menu column entitled ‘VIEW RECORDS’. This
column allows viewing of event, fault and maintenance records and is shown below:-

VIEW RECORDS
LCD Reference Description
Select Event Setting range from 0 to 249.
This selects the required event record from the possible 250 that
may be stored. A value of 0 corresponds to the latest event and so
on.
Time & Date Time & Date Stamp for the event given by the internal Real Time
Clock
Event Text Up to 32 Character description of the Event (refer to following
sections)
Event Value Up to 32 Bit Binary Flag or integer representative of the Event
(refer to following sections)
Select Fault Setting range from 0 to 4.
This selects the required fault record from the possible 5 that may
be stored. A value of 0 corresponds to the latest fault and so on.
The following cells show all the fault flags, protection starts,
protection trips, fault location, measurements etc. associated with
the fault, i.e. the complete fault record.
Select Report Setting range from 0 to 4.
This selects the required maintenance report from the possible 5
that may be stored. A value of 0 corresponds to the latest report
and so on.
Report Text Up to 32 Character description of the occurrence (refer to following
sections)
Report Type These cells are numbers representative of the occurrence. They
form a specific error code which should be quoted in any related
correspondence to AREVA T&D.
Report Data
Reset Indication Either Yes or No. This serves to reset the trip LED indications
provided that the relevant protection element has reset.

For extraction from a remote source via communications, refer to Chapter P44x/EN CM,
(Commissioning) where the procedure is fully explained.
Note that a full list of all the event types and the meaning of their values is given in chapter
P44x/EN GC (Configurations Mapping).
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 167/220

Types of Event
An event may be a change of state of a control input or output relay, an alarm condition,
setting change etc. The following sections show the various items that constitute an event:-

FIGURE 119 - FILE\OPEN\EVENTS FILE

4.9.1 Change of state of opto-isolated inputs.
If one or more of the opto (logic) inputs has changed state since the last time that the
protection algorithm ran, the new status is logged as an event. When this event is selected to
be viewed on the LCD, three applicable cells will become visible as shown below;

Time & Date of Event

“LOGIC INPUTS”
“Event Value
0101010101010101”

The Event Value is an 8 or 16 bit word showing the status of the opto inputs, where the least
significant bit (extreme right) corresponds to opto input 1 etc. The same information is
present if the event is extracted and viewed via PC.
4.9.2 Change of state of one or more output relay contacts.
If one or more of the output relay contacts has changed state since the last time that the
protection algorithm ran, then the new status is logged as an event. When this event is
selected to be viewed on the LCD, three applicable cells will become visible as shown below;

Time & Date of Event

“OUTPUT CONTACTS”
“Event Value
010101010101010101010”

The Event Value is a 7, 14 or 21 bit word showing the status of the output contacts, where
the least significant bit (extreme right) corresponds to output contact 1 etc. The same
information is present if the event is extracted and viewed via PC.
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4.9.3 Relay Alarm conditions.

Any alarm conditions generated by the relays will also be logged as individual events. The
following table shows examples of some of the alarm conditions and how they appear in the
event list:-

Alarm Condition Resulting Event

Event Text Event Value
Battery Fail Battery Fail ON/OFF Number from 0 to 31
Field Voltage Fail Field V Fail ON/OFF Number from 0 to 31
Setting group via opto invalid Setting Grp Invalid ON/OFF Number from 0 to 31
Protection Disabled Prot'n Disabled ON/OFF Number from 0 to 31
Frequency out of range Freq out of Range ON/OFF Number from 0 to 31
VTS Alarm VT Fail Alarm ON/OFF Number from 0 to 31
CB Trip Fail Protection CB Fail ON/OFF Number from 0 to 31

The previous table shows the abbreviated description that is given to the various alarm
conditions and also a corresponding value between 0 and 31. This value is appended to
each alarm event in a similar way as for the input and output events previously described. It
is used by the event extraction software, such as MiCOM S1, to identify the alarm and is
therefore invisible if the event is viewed on the LCD. Either ON or OFF is shown after the
description to signify whether the particular condition has become operated or has reset.
4.9.4 Protection Element Starts and Trips
Any operation of protection elements, (either a start or a trip condition), will be logged as an
event record, consisting of a text string indicating the operated element and an event value.
Again, this value is intended for use by the event extraction software, such as MiCOM S1,
rather than for the user, and is therefore invisible when the event is viewed on the LCD.
4.9.5 General Events
A number of events come under the heading of ‘General Events’ - an example is shown
below:-

Nature of Event Displayed Text in Event Record Displayed Value

Level 1 Password Modified PW1 Edited UI, F or R 0
Either from User Interface,
Front or Rear Port

A complete list of the ‘General Events’ is given in chapter P44x/EN GC.

Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 169/220

4.9.6 Fault Records

Each time a fault record is generated, an event is also created. The event simply states that
a fault record was generated, with a corresponding time stamp.
Note that viewing of the actual fault record is carried out in the ‘Select Fault’ cell further down
the ‘VIEW RECORDS’ column, which is selectable from up to 5 records. These records
consist of fault flags, fault location, fault measurements etc. Also note that the time stamp
given in the fault record itself will be more accurate than the corresponding stamp given in
the event record as the event is logged some time after the actual fault record is generated.
4.9.7 Maintenance Reports
Internal failures detected by the self monitoring circuitry, such as watchdog failure, field
voltage failure etc. are logged into a maintenance report. The Maintenance Report holds up
to 5 such ‘events’ and is accessed from the ‘Select Report’ cell at the bottom of the ‘VIEW
RECORDS’ column.
Each entry consists of a self explanatory text string and a ‘Type’ and ‘Data’ cell, which are
explained in the menu extract at the beginning of this section and in further detail in
Appendix A.
Each time a Maintenance Report is generated, an event is also created. The event simply
states that a report was generated, with a corresponding time stamp.
Error codes are in hexadecimal format and must be recalculated in decimal format to check
with the table in chapter P44x/EN GC.
4.9.8 Setting Changes
Changes to any setting within the relay are logged as an event. Two examples are shown in
the following table:

Type of Setting Change Displayed Text in Event Record Displayed Value

Control/Support Setting C & S Changed 0
Group 1 Change Group 1 Changed 1

NOTE: Control/Support settings are communications, measurement, CT/VT

ratio settings etc, which are not duplicated within the four setting
groups. When any of these settings are changed, the event record is
created simultaneously. However, changes to protection or
disturbance recorder settings will only generate an event once the
settings have been confirmed at the ‘setting trap’.
4.9.9 Resetting of Event / Fault Records
If it is required to delete either the event, fault or maintenance reports, this may be done from
within the ‘RECORD CONTROL’ column.
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4.9.10 Viewing Event Records via MiCOM S1 Support Software

When the event records are extracted and viewed on a PC they look slightly different than
when viewed on the LCD. The following shows an example of how various events appear
when displayed using MiCOM S1:-

− Monday 03 November 1998 15:32:49 GMT I>1 Start ON 2147483881

AREVA : MiCOM
Model Number: P441
Address: 001 Column: 00 Row: 23
Event Type: Protection operation

− Monday 03 November 1998 15:32:52 GMT Fault Recorded 0

AREVA : MiCOM
Model Number: P441
Address: 001 Column: 01 Row: 00
Event Type: Fault record

− Monday 03 November 1998 15:33:11 GMT Logic Inputs 00000000

AREVA : MiCOM
Model Number: P441
Address: 001 Column: 00 Row: 20
Event Type: Logic input changed state

− Monday 03 November 1998 15:34:54 GMT Output Contacts 0010000

AREVA : MiCOM
Model Number: P441
Address: 001 Column: 00 Row: 21
Event Type: relay output changed state
As can be seen, the first line gives the description and time stamp for the event, whilst the
additional information that is displayed below may be collapsed via the +/- symbol.
For further information regarding events and their specific meaning, refer to chapter
P44x/EN GC.
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FIGURE 120
4.10 Disturbance recorder
The integral disturbance recorder has an area of memory specifically set aside for record
storage. The number of records that may be stored is dependent upon the selected
recording duration but the relays typically have the capability of storing a minimum of 20
records, each of 10.5 second duration.
NOTE: 1. Compressed Disturbance Recorder used for Kbus/Modbus/DNP3
reach that typical size value (10.5 sec duration)
2. Uncompressed Disturbance Recorder used for IEC 60870-5/103
could be limited to 2 or 3 secondes.
Disturbance records continue to be recorded until the available memory is exhausted, at
which time the oldest record(s) are overwritten to make space for the newest one.
The recorder stores actual samples which are taken at a rate of 24 samples per cycle.
Each disturbance record consists of eight analogue data channels and thirty-two digital data
channels. Note that the relevant CT and VT ratios for the analogue channels are also
extracted to enable scaling to primary quantities).
P44x/EN AP/E33 Application Notes

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The ‘DISTURBANCE RECORDER’ menu column is shown below:

Menu text Default setting Setting range Step size

Min Max
DISTURB RECORDER
Duration 1.5s 0.1s 10.5s 0.01s
Trigger Position 33.3% 0 100% 0.1%
Trigger Mode Single Single or Extended
Analog Channel 1 VA VA, VB, VC, IA, IB, IC, IN
Analog Channel 2 VB VA, VB, VC, IA, IB, IC, IN
Analog Channel 3 VC VA, VB, VC, IA, IB, IC, IN
Analog Channel 4 VN VA, VB, VC, IA, IB, IC, IN
Analog Channel 5 IA VA, VB, VC, IA, IB, IC, IN
Analog Channel 6 IB VA, VB, VC, IA, IB, IC, IN
Analog Channel 7 IC VA, VB, VC, IA, IB, IC, IN
Analog Channel 8 IN VA, VB, VC, IA, IB, IC, IN
Digital Inputs 1 to 32 Relays 1 to 14/21 Any of 14 or 21 O/P Contacts
and or
Opto’s 1 to 8/16 Any of 8 or 16 Opto Inputs
or
Internal Digital Signals
Inputs 1 to 32 Trigger No Trigger except No Trigger, Trigger L/H, Trigger H/L
Dedicated Trip
Relay O/P’s which
are set to Trigger
L/H

Note
The available analogue and digital signals may differ between relay types and models and
so the individual courier database in Appendix should be referred to when determining
default settings etc.
The pre and post fault recording times are set by a combination of the ‘Duration’ and ‘Trigger
Position’ cells. ‘Duration’ sets the overall recording time and the ‘Trigger Position’ sets the
trigger point as a percentage of the duration. For example, the default settings show that the
overall recording time is set to 1.5s with the trigger point being at 33.3% of this, giving 0.5s
pre-fault and 1s post fault recording times.
If a further trigger occurs whilst a recording is taking place, the recorder will ignore the trigger
if the ‘Trigger Mode’ has been set to ‘Single’. However, if this has been set to ‘Extended’, the
post trigger timer will be reset to zero, thereby extending the recording time.
As can be seen from the menu, each of the analogue channels is selectable from the
available analogue inputs to the relay. The digital channels may be mapped to any of the
opto isolated inputs or output contacts, in addition to a number of internal relay digital
signals, such as protection starts, LED’s etc. The complete list of these signals may be found
by viewing the available settings in the relay menu or via a setting file in MiCOM S1. Any of
the digital channels may be selected to trigger the disturbance recorder on either a low to
high or a high to low transition, via the ‘Input Trigger’ cell. The default trigger settings are that
any dedicated trip output contacts (e.g. relay 3) will trigger the recorder.
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 173/220

FIGURE 121
Trigger choices:

(Minimum one trigger condition must be present ; for providing Drec file.)
It is not possible to view the disturbance records locally via the LCD; they must be extracted
using suitable software such as MiCOM S1. This process is fully explained in Chapter 6.

(Events or Disturbances can be extracted)

This message is displayed if the memory is empty (control in that case the trigger condition):
P44x/EN AP/E33 Application Notes

Page 174/220 MiCOM P441/P442 & P444

After extraction the Drec file can be displayed by the viewer integrated in MiCOM S1(See
Commissioning test section – chap CT)

Click down to select :

Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 175/220

5. NEW ADDITIONAL FUNCTIONS – VERSION B1.X

5.1 Maximum of Residual Power Protection – Zero Sequence Power Protection
5.1.1 Function description
The aim of protection is to provide the system with selective and autonomous protection
against resistive Phase to ground faults. High resistive faults such as vegetation fires cannot
be detected by distance protection.
When a phase to ground fault occurs, the fault can be considered as a zero-sequence power
generator. Zero-sequence voltage is at maximum value at the fault point. Zero-sequence
power is, therefore, also at maximum value at the same point. Supposing that zero-
sequence current is constant, zero-sequence power will decrease along the lines until null
value at the source’s neutral points (see below).

PA PB
Z os1 x . Zol (1-x).Zol Z os2

P3100XXa

With: Zos1: Zero-sequence source side 1 impedance of

Zol: Zero-sequence line impedance
Zos2: Zero-sequence source side2 impedance of
x: Distance to the fault From PA

Po Vo
1 1

0,5 0,5

0 0

PA Fault PB
P3101ENa

Selective fault clearance of the protection for forward faults is provided by the power
measurement combined with a time-delay inversely proportional to the measured power.
The protection does not send any trip commands for reverse faults.
In compliance with sign conventions (the zero-sequence power flows from the fault towards
the sources) and with a mean characteristic angle of the zero-sequence source impedances
of the equal to 75°, the measured power is determined by the following formula:

Sr = Vrr.m.s x Irr.m.s x cos(ϕ - ϕ0)

With: ϕ: Phaseshift between Vr and Ir

ϕ0: 255° or – 75°

Vrr.m.s, Irr.m.s: R.M.S values of the residual voltage and current
The Vr and Ir values are filtered in order to eliminate the effect of the 3rd and 5th harmonics.
P44x/EN AP/E33 Application Notes

Page 176/220 MiCOM P441/P442 & P444

Sr > Po Fixed Time

Delay

P3837ENa

3-pole trip is sent out when the residual power threshold “Residual Power" is overshot, after
a time-delay "Basis Time Delay" and a IDMT time-delay adjusted by the “K” time delay
factor.
The basis time-delay is set at a value greater than the 2nd stage time of the distance
protection of the concerned feeder if the 3-pole trip is active, or at a value greater than the
single-phase cycle time if single-pole autorecloser shots are active.
The IDMT time-delay is determined by the following formula:
T(s) = K x (Sref/Sr)
With: K: Adjustable time constant from 0 to 2sec (Time delay factor)
Sref: Reference residual power at:
10 VA for In = 1A
50 VA for In = 5A
Sr: Residual power generated by the fault
The following chart shows the adjustment menu for the zero-sequence residual overcurrent
protection, the adjustment ranges and the default in-factory adjustments.

Menu text Default setting Setting range Step size

Min Max
Group1
ZERO-SEQ. POWER
Zero Seq. Power Status Activated Activated / Disabled N/A
K Time Delay Factor 0 0 2 0.2
Basis Time Delay 1sec 0sec 10sec 0.01sec
Residual Current 0.1 x In 0.05 x In 1 x In 0.01 x In
Po threshold 510mVA 300mVA 6.0VA 30.0mVA
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 177/220

5.1.2 Settings & DDB cells assigned to zero sequence power (ZSP) function

DDB cell INPUT associated:

The ZSP TIMER BLOCK cell if assigned to an opto input in a

dedicated PSL , Zero Sequence Power function will start, but will not perform a trip
command - the associated timer will be blocked
DDB cell OUTPUT associated:

The ZSP START cell at 1 indicates that the Zero Sequence

Power function has started - in the same time, it indicates that the timers associated have
started and are running (fixed one first and then IDMT timer)

The ZSP TRIP cell at 1 indicates that the Zero Sequence Power
function has performed a trip command (after the start and when associated timers are
issued)
P44x/EN AP/E33 Application Notes

Page 178/220 MiCOM P441/P442 & P444

5.2 Capacitive Voltage Transformers Supervision (CVT)

5.2.1 Function description
This CVT supervision will detect the degradation of one or several capacitors of voltage
dividers. It is based on permanent detection of residual voltage.
A “CVT fault” signal is sent out, after a time-delay T which can be set at between 0 and 300
seconds, if the conditions are as follows:

• The residual voltage is greater than the setting threshold during a delay greater then T

• The 3 phase-phase voltages have a value greater than 0.4 Un

Vab(t) Vab(t) > 0,8*Vn

S
Q
Vab(t) < 0,4*Vn R

Vbc(t) Vbc(t) > 0,8*Vn

S
Q
Vbc(t) < 0,4*Vn R

Vca(t) Vca(t) > 0,8*Vn

S
&T T
TCTs - Alarm
Q
Vca(t) < 0,4*Vn R

Vr(t) Vr(t) > SVr

P3102ENa

FIGURE 122 - BASIC CVT SUPERVISION DIAGRAM

The table below shows the CVT supervision settings menu, settings range and the default in-
factory settings.

Menu text Default setting Setting range Step size

Min Max
Group1
SUPERVISION
CVTS Status Activated Activated / Disabled N/A
CVTS VN> 1sec 0.5sec 22sec 0.5
CVTS Time Delay 100sec 0sec 300sec 0.01sec
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 179/220

5.2.2 Settings & DDB cells assigned to Capacitive Voltage Transformers Supervision (CVT)
function

FIGURE 123 - FOR ENABLING THE FUNCTION

FIGURE 124 – SETTINGS

DDB cell OUTPUT associated:

The CVT ALARM cell at 1 indicates that the residual voltage is

greater than the threshold adjusted in the settings, during a delay greater than the timer
adjusted in MiCOM S1. That alarm is also included in the general alarm.
P44x/EN AP/E33 Application Notes

Page 180/220 MiCOM P441/P442 & P444

6. PROGRAMMABLE SCHEME LOGIC DEFAULT SETTINGS

The relay includes programmable scheme logic (PSL)- one PSL by Group of settings
enabled (maximum 4 groups of PSLogic can be assigned in the relay)
The purpose of this logic is multi-functional and includes the following:

• Enables the mapping of opto-isolated inputs, relay output contacts and the
programmable LED’s.

• Provides relay output conditioning (delay on pick-up/drop-off, dwell time, latching or

self-reset).

• Fault Recorder start mapping, i.e. which internal signals initiate a fault record.

• Enables customer specific scheme logic to be generated through the use of the PSL
editor inbuilt into the MiCOM S1 support software.
Further information regarding editing and the use of PSL can be found in the MiCOM S1
user manual. The following section details the default settings of the PSL. Note that
changes to these defaults can only be carried out using the PSL editor and not via the relay
front-plate.
6.1 HOW TO USE PSL Editor?
OFF Line method:

− Open first the application free software delivered with the relay : MiCOM S1 (can be
also downloaded from the web)

− Open the PSL Editor part.

− Open a blancking scheme or a default scheme with the good model number
(File\New\Default Scheme or Blanck Scheme)

Selection of type of relay & model number is done in that window (Version software is
displayed for compatibility ) – Italian is available with model ?40X?
ON Line method:

− Communication with the relay can be started (Device\open

connection\address1\pword AAAA) and the PSL activated in the internal logic of the
relay can be extracted, displayed, modified and loaded again in the protection.
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 181/220

− Any group from 1 to 4 can be modified (ref of group must be validated before
resenting the file from PC to relay)

Before creating a dedicated PSL for covering customized application ; please refer to the
DDB description cell by cell (conditions of set & reset) in the table included in the annex A at
the end of that technical guide.
Some additive cells can be present regarding the type of model used by the software
embedded in the relay.

Software Version Model N°

A2.11 04
A3.3 06
A4.5 07
B1.2 09

The type of model used by the relay in the settings or PSL is displayed in the bottom of your
screen by that line:

and will inform about the :

− Model number used (last 2 digits:???07??)

− PSL activated for the logic of Group1

− Number of timers still available (15 on a total of 16)

− Number of contacts still available (7 on a total of 21 for P442 model)

− Number of leds still available (0 on 8 – if all already assigned in the PSL)

− Memory Capacity still available (decrease with the numbers of cells & logical gates
linked in the dedicated PSL)
(See also the section commissioning for deeper tools explanations)
P44x/EN AP/E33 Application Notes

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6.2 Logic input mapping

The default mappings for each of the opto-isolated inputs are as shown in the following table:

− Version A : Optos are in 48VDC polarised (can be energised with the internal field
voltage offered by the relay (–J7/J9-J8/J10 in a P441)

− Version B : Optos are universal and opto range can be selected in MiCOM S1 by:
Opto A - 48VDC:
The opto inputs are specified to operate between 30 and 60V to ensure there is enough
current flowing through the opto diode to guarantee operation with component tolerances,
temperature and CTR degradation over time.
Between 13-29V is the uncertainty band.
Below 12V, logical status is guaranteed Off
Opto B – Universal opto inputs:

Setting Guaranteed No Operation Guaranteed Operation

24/27 <16,2 >19,2
30/34 <20,4 >24,0
48/54 <32,4 >38,4
110/125 <75,0 >88,0
220/250 <150 >176,0

These margins ensure that ground faults on substation batteries do not create mal-operation
of the opto inputs.

Or “Custom” can be selected in the menu to offer the possibility to adjust a different voltage
pick-up for any optos inputs:
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 183/220

P44x/EN AP/E33 Application Notes

Page 184/220 MiCOM P441/P442 & P444

Opto
Input P441 Relay P442 Relay P444 Relay
N°
1 Channel Receive (Distance Channel Receive (Distance Channel Receive (Distance
or DEF) or DEF) or DEF)
2 Channel out of Service Channel out of Service Channel out of Service
(Distance or DEF) (Distance or DEF) (Distance or DEF)
3 MCB/VTS Line MCB/VTS Line MCB/VTS Line
(Z measurement-Dist) (Z measurement-Dist) (Z measurement-Dist)
4 Block Block Block
Autoreclose(LockOut) Autoreclose(LockOut) Autoreclose(LockOut)
5 Circuit Breaker Healthy Circuit Breaker Healthy Circuit Breaker Healthy
6 Circuit breaker Manual Circuit breaker Manual Circuit breaker Manual
Close external order Close external order Close external order
7 Reset Lockout Reset Lockout Reset Lockout
8 Disable Autoreclose (1pole Disable Autoreclose (1- Disable Autoreclose (1-
and 3poles) pole and 3poles) pole and 3poles)
9 Not allocated Not allocated
10 Not allocated Not allocated
11 Not allocated Not allocated
12 Not allocated Not allocated
13 Not allocated Not allocated
14 Not allocated Not allocated
15 Not allocated Not allocated
16 Not allocated Not allocated
17 Not allocated
18 Not allocated
19 Not allocated
20 Not allocated
21 Not allocated
22 Not allocated
23 Not allocated
24 Not allocated
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 185/220

6.3 Relay output contact mapping

The default mappings for each of the relay output contacts are as shown in the following
table (PSL are equivalent for P441/442/444):-

Relay
Contact P441 Relay P442 Relay P444 Relay
N°
1 TripA+B+C & Z1 TripA+B+C & Z1 TripA+B+C & Z1
2 Any Trip Phase A Any Trip Phase A Any Trip Phase A
3 Any Trip Phase B Any Trip Phase B Any Trip Phase B
4 Any Trip Phase C AnyTrip Phase C Any Trip Phase C
5 Signal send (Dist. or DEF) Signal send (Dist. or DEF) Signal send (Dist. or DEF)
6 Any Protection Start Any Protection Start Any Protection Start
7 Any Trip Any Trip Any Trip
8 General Alarm General Alarm General Alarm
9 DEF A+B+C Trip DEF A+B+C Trip DEF A+B+C Trip
+ IN>1Trip + IN>1Trip + IN>1Trip
+ IN>2Trip + IN>2Trip + IN>2Trip
10 Dist. Trip &Any Dist. Trip &Any Dist. Trip &Any
Zone&DistUnb CR Zone&DistUnb CR Zone&DistUnb CR
11 Autoreclose lockout Autoreclose lockout Autoreclose lockout
12 Autoreclose 1P+3P cycle Autoreclose 1P+3P cycle Autoreclose 1P+3P cycle
in progress in progress in progress
13 A/R Close A/R Close A/R Close
14 Power Swing Detected Power Swing Detected Power Swing Detected
15 Not allocated Not allocated
16 Not allocated Not allocated
17 Not allocated Not allocated
18 Not allocated Not allocated
19 Not allocated Not allocated
20 Not allocated Not allocated
21 Not allocated Not allocated
22 Not allocated Not allocated
23 Not allocated
24 Not allocated
25 Not allocated
26 Not allocated
27 Not allocated
28 Not allocated
29 Not allocated
30 Not allocated
31 Not allocated
32 Not allocated
Note that when 3 pole tripping is selected in the relay menu, all trip contacts: Trip A, Trip B,
Trip C, and Any Trip close simultaneously.
P44x/EN AP/E33 Application Notes

Page 186/220 MiCOM P441/P442 & P444

6.4 Relay output conditioning

The default conditioning for each of the relay output contacts are as shown in the following
table:

Relay
Contact P441 Relay P442 Relay P444 Relay
N°
1 Straight Straight Straight
2 Straight Straight Straight
3 Straight Straight Straight
4 Straight Straight Straight
5 Straight Straight Straight
6 Straight Straight Straight
7 Straight Straight Straight
8 Straight Straight Straight
9 Straight Straight Straight
10 Straight Straight Straight
11 Straight Straight Straight
12 Straight Straight Straight
13 Straight Straight Straight
14 Straight Straight Straight
15 Not allocated Not allocated
16 Not allocated Not allocated
17 Not allocated Not allocated
18 Not allocated Not allocated
19 Not allocated Not allocated
20 Not allocated Not allocated
21 Not allocated Not allocated
22 Not allocated Not allocated
23 Not allocated
24 Not allocated
25 Not allocated
26 Not allocated
27 Not allocated
28 Not allocated
29 Not allocated
30 Not allocated
31 Not allocated
32 Not allocated

NOTE: Others conditions of relays logic are available in the relays design by
PSL.
Pulse Timer
Pick UP/Drop Off Timer
Dwell Timer
Pick Up Timer
Drop Off Timer
Latching
Straight (Transparent)
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 187/220

Input
Output Pulse setting
Pulse Timer Input
Output Pulse setting

Input

Pick Up/ Output Tp setting Td setting

Drop Off Timer Input

Output Tp setting Td setting

Input

Output Timer setting

Dwell Timer Input

Output Timer setting

Input
Timer setting
Output
Pick Up Timer Input
Timer setting
Output

Input

Output Timer setting

Drop Off Timer Input

Timer setting
Output

P0562ENa

FIGURE 125 – TIMER DEFINITION IN PSL

P44x/EN AP/E33 Application Notes

Page 188/220 MiCOM P441/P442 & P444

6.5 Programmable led output mapping

The default mappings for each of the programmable LED’s are as shown in the following
table:-

LED P441 Relay P442 Relay P444 Relay

N°
1 Any Trip A Any Trip A Any Trip A
2 Any Trip B AnyTrip B Any Trip B
3 Any Trip C AnyTrip C Any Trip C
4 Any Start Any Start Any Start
5 Z1+Aided Trip Z1+Aided Trip Z1+Aided Trip
6 Dist FWd Dist Fwd Dist Fwd
7 Dist Rev Dist Rev Dist Rev
8 A/R Enable A/R Enable A/R Enable

NOTE: All the Leds are latched in the default PSL

6.6 Fault recorder trigger
The default PSL trigger which initiates a fault record is as shown in the following table:-

P441 Relay P442 Relay P444 Relay

Any Start Any Start Any Start
Any Trip Any Trip Any Trip

FIGURE 126
If the fault recorder trigger is not assigned in the PSL, no Fault recorder can be initiated and
displayed in the list by the LCD front panel.
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 189/220

7. CURRENT TRANSFORMER REQUIREMENTS

Two calculations must be performed – once for the three phase fault current at the zone 1
reach, and once for earth (ground) faults. The highest of the two calculated Vk voltages
must be used:
7.1 CT Knee Point Voltage for Phase Fault Distance Protection

Vk ≥ KRPA x IF Z1 x (1+ X/R) . (RCT + RL)

Where:
Vk = Required CT knee point voltage (volts),
KRPA = Fixed dimensioning factor = always 0.6
IF Z1 = Max. secondary phase fault current at Zone 1 reach point (A),
X/R = Primary system reactance / resistance ratio,
RCT = CT secondary winding resistance (Ω),
RL = Single lead resistance from CT to relay (Ω).
7.2 CT Knee Point Voltage for Earth Fault Distance Protection

Vk ≥ KRPA x IFe Z1 x (1+ Xe/Re) . (RCT + 2RL)

Where:
KRPA = Fixed dimensioning factor = always 0.6
IFe Z1 = Max. secondary earth fault current at Zone 1 reach point (A),
Xe/Re = Primary system reactance / resistance ratio for earth loop.
7.3 Recommended CT classes (British and IEC)
Class X current transformers with a knee point voltage greater or equal than that calculated
can be used.
Class 5P protection CTs can be used, noting that the knee point voltage equivalent these
offer can be approximated from:
Vk = (VA x ALF) / In + (RCT x ALF x In)
Where:
VA = Voltampere burden rating,
ALF = Accuracy Limit Factor,
In = CT nominal secondary current.
7.4 Determining Vk for an IEEE “C" class CT
Where American/IEEE standards are used to specify CTs, the C class voltage rating can be
checked to determine the equivalent Vk (knee point voltage according to IEC). The
equivalence formula is:
Vk = [ (C rating in volts) x 1.05 ] + [ 100 x RCT ]

8. DDB DESCRIPTION FOR ALL TYPES P441/P442 & P444 MODELS

P44x/EN AP/E33 Application Notes

Page 190/220 MiCOM P441/P442 & P444

BLANK PAGE
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 191/220

In
DDB label Default PSL Set with : Reset with :
Out
Changement of Group by Optos
∗
No cell assigned In Opto1 opto energised (>1 sec)( ) – Must be not assigned in the PSL opto power off
At1 :LSB Bit (see table in section 3.3.1 in chap AP) At 0 : (see table in section 3.3.1 in chap AP)
No cell assigned In Opto2 opto energised (>1 sec)(*) – Must be not assigned in the PSL opto power off
At1 :MSB Bit (see table in section 3.3.1 in chap AP) At 0 : (see table in section 3.3.1 in chap AP)
SG-opto Invalid Out Setting Group selected via opto are invalid Set 0 : No alarm is present
Example :1group is requested by the optos status but that group is not
present in the settings
(Gr3 requested but only Gr1&2 are present in MiCOM S1-The settings
restart with GR1 & that cell switch on at 1)
OPTOS INPUTS (48Vcc Version A / Universal Version B-C)
Opto In P441 / P442 / P444 P441 / P442 / P444
Label
Opto energised for a minimum time : 7 ms (48Vdc), 10 ms (universal) to be See Hysteresis description in sect 6.2 chapter P44x/EN AP
1/8
validated by internal logic
See Hysteresis description in sect 6.2 chapter P44x/EN AP
Opto In P442 / P444 P442 / P444
Label
Opto energised for a minimum time : 7 ms (48Vdc), 10 ms (universal) to be See Hysteresis description in sect 6.2 chapter P44x/EN AP
9/16
validated by internal logic
See Hysteresis description in sect 6.2 chapter P44x/EN AP
Opto In P444 P444
Label
Opto energised for a minimum time : 1,2 sec to be validated by internal See Hysteresis description in sect 6.2 chapter P44x/EN AP
17/24
logic
See Hysteresis description in sect 6.2 chapter P44x/EN AP
Opto In Not Used Not Used
Label
25/32

∗
Minimum time >1 sec for: changement Gr/TPAR/SPAR/AR enable
P44x/EN AP/E33 Application Notes

Page 192/220 MiCOM P441/P442 & P444

In
DDB label Default PSL Set with : Reset with :
Out
OUTPUT RELAYS
Relay Out P441 / P442 / P444 P441 / P442 / P444
Label
Set1 :For any DDB cell at 1 if linked by PSL & regarding the type of logic Set 0 :For any DDB cell at 0 if linked by PSL & regarding
selected in PSL by MiCOM S1 the type of logic selected in PSL by MiCOM S1
Programmable Relays : All relays are assigned in Type of Logic:
01/14
The default PSL (See DDB table description) Pulse timer
Type of Logic: Pick Up/Drop Off Timer
Pulse timer Dwell Timer
Pick Up/Drop Off Timer Pick Up Timer
Dwell Timer Drop Off Timer
Pick Up Timer Latching
Drop Off Timer Straight (used in default PSL)
Latching
Straight (used in default PSL)
Relay Out P442 / P444 P442 / P444
Label
Set1 :For any DDB cell at 1 if linked by PSL & regarding the type of logic Set 0 :For any DDB cell at 0 if linked by PSL & regarding
selected in PSL by MiCOM S1 the type of logic selected in PSL by MiCOM S1
15/21
Programmable Relay – Not assigned in default PSL Type of Logic: (See Description above)
Type of Logic: (See Description above)
Relay Out P444 P444
Label
Set1 :For any DDB cell at 1 if linked by PSL & regarding the type of logic Set 0 :For any DDB cell at 0 if linked by PSL & regarding
selected in PSL by MiCOM S1 the type of logic selected in PSL by MiCOM S1
22/32
Programmable Relay– Not assigned in default PSL Type of Logic: (See Description above)
Type of Logic: (See Description above)
LEDS (Right side – Front panel)
LED 1 Led Set1 : For any DDB cell at 1 if linked by PSL Set 0 : For any DDB cell at 0 if linked by PSL & regarding
Programmable Led : ANY TRIP A in the default PSL the type of logic selected in PSL by MiCOM S1
(Latched or not Latched)
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 193/220

In
DDB label Default PSL Set with : Reset with :
Out
LED 2 Led Set1 : For any DDB cell at 1 if linked by PSL Set 0 : For any DDB cell at 0 if linked by PSL & regarding
Programmable Led : ANY TRIP B in the default PSL the type of logic selected in PSL by MiCOM S1
(Latched or not Latched)
LED 3 Led Set1 : For any DDB cell at 1 if linked by PSL Set 0 : For any DDB cell at 0 if linked by PSL & regarding
Programmable Led : ANY TRIP C in the default PSL the type of logic selected in PSL by MiCOM S1
(Latched or not Latched)
LED 4 Led Set1 : For any DDB cell at 1 if linked by PSL Set 0 : For any DDB cell at 0 if linked by PSL & regarding
Programmable Led : General Start in the default PSL the type of logic selected in PSL by MiCOM S1
(Latched or not Latched)
LED 5 Led Set1 : For any DDB cell at 1 if linked by PSL Set 0 : For any DDB cell at 0 if linked by PSL & regarding
Programmable Led : Z1+Aided Trip in the default PSL the type of logic selected in PSL by MiCOM S1
(Latched or not Latched)
LED 6 Led Set1 : For any DDB cell at 1 if linked by PSL Set 0 : For any DDB cell at 0 if linked by PSL & regarding
Programmable Led : Dist FWD in the default PSL the type of logic selected in PSL by MiCOM S1
(Latched or not Latched)
LED 7 Led Set1 : For any DDB cell at 1 if linked by PSL Set 0 : For any DDB cell at 0 if linked by PSL & regarding
Programmable Led : Dist REV in the default PSL the type of logic selected in PSL by MiCOM S1
(Latched or not Latched)
LED 8 Led Set1 : For any DDB cell at 1 if linked by PSL Set 0 : For any DDB cell at 0 if linked by PSL & regarding
Programmable Led : Auto Reclose Enable in the default PSL the type of logic selected in PSL by MiCOM S1
(Latched or not Latched)
P44x/EN AP/E33 Application Notes

Page 194/220 MiCOM P441/P442 & P444

In
DDB label Default PSL Set with : Reset with :
Out
AUTO RECLOSE (AR) Logic
SPAR Enable In Opto8 opto energised (> 1 sec) if linked by PSL Reset at 0 : opto power off
+Inv At1 :1P AR internal is enabled in the AR logic At 0 : AR 1P internal is disabled
(higher priority than MiCOM S1) (even if selected enable by MiCOM S1)
AR logic becomes 3P only with AR 3P cycle -if TPAR =1
TPAR Enable In Opto8 opto energised (> 1 sec) if linked by PSL Reset at 0 : opto power off
+Inv At1 :3P AR internal is enabled in the AR logic At 0 : AR 3P internal is disabled
(higher priority than MiCOM S1) (even if selected enable by MiCOM S1)
logic becomes :no more 3P cycle available (1P could exist
if SPAR at 1)
A/R Internal In opto energised (> 1 sec) if linked by PSL Reset at 0 : opto power off
At1 :AR internal becomes present At 0 :no Ban Tri logic available.
[AR becomes enable by external contact AR is disable
example :Wdog of Main1 when pick up activates the internal AR in
Main2(P44x)]
A/R 1p in Prog In Relay opto energised if linked by PSL Reset at 0 : opto power off
12 At1 : External 1P AR cycle in progress – requested for blocking the internal
DEF function
A/R 3p in Prog In Relay opto energised if linked by PSL Reset at 0 : opto power off
12 External 3P Arcycle in progress - requested for blocking the internal DEF
function – (pb of Pole Operating Time)
A/R Close In Relay opto energised if linked by PSL Reset at 0 : opto power off
13 At1 :External AR gives a CB closing order – for using internal synchro
conditions of P44X
A/R reclaim In opto energised if linked by PSL Reset at 0 : opto power off
At1 :Reclaim time from external AR in progress – requested to initiate
internal TOR logic / Used in Z1X logic (by specific PSL)
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 195/220

In
DDB label Default PSL Set with : Reset with :
Out
BAR In Opto opto energised if linked by PSL Reset at 0 : opto power off
4 Set at1 :External condition which blocks the internal AR AR Lock out is reseted
(other internal blocking conditions can be selected in MiCOM
S1 :Autoreclose/Block AR) – see also logic AR lockout figure..
Ext Chk Synch In opto energised if linked by PSL Reset at 0 : opto power off
OK At1 :External check synchro condition satisfied – to be used with internal Conditiond of external synchro are unvailable
AR close by specific PSL – (With AND logic between Arclose&CsyncExt)
CB Healthy In Opto opto energised if linked by PSL Reset at 0 : opto power off
5 At1 :contact from CB when CB is operationnal (gas pressure/mechanical At 0 : AR cycle is stopped (if that cell is assigned in the
state)- Must be at 1 inside the time window (adjusted by MiCOM S1 : PSL). At the end of InhWInd the signal AR BAR picks up.
group1/Autoreclose mode/AR Inhibit Wind) during an AR cycle (signals :AR
close & AR Reclaim pick up when CB healthy is detected during the
InhWind timer)
Force 3P trip In opto energised if linked by PSL Reset at 0 : opto power off
At1 :External command for tripping 3P only (Order issued from Main1 to
Main2) – next trip will be 3P
Man.Close CB In Opto opto energised if linked by PSL Reset at 0 : opto power off
6 At1 :External manual close command – requested to initiate SOTF logic &
to close CB (Arlock out during SOTF logic)
Man.Trip CB In opto energised if linked by PSL Reset at 0 : opto power off
At1 :External manual trip command to provide a CB trip command by CB
control if selected in MiCOM S1
CB In opto energised if linked by PSL Reset at 0 : opto power off
Discrepancy At1 : OR
Contact from external status of CB poles (one pole opened) – that data drop Off Internal Logic
must be at 1 before end of Dead time1 if assigned in the PSL At 0 : Stop the 1P cycle if absent at the end of dead time1.
OR AR is ofrced in AR Lock Out
Internal logic = Any pole &Not All pole Dead
(CB Aux must be connected 52a or 52b)
External TripA In opto energised if linked by PSL Reset at 0 : opto power off
At1 :External trip command A
P44x/EN AP/E33 Application Notes

Page 196/220 MiCOM P441/P442 & P444

In
DDB label Default PSL Set with : Reset with :
Out
Activate a Trip command phase A (DDB :Any TripA)
(No dwell timer is associated as for an internal trip)
Activate internal AR
Integrated in the Any Trip & Any TripA cell
External TripB In opto energised if linked by PSL Reset at 0 : opto power off
At1 :External trip command B
Activate a Trip command phase B(DDB :Any TripB)
(No dwell timer is associated as for an internal trip)
Activate internal AR
Integrated in the Any Trip & Any TripB cell
External TripC In opto energised if linked by PSL Reset at 0 : opto power off
At1 :External trip command C
Activate a Trip command phase C(DDB :Any TripC)
(No dwell timer is associated as for an internal trip)
Activate internal AR
Integrated in the Any Trip & Any TripC cell
AR Lockout Out AR is blocked by passing over the number of shots selected in Auto At0 : AR Cycles continue if fault still present
Shot> Reclose/trip mode (in MiCOM S1) (not erased by the previous Arcycle)
Set at 1 : Reset at 0 :
(AR Enable) & Reset Trip1P + Reset Trip3P
[(Trip1P&No SPAR)+(Trip3P&NoTPAR)
+(Trip1P+Trip3P)&(Number of shots=MiCOM S1 value)]
AR Fail Out Set at 1 : Absence of check sync condition involve AR failure (For 3P cycle) Reset at 0 : by 3 Poles Closed
A/R close Out Relay 13 Set at 1 :AR internal command :CB Close Reset at 0 with :
Starts as AR Reclaim Close Pulse Time (Setting)
OR
Trip1P or Trip3P
A/R 1p in Prog Out Relay 12 1P AR cycle in progress (could be connected to external Main2 for Blocking Set 0 with :
DEF) End of 1P Dead Time
+AR Lock out (BAR)
+ 3P TRip
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 197/220

In
DDB label Default PSL Set with : Reset with :
Out
A/R 3p in Prog Out Relay 12 3P AR cycle in progress (could be connected to external Main2) Set 0 with :
End of 3P Dead time (DAR)
+AR Lock Out (BAR)
+End of Dead time1 (HSAR)
A/R 1st in Prog Out First high speed AR Cycle in progress (could be connected to external Set 0 with :
Main2) End of 3P Dead time (DAR)
+AR Lock Out (BAR)
+End of Dead time1 (HSAR)
A/R 234 in Prog Out Further delayed AR Cyles in progress (could be connected to external Set 0 with :
Main2) End of 3P Dead time (DAR)
+AR Lock Out (BAR)
+End of Dead time1 (HSAR)
A/R Trip 3P Out AR signal which force all trips to be 3P – picks up at the end of the first trip At 0 : AR1P could operate if programmed
(1P or 3P)
- Can be connected to Main2 as an external Ban Tri
Set at 1 : Reset at 0 :
(AR enable MiCOM S1)&(No SPAR) SPAR & AR enable MiCOM S1
+ (InhibitWind at 0)
A/R Reclaim Out Set at 1 :Reclaim timer in progress.(Value adjusted in MiCOM S1) Reset at 0 with :
Picks up at the end of the dead time –in synchronism with AR Close order End of Reclaim time (MiCOM S1)
- Can be connected to Main2 for cycle in progress external information OR
- Initiate the internal TOR logic Reset (Trip1P or Trip3P)
(See Figure 78 section 4.5.3)
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In
DDB label Default PSL Set with : Reset with :
Out
AR Discrim Out Dicrim status detected (inter or Externaly)-timer in progress Rest 0 :
End of Discrim timer (MiCOM S1)
+Trip 3P (DEC 3P)
+AR Lock Out (BAR)
A/R Enable Out Led 8 Copy of status AR Enable
Set at 1 : Reset at 0: If SPAR and TPAR Optos at 0 (if integrated in
[(optos SPAR) +(optoTPAR)]& (AR enable byMiCOM S1) PSL) + AR Disable in MiCOM S1
A/R SPAR Out Set at 1 :1P AR activated (copy of opto SPAR or MiCOM S1) Reset at 0: if SPARopto=0 or AR Disable in MiCOM S1
Enable
A/R TPAR Out Set at 1 :3P AR activated (copy of opto TPAR or MiCOM S1) Reset at 0: if TPARopto=0 or AR Disable in MiCOM S1
Enable
A/R Lockout Out Relay 11 AR function locked out/No more cycle is initiated by the AR (Pole is kept At0 : AR is activated
opened) – Reset must be done for enabling the AR logic again (AR Reset at 0 =
counters are resetted) [Reset(Trip1P)+Reset(Trip3P)]
Set at 1 = & (End of RC timer)
ARenable & & Reset (BAR )
[(BAR =1 (see internal logic figure.. section..) & Reset (AR BAR n shot>)
+(AR BAR n shot>) AR lockout by number of shots & Reset (No CB Healty)
+(No CB Healthy at the end of InhWind(MiCOM S1)) & Reset (No Discrepancy)
+[No Discrepancy (opto or internal by CBAux if present in PSL) at the end
of 1P Dead time1]
+ (Trip 1P or3P maintained /still present at the end of the1Por3P Dead
time)
+(After discrim timer if Trip3P occures during a 1PAR Cycle) ]
A/R Force Sync Out Force the Synchro condition ok at 1 Reset 0 :
(Could be used during test for getting Arclose whatever are the real With Reset of A/R Reclaim (See DDB description)
conditions of CheckSyn )
LED 8 AR Enable Latched by PSL design
(See DDB Description)
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 199/220

In
DDB label Default PSL Set with : Reset with :
Out
CHECK SYNC Logic
Check Out Set at 1 : Check Synchro conditions are satisfied Set at 0 : Conditions of checksyn unsatisfied (thresholds of
Synch .OK Used with AR close in dedicated PSL – AND gate : dead & live definied in MiCOM S1 :system checks)
[(AR Close) or (Manual Close) & (Checksync OK)]
Control No C/S Out Set at 1 : Internal conditions of Csync are not fulfilled Set at 0 :CSYnc conditions available
V<Dead line Out Set at 1 : Condition of Dead line at 1 (voltage below the threshold value Set at 0 : Condition of Dead line at 0 (voltage above the
(settable in MiCOM S1) – Default value is 13V threshold value (settable in MiCOM S1)
V>Live line Out Set at 1: Condition of Live line at 1 (voltage above the threshold value Set at 0 : Condition of Live line at 0 (voltage below the
(settable in MiCOM S1) – Default value is 32V threshold value (settable in MiCOM S1)
V<Dead Bus Out Set at 1: Condition of Dead Bus at 1 (voltage below the threshold value Set at 0 : Condition of Dead Bus at 0 (voltage above the
(settable in MiCOM S1) – Default value is 13V threshold value (settable in MiCOM S1)
V>Live Bus Out Set at 1: Condition of Live Bus at 1 (voltage above the threshold value Set at 0 : Condition of Live Bus at 0 (voltage below the
(settable in MiCOM S1) – Default value is 32V threshold value (settable in MiCOM S1)
MCB/VTS Bus In Set at 1 :Internal fault in VT used for synchro ref Reset at 0 : opto power off
Csync function is blocked
MCB/VTS Line In Set at 1 :Internal fault in VT used for Z measurement ref (Main VT) Reset at 0 : opto power off
Distance &all Directionnal functions are blocked(can unblocked with
different VTS timer- see MiCOM S1 settings)
Ctrl Cls In Prog Out Set at 1 :Manual close in progress – using CB control (Timer manual Set at 0 :End of Timer manual closing
closing delay in progress)
Control Close Out Set at1 :CB Close 3P command by internal CB Control Reset at 0 :
(Control with synchrocheck manual condition could be used in dedicated End of Timer MiCOM S1 (Close pulse timer)
PSL – MiCOM S1Chk scheme ManCB) +Any Trip
See CB Control logic sect 4.8 fig 115 +CBC No Csync
+CBC Unhealthy
See CB Control logic sect 4.8 fig 115
Control Trip Out Set at 1 :CB Trip 3P command by internal CB Control Reset at 0 :
See CB Control logic sect 4.8 fig 115 End of timer MiCOM S1 (Trip pulse timer)
P44x/EN AP/E33 Application Notes

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In
DDB label Default PSL Set with : Reset with :
Out
SOTF – TOR Logic
Man Close CB In Opto opto energised if linked by PSL Reset at 0 : opto power off
6 At1 :
AND no CB Control is activated in MiCOM S1
External command for closing manualy the CB
Will initiate SOTF logic if SOTF not disable in MiCOM S1(BitD)
AND CB control enable will initiate CB close in progress if All pole dead =
SOTF Enable
AR Reclaim In opto energised if linked by PSL Reset at 0 : opto power off
When at 1 (See AR DDB) start the TOR logic
CB Aux A In opto energised if linked by PSL Reset at 0 : opto power off
(See CB DDB ) used for Any pole dead/All pole dead
CB Aux B In opto energised if linked by PSL Reset at 0 : opto power off
(See CB DDB ) used for Any pole dead/All pole dead
CB Aux C In opto energised if linked by PSL Reset at 0 : opto power off
(See CB DDB ) used for Any pole dead/All pole dead
SOTF Enable Out When SOTF logic is enable Timer 500msec issued after Any pole Dead
Set at 1 : + Reset of one conditions requested for SOTF enable
[Sotf not disable (Bit D in MiCOM S1)] AND
All pole dead & End Timer (110sec/default)
+ Input Man Close
+ (CB control & Close in progress)
TOR Out When SOTF logic is enable Reset 500ms after Any pole dead stops
Enable Set at 1 :
By a Pulse of 500msec initiated by :
AR Reclaim internal+AR reclaim External Input
OR
Any pole opened for more than 200ms
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 201/220

In
DDB label Default PSL Set with : Reset with :
Out
TOC Start A Out Set1 :Trip order phase A initiated by levels detectors in SOTF logic (Pickup Set 0 : Reset of Level detectors logic
20ms delayed )
TOC Start B Out Set1 :Trip order phase B initiated by levels detectors in SOTF logic (Pickup Set 0 : Reset of Level detectors logic
20ms delayed )
TOC Start C Out Set1 :Trip order phase C initiated by levels detectors in SOTF logic (Pickup Set 0 : Reset of Level detectors logic
20ms delayed )
AR Reclaim Out When at 1 (See AR DDB) start the TOR logic Set 0 : (See AR DDB)
SOTF/TOR Out Set1 :Trip order initiated by any condition fulfilled in the SOTF/TOR logic Set 0 :When conditions reset
Trip (See logic section 2.12 – fig 37) (See logic section 2.12 – fig 37)
Any Pole Dead Out Set1 :Minimum 1 pole is open Set 0 :All poles are detected not dead
Pole Dead A+Pole DeadB+Pole Dead C
Detection of pole status made by Cbaux or internal thresholds (see dead Detection of pole status made by Cbaux or internal
pole logic in SOTF section 2.12 – fig 35) thresholds
All Pole Dead Out Set1 :All poles are open Set 0 :1pole is detected not dead
Pole DeadA & P.DeadB & P.Dead C
Detection of pole status made by Cbaux or internal thresholds (see dead Detection of pole status made by Cbaux or internal
pole logic in SOTF section 2.12 – fig 35) thresholds
CIRCUIT BREAKER Logic (CB Control / CB Monitoring / CB Fail)
CB Aux A (52a) In opto energised if linked by PSL Reset at 0 : opto power off
At1 :Status input from CB-Pole A is closed Set 0 :Pole A is opened
CB Aux A (52b) In opto energised if linked by PSL Reset at 0 : opto power off
At1 :Status input from CB-Pole A is opened Set 0 :Pole A is closed
CB Aux B (52a) In opto energised if linked by PSL Reset at 0 : opto power off
At1 :Status input from CB-Pole B is closed Set 0 :Pole B is opened
CB Aux B (52b) In opto energised if linked by PSL Reset at 0 : opto power off
At1 :Status input from CB-Pole B is opened Set 0 :Pole B is closed
CB Aux C (52a) In opto energised if linked by PSL Reset at 0 : opto power off
At1 :Status input from CB-Pole C is closed Set 0 :Pole A is opened
P44x/EN AP/E33 Application Notes

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In
DDB label Default PSL Set with : Reset with :
Out
CB Aux C (52b) In opto energised if linked by PSL Reset at 0 : opto power off
At1 :Status input from CB-Pole C is opened Set 0 :Pole C is closed
CB Healthy In Opto 5 See DDB description of AR Logic (CB control not used) See DDB description of AR Logic
Man Close CB In Opto 6 See DDB Description in SOTF logic (CB control not used) See DDB Description in SOTF logic
Man Trip CB In See DDB description of AR Logic See DDB description of AR Logic
CB Discrepancy In See DDB description of AR Logic See DDB description of AR Logic
Reset Lockout In Opto 7 opto energised if linked by PSL Reset at 0 : opto power off
At1 :Provides a CB monitoring lockout reset (all counters & values are
reset)
Reset All Values In opto energised if linked by PSL Reset at 0 : opto power off
At1 :Provides a CB monitoring reset (all counters & values are reset)
CB Fail Alarm Out Set 1 :For any Breaker failure on any trip for any phase Reset 0 : (selectable in MiCOM S1 : CB fail & I< logic)
Iphase<
+ CB open & Iphase<
+Trip reset & Iphase
+Trip reset OR Iphase<<
I^ Maint Alarm Out Set1 : :Alarm Maintenace picks up when the maximum broken current (1st
level) calculated by monitoring task is reached (set in MiCOM
S1 :I^Maintenance)
(min1/Max 25000A)
I^ Lockout Alarm Out Set1 : Lockout :Alarm picks up when the maximum broken current (2nd Set 0 :When the maximum broken current (2nd level)
level) calculated by monitoring task is reached (set in MiCOM calculated by monitoring task is not reached
S1 :I^Maintenance)
(min1/Max 25000A)
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 203/220

In
DDB label Default PSL Set with : Reset with :
Out
CB Ops Maint Out Set1 :Alarm picks up when the maximum number of CB operations initiated Set 0 :untill number of operations is bellow the MiCOM S1
by internal or external Trip (set in MiCOM S1 :CB Ops Maint) is reached value
(min1/Max 10000) Counter can be reseted by « Reset all values »
CB Ops Lockout Out Set1 :When CB is lockout due to number of CB operations bigger than in Set 0 :untill number of operations is bellow the MiCOM S1
MiCOM S1 value(CB Ops Lock) value
(min1/Max 10000) Counter can be reseted by « Reset all values »
CB Op Time Out Set1 :Alarm picks up for an excessive operating time on any phase (slowest Set 0 :untill operating time is bellow the MiCOM S1 value
Maint pole detection calculated by I< of CB Fail logic))
In MiCOM S1-CB Time maint (min5/Max 500 msec)
CB Op Time lock Out Set1 :Alarm picks up for an excessive operating time on any phase (slowest Set 0 :untill operating time is bellow the MiCOM S1 value
pole detection calculated by I< of CB Fail logic)
In MiCOM S1-CB Time Lockout (min5/Max 500 msec)
F.F Pre Lockout Out Set1 :CB Trip Prelockout Alarm ReSet 0 : end of timer in MiCOM S1 (Fault Freq Time)
With (Maint Lockout –1) + (Fault Frequency-1) at 1 (min0/Max 9999 sec)
F.F Lock Out Set1 : CB Trip Lockout Alarm Reset 0 : By user interface OR CB Close
With : (Maint Lockout =1) + (Fault Frequence=1) (selectable in MiCOM S1)
Lockout Alarm Out Set1 :Lockout Alarm with Reset 0 : By user interface OR CB Close
CBC Unhealthy (selectable in MiCOM S1)
+CBC No Check Sync
+CBC Fail to Close
+CBC Fail To Trip
+FF Lock
+CB OpTime Lock
+CB Ops Lock
CB Status Alarm Out Displayed with 2 LSB of « Plan Status « at 00 or 11 from LCD of relay Set 0 : When conditions reset
Set1 :When CB discrepency status is detected after CBA timer issued by Opto or internal logic
opto input or internaly by CBAux logic – Alarm issued after 5 sec.
See CB aux Logic in sect 4.7.1 Figure 109
Man CB trip Fail Out Set1 :CB Fail on Manual Trip Set 0 :
See CB Control logic section 4.8 Figure 115 See CB Control logic section 4.8 Figure 115
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In
DDB label Default PSL Set with : Reset with :
Out
Man CB Cls Fail Out Set1 :CB Fail on Manual Close Set 0 :
See CB Control logic section 4.8 Figure 115 See CB Control logic section 4.8 Figure 115
Man CB Out Set1 : CB Unhealthy for Manual Control Set 0 :
Unhealthy See CB Control logic section 4.8 Figure 115 See CB Control logic section 4.8 Figure 115
CB Aux A Out Set1 :Pole A is opened Set 0 :Pole A is closed
CB Pole A Status detceted by internal logic & CBAux optos input status CB Pole A Status detceted by internal logic & CBAux optos
(See CB Section 4.6 – Figure 109) input status (See CB Section 4.6 – Figure 109)
CB Aux B Out Set1 :Pole B is opened Set 0 :Pole B is closed
CB Pole A Status detceted by internal logic & CBAux optos input status CB Pole A Status detceted by internal logic & CBAux optos
(See CB Section 4.6 – Figure 109) input status (See CB Section 4.6 – Figure 109)
CB Aux C Out Set1 :Pole C is opened Set 0 :Pole C is closed
CB Pole A Status detceted by internal logic & CBAux optos input status CB Pole A Status detceted by internal logic & CBAux optos
(See CB Section 4.6 – Figure 109) input status (See CB Section 4.6 – Figure 109)
Any Pole Dead Out See DDB Description in SOTF logic See DDB Description in SOTF logic
All Pole Dead Out See DDB Description in SOTF logic See DDB Description in SOTF logic
TBF1 Trip Out Trip Order :Breaker Failure trip from timer tBF1 in CB Fail ogic Reset end of Timer tBF1
TBF2 Trip Out Trip order : Breaker Failure trip from timer tBF2 in CB Fail ogic Reset end of Timer tBF2
DISTANCE PROTECTION Logic
DIST.Chan Recv In Opto1 opto energised if linked by PSL Reset at 0 : opto power off
At1 :Signal (carrier)received on main channel for Distance scheme logic Set 0 :No carrier received
(depending on MiCOM S1 settings :Program mode/standard Mode)
DIST COS In Opto2 opto energised if linked by PSL Reset at 0 : opto power off
At1 :Signal (Loss of carrier/Loss of Guard) is detected out of service by
external device
Application Notes P44x/EN AP/E33

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In
DDB label Default PSL Set with : Reset with :
Out
Z1X Extension In opto energised if linked by PSL OR any internal DDB by dedicated PSL Reset at 0 : opto power off
At1 :Signal will initiate Z1 extension logic if selected in MiCOM S1.
That cell can be assigned to any external/Internal condition for starting Z1X
logic
(See Z1X logic section 4.5.4 Figure 13 Figure 14)
MCB/VTS Line In Opto3 opto energised if linked by PSL Reset at 0 : opto power off
(Z measure At1 :Fuse Failure by external MCB status on Main VT (Z measurement) .All
VT main) Distance & Directionnality will be blocked after a FFU timer adjusted by
MiCOM S1
(See Fuse Failure logic section 4.2 Figure 66)
Even if Main VT are Bus side – that cell must be linked to MCB status)
MCB/VTS Bus In See Check Sync DDB description See Check Sync DDB description
(Sync Ref) (Used in Synchrocheck logic) (Used in Synchrocheck logic)
VTS Fast Out Set1 :Copy of Instantaneous unconfirmed Fuse Failure (in internal logic Set 0 :Rest of one of the conditions
detection)
(See Fuse Failure logic section 4.2 Figure 66) (See FFailure logic in section 4.2 Figure 66)
Protections blocked.Min Z can be unblocked by I>&I2>&IN&∆I (for
1P/2P/3P Failure)
VTS Fail Alarm Out Set1 :VT Alarm indication with : Reset 0 :
internal logic after timer is issued+ MCB by opto at1 Healthy network detected
The Distance/WInfeed & Directionnal functions are blocked (only Non direc + All pole Dead
I> are working)
(See Fuse Failure logic section 4.2 Figure 66) (See FFailure logic in section 4.2 Figure 66)
Dist Timer Block In opto energised if linked by PSL OR any internal DDB by dedicated PSL Reset at 0 : opto power off if assigned to an opto
(Usefull during test) OR
Set1 :The DIST Timer will be blocked & DIST will start but will not perform a DDB at 0 if assigned to a DDB cell
Trip command.
COS Alarm Out Set1 :Alarm for Carrier Out Of Service Set 0 : Rest of initiale condition
DIST Sig Send Out Relay 05 Set1 :Signal send in Distance Protection scheme Set 0 :
(See logic of distance section 2.8.2.4)
P44x/EN AP/E33 Application Notes

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In
DDB label Default PSL Set with : Reset with :
Out
DIST UNB CR Out Set1 :Unblock Main channel signal received Set 0 :
See Led 5 / Relay 10 description
Dist Fwd Out Led6 Set1 :Directionnal Forward detected in distance Algorithms (Deltas or Set 0 : With reset of Any Start/Dist Start
Classical) AND (CVMR)
See Description of Algorithms in chapter P44x/EN HW, item 4)
Assigned to Led 6 by default
Dist Rev Out Led7 Set1 :Directionnal Reverse detected in distance Algorithms (Deltas or Set 0 : With reset of Any Start/Dist Start
Classical) AND (CVMR)
(See Description of Algorithms in chapter P44x/EN HW, item 4)
Assigned to Led 7 by default
Dist Trip A Out Set1 :Trip Phase A with Distance protection logic Set 0 :Reset Dist Trip signal
(See Trip logic in Section 2.5 Figure 94) (fixed pulse duration is 80ms)
Dist Trip B Out Set1 :Trip Phase B with Distance protection logic Set 0 :Reset Dist Trip signal
(See Trip logic in Section 2.5 Figure 94) (fixed pulse duration is 80ms)
Dist Trip C Out Set1 :Trip Phase C with Distance protection logic Set 0 :Reset Dist Trip signal
(See Trip logic in Section 2.5 Figure 94) (fixed pulse duration is 80ms)
DIST Start A Out Set1 : Distance Protection logic start phase A Set 0 : Reset of R/X computation made by All pole Dead
(See Description of Algorithms in chapter 3) detection
I Dead calculated by Laurent (3 or 4 samples requested)
V Dead calculated by CB Fail (More than 10ms requested)
DIST Start B Out Set1 : Distance Protection logic start phase B Set 0 : Reset of R/X computation made by All pole Dead
(See Description of Algorithms in chapter 3) detection
I Dead calculated by Laurent (3 or 4 samples requested)
V Dead calculated by CB Fail (More than 10ms requested)
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 207/220

In
DDB label Default PSL Set with : Reset with :
Out
DIST Start C Out Set1 : Distance Protection logic start phase C Set 0 : Reset of R/X computation made by All pole Dead
(See Description of Algorithms in chapter 3) detection
I Dead calculated by Laurent (3 or 4 samples requested)
V Dead calculated by CB Fail (More than 10ms requested)
DIST Sch Accel. Out Set1 :Distance scheme accelerating - POP Set 0 : If disabled in MiCOM S1
(Copy of MiCOM S1 setting Dist scheme)
DIST Sch Perm Out Set1 :Distance scheme Permissive - PUP Set 0 : If disabled in MiCOM S1
(Copy of MiCOM S1 setting Dist scheme)
DIST Sch Block Out Set1 :Distance scheme Blocking – BOP Z1 – BOP Z2 Set 0 : If disabled in MiCOM S1
(Copy of MiCOM S1 setting Dist scheme)
Z1 = Z'1 Out Led5 Set1 :Fault is detected in Z1(convergence of loop in Z1) Set 0 : Reset of R/X computation made by All pole Dead
Relay See Led 5/Relay01/Relay 10 description detection (See Dist Start DDB reset description)
01-10
Z1X = Z'1x Out Led5 Set1 :Fault is detected in Z1x(convergence of loop in Z1x) and filtered by Set 0 : Reset of R/X computation made by All pole Dead
Relay blocking/unblocking PSwing/Rguard logic detection (See Dist Start DDB reset description)
10 See Led 5/Relay10 description
Z2 = Z'2 Out Led5 Set1 :Fault is detected in Z2(convergence of loop in Z2) and filtered by Set 0 : Reset of R/X computation made by All pole Dead
Relay blocking/unblocking PSwing/Rguard logic detection (See Dist Start DDB reset description)
10 See Relay 10 / Led5 description
Z3 = Z'3 Out Led5 Set1 :Fault is detected in Z3(convergence of loop in Z3) and filtered by Set 0 : Reset of R/X computation made by All pole Dead
Relay blocking/unblocking PSwing/Rguard logic detection (See Dist Start DDB reset description)
10 See Relay 10 / Led5 description
Z4 = Z'4 Out Led5 Set1 :Fault is detected in Z4(convergence of loop in Z4) and filtered by Set 0 : Reset of R/X computation made by All pole Dead
Relay blocking/unblocking PSwing/Rguard logic detection (See Dist Start DDB reset description)
10 See Relay 10 / Led5 description
P44x/EN AP/E33 Application Notes

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In
DDB label Default PSL Set with : Reset with :
Out
Zp Out Led5 Set1 :Fault is detected in Zp(convergence of loop in Zp) – See Relay 10 / Set 0 : Reset of R/X computation made by All pole Dead
Relay Led5 description detection (See Dist Start DDB reset description)
10
T1 Out Set1 :Timer Distance for Z1 (tZ1 in MiCOM S1) is issued (If T1=0 picks up Set 0 : Timer Distance T1 is not issued
when relay starts (CVMR or Predef)
End of Timer =1
T2 Out Set1 :Timer Distance for Z2 (tZ2 in MiCOM S1) is issued Set 0 : Timer Distance T2 is not issued
End of Timer =1
T3 Out Set1 :Timer Distance for Z3 (tZ3 in MiCOM S1) is issued Set 0 : Timer Distance T3 is not issued
End of Timer =1
T4 Out Set1 :Timer Distance for Z4 (tZ4 in MiCOM S1) is issued Set 0 : Timer Distance T4 is not issued
End of Timer =1
Tzp Out Set1 :Timer Distance for Zp (tZp in MiCOM S1) is issued Set 0 : Timer Distance T Zp is not issued
End of Timer =1
Dist Fwd No Filt Out Set1 :Directionnal Forward decision made by Distance logic without any Set 0 : Identical to Dist Fwd reset logic
filter by CVMR or Zone
Picks up quicker than Dist Fwd
Dist Rev No Filt Out Set1 :Directionnal Reverse decision made by Distance logic without any Set 0 : Identical to Dist Rev reset logic
filter by CVMR or Zone
Picks up quicker than Dist Rev
Dist Out Set1 : logic with CVMR at 1 (Minimum 1 loop has been detected in the Set 0 : Reset of R/X computation made by All pole Dead
Convergency quad) detection (See Dist Start DDB reset description)
Cross Country Out Set1 : Cross country logic is activated Set 0 : With reset of initiale conditions
Filt (1 Fault Fwd/1 Fault Rev detected)
Relay Out Assigned in default PSL : »TRIP Z1 » - Default logic Set 0 : See PSL logic
Label Z1&[( Dist TripA)+ (Dist TripB)+ (Dist TripC)]
01
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 209/220

In
DDB label Default PSL Set with : Reset with :
Out
Relay Out Assigned in default PSL : »Dist Aided Trip » - Default logic Set 0 : See PSL logic
Label [( Dist TripA)+ (Dist TripB)+ (Dist TripC)]
10 & Dist Unb CR
& (Z1+Z1x+Z2+Z3+Zp+Z4)
LED 5 Led Assigned in default PSL : »Z1+Aided Trip » Set 0 : See PSL logic
Relay10 + Z1 + Z1x
Associated DISTANCE PROTECTION Logic
Power Swing Out Relay Set1 : Power Swing detected Set 0 : Reset of initiale conditions
14 (See description logic in section 2.14 Figure 40)
Reversal Guard Out Set1 :Reversal guard logic is activated (Directionnal switching from Rev to Set 0 :
Fwd in parallel line application)
See Description logic in section 2.8.2.4 Figure 3)
WI Trip A Out Set1 : For Trip phase A in Weak infeed logic Set 0 :
(See Weak Infeed logic section 2.9.3 Figure 24) (See Weak Infeed logic section 2.9.3 Figure 24)
WI Trip B Out Set1 : For Trip phase B in Weak infeed logic Set 0 :
(See Weak Infeed logic section 2.9.3 Figure 24) (See Weak Infeed logic section 2.9.3 Figure 24)
WI Trip C Out Set1 : For Trip phase C in Weak infeed logic Set 0 :
(See Weak Infeed logic section 2.9.3 Figure 24) (See Weak Infeed logic section 2.9.3 Figure 24)
Aided DEF PROTECTION Logic
DEF.Chan Recv In Opto1 opto energised if linked by PSL opto power off
At1 :Signal (carrier)received on main channel for DEF scheme logic Set 0 :No carrier received
(depending on MiCOM S1 settings :Aided DEF/Scheme logic)
Selected shared by default – Can operate as an independant scheme with
adifferent opto from Dist
P44x/EN AP/E33 Application Notes

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In
DDB label Default PSL Set with : Reset with :
Out
DEF COS In Opto2 opto energised if linked by PSL Reset at 0 : opto power off
At1 :Signal (Loss of carrier/Loss of Guard) is detected out of service by
external device
Selected shared by default – Can operate as an independant scheme with
adifferent opto from Dist
DEF Timer Block In opto energised if linked by PSL OR any internal DDB by dedicated PSL Reset at 0 : opto power off if assigned to an opto
Set1 :The DEF Timer will be blocked & DEF will start but will not perform OR
any Trip command. DDB at 0 if assigned to a DDB cell
DEF Sig Send Out Relay Set1 :Signal send in DEF Protection scheme Set 0 :
05 (See logic of DEF section 2.18 Figure 48 and Figure 49)
DEF UNB CR Out Set1 :Unblock DEF Channel Set 0 :
DEF Rev Out Set1 :Directionnal Reverse detected in DEF Algorithms (Deltas or Set 0 : Reset of R/X computation made by All pole Dead
Classical) detection (See Dist Start DDB reset description)
See Description of Algorithms in section 2.18 Figure 50)
DEF Fwd Out Set1 :Directionnal Foward detected in DEF Algorithms (Deltas or Classical) Set 0 : Reset of R/X computation made by All pole Dead
(See Description of Algorithms in section 2.18 Figure 50) detection (See Dist Start DDB reset description)
DEF Start A Out Set1 :Start Phase A with DEF protection logic Set 0 : Reset of R/X computation made by All pole Dead
(See Trip logic in section 2.18) detection (See Dist Start DDB reset description)
DEF Start B Out Set1 :Start Phase B with DEF protection logic Set 0 : Reset of R/X computation made by All pole Dead
(See Trip logic in section 2.18) detection (See Dist Start DDB reset description)
DEF Start C Out Set1 :Start Phase C with DEF protection logic Set 0 : Reset of R/X computation made by All pole Dead
(See Trip logic in section 2.18) detection (See Dist Start DDB reset description)
DEF Trip A Out Relay Set1 : DEF Protection logic Trip phase A Set 0 : Reset DEF Trip Order
09 (See Description of Algorithms in Figure 52)
DEF Trip B Out Relay Set1 : DEF Protection logic Trip phase B Set 0 : Reset DEF Trip Order
09 (See Description of Algorithms in Figure 52)
DEF Trip C Out Relay Set1 : DEF Protection logic Trip phase C Set 0 : Reset DEF Trip Order
09 (See Description of Algorithms in Figure 52)
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MiCOM P441/P442 & P444 Page 211/220

In
DDB label Default PSL Set with : Reset with :
Out
ZERO SEQUENCE POWER PROTECTION ZSP Logic (since version B1.0)
ZSP Timer Block In Input energised if linked by PSL OR any internal DDB by dedicated PSL Reset at 0 : opto power off if assigned to an opto
Set 1:The ZSP Timer will be blocked & ZSP will start but will not perform OR
any Trip command DDB at 0 if assigned to a DDB cell
ZSP Start Out Set 1:Zero sequence power function Start (Timer associated picks up) Set 0:Reset with IN or SR below the threshold IN> or SR>
with fixed time delay first and IDMT curve timer Hysteresis=
(See Pole Dead description in Figure 60)
ZSP Trip Out Set 1:3P Trip order performed by Zero sequence power function when Set 0:Reset ZSP Trip Order
associated timers are issued
BACK UP OVERCURRENT PROTECTION IN>1/IN>2/I2>/I>1/I>2/I>3/I>4 Logic
IN>1 Timer Block In opto energised if linked by PSL OR any internal DDB by dedicated PSL Reset at 0 : opto power off if assigned to an opto
Set1 :The IN>1 Timer will be blocked & IN>1 will start but will not perform OR
any Trip command. DDB at 0 if assigned to a DDB cell
IN>2 Timer Block In opto energised if linked by PSL OR any internal DDB by dedicated PSL Reset at 0 : opto power off if assigned to an opto
Set1 :The IN>2 Timer will be blocked & IN>2 will start but will not perform OR
any Trip command. DDB at 0 if assigned to a DDB cell
I>1 Timer Block In opto energised if linked by PSL OR any internal DDB by dedicated PSL Reset at 0 : opto power off if assigned to an opto
Set1 :The I>1 Timer will be blocked & I>1 will start but will not perform any OR
Trip command. DDB at 0 if assigned to a DDB cell
I>2 Timer Block In opto energised if linked by PSL OR any internal DDB by dedicated PSL Reset at 0 : opto power off if assigned to an opto
Set1 :The I>2 Timer will be blocked & I>2 will start but will not perform any OR
Trip command. DDB at 0 if assigned to a DDB cell
I>3 Timer Block In opto energised if linked by PSL OR any internal DDB by dedicated PSL Reset at 0 : opto power off if assigned to an opto
Set1 :The I>3 Timer will be blocked & I>3 will start but will not perform any OR
Trip command. DDB at 0 if assigned to a DDB cell
I>4 Timer Block In opto energised if linked by PSL OR any internal DDB by dedicated PSL Reset at 0 : opto power off if assigned to an opto
Set1 :The I>4 Timer will be blocked & I>4 will start but will not perform any OR
Trip command. DDB at 0 if assigned to a DDB cell
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In
DDB label Default PSL Set with : Reset with :
Out
I2> Timer Block In opto energised if linked by PSL OR any internal DDB by dedicated PSL Reset at 0 : opto power off if assigned to an opto
Set1 :The I2> Timer will be blocked & I2> will start but will not perform any OR
Trip command with negative overcurrent detection DDB at 0 if assigned to a DDB cell
IN>1 Trip Out Relay Set1 : Earth Fault stage 1 – 3Poles Trip order performed when associated Set 0 : Reset IN>1 Trip Order
09 timer is issued
IN>2 Trip Out Relay Set1 : Earth Fault stage 2 – 3Poles Trip order performed when associated Set 0 : Reset IN>2Trip Order
09 timer is issued
IN>1 Start Out Set1 : Earth Fault stage 1 – Start function (Timer associated picks up) Set 0 : Reset with IN below the threshold IN>1
Directionnal or not - with DT or IDMT curves Hysteresis=
Negative or positive sequence polarisation (See Pole Dead description in Figure 60)
IN>2 Start Out Set1 : Earth Fault stage 2 – Start function (Timer associated picks up) Set 0 : Reset with IN below the threshold IN>2
Directionnal or not - DT only Hysteresis=
Negative or positive sequence polarisation (See Pole Dead description in Figure 60)
I2> Start Out Set1 : Negative sequence current detection – Start function (Timer Set 0 : Reset with IN below the threshold I2>
associated picks up) Hysteresis=
Directionnal or not - with DT curves
Negative polarisation (See Pole Dead description in Figure 60)
I2> Trip Out Set1 : Negative sequence current detection – 3P Trip order performed Set 0 : Reset I2> Trip Order
when associated timer is issued
I>Start Out Set1 :Any Overcurrent function start for phase A Set 0 : Reset with Iphase A below the lowest threshold I>1
Any A Hysteresis=
(See Pole Dead description in Figure 60)
I>Start Out Set1 :Any Overcurrent function start for phase B Set 0 : Reset with Iphase B below the lowest threshold I>1
Any B Hysteresis=
(See Pole Dead description in Figure 60)
I>Start Out Set1 :Any Overcurrent function start for phase C Set 0 : Reset with Iphase C below the lowest threshold I>1
Any C Hysteresis=
(See Pole Dead description in Figure 60)
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 213/220

In
DDB label Default PSL Set with : Reset with :
Out
I>1 Start Out Set1 :Overcurrent stage1 start Set 0 : Reset with Iphase A below the threshold I>1
Directionnal or not - with DT or IDMT curves Hysteresis=
Directionnal managed by Deltas Algorithms
VTS Block timer facility (See Pole Dead description in Figure 60)
I>2 Start Out Set1 :Overcurrent stage2 start Set 0 : Reset with Iphase A below the threshold I>2
Directionnal or not - with DT or IDMT curves Hysteresis=
Directionnal managed by Deltas Algorithms
VTS Block timer facility (See Pole Dead description in Figure 60)
I>3 Start Out Set1 :Overcurrent stage3 start Set 0 : Reset with Iphase A below the threshold I>3
Not Directionnal with DT curves Hysteresis=
Use without timer for SOTF
(see description in section 2.12 Figure 35) (See Pole Dead description in Figure 60)
I>4 Start Out Set1 :Overcurrent stage4 start Set 0 : Reset with Iphase A below the threshold I>4
Not Directionnal with DT curves Hysteresis=
Use without timer for SOTF
(see description in section 2.14) (See Pole Dead description in Figure 60)
I>1 Trip Out Set1 :Overcurrent Stage 1 Trip 3P performed when associated timer is Set 0 : Reset I>1 Trip Order
issued
I>2 Trip Out Set1 :Overcurrent Stage 2 Trip 3P performed when associated timer is Set 0 : Reset I>2 Trip Order
issued
I>3 Trip Out Set1 :Overcurrent Stage 3 Trip 3P performed when associated timer is Set 0 : Reset I>3 Trip Order
issued
I>4 Trip Out Set1 :Overcurrent Stage 4 Trip 3P performed when associated timer is Set 0 : Reset I>4 Trip Order
issued
Stub Bus Enable Out opto energised if linked by PSL Reset at 0 : opto power off if assigned to an opto
At1 :Status input from HV line isolator opened – indicates that line is dead
& disconnected
At1 : I>4 is activated as a back up Stub Bus protection
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In
DDB label Default PSL Set with : Reset with :
Out
BACK UP VOLTAGE PROTECTION V<1/V<2/V>1/V>2 Logic
V<1 Timer Block In opto energised if linked by PSL OR any internal DDB by dedicated PSL Reset at 0 : opto power off if assigned to an opto
Set1 :The V<1 Timer will be blocked & V<1 will start but will not perform OR
any Trip command. DDB at 0 if assigned to a DDB cell
V<2 Timer Block In opto energised if linked by PSL OR any internal DDB by dedicated PSL Reset at 0 : opto power off if assigned to an opto
Set1 :The V<2 Timer will be blocked & V<2 will start but will not perform OR
any Trip command. DDB at 0 if assigned to a DDB cell
V>1 Timer Block In opto energised if linked by PSL OR any internal DDB by dedicated PSL Reset at 0 : opto power off if assigned to an opto
Set1 :The V>1 Timer will be blocked & V>1 will start but will not perform OR
any Trip command. DDB at 0 if assigned to a DDB cell
V>2 Timer Block In opto energised if linked by PSL OR any internal DDB by dedicated PSL Reset at 0 : opto power off if assigned to an opto
Set1 :The V>2 Timer will be blocked & V>2 will start but will not perform OR
any Trip command. DDB at 0 if assigned to a DDB cell
V<1 Alarm Out Set1 :1st stage undervoltage Alarm picks up when V<1 starts Set 0 : Reset with V measure over the threshold V<1
Hysteresis=
V<2 Alarm Out Set1 :2nd stage undervoltage Alarm picks up when V<1 starts Set 0 : Reset with V measure over the threshold V<2
Hysteresis=
V>1 Alarm Out Set1 :1st stage Overvoltage Alarm picks up when V<1 starts Set 0 : Reset with V measure below the threshold V>1
Hysteresis=
V>2 Alarm Out Set1 :2nd stage Overvoltage Alarm picks up when V<1 starts Set 0 : Reset with V measure below the threshold V>2
Hysteresis=
V<Start Out Set1 :Any Undervoltage function start for phase A Set 0 : Reset with V phase A measure over the lowest
Any A threshold V<
Hysteresis=
V<Start Out Set1 :Any Undervoltage function start for phase B Set 0 : Reset with V phase B measure over the lowest
Any B threshold V<
Hysteresis=
Application Notes P44x/EN AP/E33

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In
DDB label Default PSL Set with : Reset with :
Out
V<Start Out Set1 :Any Undervoltage function start for phase C Set 0 : Reset with V phase C measure over the lowest
Any C threshold V<
Hysteresis=
V<1 Start Out Set1 :1st Stage Undervoltage function start for any phase Set 0 : Reset with V measure over the threshold V<1
Hysteresis=
V<2 Start Out Set1 :2nd Stage Undervoltage function start for any phase Set 0 : Reset with V measure below the threshold V<2
Hysteresis=
V<1 Trip Out Set1 :1st Stage Undervoltage function trip 3 phase Set 0 : Reset of V<1 Trip order
nd
V<2 Trip Out Set1 :2 Stage Undervoltage function trip 3 phase Set 0 : Reset of V<2 Trip order
V>Start Out Set1 :Any Overvoltage function start for phase A Set 0 : Reset with V phase A measure below the lowest
Any A threshold V<
Hysteresis=
V>Start Out Set1 :Any Overvoltage function start for phase B Set 0 : Reset with V phase B measure below the lowest
Any B threshold V<
Hysteresis=
V>Start Out Set1 :Any Overvoltage function start for phase C Set 0 : Reset with V phase C measure below the lowest
Any C threshold V<
Hysteresis=
V>1 Start Out Set1 :1st Stage Overvoltage function start for any phase Set 0 : Reset with V measure below the threshold V>1
Hysteresis=
V>2 Start Out Set1 :2nd Stage Overvoltage function start for any phase Set 0 : Reset with V measure below the threshold V>2
Hysteresis=
V>1 Trip Out Set1 :1st Stage Overvoltage function 3 phase TRIP Set 0 : Reset of V>1 Trip order
V>2 TRip Out Set1 :2nd Stage Overvoltage function 3 phase TRIP Set 0 : Reset of V>2 Trip order
P44x/EN AP/E33 Application Notes

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In
DDB label Default PSL Set with : Reset with :
Out
ALARMS
F out of Range Out Set1 :Alarm when frequency tracking does not operate correctly and Set 0 : With frequency tracking operating correctly
provides a Frequency out of range
CT Fail Alarm Out Set1 :Alarm from the current transformers supervision Set 0 :No CT Fail Alarm detected
Brok.Cond. Out Set1 : Alarm from the Start of Broken Conductor function Set 0 :No Brok.Cond.Alarm detected
Alarm
CVT Alarm Out Set 1:Alarm from the capacitive voltage transformers supervision Set 0 :No CVT Fail Alarm detected
Field Volt Fail Out Set1 : Field Voltage Failure (Internal 48Vcc delivered by the relay can be Set 0 :With reset of min Field voltage detection
used for Optos polarisation)
Alarm User1 In Set1 : Alarm for user – application customized must be linked to dedicated Set 0 :With reset of conditions linked to that cell
DDB cells
Alarm User2 In Set1 : Alarm for user – application customized must be linked to dedicated Set 0 :With reset of conditions linked to that cell
DDB cells
Alarm User3 In Set1 : Alarm for user – application customized must be linked to dedicated Set 0 :With reset of conditions linked to that cell
DDB cells
Alarm User4 In Set1 : Alarm for user – application customized must be linked to dedicated Set 0 :With reset of conditions linked to that cell
DDB cells
Alarm User5 In Set1 : Alarm for user – application customized must be linked to dedicated Set 0 :With reset of conditions linked to that cell
DDB cells
General Alarm Out Relay Set1 :For any Alarm started & included in the list : Set 0 : Reset if all initiale condition reset
08 Battery Fail
Field Volt Fail
General Alarm
Prot’n Disabled
F out of range
VT Fail Alarm
CT Fail Alarm
CVT Fail Alarm
CB Fail Alarm
Application Notes P44x/EN AP/E33

MiCOM P441/P442 & P444 Page 217/220

In
DDB label Default PSL Set with : Reset with :
Out
General Alarm Out Relay I^Maint Alarm Set 0 : Reset if all initiale condition reset
08 I^Lockout Alarm
CB Ops Maint
CB Ops Lockout
CB Op Time Maint
CB Op Time Lock
F.F. Pre Lockout
F.F Lock
Lockout Alarm
CB Status Alarm
Man CB Trip Fail
Man CB Cls Fail
Man CB Unhealthy
Control No C/C
AR Lockout Shot>
SG-opto Invalid
A/R Fail
V<1 Alarm
V<2 Alarm
V>1 Alarm
V>2 Alarm
COS Alarm
User Alarlm1
User Alarm2
START LOGIC
Any Start Out Led4 Set1 :Any Protection start loig with any phase Set 0 :Reset with reset from all started function
Relay Assigned to Led 4 by default (21/67N/50/51…)
06 (Fault record Trigger in default PSL with 20ms Dwell Timer)
1ph Fault Out Set1 : Single phase fault detected with Distance Funct. Set 0 : with Distance Reset
2ph Fault Out Set1 : Two phase fault detected with Distance Funct. Set 0 : with Distance Reset
3ph Fault Out Set1 : Three phase fault detected with Distance Funct. Set 0 : with Distance Reset
P44x/EN AP/E33 Application Notes

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In
DDB label Default PSL Set with : Reset with :
Out
TRIP LOGIC
User Trip A In opto energised if linked by PSL OR any internal DDB by dedicated PSL Reset at 0 : opto power off if assigned to an opto
Set1 :Trip A Internal input managed with the general trip logic(With OR
AR/Evolving fault…) DDB at 0 if assigned to a DDB cell
Can be assigned by external condition
User Trip B In opto energised if linked by PSL OR any internal DDB by dedicated PSL Reset at 0 : opto power off if assigned to an opto
Set1 :Trip B Internal input managed with the general trip logic(With OR
AR/Evolving fault…) DDB at 0 if assigned to a DDB cell
Can be assigned by external condition
User Trip C In opto energised if linked by PSL OR any internal DDB by dedicated PSL Reset at 0 : opto power off if assigned to an opto
Set1 :Trip C Internal input managed with the general trip logic(With OR
AR/Evolving fault…) DDB at 0 if assigned to a DDB cell
Can be assigned by external condition
Any Trip Out Relay Set1 :Any Trip 1P or 3P initiated by internal Trip or external Trip decision Set 0 :Reset conditions
07 (Fault record Trigger in default PSL)
Any Int Trip A Out Set1 : Any Internal Trip with Phase A with any internal protection decision Set 0 :Reset conditions
Any Int Trip B Out Set1 : Any Internal Trip with Phase B with any internal protection decision Set 0 :Reset conditions
Any Int Trip C Out Set1 : Any Internal Trip with Phase C- with any internal protection decision Set 0 :Reset conditions
Any Trip A Out Led1 Set1 :Any Internal or External Trip phase A – with any protection decision Set 0 :Reset conditions
Relay (internal or external)
02 Assigned to Led 1 by default
Any Trip B Out Led2 Set1 :Any Internal or External Trip phase B – with any protection decision Set 0 :Reset conditions
Relay (internal or external)
03 Assigned to Led 2 by default
Any Trip C Out Led3 Set1 :Any Internal or External Trip phase C – with any protection decision Set 0 :Reset conditions
Relay (internal or external)
04 Assigned to Led 3 by default
1P Trip Out Set1 :Single pole Trip decision (int or Ext) Set 0 :Reset conditions
Application Notes P44x/EN AP/E33

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In
DDB label Default PSL Set with : Reset with :
Out
3P Trip Out Set1 :Three pole Trip decision (int or Ext) Set 0 :Reset conditions
Brk Conduct. Out Set1 :3P Trip decision by Broken Conductor protection Set 0 :Reset conditions
Trip
Loss.Load Out Set1 :3P Trip decision by Loss of Load protection (in application without Set 0 :Reset conditions
Trip communication scheme & a 3P Trip logic)
MISCELLANEOUS LOGIC
BLK Protection In opto energised if linked by PSL OR any internal DDB by dedicated PSL Set 0 :Reset conditions
Set1 :All protections functions are blocked (21/67N/50/51…)
Prot’n Disabled Out Set1 :When TEST MODE is enable Set 0 :Reset conditions – No blocking conditions available :
All the protections functions are out of order. (Test mode disable) + (Opto BLK Protec =0)
Reset Latches In opto energised if linked by PSL OR any internal DDB by dedicated PSL Reset at 0 : opto power off if assigned to an opto
Set1 :Permanent Alarms & Leds & relayslatched are reset OR
DDB at 0 if assigned to a DDB cell
P44x/EN AP/E33 Application Notes

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