19-4675; Rev 10; 3/11

1024-Bit, 1-Wire EEPROM

General Description Features

DS2431
The DS2431 is a 1024-bit, 1-Wire® EEPROM chip orga- ♦ 1024 Bits of EEPROM Memory Partitioned Into
nized as four memory pages of 256 bits each. Data is Four Pages of 256 Bits
written to an 8-byte scratchpad, verified, and then
♦ Individual Memory Pages Can Be Permanently
copied to the EEPROM memory. As a special feature, the
Write Protected or Put in EPROM-Emulation Mode
four memory pages can individually be write protected or
put in EPROM-emulation mode, where bits can only be (“Write to 0”)
changed from a 1 to a 0 state. The DS2431 communi- ♦ Switchpoint Hysteresis and Filtering to Optimize
cates over the single-conductor 1-Wire bus. The commu- Performance in the Presence of Noise
nication follows the standard 1-Wire protocol. Each ♦ IEC 1000-4-2 Level 4 ESD Protection (±8kV
device has its own unalterable and unique 64-bit ROM
Contact, ±15kV Air, Typical)
registration number that is factory lasered into the chip.
The registration number is used to address the device in ♦ Reads and Writes Over a Wide Voltage Range
a multidrop, 1-Wire net environment. from 2.8V to 5.25V from -40°C to +85°C
♦ Communicates to Host with a Single Digital
Signal at 15.4kbps or 125kbps Using 1-Wire
Applications Protocol
Accessory/PCB Identification ♦ Also Available as Automotive Version Meeting
Medical Sensor Calibration Data Storage AEC-Q100 Grade 1 Qualification Requirements
Analog Sensor Calibration Including IEEE (DS2431-A1; Refer to the IC Data Sheet for
P1451.4 Smart Sensors Details)
Ink and Toner Print Cartridge Identification
After-Market Management of Consumables
Ordering Information
PART TEMP RANGE PIN-PACKAGE
DS2431+ -40°C to +85°C 3 TO-92
Typical Operating Circuit DS2431+T&R -40°C to +85°C 3 TO-92
DS2431P+ -40°C to +85°C 6 TSOC
DS2431P+T&R -40°C to +85°C 6 TSOC
VCC
DS2431G+ -40°C to +85°C 2 SFN
RPUP DS2431G+T&R -40°C to +85°C 2 SFN
DS2431Q+T&R -40°C to +85°C 6 TDFN-EP* (2.5k pcs)
IO
DS2431X-S+ -40°C to +85°C 3x3 UCSPR (2.5k pcs)
μC DS2431 DS2431X+ -40°C to +85°C 3x3 UCSPR (10k pcs)
Note: The leads of TO-92 packages on tape and reel are
formed to approximately 100-mil (2.54mm) spacing. For
GND details, refer to the package outline drawing.
+Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
*EP = Exposed pad.

Pin Configurations appear at end of data sheet.

1-Wire is a registered trademark of Maxim Integrated Products, Inc.

________________________________________________________________ Maxim Integrated Products 1

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
 1024-Bit, 1-Wire EEPROM
ABSOLUTE MAXIMUM RATINGS
DS2431

IO Voltage Range to GND .......................................-0.5V to +6V Lead Temperature (excluding UCSP, soldering, 10s).....+300°C
IO Sink Current ...................................................................20mA Soldering Temperature (reflow)
Operating Temperature Range ...........................-40°C to +85°C TO-92 ............................................................................+250°C
Junction Temperature ......................................................+150°C AIl other packages, excluding SFN ..............................+260°C
Storage Temperature Range .............................-55°C to +125°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
(TA = -40°C to +85°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
IO PIN: GENERAL DATA
1-Wire Pullup Voltage VPUP (Note 2) 2.8 5.25 V
1-Wire Pullup Resistance RPUP (Notes 2, 3) 0.3 2.2 k

Input Capacitance CIO (Notes 4, 5) 1000 pF
Input Load Current IL IO pin at VPUP 0.05 6.7 μA
VPUP -
High-to-Low Switching Threshold VTL (Notes 5, 6, 7) 0.5 V
1.8
Input Low Voltage VIL (Notes 2, 8) 0.5 V
VPUP -
Low-to-High Switching Threshold VTH (Notes 5, 6, 9) 1.0 V
1.0
Switching Hysteresis VHY (Notes 5, 6, 10) 0.21 1.70 V
Output Low Voltage VOL At 4mA (Note 11) 0.4 V
Standard speed, RPUP = 2.2k
5
Recovery Time Overdrive speed, RPUP = 2.2k
2
tREC μs
(Notes 2,12) Overdrive speed, directly prior to reset
5
pulse; RPUP = 2.2k

Rising-Edge Hold-Off Time Standard speed 0.5 5.0
tREH μs
(Notes 5, 13) Overdrive speed Not applicable (0)
Time Slot Duration Standard speed 65
t SLOT μs
(Notes 2, 14) Overdrive speed 8
IO PIN: 1-Wire RESET, PRESENCE-DETECT CYCLE
Standard speed 480 640
Reset Low Time (Note 2) tRSTL μs
Overdrive speed 48 80
Standard speed 15 60
Presence-Detect High Time t PDH μs
Overdrive speed 2 6
Standard speed 60 240
Presence-Detect Low Time t PDL μs
Overdrive speed 8 24
Presence-Detect Sample Time Standard speed 60 75
tMSP μs
(Notes 2, 15) Overdrive speed 6 10

2 _______________________________________________________________________________________
 1024-Bit, 1-Wire EEPROM
ELECTRICAL CHARACTERISTICS (continued)

DS2431
(TA = -40°C to +85°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
IO PIN: 1-Wire WRITE
Standard speed 60 120
Write-Zero Low Time
tW0L Overdrive speed, VPUP > 4.5V 5 15.5 μs
(Notes 2, 16, 17)
Overdrive speed 6 15.5
Write-One Low Time Standard speed 1 15
tW1L μs
(Notes 2, 17) Overdrive speed 1 2
IO PIN: 1-Wire READ
Read Low Time Standard speed 5 15 - 
tRL μs
(Notes 2, 18) Overdrive speed 1 2-
Read Sample Time Standard speed tRL +  15
tMSR μs
(Notes 2, 18) Overdrive speed tRL +  2
EEPROM
Programming Current I PROG (Notes 5, 19) 0.8 mA
Programming Time t PROG (Notes 20, 21) 10 ms
Write/Erase Cycles (Endurance) At +25°C 200k
NCY 
(Notes 22, 23) At +85°C (worst case) 50k
Data Retention
tDR At +85°C (worst case) 40 Years
(Notes 24, 25, 26)

Note 1: Specifications at TA = -40°C are guaranteed by design only and not production tested.
Note 2: System requirement.
Note 3: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times.
The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more
heavily loaded systems, an active pullup such as that found in the DS2482-x00, DS2480B, or DS2490 may be required.
Note 4: Maximum value represents the internal parasite capacitance when VPUP is first applied. If a 2.2kΩ resistor is used to pull
up the data line, 2.5µs after VPUP has been applied, the parasite capacitance does not affect normal communications.
Note 5: Guaranteed by design, characterization, and/or simulation only. Not production tested.
Note 6: VTL, VTH, and VHY are a function of the internal supply voltage, which is a function of VPUP, RPUP, 1-Wire timing, and
capacitive loading on IO. Lower VPUP, higher RPUP, shorter tREC, and heavier capacitive loading all lead to lower values of
VTL, VTH, and VHY.
Note 7: Voltage below which, during a falling edge on IO, a logic 0 is detected.
Note 8: The voltage on IO must be less than or equal to VILMAX at all times the master is driving IO to a logic 0 level.
Note 9: Voltage above which, during a rising edge on IO, a logic 1 is detected.
Note 10: After VTH is crossed during a rising edge on IO, the voltage on IO must drop by at least VHY to be detected as logic 0.
Note 11: The I-V characteristic is linear for voltages less than 1V.
Note 12: Applies to a single device attached to a 1-Wire line.
Note 13: The earliest recognition of a negative edge is possible at tREH after VTH has been reached on the preceding rising edge.
Note 14: Defines maximum possible bit rate. Equal to tW0LMIN + tRECMIN.
Note 15: Interval after tRSTL during which a bus master is guaranteed to sample a logic 0 on IO if there is a DS2431 present.
Minimum limit is tPDHMAX; maximum limit is tPDHMIN + tPDLMIN.
Note 16: Numbers in bold are not in compliance with legacy 1-Wire product standards. See the Comparison Table.
Note 17: ε in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to VTH. The actual
maximum duration for the master to pull the line low is tW1LMAX + tF - ε and tW0LMAX + tF - ε, respectively.
Note 18: δ in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input-high
threshold of the bus master. The actual maximum duration for the master to pull the line low is tRLMAX + tF.

_______________________________________________________________________________________ 3
 1024-Bit, 1-Wire EEPROM
DS2431

Note 19: Current drawn from IO during the EEPROM programming interval. The pullup circuit on IO during the programming interval
should be such that the voltage at IO is greater than or equal to VPUPMIN. If VPUP in the system is close to VPUPMIN, a low-
impedance bypass of RPUP, which can be activated during programming, may need to be added.
Note 20: Interval begins tREHMAX after the trailing rising edge on IO for the last time slot of the E/S byte for a valid Copy Scratchpad
sequence. Interval ends once the device’s self-timed EEPROM programming cycle is complete and the current drawn by
the device has returned from IPROG to IL.
Note 21: tPROG for units branded version “A1” is 12.5ms. tPROG for units branded version “A2” and later is 10ms.
Note 22: Write-cycle endurance is degraded as TA increases.
Note 23: Not 100% production tested; guaranteed by reliability monitor sampling.
Note 24: Data retention is degraded as TA increases.
Note 25: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the
data sheet limit at operating temperature range is established by reliability testing.
Note 26: EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term storage at elevated tem-
peratures is not recommended; the device can lose its write capability after 10 years at +125°C or 40 years at +85°C.

COMPARISON TABLE
LEGACY VALUES DS2431 VALUES
STANDARD SPEED OVERDRIVE SPEED STANDARD SPEED OVERDRIVE SPEED
PARAMETER
(μs) (μs) (μs) (μs)
MIN MAX MIN MAX MIN MAX MIN MAX
t SLOT (including tREC) 61 (undefined) 7 (undefined) 65* (undefined) 8* (undefined)
tRSTL 480 (undefined) 48 80 480 640 48 80
t PDH 15 60 2 6 15 60 2 6
t PDL 60 240 8 24 60 240 8 24
tW0L 60 120 6 16 60 120 6 15.5
*Intentional change; longer recovery time requirement due to modified 1-Wire front-end.
Note: Numbers in bold are not in compliance with legacy 1-Wire product standards.

4 _______________________________________________________________________________________
 1024-Bit, 1-Wire EEPROM
Pin Description

DS2431
PIN
NAME FUNCTION
TSOC TO-92 TDFN-EP SFN UCSPR
A2, A3, C2,
3, 4, 5, 6 3 1, 4, 5, 6 — N.C. Not Connected
C3
1-Wire Bus Interface. Open-drain signal
2 2 2 1 C1 IO
that requires an external pullup resistor.
1 1 3 2 A1 GND Ground Reference
Exposed Pad. Solder evenly to the
board’s ground plane for proper
— — EP — — EP operation. Refer to Application Note
3273: Exposed Pads: A Brief
Introduction for additional information.

Detailed Description
The DS2431 combines 1024 bits of EEPROM, an
8-byte register/control page with up to 7 user read/write PARASITE POWER
bytes, and a fully featured 1-Wire interface in a single
chip. Each DS2431 has its own 64-bit ROM registration
number that is factory lasered into the chip to provide a
guaranteed unique identity for absolute traceability.
Data is transferred serially through the
1-Wire protocol, which requires only a single data lead IO
1-Wire 64-BIT
FUNCTION CONTROL LASERED ROM
and a ground return. The DS2431 has an additional
memory area called the scratchpad that acts as a
buffer when writing to the main memory or the register
page. Data is first written to the scratchpad from which DS2431
MEMORY
it can be read back. After the data has been verified, a FUNCTION
Copy Scratchpad command transfers the data to its CONTROL UNIT
final memory location. The DS2431 applications include
accessory/PCB identification, medical sensor calibra- CRC-16
tion data storage, analog sensor calibration including GENERATOR
IEEE P1451.4 smart sensors, ink and toner print car- 64-BIT
tridge identification, and after-market management of DATA MEMORY SCRATCHPAD
consumables. 4 PAGES OF
256 BITS EACH
Overview
The block diagram in Figure 1 shows the relationships REGISTER PAGE
between the major control and memory sections of the 64 BITS
DS2431. The DS2431 has four main data components:
64-bit lasered ROM, 64-bit scratchpad, four 32-byte
pages of EEPROM, and a 64-bit register page. Figure 1. Block Diagram

_______________________________________________________________________________________ 5
 1024-Bit, 1-Wire EEPROM
DS2431

AVAILABLE COMMANDS: DATA FIELD AFFECTED:

READ ROM 64-BIT REG. #, RC-FLAG
DS2431 COMMAND LEVEL:
MATCH ROM 64-BIT REG. #, RC-FLAG
SEARCH ROM 64-BIT REG. #, RC-FLAG
1-Wire ROM FUNCTION COMMANDS
SKIP ROM RC-FLAG
(SEE FIGURE 9)
RESUME RC-FLAG
OVERDRIVE-SKIP ROM RC-FLAG, OD-FLAG
OVERDRIVE-MATCH ROM 64-BIT REG. #, RC-FLAG, OD-FLAG

WRITE SCRATCHPAD 64-BIT SCRATCHPAD, FLAGS

DS2431-SPECIFIC
READ SCRATCHPAD 64-BIT SCRATCHPAD
MEMORY FUNCTION COMMANDS
COPY SCRATCHPAD DATA MEMORY, REGISTER PAGE
(SEE FIGURE 7)
READ MEMORY DATA MEMORY, REGISTER PAGE

Figure 2. Hierarchical Structure for 1-Wire Protocol

MSB LSB

8-BIT 8-BIT FAMILY CODE

48-BIT SERIAL NUMBER
CRC CODE (2Dh)

MSB LSB MSB LSB MSB LSB

Figure 3. 64-Bit Lasered ROM

The hierarchical structure of the 1-Wire protocol is 64-Bit Lasered ROM

shown in Figure 2. The bus master must first provide Each DS2431 contains a unique ROM code that is 64
one of the seven ROM function commands: Read ROM, bits long. The first 8 bits are a 1-Wire family code. The
Match ROM, Search ROM, Skip ROM, Resume, next 48 bits are a unique serial number. The last 8 bits
Overdrive-Skip ROM, or Overdrive-Match ROM. Upon are a cyclic redundancy check (CRC) of the first 56 bits.
completion of an Overdrive-Skip ROM or Overdrive- See Figure 3 for details. The 1-Wire CRC is generated
Match ROM command byte executed at standard using a polynomial generator consisting of a shift regis-
speed, the device enters overdrive mode where all ter and XOR gates as shown in Figure 4. The polynomial
subsequent communication occurs at a higher speed. is X8 + X5 + X4 + 1. Additional information about the
The protocol required for these ROM function com- 1-Wire CRC is available in Application Note 27:
mands is described in Figure 9. After a ROM function Understanding and Using Cyclic Redundancy Checks
command is successfully executed, the memory func- with Maxim iButton® Products.
tions become accessible and the master can provide The shift register bits are initialized to 0. Then, starting
any one of the four memory function commands. The with the least significant bit of the family code, one bit
protocol for these memory function commands is at a time is shifted in. After the 8th bit of the family code
described in Figure 7. All data is read and written has been entered, the serial number is entered. After
least significant bit first. the last bit of the serial number has been entered, the
shift register contains the CRC value. Shifting in the 8
bits of the CRC returns the shift register to all 0s.

iButton is a registered trademark of Maxim Integrated Products, Inc.

6 _______________________________________________________________________________________
 1024-Bit, 1-Wire EEPROM

DS2431
POLYNOMIAL = X8 + X5 + X4 + 1

1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH

STAGE STAGE STAGE STAGE STAGE STAGE STAGE STAGE

X0 X1 X2 X3 X4 X5 X6 X7 X8

INPUT DATA

Figure 4. 1-Wire CRC Generator

Memory Access ally set to open (unprotected), write protected, or

EPROM mode by setting the associated protection byte
Data memory and registers are located in a linear
in the register row. The last two rows contain protection
address space, as shown in Figure 5. The data memory
registers and reserved bytes. The register row consists
and the registers have unrestricted read access. The
of 4 protection control bytes, a copy-protection byte,
DS2431 EEPROM array consists of 18 rows of 8 bytes
the factory byte, and 2 user byte/manufacture ID bytes.
each. The first 16 rows are divided equally into four
The manufacturer ID can be a customer-supplied iden-
memory pages (32 bytes each). These four pages are
tification code that assists the application software in
the primary data memory. Each page can be individu-
identifying the product the DS2431 is associated with.

ADDRESS RANGE TYPE DESCRIPTION PROTECTION CODES

0000h to 001Fh R/(W) Data Memory Page 0 —
0020h to 003Fh R/(W) Data Memory Page 1 —
0040h to 005Fh R/(W) Data Memory Page 2 —
0060h to 007Fh R/(W) Data Memory Page 3 —
55h: Write Protect P0; AAh: EPROM Mode P0;
0080h* R/(W) Protection Control Byte Page 0
55h or AAh: Write Protect 80h
55h: Write Protect P1; AAh: EPROM Mode P1;
0081h* R/(W) Protection Control Byte Page 1
55h or AAh: Write Protect 81h
55h: Write Protect P2; AAh: EPROM Mode P2;
0082h* R/(W) Protection Control Byte Page 2
55h or AAh: Write Protect 82h
55h: Write Protect P3; AAh: EPROM Mode P3;
0083h* R/(W) Protection Control Byte Page 3
55h or AAh: Write Protect 83h
55h or AAh: Copy Protect 0080h:008Fh, and Any
0084h* R/(W) Copy Protection Byte
Write-Protected Pages
AAh: Write Protect 85h, 86h, 87h;
0085h R Factory Byte. Set at Factory.
55h: Write Protect 85h; Unprotect 86h, 87h
0086h R/(W) User Byte/Manufacturer ID —
0087h R/(W) User Byte/Manufacturer ID —
0088h to 008Fh — Reserved —
*Once programmed to AAh or 55h this address becomes read only. All other codes can be stored, but neither write protect the
address nor activate any function.
Figure 5. Memory Map

_______________________________________________________________________________________ 7
 1024-Bit, 1-Wire EEPROM
Contact the factory to set up and register a custom byte is set to 55h or AAh, all copy attempts to the regis-
DS2431

manufacturer ID. The last row is reserved for future use. ter row and user-byte row are blocked. In addition, all
It is undefined in terms of R/W functionality and should copy attempts to write-protected main memory pages
not be used. (i.e., refresh) are blocked.
In addition to the main EEPROM array, an 8-byte Address Registers and Transfer Status
volatile scratchpad is included. Writes to the EEPROM The DS2431 employs three address registers: TA1, TA2,
array are a two-step process. First, data is written to the and E/S (Figure 6). These registers are common to
scratchpad and then copied into the main array. This many other 1-Wire devices but operate slightly different-
allows the user to first verify the data written to the ly with the DS2431. Registers TA1 and TA2 must be
scratchpad prior to copying into the main array. The loaded with the target address to which the data is writ-
device only supports full row (8-byte) copy operations. ten or from which data is read. Register E/S is a read-
For data in the scratchpad to be valid for a copy opera- only transfer-status register used to verify data integrity
tion, the address supplied with a Write Scratchpad with write commands. E/S bits E[2:0] are loaded with the
command must start on a row boundary, and 8 full incoming T[2:0] on a Write Scratchpad command and
bytes must be written into the scratchpad. increment on each subsequent data byte. This is, in
The protection control registers determine how incom- effect, a byte-ending offset counter within the 8-byte
ing data on a Write Scratchpad command is loaded scratchpad. Bit 5 of the E/S register, called PF, is a logic
into the scratchpad. A protection setting of 55h (write 1 if the data in the scratchpad is not valid due to a loss
protect) causes the incoming data to be ignored and of power or if the master sends fewer bytes than needed
the target address main memory data to be loaded into to reach the end of the scratchpad. For a valid write to
the scratchpad. A protection setting of AAh (EPROM the scratchpad, T[2:0] must be 0 and the master must
mode) causes the logical AND of incoming data and have sent 8 data bytes. Bits 3, 4, and 6 have no func-
target address main memory data to be loaded into the tion; they always read 0. The highest valued bit of the
scratchpad. Any other protection control register set- E/S register, called authorization accepted (AA), acts as
ting leaves the associated memory page open for unre- a flag to indicate that the data stored in the scratchpad
stricted write access. Protection-control byte settings of has already been copied to the target memory address.
55h or AAh also write protect the protection-control Writing data to the scratchpad clears this flag.
byte. The protection-control byte setting of 55h does
not block the copy. This allows write-protected data to Writing with Verification
be refreshed (i.e., reprogrammed with the current data) To write data to the DS2431, the scratchpad must be
in the device. used as intermediate storage. First, the master issues
the Write Scratchpad command to specify the desired
The copy-protection byte is used for a higher level of target address, followed by the data to be written to the
security and should only be used after all other protec- scratchpad. Note that Copy Scratchpad commands
tion control bytes, user bytes, and write-protected must be performed on 8-byte boundaries, i.e., the three
pages are set to their final value. If the copy-protection

BIT # 7 6 5 4 3 2 1 0

TARGET ADDRESS (TA1) T7 T6 T5 T4 T3 T2 T1 T0

TARGET ADDRESS (TA2) T15 T14 T13 T12 T11 T10 T9 T8

ENDING ADDRESS WITH

DATA STATUS (E/S) AA 0 PF 0 0 E2 E1 E0
(READ ONLY)

Figure 6. Address Registers

8 _______________________________________________________________________________________
 1024-Bit, 1-Wire EEPROM
LSBs of the target address (T2, T1, T0) must be equal Write Scratchpad [0Fh]

DS2431
to 000b. If T[2:0] are sent with nonzero values, the copy The Write Scratchpad command applies to the data
function is blocked. Under certain conditions (see the memory and the writable addresses in the register
Write Scratchpad [0Fh] section) the master receives an page. For the scratchpad data to be valid for copying
inverted CRC-16 of the command, address (actual to the array, the user must perform a Write Scratchpad
address sent), and data at the end of the Write command of 8 bytes starting at a valid row boundary.
Scratchpad command sequence. Knowing this CRC The Write Scratchpad command accepts invalid
value, the master can compare it to the value it has cal- addresses and partial rows, but subsequent Copy
culated to decide if the communication was successful Scratchpad commands are blocked.
and proceed to the Copy Scratchpad command. If the After issuing the Write Scratchpad command, the mas-
master could not receive the CRC-16, it should send ter must first provide the 2-byte target address, fol-
the Read Scratchpad command to verify data integrity. lowed by the data to be written to the scratchpad. The
As a preamble to the scratchpad data, the DS2431 data is written to the scratchpad starting at the byte off-
repeats the target address TA1 and TA2 and sends the set of T[2:0]. The E/S bits E[2:0] are loaded with the
contents of the E/S register. If the PF flag is set, data starting byte offset and increment with each subse-
did not arrive correctly in the scratchpad, or there was quent byte. Effectively, E[2:0] is the byte offset of the
a loss of power since data was last written to the last full byte written to the scratchpad. Only full data
scratchpad. The master does not need to continue bytes are accepted.
reading; it can start a new trial to write data to the
scratchpad. Similarly, a set AA flag together with a When executing the Write Scratchpad command, the
cleared PF flag indicates that the device did not recog- CRC generator inside the DS2431 (Figure 13) calcu-
nize the Write command. lates a CRC of the entire data stream, starting at the
command code and ending at the last data byte as
If everything went correctly, both flags are cleared. sent by the master. This CRC is generated using the
Now the master can continue reading and verifying CRC-16 polynomial by first clearing the CRC generator
every data byte. After the master has verified the data, and then shifting in the command code (0Fh) of the
it can send the Copy Scratchpad command, for exam- Write Scratchpad command, the target addresses (TA1
ple. This command must be followed exactly by the and TA2), and all the data bytes. Note that the CRC-16
data of the three address registers, TA1, TA2, and E/S. calculation is performed with the actual TA1 and TA2
The master should obtain the contents of these regis- and data sent by the master. The master can end the
ters by reading the scratchpad. Write Scratchpad command at any time. However, if
Memory Function Commands the end of the scratchpad is reached (E[2:0] = 111b),
the master can send 16 read time slots and receive the
The Memory Function Flowchart (Figure 7) describes CRC generated by the DS2431.
the protocols necessary for accessing the memory of
the DS2431. An example on how to use these functions If a Write Scratchpad command is attempted to a write-
to write to and read from the device is in the Memory protected location, the scratchpad is loaded with the
Function Example section. The communication data already existing in memory rather than the data
between the master and the DS2431 takes place either transmitted. Similarly, if the target address page is in
at standard speed (default, OD = 0) or at overdrive EPROM mode, the scratchpad is loaded with the bit-
speed (OD = 1). If not explicitly set into overdrive wise logical AND of the transmitted data and data
mode, the DS2431 assumes standard speed. already existing in memory.

_______________________________________________________________________________________ 9
 1024-Bit, 1-Wire EEPROM
DS2431

BUS MASTER Tx MEMORY FROM ROM FUNCTIONS

FUNCTION COMMAND FLOWCHART (FIGURE 9)

0Fh N AAh N TO FIGURE 7b

WRITE SCRATCHPAD? READ SCRATCHPAD?

Y Y

BUS MASTER Tx BUS MASTER Rx

TA1 (T[7:0]), TA2 (T[15:8]) TA1 (T[7:0]), TA2 (T[15:8]),
AND E/S BYTE

DS2431
SETS PF = 1 DS2431 SETS
CLEARS AA = 0 SCRATCHPAD
SETS E[2:0] = T[2:0] BYTE COUNTER = T[2:0]

MASTER Tx DATA BYTE DS2431 BUS MASTER Rx

APPLIES ONLY
TO SCRATCHPAD INCREMENTS DATA BYTE FROM
IF THE MEMORY
BYTE COUNTER SCRATCHPAD
AREA IS NOT
PROTECTED.

DS2431 IF WRITE PROTECTED,

Y THE DS2431 COPIES
INCREMENTS MASTER Tx RESET? Y
E[2:0] THE DATE BYTE FROM MASTER Tx RESET?
THE TARGET ADDRESS
N INTO THE SCRATCHPAD.
N
IF IN EPROM MODE,
THE DS2431 LOADS
N THE BITWISE LOGICAL
E[2:0] = 7? N
AND OF THE TRANSMITTED BYTE COUNTER
BYTE AND THE DATA = E[2:0]?
Y BYTE FROM THE TARGETED
ADDRESS INTO THE Y
SCRATCHPAD.
N BUS MASTER Rx CRC-16
T[2:0] = 0?
OF COMMAND, ADDRESS,
E/S BYTE, AND DATA BYTES
Y AS SENT BY THE DS2431

PF = 0

BUS MASTER N
MASTER Tx RESET?
Rx "1"s
DS2431 Tx CRC-16 OF
COMMAND, ADDRESS,
Y
AND DATA BYTES AS THEY
WERE SENT BY THE BUS
MASTER

BUS MASTER N
MASTER Tx RESET?
Rx "1"s

Y
FROM FIGURE 7b

TO ROM FUNCTIONS
FLOWCHART (FIGURE 9)

Figure 7a. Memory Function Flowchart

10 ______________________________________________________________________________________
 1024-Bit, 1-Wire EEPROM

DS2431
FROM FIGURE 7a 55h N F0h N
COPY SCRATCHPAD? READ MEMORY?

Y Y
APPLICABLE TO ALL R/W
MEMORY LOCATIONS.
BUS MASTER Tx BUS MASTER Tx
TA1 (T[7:0]), TA2 (T[15:8]) TA1 (T[7:0]), TA2 (T[15:8])
AND E/S BYTE

Y
Y Y ADDRESS < 90h?
AUTH. CODE
T[15:0] < 0090h?
MATCH?
N DS2431 SETS MEMORY
N N ADDRESS = (T[15:0])

N
PF = 0?
DS2431 BUS MASTER Rx
INCREMENTS DATA BYTE FROM
Y ADDRESS MEMORY ADDRESS
COUNTER

Y
COPY PROTECTED?
Y BUS MASTER
MASTER Tx RESET?
Rx "1"s
N

N
AA = 1

N
Y MASTER Tx RESET?
DS2431 COPIES ADDRESS < 8Fh?
DURATION: tPROG SCRATCHPAD * Y
DATA TO ADDRESS
N

BUS MASTER
Rx "1"s DS2431 Tx "0" BUS MASTER N
MASTER Tx RESET?
Rx "1"s

Y
N Y
MASTER Tx RESET? MASTER Tx RESET?

Y N

DS2431 Tx "1"

N
MASTER Tx RESET?

Y
TO FIGURE 7a

* 1-Wire IDLE HIGH FOR POWER.

Figure 7b. Memory Function Flowchart (continued)

______________________________________________________________________________________ 11
 1024-Bit, 1-Wire EEPROM
Read Scratchpad [AAh] 1-Wire Bus System
DS2431

The Read Scratchpad command allows verifying the

The 1-Wire bus is a system that has a single bus mas-
target address and the integrity of the scratchpad data.
ter and one or more slaves. In all instances the DS2431
After issuing the command code, the master begins
is a slave device. The bus master is typically a micro-
reading. The first two bytes are the target address. The
controller. The discussion of this bus system is broken
next byte is the ending offset/data status byte (E/S) fol-
down into three topics: hardware configuration, trans-
lowed by the scratchpad data, which may be different
action sequence, and 1-Wire signaling (signal types
from what the master originally sent. This is of particular
and timing). The 1-Wire protocol defines bus transac-
importance if the target address is within the register
tions in terms of the bus state during specific time slots,
page or a page in either write-protection mode or
which are initiated on the falling edge of sync pulses
EPROM mode. See the Write Scratchpad [0Fh] section
from the bus master.
for details. The master should read through the scratch-
pad (E[2:0] - T[2:0] + 1 bytes), after which it receives Hardware Configuration
the inverted CRC based on data as it was sent by the
The 1-Wire bus has only a single line by definition; it is
DS2431. If the master continues reading after the CRC,
important that each device on the bus be able to drive
all data is logic 1.
it at the appropriate time. To facilitate this, each device
Copy Scratchpad [55h] attached to the 1-Wire bus must have open-drain or
The Copy Scratchpad command is used to copy data three-state outputs. The 1-Wire port of the DS2431 is
from the scratchpad to writable memory sections. After open drain with an internal circuit equivalent to that
issuing the Copy Scratchpad command, the master shown in Figure 8.
must provide a 3-byte authorization pattern, which A multidrop bus consists of a 1-Wire bus with multiple
should have been obtained by an immediately preced- slaves attached. The DS2431 supports both a standard
ing Read Scratchpad command. This 3-byte pattern and overdrive communication speed of 15.4kbps (max)
must exactly match the data contained in the three and 125kbps (max), respectively. Note that legacy
address registers (TA1, TA2, E/S, in that order). If the 1-Wire products support a standard communication
pattern matches, the target address is valid, the PF flag speed of 16.3kbps and overdrive of 142kbps. The
is not set, and the target memory is not copy protected, slightly reduced rates for the DS2431 are a result of
then the AA flag is set and the copy begins. All 8 bytes additional recovery times, which in turn were driven by
of scratchpad contents are copied to the target memo- a 1-Wire physical interface enhancement to improve
ry location. The duration of the device’s internal data noise immunity. The value of the pullup resistor primari-
transfer is tPROG during which the voltage on the 1-Wire ly depends on the network size and load conditions.
bus must not fall below 2.8V. A pattern of alternating 0s The DS2431 requires a pullup resistor of 2.2kΩ (max) at
and 1s are transmitted after the data has been copied any speed.
until the master issues a reset pulse. If the PF flag is set
The idle state for the 1-Wire bus is high. If for any rea-
or the target memory is copy protected, the copy does
son a transaction needs to be suspended, the bus
not begin and the AA flag is not set.
must be left in the idle state if the transaction is to
Read Memory [F0h] resume. If this does not occur and the bus is left low for
The Read Memory command is the general function to more than 16µs (overdrive speed) or more than 120µs
read data from the DS2431. After issuing the com- (standard speed), one or more devices on the bus
mand, the master must provide the 2-byte target could be reset.
address. After these 2 bytes, the master reads data
beginning from the target address and can continue
Transaction Sequence
until address 008Fh. If the master continues reading, The protocol for accessing the DS2431 through the
the result is logic 1s. The device’s internal TA1, TA2, 1-Wire port is as follows:
E/S, and scratchpad contents are not affected by a • Initialization
Read Memory command.
• ROM Function Command
• Memory Function Command
• Transaction/Data

12 ______________________________________________________________________________________
 1024-Bit, 1-Wire EEPROM

DS2431
VPUP

BUS MASTER DS2431 1-Wire PORT

RPUP
DATA
Rx Rx

Tx IL Tx
Rx = RECEIVE
Tx = TRANSMIT
OPEN-DRAIN
100Ω MOSFET
PORT PIN

Figure 8. Hardware Configuration

Initialization Search ROM [F0h]

When a system is initially brought up, the bus master
All transactions on the 1-Wire bus begin with an initial-
might not know the number of devices on the 1-Wire
ization sequence. The initialization sequence consists
bus or their registration numbers. By taking advantage
of a reset pulse transmitted by the bus master followed
of the wired-AND property of the bus, the master can
by presence pulse(s) transmitted by the slave(s). The
use a process of elimination to identify the registration
presence pulse lets the bus master know that the
numbers of all slave devices. For each bit of the regis-
DS2431 is on the bus and is ready to operate. For more
tration number, starting with the least significant bit, the
details, see the 1-Wire Signaling section.
bus master issues a triplet of time slots. On the first slot,
1-Wire ROM Function each slave device participating in the search outputs
the true value of its registration number bit. On the sec-
Commands ond slot, each slave device participating in the search
Once the bus master has detected a presence, it can outputs the complemented value of its registration num-
issue one of the seven ROM function commands that ber bit. On the third slot, the master writes the true
the DS2431 supports. All ROM function commands are value of the bit to be selected. All slave devices that do
8 bits long. A list of these commands follows (see the not match the bit written by the master stop participat-
flowchart in Figure 9). ing in the search. If both of the read bits are zero, the
master knows that slave devices exist with both states
Read ROM [33h] of the bit. By choosing which state to write, the bus
The Read ROM command allows the bus master to read master branches in the ROM code tree. After one com-
the DS2431’s 8-bit family code, unique 48-bit serial num- plete pass, the bus master knows the registration num-
ber, and 8-bit CRC. This command can only be used if ber of a single device. Additional passes identify the
there is a single slave on the bus. If more than one slave registration numbers of the remaining devices. Refer to
is present on the bus, a data collision occurs when all Application Note 187: 1-Wire Search Algorithm for a
slaves try to transmit at the same time (open drain pro- detailed discussion, including an example.
duces a wired-AND result). The resultant family code and
48-bit serial number result in a mismatch of the CRC. Skip ROM [CCh]
This command can save time in a single-drop bus sys-
Match ROM [55h] tem by allowing the bus master to access the memory
The Match ROM command, followed by a 64-bit ROM functions without providing the 64-bit ROM code. If
sequence, allows the bus master to address a specific more than one slave is present on the bus and, for
DS2431 on a multidrop bus. Only the DS2431 that exact- example, a read command is issued following the Skip
ly matches the 64-bit ROM sequence responds to the ROM command, data collision occurs on the bus as
subsequent memory function command. All other slaves multiple slaves transmit simultaneously (open-drain
wait for a reset pulse. This command can be used with a pulldowns produce a wired-AND result).
single device or multiple devices on the bus.

______________________________________________________________________________________ 13
 1024-Bit, 1-Wire EEPROM
DS2431

BUS MASTER Tx
RESET PULSE
FROM FIGURE 9b
FROM MEMORY FUNCTIONS
FLOWCHART (FIGURE 7)

OD N
RESET PULSE? OD = 0

BUS MASTER Tx ROM DS2431 Tx

FUNCTION COMMAND PRESENCE PULSE

33h 55h F0h CCh

READ ROM N MATCH ROM N SEARCH ROM N SKIP ROM N
COMMAND? COMMAND? COMMAND? COMMAND? TO FIGURE 9b

Y Y Y Y

RC = 0 RC = 0 RC = 0 RC = 0

DS2431 Tx BIT 0
DS2431 Tx
FAMILY CODE MASTER Tx BIT 0 DS2431 Tx BIT 0
(1 BYTE)
MASTER Tx BIT 0

N N
BIT 0 MATCH? BIT 0 MATCH?

Y
Y

DS2431 Tx BIT 1
DS2431 Tx
SERIAL NUMBER MASTER Tx BIT 1 DS2431 Tx BIT 1
(6 BYTES)
MASTER Tx BIT 1

N N
BIT 1 MATCH? BIT 1 MATCH?

Y Y

DS2431 Tx BIT 63
DS2431 Tx
MASTER Tx BIT 63 DS2431 Tx BIT 63
CRC BYTE
MASTER Tx BIT 63

N N
BIT 63 MATCH? BIT 63 MATCH?

Y Y

RC = 1 RC = 1
TO FIGURE 9b

FROM FIGURE 9b

TO MEMORY FUNCTIONS
FLOWCHART (FIGURE 7)

Figure 9a. ROM Functions Flowchart

14 ______________________________________________________________________________________
 1024-Bit, 1-Wire EEPROM

DS2431
TO FIGURE 9a

FROM FIGURE 9a A5h 3Ch 69h

RESUME N OVERDRIVE- N OVERDRIVE- N
COMMAND? SKIP ROM? MATCH ROM?

Y Y Y

RC = 0; OD = 1 RC = 0; OD = 1
N
RC = 1?

Y
MASTER Tx BIT 0

MASTER Tx Y N
BIT 0 MATCH? OD = 0
RESET?

N Y

MASTER Tx BIT 1

MASTER Tx Y
RESET?
N
N BIT 1 MATCH? OD = 0

MASTER Tx BIT 63

N
BIT 63 MATCH? OD = 0

RC = 1
FROM FIGURE 9a

TO FIGURE 9a

Figure 9b. ROM Functions Flowchart (continued)

______________________________________________________________________________________ 15
 1024-Bit, 1-Wire EEPROM
Resume [A5h] 1-Wire Signaling
DS2431

To maximize the data throughput in a multidrop envi-

The DS2431 requires strict protocols to ensure data
ronment, the Resume command is available. This com-
integrity. The protocol consists of four types of signal-
mand checks the status of the RC bit and, if it is set,
ing on one line: reset sequence with reset pulse and
directly transfers control to the memory function com-
presence pulse, write-zero, write-one, and read-data.
mands, similar to a Skip ROM command. The only way
Except for the presence pulse, the bus master initiates
to set the RC bit is through successfully executing the
all falling edges. The DS2431 can communicate at two
Match ROM, Search ROM, or Overdrive-Match ROM
different speeds: standard speed and overdrive speed.
command. Once the RC bit is set, the device can
If not explicitly set into the overdrive mode, the DS2431
repeatedly be accessed through the Resume com-
communicates at standard speed. While in overdrive
mand. Accessing another device on the bus clears the
mode, the fast timing applies to all waveforms.
RC bit, preventing two or more devices from simultane-
ously responding to the Resume command. To get from idle to active, the voltage on the 1-Wire line
needs to fall from VPUP below the threshold VTL. To get
Overdrive-Skip ROM [3Ch] from active to idle, the voltage needs to rise from
On a single-drop bus this command can save time by VILMAX past the threshold VTH. The time it takes for the
allowing the bus master to access the memory func- voltage to make this rise is seen in Figure 10 as ε, and
tions without providing the 64-bit ROM code. Unlike the its duration depends on the pullup resistor (RPUP) used
normal Skip ROM command, the Overdrive-Skip ROM and the capacitance of the 1-Wire network attached.
command sets the DS2431 into the overdrive mode The voltage VILMAX is relevant for the DS2431 when
(OD = 1). All communication following this command determining a logical level, not triggering any events.
must occur at overdrive speed until a reset pulse of
Figure 10 shows the initialization sequence required to
minimum 480µs duration resets all devices on the bus
begin any communication with the DS2431. A reset
to standard speed (OD = 0).
pulse followed by a presence pulse indicates that the
When issued on a multidrop bus, this command sets all DS2431 is ready to receive data, given the correct ROM
overdrive-supporting devices into overdrive mode. To and memory function command. If the bus master uses
subsequently address a specific overdrive-supporting slew-rate control on the falling edge, it must pull down
device, a reset pulse at overdrive speed must be the line for tRSTL + tF to compensate for the edge. A
issued followed by a Match ROM or Search ROM com- tRSTL duration of 480µs or longer exits the overdrive
mand sequence. This speeds up the time for the mode, returning the device to standard speed. If the
search process. If more than one slave supporting DS2431 is in overdrive mode and tRSTL is no longer
overdrive is present on the bus and the Overdrive-Skip than 80µs, the device remains in overdrive mode. If the
ROM command is followed by a read command, data device is in overdrive mode and tRSTL is between 80µs
collision occurs on the bus as multiple slaves transmit and 480µs, the device resets, but the communication
simultaneously (open-drain pulldowns produce a wired- speed is undetermined.
AND result).
After the bus master has released the line it goes into
Overdrive-Match ROM [69h] receive mode. Now the 1-Wire bus is pulled to VPUP
The Overdrive-Match ROM command followed by a 64- through the pullup resistor or, in the case of a DS2482-
bit ROM sequence transmitted at overdrive speed x00 or DS2480B driver, through the active circuitry.
allows the bus master to address a specific DS2431 on When the threshold VTH is crossed, the DS2431 waits
a multidrop bus and to simultaneously set it in overdrive for tPDH and then transmits a presence pulse by pulling
mode. Only the DS2431 that exactly matches the 64-bit the line low for tPDL. To detect a presence pulse, the
ROM sequence responds to the subsequent memory master must test the logical state of the 1-Wire line at
function command. Slaves already in overdrive mode tMSP.
from a previous Overdrive-Skip ROM or successful The t RSTH window must be at least the sum of
Overdrive-Match ROM command remain in overdrive t PDHMAX , t PDLMAX , and t RECMIN . Immediately after
mode. All overdrive-capable slaves return to standard tRSTH is expired, the DS2431 is ready for data commu-
speed at the next reset pulse of minimum 480µs dura- nication. In a mixed population network, tRSTH should
tion. The Overdrive-Match ROM command can be used be extended to minimum 480µs at standard speed and
with a single device or multiple devices on the bus. 48µs at overdrive speed to accommodate other 1-Wire
devices.

16 ______________________________________________________________________________________
 1024-Bit, 1-Wire EEPROM

DS2431
MASTER Tx "RESET PULSE" MASTER Rx "PRESENCE PULSE"
ε
tMSP
VPUP
VIHMASTER
VTH

VTL
VILMAX
0V
tPDH
tRSTL tPDL tREC
tF
tRSTH

RESISTOR MASTER DS2431

Figure 10. Initialization Procedure: Reset and Presence Pulse

Read/Write Time Slots Slave-to-Master

Data communication with the DS2431 takes place in A read-data time slot begins like a write-one time slot.
time slots that carry a single bit each. Write time slots The voltage on the data line must remain below VTL
transport data from bus master to slave. Read time until the read low time tRL is expired. During the tRL
slots transfer data from slave to master. Figure 11 illus- window, when responding with a 0, the DS2431 starts
trates the definitions of the write and read time slots. pulling the data line low; its internal timing generator
All communication begins with the master pulling the determines when this pulldown ends and the voltage
data line low. As the voltage on the 1-Wire line falls starts rising again. When responding with a 1, the
below the threshold VTL, the DS2431 starts its internal DS2431 does not hold the data line low at all, and the
timing generator that determines when the data line is voltage starts rising as soon as tRL is over.
sampled during a write time slot and how long data is The sum of tRL + δ (rise time) on one side and the inter-
valid during a read time slot. nal timing generator of the DS2431 on the other side
define the master sampling window (t MSRMIN to
Master-to-Slave tMSRMAX), in which the master must perform a read
For a write-one time slot, the voltage on the data line from the data line. For the most reliable communication,
must have crossed the VTH threshold before the write- tRL should be as short as permissible, and the master
one low time tW1LMAX is expired. For a write-zero time should read close to but no later than tMSRMAX. After
slot, the voltage on the data line must stay below the reading from the data line, the master must wait until
VTH threshold until the write-zero low time tW0LMIN is tSLOT is expired. This guarantees sufficient recovery
expired. For the most reliable communication, the volt- time tREC for the DS2431 to get ready for the next time
age on the data line should not exceed VILMAX during slot. Note that tREC specified herein applies only to a
the entire tW0L or tW1L window. After the VTH threshold single DS2431 attached to a 1-Wire line. For multide-
has been crossed, the DS2431 needs a recovery time vice configurations, tREC must be extended to accom-
tREC before it is ready for the next time slot. modate the additional 1-Wire device input capacitance.
Alternatively, an interface that performs active pullup
during the 1-Wire recovery time such as the DS2482-
x00 or DS2480B 1-Wire line drivers can be used.

______________________________________________________________________________________ 17
 1024-Bit, 1-Wire EEPROM
DS2431

WRITE-ONE TIME SLOT

tW1L
VPUP
VIHMASTER
VTH

VTL
VILMAX
0V
ε
tF
tSLOT

RESISTOR MASTER

WRITE-ZERO TIME SLOT

tW0L
VPUP
VIHMASTER
VTH

VTL
VILMAX
0V
ε
tF tREC
tSLOT

RESISTOR MASTER

READ-DATA TIME SLOT

tMSR
tRL
VPUP
VIHMASTER
VTH MASTER
SAMPLING
VTL WINDOW
VILMAX
0V
δ
tF tREC
tSLOT

RESISTOR MASTER DS2431

Figure 11. Read/Write Timing Diagrams

18 ______________________________________________________________________________________
 1024-Bit, 1-Wire EEPROM
Improved Network Behavior (Figure 12, Case B, tGL < tREH). Deep voltage drops

DS2431
or glitches that appear late after crossing the VTH
(Switchpoint Hysteresis) threshold and extend beyond the tREH window can-
In a 1-Wire environment, line termination is possible not be filtered out and are taken as the beginning of a
only during transients controlled by the bus master new time slot (Figure 12, Case C, tGL ≥ tREH).
(1-Wire driver). 1-Wire networks, therefore, are suscep- Devices that have the parameters VHY and tREH speci-
tible to noise of various origins. Depending on the fied in their electrical characteristics use the improved
physical size and topology of the network, reflections 1-Wire front-end.
from end points and branch points can add up or can-
cel each other to some extent. Such reflections are visi- CRC Generation
ble as glitches or ringing on the 1-Wire communication The DS2431 uses two different types of CRCs. One
line. Noise coupled onto the 1-Wire line from external CRC is an 8-bit type and is stored in the most signifi-
sources can also result in signal glitching. A glitch dur- cant byte of the 64-bit ROM. The bus master can com-
ing the rising edge of a time slot can cause a slave pute a CRC value from the first 56 bits of the 64-bit
device to lose synchronization with the master and, ROM and compare it to the value stored within the
consequently, result in a Search ROM command com- DS2431 to determine if the ROM data has been
ing to a dead end or cause a device-specific function received error-free. The equivalent polynomial function
command to abort. For better performance in network of this CRC is X 8 + X 5 + X 4 + 1. This 8-bit CRC is
applications, the DS2431 uses a new 1-Wire front-end, received in the true (noninverted) form. It is computed
which makes it less sensitive to noise. at the factory and lasered into the ROM.
The DS2431’s 1-Wire front-end differs from traditional The other CRC is a 16-bit type, generated according to
slave devices in three characteristics. the standardized CRC-16 polynomial function X16 + X15
1) There is additional lowpass filtering in the circuit that + X2 + 1. This CRC is used for fast verification of a data
detects the falling edge at the beginning of a time transfer when writing to or reading from the scratchpad.
slot. This reduces the sensitivity to high-frequency In contrast to the 8-bit CRC, the 16-bit CRC is always
noise. This additional filtering does not apply at communicated in the inverted form. A CRC generator
overdrive speed. inside the DS2431 chip (Figure 13) calculates a new 16-
2) There is a hysteresis at the low-to-high switching bit CRC, as shown in the command flowchart (Figure 7).
threshold VTH. If a negative glitch crosses VTH but The bus master compares the CRC value read from the
does not go below VTH - VHY, it is not recognized device to the one it calculates from the data and
(Figure 12, Case A). The hysteresis is effective at decides whether to continue with an operation or to
any 1-Wire speed. reread the portion of the data with the CRC error.
3) There is a time window specified by the rising edge With the Write Scratchpad command, the CRC is gen-
hold-off time tREH during which glitches are ignored, erated by first clearing the CRC generator and then
even if they extend below the VTH - VHY threshold shifting in the command code, the target addresses
TA1 and TA2, and all the data bytes as they were sent

tREH tREH
VPUP

VTH
VHY

CASE A CASE B CASE C

0V
tGL tGL

Figure 12. Noise Suppression Scheme

______________________________________________________________________________________ 19
 1024-Bit, 1-Wire EEPROM
DS2431

POLYNOMIAL = X16 + X15 + X2 + 1

1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH

STAGE STAGE STAGE STAGE STAGE STAGE STAGE STAGE

X0 X1 X2 X3 X4 X5 X6 X7

9TH 10TH 11TH 12TH 13TH 14TH 15TH 16TH

STAGE STAGE STAGE STAGE STAGE STAGE STAGE STAGE

X8 X9 X10 X11 X12 X13 X14 X15 X16 CRC OUTPUT

INPUT DATA

Figure 13. CRC-16 Hardware Description and Polynomial

by the bus master. The DS2431 transmits this CRC only TA1 and TA2, the E/S byte, and the scratchpad data as
if E[2:0] = 111b. they were sent by the DS2431. The DS2431 transmits
With the Read Scratchpad command, the CRC is gen- this CRC only if the reading continues through the end
erated by first clearing the CRC generator and then of the scratchpad. For more information on generating
shifting in the command code, the target addresses CRC values, refer to Application Note 27.

Command-Specific 1-Wire Communication Protocol—Legend

SYMBOL DESCRIPTION
RST 1-Wire reset pulse generated by master.
PD 1-Wire presence pulse generated by slave.
Select Command and data to satisfy the ROM function protocol.
WS Command "Write Scratchpad."
RS Command "Read Scratchpad."
CPS Command "Copy Scratchpad."
RM Command "Read Memory."
TA Target address TA1, TA2.
TA-E/S Target address TA1, TA2 with E/S byte.
<8–T[2:0] bytes> Transfer of as many bytes as needed to reach the end of the scratchpad for a given target address.
<Data to EOM> Transfer of as many data bytes as are needed to reach the end of the memory.
CRC-16 Transfer of an inverted CRC-16.
FF Loop Indefinite loop where the master reads FF bytes.
AA Loop Indefinite loop where the master reads AA bytes.
Programming Data transfer to EEPROM; no activity on the 1-Wire bus permitted during this time.

20 ______________________________________________________________________________________
 1024-Bit, 1-Wire EEPROM
Command-Specific 1-Wire Communication Protocol—Color Codes

DS2431
Master to Slave Slave to Master Programming

1-Wire Communication Examples

Write Scratchpad (Cannot Fail)

RST PD Select WS TA <8–T[2:0] bytes> CRC-16 FF Loop

Read Scratchpad (Cannot Fail)

RST PD Select RS TA-E/S <8–T[2:0] bytes> CRC-16 FF Loop

Copy Scratchpad (Success)

RST PD Select CPS TA-E/S Programming AA Loop

Copy Scratchpad (Invalid Address or PF = 1 or Copy Protected)

RST PD Select CPS TA-E/S FF Loop

Read Memory (Success)

RST PD Select RM TA <Data to EOM> FF Loop

Read Memory (Invalid Address)

RST PD Select RM TA FF Loop

______________________________________________________________________________________ 21
 1024-Bit, 1-Wire EEPROM
Memory Function Example
DS2431

Write to the first 8 bytes of memory page 1. Read the With only a single DS2431 connected to the bus mas-
entire memory. ter, the communication looks like this:
MASTER MODE DATA (LSB FIRST) COMMENTS
Tx (Reset) Reset pulse
Rx (Presence) Presence pulse
Tx CCh Issue “Skip ROM” command
Tx 0Fh Issue “Write Scratchpad” command
Tx 20h TA1, beginning offset = 20h
Tx 00h TA2, address = 0020h
Tx <8 Data Bytes> Write 8 bytes of data to scratchpad
Rx <2 Bytes CRC-16> Read CRC to check for data integrity
Tx (Reset) Reset pulse
Rx (Presence) Presence pulse
Tx CCh Issue “Skip ROM” command
Tx AAh Issue “Read Scratchpad” command
Rx 20h Read TA1, beginning offset = 20h
Rx 00h Read TA2, address = 0020h
Rx 07h Read E/S, ending offset = 111b, AA, PF = 0
Rx <8 Data Bytes> Read scratchpad data and verify
Rx <2 Bytes CRC-16> Read CRC to check for data integrity
Tx (Reset) Reset pulse
Rx (Presence) Presence pulse
Tx CCh Issue “Skip ROM” command
Tx 55h Issue “Copy Scratchpad” command
Tx 20h TA1
Tx 00h TA2 (AUTHORIZATION CODE)
Tx 07h E/S
— <1-Wire Idle High> Wait t PROGMAX for the copy function to complete
Rx AAh Read copy status, AAh = success
Tx (Reset) Reset pulse
Rx (Presence) Presence pulse
Tx CCh Issue “Skip ROM” command
Tx F0h Issue “Read Memory” command
Tx 00h TA1, beginning offset = 00h
Tx 00h TA2, address = 0000h
Rx <144 Data Bytes> Read the entire memory
Tx (Reset) Reset pulse
Rx (Presence) Presence pulse

22 ______________________________________________________________________________________
 1024-Bit, 1-Wire EEPROM
Pin Configurations

DS2431
SIDE VIEW FRONT VIEW

GND 1 1

IO 2 2

N.C. 3 3

TO-92 FRONT VIEW (T&R VERSION)

TOP VIEW TOP VIEW

GND N.C. N.C.
+
A1 A2 A3
GND 1 6 N.C.

IO 2 5 N.C.
DS2431 DS2431
N.C. 3 4 N.C. C1 C2 C3

IO N.C. N.C.
TSOC
UCSPR

TOP VIEW

BOTTOM VIEW SIDE VIEW

DS2431 1 2
+
N.C. 1 6 N.C.
ymrrF
2431

IO 2 5 N.C. IO GND

GND 3 4 N.C.
*EP SFN
(6mm × 6mm × 0.9mm)

NOTE: THE SFN PACKAGE IS QUALIFIED FOR ELECTRO-MECHANICAL

TDFN-EP CONTACT APPLICATIONS ONLY, NOT FOR SOLDERING. FOR MORE
(3mm × 3mm) INFORMATION, REFER TO APPLICATION NOTE 4132: ATTACHMENT
*EXPOSED PAD METHODS FOR THE ELECTRO-MECHANICAL SFN PACKAGE.

______________________________________________________________________________________ 23
 1024-Bit, 1-Wire EEPROM
SFN Package Orientation on Tape and Reel
DS2431

USER DIRECTION OF FEED

LEADS FACE UP IN ORIENTATION SHOWN ABOVE.

Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.

PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.

3 TO-92 (Bulk) Q3+1 21-0248 —
3 TO-92 (T&R) Q3+4 21-0250 —
6 TSOC D6+1 21-0382 90-0321
2 SFN G266+1 21-0390 —
6 TDFN-EP T633+2 21-0137 90-0058
Refer to
6 UCSPR BR622+1 21-0376
Application Note 1891

24 ______________________________________________________________________________________
 1024-Bit, 1-Wire EEPROM
Revision History

DS2431
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
0 050704 Initial release. ——

Replaced Pin Configuration. 1

In the Electrical Characteristics table, changed VTL(MIN) from 0.5V to 0.46V and
1 081604 2
VTL(MAX) from 4.1V to 4.4V; changed VHY(MIN) from 0.22V to 0.21V
In the Copy Scratchpad [55h] section, corrected the copy time from 13ms to 12.5ms. 14

Added the SFN package and updated the Ordering Information table. 1, 24
In the Pin Configuration, added a note to the CSP package outline “*See package
1
reliability report for important guidelines on qualified usage conditions.”

2 090506 In the Electrical Characteristics table, changed the t PROG (programming time) EC
table parameter from 12.5ms to 10ms for version A2 (see also pages 1, 13).
1, 2, 3, 13
Removed tFPD and updated tPDH, tMSP, tW0L accordingly. Changed IPROG max to
0.8mA to match GBD.
Updated Memory Function Example table. 23

Added CSP package outline drawing number to Pin Configuration. 1

Changed VTL(MIN) from 0.46V to 0.5V in the Electrical Characteristics table. 2

In the Absolute Maximum Ratings, changed storage temp to -55°C to +125°C; in the
3 122106 Electrical Characteristics table, changed VTH, VTL based on VPUP and data retention
to 40 years min at 85°C; added note to retention spec: “EEPROM writes can become
1, 2, 3
nonfunctional after the data-retention time is exceeded. Long-term storage at
elevated temperatures is not recommended; the device can lose its write capability
after 10 years at +125°C or 40 years at +85°C.”
In the Ordering Information table, removed all leaded part numbers and added the
1, 24
TDFN-EP package.
In the Electrical Characteristics table, changed the VIL(MAX) spec from 0.3V to 0.5V;
removed
from the tW1L(MAX) spec; added Note 17 to tW0L spec; updated EC table 2, 3
Notes 17 and 18; corrected Note 20.
Added EP function to the Pin Description table. 3
4 102207
Added
to Figure 11 Write-Zero Time Slot. 19
In the Pin Configuration, added the package drawing information/weblink and a note
that the SFN package is qualified for electro-mechanical contact applications only,
not for soldering. Added the SFN Package Orientation on Tape-and-Reel section. In
24
the Ordering Information, added note to contact factory for availability of the UCSPR
package. Added note that TO-92 T&R leads are formed to approximately 100-mil
spacing.
In the SFN Pin Configuration, added reference to Application Note 4132. 24
5 032008
Added Package Information table. 25

6 8/08 Created newer template-style data sheet. All

______________________________________________________________________________________ 25
 1024-Bit, 1-Wire EEPROM
Revision History (continued)
DS2431

REVISION REVISION PAGES

DESCRIPTION
NUMBER DATE CHANGED
Deleted “contact factory” note in Ordering Information; updated Pin Description and
7 6/09 1, 5, 23
Pin Configurations to reflect changes in pin assignment of UCSPR package.
8 10/09 Corrected part number in Ordering Information table. 1

9 12/10 Deleted the automotive version reference in the Features section 1

10 3/11 Added the automotive version reference to the Features section 1

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

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