Introduction: > © The counters ate composed wilh Flip-Flops and combinational clements ¢ isa ecquential circuit forming by the cascading of FFs. © Acounter circuit with n-FFs has maximum 2" possible states. {otal numbor of states and n = number of FFs then, Also, if N Ns2 BM) = 1 2log,N = BEEK (8.2) © If N = 25, then we get BINARY COUNTER. © TEN < 2% then we get NON-BINARY COUNTER: © MOD Number: © Tho "MOD-number" indicates the number of states in counting. sequence. A © FornFFs, counter withiave eet aes and then this Counter is said to be "MOD-2° Counte * MOD number indicates the trequehoy division obtained from the Last FF, * Itwould be capable of counting upto (2”— 1) before returning to zero stato. f= Based upon the applying CLK pulse, Counters are ui wo types: © “Asynchronous counter (Ripple counter) © Synchronous counter. To 1ES MADE EASY, Now Dal (© Copyright Subject mat ai — India’s Bost Institute for IES, GATE & PSUs — osi LECTRONICSENGG (2011) DIGTAL ELECTRONICS (2 ites Mh bitetizenr2. was ©. Synchronous Counter Asynchronous Counter vent] 1 AlFFeeetiggered wih 4 Totes oma CLK. 2. Operations faster 2 a) 4 5, lis design is complex. 5, is designs relatively ey. + UP/Down Counter: © Wacounter countsin ouch a wai that tt irl equivalent cl output irexeaces with Successive CLK pulses, is caled as "UP Counter® «ifthe decimal equivalent the output deoredses with successive CLK pulses then itis called “Down Counter" + 2 UP/Down Counter” can count in any direction depending upenthecontrl input, ; Application of Counters: + Tocount he runner of CLK Pulses. “To count the sumer of tems in industry, — Ls 2 “Frequency divider” ¢ Intime measurement. * For distance measurement in Radar system. «In Anatog 0 Digital converter (ADC). * Iameacurementof PRI (Pulse Repelition Interference). Note: = | "MOD-N Counter’, applied input frequency is“, then outcut frequency is {1M = i two counters are cascaded with MOD-M followed by MOD-H, then umber of eral stjes of combined Goneris (Ue) and counter icalled*MOD-MN" cotnle, MOD-MN counter wet] Ufone {MN AEE © Copyright Subject matier a IES MADE EASY, Now Dain No part , GATE & PSUs —ew OPE TEOTE aes co 4 1 Mleb: wen Asynchronous (Ripple Counter): . unter” and @ * Hore wo discussed the "Binary c modo FFs (10, JK of FFF), © Figure 8.2(a) shows the 3-bitt sy ripple cour a series eon cach FF ¢ + ThoFF hol jon of Complementing Fl ted to tho CP inp ing the LSB receiv fio) Fret Se) Ak ruse Fig. 8.2(a) * Qpinil change tis state in every CLK pulse : © Qywitlel ‘00 Qi chang 10.0. © Truth table: SCLK 2 2) we i 2 4 5 6 sa = 0.0 d 6,9} 3 i ic eS 01s Initially alt EFS ere get to 2610, ? Maximum possible states =.8 (Irom 0, 107). Fixed sequence follows, Sp.itis an Uy IP. Counter’? > (E5 MADE EASY, Now "input frequency is then here output frequency = 1 In tipple counter with A-FFS there are 20 © Wilh n-FFs the maxin Possible states, MUM count that can by * Ts glso called (2": 1) seatar counter © Copyright. Subjoct matter N WOES? ee Institute for 188, @LECTRONICS ENGG (2011) DIGITALELECTRONICS © Timing Diagram: + Wouse (-vo) edge triggering. “Strobe Input". fetermination of UP/Down Counter Triggering with | CLK connectionin | Access as (-ve) edge Q UP Counter (-ve) edge a Down Counter (+ve) edge Q Down Counter — Ltve) edge a UP Counter fasra rete er ee ores India’s Bes! Institute for 1 TE & PSUS.~ CLASSROOMS Non-Binary Ripple Counter: er of Mod-10 Counter sTuDY COURSE (CSC) eats + Witen Decade counter cdtins fr’ Cy Sg gale =O NOR-gate jed in any form without we iBook migy be reproduced or it far 19 ES WADE EASY, Now 06 © Copyright: Subject mJECTRONICS ENGG (2011) DIGITAL ELECTRONICS Protests Exampto 8.1 Design a 4-bit binary UP/DOWN ripple counter witli a controt for UP/DOWN connting, qed Solution hel Tho 4-bit binary UP/DOWN tipple counter is stiowa be reproduce roo may Example 5.2) MOD-60 counter was a 10 troquency, down 0 1 He. Consist an IES WADE EASY, Now Dain, Ho Bi ~ NAND gate, (Tho ot THz. © Copyright: Subject me eae 5g inca Boat neta or eS, GATE PSUS — | + Sembee ‘Nawee Guewee cease (30)(132) CLASSROOM STUDY COURSE (csc) cr, Now Terprna Gow HAT, Kas SH a on (011-45124612, ‘onanosat651, wie Dai 110016: Regd. Ooo: 25 Ber Say fp: wor maderasyin E-mail: ieee Need Example The ripple counter shown in the iu in any form without the watten permission, ig Book May OG reproduced-or SETS SESE — inaia’s Bost inottate tor es © Copyright: Subject matter to IES MADE EASY, N “S, GATE & PStieELECTRONICS ENGG (2011) {ay Mod's {e) Mod-7 counter = It's also an UP Counter, + Example 8.5. Inthe modulo-6 ripple coun -Q QQ, VF Oe A eS. counter, Ans. (a) | DIGITALELECTRONICS ‘E6a Wew Deni C016, Hogi OWicw 2A, Go Zara, Haw Don TVOOTE ASAE, We: wor mtessyin, Ema lesmnce » igure, the output. counter. Whatiate 1133) ayaten coin Student! tes Tia bart of this book may be reproduced 0 1D IES MADE EASY, New Doth a 8 ° — India's Best Institute for 1ES; GATE & PSUs — Rasa renee er Boon Coase CED + Casioon shy 1 Ponal Suey couse {ero Gren Coosa 100)ew Dot 10 ea wor? past | tlip- flop. 1 the | conds, the. kl to. Example 8.7 A Abit mi propagation dkay of 6° ook frequency nel ouuto-16-ripple counter ach tip-top #8 ‘ean be used 18.66 (a) 20 MHz (oy TOME (c) 8 Mile (ad) 5 Mele 50 nanos inavinnnan ele Solution: Synchronous (Parallel) Counters: +The problems encotintefec with ipple counters ae eased bythe: | the: acéumulated FFs propagation delay In other words, thie FFs do , Not charge st svicvoris with the input iat write! sin = “sypahtel La i i ‘SR counters Sorias-carry a [ : countor, Pielohcary Ring ‘Twisted comer so cotter Wotnecn count) Solstarting ring counter [Not so-staring fing counter India’s Bost Insltato for1E8, GA ios “Kak So ys wench Ema a Cesyripnt Subject mal =— ILECTRONICS ENGG (2011) DIGITAL ELECTRONICS ESN ne itcioan enn ne am One Eh EDs on Tam ‘NOT-Self Starting Ring Counter: + itis nothing but SISO shilt register, + tis alo known as “End-Carry Counter’ + itis 2 synchronous counter. 3, BF] Ta ist . cu PLT, z Fig. 8.40) + In this counter LSB-FF input (0) Se only one bit is high and circu (il Initetly Dy =) Clock 'Q,".0, A, 0, tpul-"O,° iS connected to the MSB-FF Fig. 8.4(6) ‘State diagram => within FFs, there are n-states present in ring counter. ness a states px = with n FFs, maxieitim count possible in ring counter is (2-1). => Decoding is very easy in Ring counter, because there is no aid of extra circuit. “a (or IES. GATE 8 PSUs — far fo 6S MAOEEASY, New Dal 1135) € samen (his Book may be raproauced ora rights Sub © Con JS} ELECTRONICS fig. 85 a. co 8 6 41 660 2);0 1 0 6 230 0 1 6 e {ooo 4 |i 0,0 6 0 1\5 o 60 414 lo oo 5 Ji 000 fing counter the used states = 4 znd the unused Bn4n 2, (CLK frequency is “T the FFs output quency. is “HN" (where N = No. of states). = This counter is also called “And catty counter", © Twisted-Ring Counter: - = This counter is nothing but a shift register zhich is aleo known * Johnson Counter . Telling Counter Sy Subject matter to IES MADE EASY, New Suinl No pa Telus Sook may beret iar tah,ELECTRONICS ENGG (2011) DIGITALELECTRONICS (137) Syates 20m £ Pg ql ito *0 0 : 2 | 1d1o™o 2 ay] dio 2 an peg ] 2888 . 5. (flogts 14 7 6 [oom z + fosotet! i 8 |o *o *o *o. iz = with n FFs there até 2n states in this counter, fe > with n FFs the maximum count by this couiiter is (2” - 1). B _In_notme! “Johnson Counter” with n FFs and the input | 2 frequency is." then output freauengy. of Rss “Wan* (where - | « Ina>Counler fa feedback connection is used the.number of possible slates will decreases. : “ Synchronous-Series Carry Counter: “Q 9 1ES WADE EASY, Now Dati © Copyright Subject matELEC SE(CSC) i 1 groom STUDY COUR’ : a Na hOB [SESSLER nt ests ws meme © Circuit Operation «The basie principle of operation of th “Tho d and K inputs of the FFs are those FFs that ate supposed to toggle en hava d= K = bwhen synchronous counter is nected so that only a given NOT will that NGT oceuts’ + lathis counter, Tere 2 byagrry 10 2) Iya. ote) (8.8) + Most unpottant advantages of this counter is that it f@duces the “decoding ever" Junter ig much lower than an asynchronous € 2 fB.7) ® Synchronous-Parallel Carry Counter: i + Itie physically same as that the counter shown in figure 8.7, but it hi is logically different. : + ACs the “Festost Countert @ Genviiaht Subiect maar ta \ES MAE FASY Naw fnihi Na hart al Nis Honiinay ha renvadhioad AF (6) Bekertine: Solutios “(a1 is eqoal to, Nig |. and £9 thé poral eounictYRONICS ENGG (2011) DIGHAL ELEETONIE® ANT, wats al He PRAHA mnuat bo acted ninen OU Ma GE hapa ol hi ( «also tied to the input prifeos. Her and dapae ata bec by the foi npn AND Gate wiisa mpObs ie A ALO ane J detennines! as a1 Ga) egal ob he ambor ahs aol conten 1M G8 M0 LSE MI Synchronous Counter design: + Synchrounouss countors tor any given count aequange ANNO canbe designed in the follwing Way: 1. Find tho number of Flip Hops requite), |Waito the count sequonce in tho Kab Foun Determine tho Flip-Hlop inpita which mist be proseni for the dosired next stato from tha prosont slate using tho oxetialiont tablo of tho Flip-tlops. 4. Proparo K-map for each Flip-lop input in tons of Hi fey outputs as tho input variables, Simply tho Kemaps ani ebtialt the minimized expressions Connect the circult using Flip-tlop corresponding to the minienized expressions: had other gates o Exhinple 8.9 fe ver Design a Spit eynchtonons€ The nomnbor of Fig: Hops esiquited Retens i FEO: FFT and FFP and nny aut a ode bow — Indla'y Beet Instie a IiBICb, Wath rene Fb soe goon [eB iunaELECTRO} sav inure Fant Oe S un rooney CAN of lip-tlops aro given, { earninod by USING son a foc ito ivvcountenavence an ye ne fuss to the Agr Teo fst We eticider Oy 5 ie the second Se CH “fe 0. neelere, het Sy raiie1O TES TIADE ERGY, New Dain Wo par ofa book may be reproduced or vlad any form wut thewLECTRONICS ENGG (201 __DIGNAL ELECTRONICS wth diy i lk een ae © Exumpto 8.10 A Dit tipple counter and a 4 bit synctite = countor ion dotay of 10 ns) made using tip Hops i 3 cach. H the worst c To the ripple courter end the |] E hroneus counter be Rand $ respectively, ther a) 13 (R= 10s, $= 40ns IR tons, = song's | | E (CB = tans, § (2) R= 90a oe a 8 {GATE-2004) Sclution” pple coutens 4s tens Ons. y= Example BT gS AL A0 to 6 counter consists of 3 flip flops and circuit of 2 input atte) 19165 MADE EASY, How Dal No part ot ‘ “ (a) ona AND gate Ab) on0.OR ate ~ (¢) on AND ey 1 ng Cus ‘© Cooyight: SubjectAnh pe) CLASSROOM STUDY COURSE | 1 avaey thar otonanativt ALU rf ~ je vwitly \ m Saitrogiate 1 Reameaey Binns Sotution: (by Ausaossing uv suaneny ebys R. Becedter A Sorat te paratter dite SANyTsion @P-3.a Ayre aa qn sy fP-2.a Pe ARF © 2) 08. 04,90, 11 BVO Wado (E}CONOT, 11200, DL LAR I COL A) Sstution * - S “Example 8.14 ~The given figure sin a nipphs count * giggered tlip-lops {the present state ortho coUMIe 15 0,0, next state (Q,Q,Q,)witl bo USMY positive mye) UE, then thy 4 ieee Titer 1 ES WEEE ew oar areELECTRONICS ENGG (2011) DIGITAL ELECTRONICS [143] e Stodent A ao cue et (b) 160 ee (w) 101 Baliga S25. [GATE-2005) it, CLK is (+)ve'ectge tigcered and Q fs | connected as output so this counters an “UP Counter” i Oy 2), Oye | Prgcont tate Ot day Ge 1 From this gion cr fio dae 1G 9G SARS (b) 7 Exampte 8.15 What are the counting ststes (Q,, Sin the figure below? fer the counter shows (a) 14,10, 00-44, 4 {c} 00, 41,01; 10, 00, Solution: opie Initialy all.FFs are set 10 2650, CLK eK rie ts us 48 1 Ter 10 1E5 MADE EASY, New Deli: Na part of nis boom may be repro Mais zig ae 3 correct sequerice is, © Copyright Subject mat SEER — ces nor rae 15, a0 6 PSU —Soa, New DOR eae, Wobr wa Foe mae in «own courte is 0110. Alte ¢ counter willbe a fe (b) O10: Ue (g) COOL. = he init 6 pown Counter, $0 mob-1 0110 cont ne counter contents ais of couMeL Ot eA falany pa y panlicular tine © Mita i Pig e number ot aK