Mipi A PHY Specification v1 1 1

Specification for
14BDRAF
A-PHY®
Version 1.1.1 – 13 December 2022

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MIPI Board Adopted 24 May 2023
* NOTE TO IMPLEMENTERS *
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This document is a MIPI Specification. MIPI member companies’ rights and obligations apply to this Specification as
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Specification for
1
A-PHY®
Version 1.1.1
10B
13 December 2022
8
MIPI Board Adopted 24 May 2023
Further technical changes to this document are expected as work continues in the A-PHY Working
2B
Group.
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Specification for A-PHY Version 1.1.1
13-Dec-2022
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Version 1.1.1 Specification for A-PHY
13-Dec-2022
Contents
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Figures ...................................................................................................................................... x
Tables .................................................................................................................................... xiv
Release History...................................................................................................................... xix
1 Introduction ................................................................................................................. 1
1.1 Scope ................................................................................................................................... 1
1.1.1 In Scope ........................................................................................................................ 1
1.1.2 Out of Scope ................................................................................................................. 1
1.2 Purpose ................................................................................................................................ 2
2 Terminology ................................................................................................................. 3
2.1
Use of Special Terms ........................................................................................................... 3
2.2
Definitions ........................................................................................................................... 3
2.3
Abbreviations ...................................................................................................................... 4
2.4
Acronyms ............................................................................................................................ 5
3 References .................................................................................................................... 7
3.1 Normative References ......................................................................................................... 7
3.2 Informative References ....................................................................................................... 7
4 Overview ...................................................................................................................... 9
5 Architecture ............................................................................................................... 11
5.1 High Level Structure ......................................................................................................... 11
5.2 A-PHY Ports...................................................................................................................... 13
5.2.1 C-Port .......................................................................................................................... 13
5.2.2 D-Port ......................................................................................................................... 13
5.2.3 Q-Port ......................................................................................................................... 14
5.2.4 Gears ........................................................................................................................... 16
5.2.4.1 Normative Downlink and Reverse Downlink Gears ......................................... 16
5.2.4.2 Normative-Optional Gears ................................................................................ 17
5.2.4.3 Normative Uplink Gears.................................................................................... 17
5.2.4.4 Q-Port Configurations Per Gear ........................................................................ 18
5.3 Profiles .............................................................................................................................. 21
5.4 Safety ................................................................................................................................. 22
6 Interconnect ............................................................................................................... 23
6.1 Lane Configuration............................................................................................................ 23
6.2 Cable Topology ................................................................................................................. 24
6.3 Boundary Conditions......................................................................................................... 24
6.4 S-Parameter Specifications................................................................................................ 25
6.5 Characterization Conditions .............................................................................................. 25
6.6 Interconnect Specifications ............................................................................................... 26
6.6.1 Total Interconnect ....................................................................................................... 26
6.6.2 Cable TLIS (Transmission Line Interconnect Structure) ............................................ 27
6.6.2.1 Characteristic Impedance .................................................................................. 27
6.6.2.2 Insertion Loss .................................................................................................... 27
6.6.2.3 Return Loss........................................................................................................ 28
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6.6.2.4 Coupling Attenuation......................................................................................... 29

6.6.2.5 Alien Cable Bundle Crosstalk ........................................................................... 31
6.6.2.6 STQ Inter-Pair Crosstalk ................................................................................... 32
6.6.2.7 STQ Inter-Pair Skew ......................................................................................... 32
6.6.3 ENIS (End Node Interconnect Structure) ................................................................... 33
6.6.3.2 Insertion Loss .................................................................................................... 34
6.6.3.3 Return Loss........................................................................................................ 35
6.6.3.4 Mode Conversion .............................................................................................. 35
6.6.3.5 Receiver Alien Near End Crosstalk ................................................................... 36
6.6.4 PCB TLIS (Transmission Line Interconnect Structure) (Informative) ....................... 37
6.6.4.2 Insertion Loss .................................................................................................... 37
6.6.4.3 Return Loss........................................................................................................ 37
6.6.5 Power Distribution ...................................................................................................... 38
6.6.5.1 DC Requirements .............................................................................................. 38
6.6.5.2 AC Requirements .............................................................................................. 39
6.6.5.3 Power Over Coax .............................................................................................. 40
6.6.5.4 Power Over Differential Line ............................................................................ 41
6.6.6 Ground Voltage Offset ................................................................................................ 41
7 EMC Environmental Conditions ............................................................................. 43
7.1RF Ingress ......................................................................................................................... 43
7.2Bulk Current Injection (BCI) ............................................................................................ 44
7.3Fast Transient .................................................................................................................... 44
7.4Alien Cable Bundle Max PSD Level................................................................................. 45
7.5Car Noise (PSD) ................................................................................................................ 46
8 PHY Layer ................................................................................................................. 47
8.1 Architecture ....................................................................................................................... 47
8.1.1 High Level Structure ................................................................................................... 47
8.1.1.1 Single-Lane Highly Asymmetric ....................................................................... 47
8.1.1.2 Dual Downlink Lane Highly Asymmetric Q-Port ............................................. 48
8.1.1.3 Asymmetric Q-Port ........................................................................................... 48
8.1.1.4 Symmetric Q-Port.............................................................................................. 49
8.1.2 Port Specification Generalization ............................................................................... 50
8.1.3 Primary-Secondary Clocking Schemes....................................................................... 50
8.1.4 PHY Layer Implementation Guidelines ...................................................................... 50
8.1.4.1 A-PHY P1 G1/G2 Architecture ......................................................................... 50
8.1.4.2 A-PHY P2 G1/G2 Architecture ......................................................................... 52
8.1.4.3 A-PHY PAM-X Single-Lane Architecture ........................................................ 53
8.1.4.4 A-PHY G3–G5 Dual Lane Downlink Highly Asymmetric Architecture .......... 54
8.1.4.5 A-PHY G3–G5 A-Symmetric Q-Port Architecture ........................................... 55
8.1.4.6 A-PHY G3–G5 Symmetric Q-Port Architecture ............................................... 56
8.1.5 PHY-Related A-Packet Fields ..................................................................................... 57
8.2 RTS .................................................................................................................................... 58
8.2.1 PAM-X Payload Data Modulation Assignment by Source ......................................... 62
8.2.2 Active Message Counter Window .............................................................................. 63
8.2.3 Retransmission Request / Ack Types .......................................................................... 64
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8.2.3.1 Retransmission Request Triggering by the Receiver ......................................... 64

8.2.3.2 Retransmission Request Handling at TX RTS................................................... 65
8.2.3.3 Format of Single/Gap Retransmission Request Sent Over Downlink ............... 65
8.2.4 Time Bounded RTS..................................................................................................... 68
8.2.5 A-Packet – PHY Related Header/Tail Modifications ................................................. 69
8.2.5.1 Tx Delay ............................................................................................................ 69
8.2.5.2 Message Counter and Original Indication Bit ................................................... 69
8.2.5.3 Header CRC (CRC-8)........................................................................................ 70
8.2.5.4 A-Packet Tail CRC (CRC-32) ........................................................................... 71
8.2.6 Fully Paced A-Packet Stream from TX Data Link Layer to TX RTS ......................... 72
8.2.6.1 Max Net Link Rate for 8B/10B PCS ................................................................. 72
8.2.6.2 Max Net Link Rate for PAM-X PCS ................................................................. 72
8.2.6.3 8B/10B PCS Fully Paced, A-Packets Stream from Link to TX RTS ................ 73
8.2.6.4 PAM-X PCS Fully Paced, A-Packets Stream from Link to TX RTS ................ 73
8.2.7 Scheduling Priority for A-Packets at TX RTS ............................................................ 75
8.2.7.1 Delayed Original A-Packet ................................................................................ 75
8.2.8 RTS Bypass ................................................................................................................. 76
8.3 Physical Coding Sub-Layer (PCS) .................................................................................... 78
8.3.1 PAM-X PCS ................................................................................................................ 78
8.3.1.1 PAM16 Sub-Constellation Bit to Symbol mapping........................................... 80
8.3.1.2 Symbol and Token Rate/Period ......................................................................... 82
8.3.1.3 A-Packet to Token Conversion .......................................................................... 84
8.3.1.4 Downlink Scrambler .......................................................................................... 87
8.3.1.5 Downlink Training Mode .................................................................................. 88
8.3.1.6 Downlink Idle Mode.......................................................................................... 92
8.3.1.7 Downlink Normal Mode.................................................................................... 93
8.3.1.8 Highly Asymmetric Downlink JITC Re-Training ............................................. 95
8.3.1.9 PAM-X Reverse Downlink For Symmetric Q-Port ........................................... 96
8.3.2 8B/10B PCS ................................................................................................................ 98
8.3.2.1 10b Symbols to NRZ Mapping........................................................................ 100
8.3.2.2 8B/10B Encoding ............................................................................................ 100
8.3.2.3 Uplink / Reverse Downlink Scrambler ............................................................ 101
8.3.2.4 Downlink Scrambler ........................................................................................ 101
8.3.2.5 Byte Stream Controller .................................................................................... 102
8.3.2.6 Training Mode ................................................................................................. 104
8.3.2.7 Idle Mode......................................................................................................... 105
8.3.2.8 Normal Mode................................................................................................... 106
8.3.2.9 Double Rate Uplink .......................................................................................... 110
8.3.2.10 8B/10B Reverse Downlink for Asymmetric Q-Port ......................................... 113
8.3.3 Repetitive Scrambler Reset for Test (RSRT) Mode .................................................. 114
8.3.3.1 First Reset Point ............................................................................................... 114
8.3.3.2 Next Reset Point ............................................................................................... 114
8.3.4 Startup Procedure ...................................................................................................... 115
8.3.4.1 “Mission Mode” Startup Procedure .................................................................. 116
8.3.4.2 Unidirectional Startup Procedure ..................................................................... 119
9 PMD Electrical Specification ................................................................................. 121
9.1 TX Electrical Specification ............................................................................................. 121
9.1.1 Test Mode Pattern Generator (TMPG)...................................................................... 122
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9.1.1.1 LFSR Usage Example ..................................................................................... 123

9.1.2 Test Modes ................................................................................................................ 125
9.1.2.1 TM1: Test Mode 1: Transmit PSD................................................................... 125
9.1.2.2 TM2: Test Mode 2: Droop ............................................................................... 125
9.1.2.3 TM3: Test Mode 3: Transmit Jitter .................................................................. 125
9.1.2.4 TM4: Test Mode 4: Transmit Linearity ........................................................... 125
9.1.2.5 TM5: Test Mode 5: In Silent State .................................................................. 126
9.1.2.6 TM6: Test Mode 6: Unidirectional Startup...................................................... 126
9.1.3 Transmitter Power Spectral Density Mask ............................................................... 127
9.1.3.1 Requirement .................................................................................................... 127
9.1.3.2 Processing Procedure....................................................................................... 132
9.1.4 Transmitter Maximum Output Droop ....................................................................... 135
9.1.4.1 Requirement .................................................................................................... 135
9.1.5 Transmitter Timing Jitter .......................................................................................... 136
9.1.5.1 Requirement .................................................................................................... 136
9.1.6 Transmitter Symbol Rate Accuracy .......................................................................... 137
9.1.7 NRZ Downlink Transmitter Eye Opening ................................................................ 137
9.1.7.1 Requirement .................................................................................................... 137
9.1.7.3 NRZ Jitter (Informative).................................................................................. 139
9.1.8 PAM-X Transmitter Linearity ................................................................................... 140
9.1.8.1 Requirement .................................................................................................... 140
9.1.9 PAM-X Transmitter Dual Lane, Inter-Pair Skew ...................................................... 142
9.1.9.1 Requirement .................................................................................................... 142
9.2 RX Electrical Specification ............................................................................................. 143
9.2.1 Profile 1 Receiver Bit Error Rate .............................................................................. 143
9.2.2 Profile 2 Downlink Receiver Pre-RTS Packet Error Rate ........................................ 143
9.2.3 Profile 2 Uplink Receiver Bit Error Rate .................................................................. 143
9.2.4 Receiver Symbol Rate Frequency Tolerance ............................................................ 143
9.2.5 Receiver Test Modes ................................................................................................. 143
9.2.5.1 RTM6: Receiver Test Mode 6: Unidirectional Startup .................................... 143
10 Modes of Operation................................................................................................. 145
10.1 Non-Active Mode ............................................................................................................ 145
10.2 Active Mode .................................................................................................................... 145
10.3 Operation Mode State Machine ....................................................................................... 146
10.3.1 General Operation ..................................................................................................... 147
10.3.2 States ......................................................................................................................... 148
10.3.2.1 Power-Up State ................................................................................................ 148
10.3.2.2 Start-Up State .................................................................................................. 148
10.3.2.3 Normal State .................................................................................................... 149
10.3.2.4 Sleep State ....................................................................................................... 149
10.3.3 Transitions................................................................................................................. 150
10.3.3.1 Power-Off Transition ....................................................................................... 150
10.3.3.2 Reset Transition ............................................................................................... 150
10.3.3.3 Ready Transition.............................................................................................. 150
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10.3.3.4 Stop Transition................................................................................................. 150

10.3.3.5 Link Establish Transition ................................................................................. 150
10.3.3.6 Link Down Transition...................................................................................... 151
10.3.3.7 Sleep Transition ............................................................................................... 151
10.3.3.8 Wakeup Transition ........................................................................................... 152
10.3.4 Test Mode ................................................................................................................. 152
10.4 FSM Parameters .............................................................................................................. 153
10.5 Wake-Up Protocol ........................................................................................................... 155
10.5.1 General ...................................................................................................................... 155
10.5.1.1 System Architecture (Informative) .................................................................. 155
10.5.2 Wake-Up Pattern (WUP) Signal ............................................................................... 157
10.5.2.1 PRBS9 Pattern ................................................................................................. 157
10.5.2.2 WUP Amplitude .............................................................................................. 158
10.5.2.3 WUP Bit Rate .................................................................................................. 158
10.5.2.4 WUP Duration ................................................................................................. 158
10.5.2.5 WUP Generation.............................................................................................. 158
10.5.2.6 WUP Detection ................................................................................................ 158
10.5.3 WUP Handshake Procedure ...................................................................................... 159
10.5.4 WUP Parameters ....................................................................................................... 160
11 Data Link Layer ...................................................................................................... 161
11.1 Architecture Overview .................................................................................................... 161
11.2 A-Packet Format.............................................................................................................. 163
11.2.1 A-Packet Header (A-Header) Fields ......................................................................... 165
11.2.1.1 Adaptation Descriptor Field ............................................................................ 165
11.2.1.2 Service Descriptor Field .................................................................................. 165
11.2.1.3 Placement Descriptor Field ............................................................................. 169
11.2.1.4 PHY2 Field ...................................................................................................... 169
11.2.1.5 Target Address Field ........................................................................................ 170
11.2.1.6 PHY3 Field ...................................................................................................... 171
11.2.1.7 Payload Length Field ....................................................................................... 171
11.2.1.8 PHY Header CRC Field................................................................................... 171
11.2.2 A-Packet Payload (A-Payload) ................................................................................. 172
11.2.3 A-Packet Tail (A-Tail) (CRC-32 Field) .................................................................... 172
11.3 Link Service .................................................................................................................... 173
11.3.1 BIST .......................................................................................................................... 173
11.3.1.1 BIST Modes..................................................................................................... 174
11.3.1.2 BIST Payload Patterns ..................................................................................... 176
11.3.1.3 BIST Rate ........................................................................................................ 177
11.3.1.4 BIST Burst ....................................................................................................... 177
11.3.1.5 BIST Generator and BIST Monitor ................................................................. 178
11.3.2 Keep-Alive ................................................................................................................ 179
11.3.3 Remote Sleep Command .......................................................................................... 179
11.3.4 Running Time-Base Count (RTBC) .......................................................................... 180
11.4 Local Functions ............................................................................................................... 181
11.4.1 Local Table (LOC_TBL) Recommendations (Informative) ..................................... 182
11.5 Multi-Port Functions ....................................................................................................... 184
11.5.1 Multi-Port Routing Function .................................................................................... 184
11.5.1.1 Packet Duplication Stage ................................................................................. 184
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11.5.1.2 Packet Forwarding Stage ................................................................................. 185

11.5.1.3 Routing Table (ROUT_TBL) Recommendations (Informative) ..................... 186
11.5.1.4 Duplication Table (DUP_TBL) Recommendations (Informative) .................. 187
11.6 Network Functions .......................................................................................................... 189
11.6.1 Scheduling and Priorities .......................................................................................... 189
11.6.2 Clock Forwarding Service ........................................................................................ 190
11.6.2.1 CFS A-Packet Format ...................................................................................... 190
11.7 APPI Signal Interface ...................................................................................................... 193
11.7.1 Signals Description ................................................................................................... 193
11.7.1.1 APPI Signals.................................................................................................... 193
11.7.2 APPI Clock ............................................................................................................... 194
11.7.3 APPI A-Packet Mapping ........................................................................................... 195
11.7.4 APPI Timing Diagrams ............................................................................................. 196
12 A-PHY Control and Management Database (ACMD) and Protocol (ACMP) .. 197
12.1 Control and Management System Architecture (Informative) ........................................ 198
12.2 ACMD ............................................................................................................................. 201
12.2.1 Register Base Address Alignment ............................................................................. 201
12.2.2 Register Data Byte Order .......................................................................................... 201
12.2.3 Register Space........................................................................................................... 202
12.2.4 Register List .............................................................................................................. 204
12.2.5 Detailed Register Description ................................................................................... 206
12.2.5.1 ACMD Programming ...................................................................................... 206
12.2.5.2 Port Programming ........................................................................................... 213
12.3 ACMP.............................................................................................................................. 221
12.3.1 ACMP Mode 0 (ACMP-M0) Message Format ......................................................... 222
12.3.1.1 ACMP-M0 Message Header Part .................................................................... 223
12.3.1.2 ACMP-M0 Message Payload Part ................................................................... 224
12.3.1.3 ACMP-M0 Message Mapping to I2C .............................................................. 225
12.3.2 ACMP-M0 Message Receiver Rules and Responsibilities ....................................... 226
12.3.2.1 ACMP-M0 Header CRC (HCRC) Errors ........................................................ 226
12.3.2.2 ACMP-M0 Payload CRC (PCRC) Errors ....................................................... 226
12.3.2.3 Message Counter (MC) ................................................................................... 226
12.3.2.4 Keep-Alive ...................................................................................................... 226
12.3.2.5 Message Format Setting .................................................................................. 226
12.3.2.6 Virtual Base Address Maintenance .................................................................. 226
12.3.2.7 Accessing Register Data .................................................................................. 226
12.3.3 ACMP Interrupts ....................................................................................................... 227
12.3.3.1 ACMPI in I2C .................................................................................................. 227
12.3.3.2 ACMPI in I3C ................................................................................................. 227
Annex A PMD Simplified Implementation Examples (Informative) ........................... 229
A.1 Profile 1 G1–2 Source PMD ........................................................................................... 229
A.1.1 PMD without External Diplexer (Internal Replica) .................................................. 229
A.1.2 PMD With External Diplexer.................................................................................... 229
A.2 Profile 1 G1–2 Sink PMD ............................................................................................... 230
A.3 G3–5 Source PMD .......................................................................................................... 230
A.4 G3–5 Sink PMD .............................................................................................................. 231
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Annex B 8B/10B Line Coding (Normative) .................................................................... 233

B.1 Data Symbols .................................................................................................................. 233
B.2 Control Symbols .............................................................................................................. 236
B.3 Running Disparity ........................................................................................................... 237
B.3.1 RD Characteristics .................................................................................................... 237
B.4 Bit Order and Binary Value ............................................................................................. 237
Participants .......................................................................................................................... 239
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Figures
Figure 1 Data and Power Logical Structure ..................................................................................... 9
Figure 2 High Level Layer Structure................................................................................................ 9
Figure 3 A-PHY High Level Structure ........................................................................................... 12
Figure 4 Star Quad Arrangement of Quad Conductors into Two Differential Pairs ....................... 14
Figure 5 A-PHY Interconnect ......................................................................................................... 23
Figure 6 Cable Topologies.............................................................................................................. 24
Figure 7 Set-up for S-parameter Characterization of End Nodes and TLIS ................................... 25
Figure 8 Interconnect Test Points Definition .................................................................................. 26
Figure 9 Coax and SDP/STQ Cable Insertion Loss Limits ............................................................ 27
Figure 10 Cable TLIS Return Loss Limits ..................................................................................... 28
Figure 11 Cable TLIS Coupling Attenuation.................................................................................. 29
Figure 12 Cable TLIS Attenuation Limits ...................................................................................... 30
Figure 13 Alien Cable Bundle Crosstalk Limit .............................................................................. 31
Figure 14 STQ Inter-Pair Crosstalk Limit ...................................................................................... 32
Figure 15 Single-Ended End Node Routing Example .................................................................... 33
Figure 16 End Node Insertion Loss Limit ...................................................................................... 34
Figure 17 End Node Return Loss Limits ........................................................................................ 35
Figure 18 Receiver ANEXT Limit ................................................................................................. 36
Figure 19 PCB-Based Interconnect ................................................................................................ 37
Figure 20 Power Ripple Gain Function .......................................................................................... 39
Figure 21 Power Over Coax (PoC) Configuration ......................................................................... 40
Figure 22 Power Over Differential Line (PoDL) Configuration .................................................... 41
Figure 23 Examples of Applicable Pulses ...................................................................................... 43
Figure 24 P2 Decaying Sawtooth Model at 40 MHz / 4 nS Tr / 150 mV to 15 mV in 150 nS....... 44
Figure 25 Alien Bundle PSD Limit Line ........................................................................................ 45
Figure 26 A-PHY Single Lane Highly Asymmetric Unified Architecture ..................................... 47
Figure 27 A-PHY Dual Lane Downlink Highly Asymmetric Q-Port Architecture ........................ 48
Figure 28 A-PHY Asymmetric Q-Port Architecture ....................................................................... 48
Figure 29 A-PHY Symmetric Q-Port Architecture......................................................................... 49
Figure 30 A-PHY P1 G1/G2 Architecture ...................................................................................... 51
Figure 31 A-PHY P2 G1/G2 Architecture ...................................................................................... 52
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Figure 32 A-PHY P2 G3-G5 Single Lane Architecture.................................................................. 53

Figure 33 A-PHY P2 G3-G5 Dual Lane Downlink Highly Asymmetric Architecture................... 54
Figure 34 A-PHY G3–G5 A-Symmetric Q-Port Architecture ........................................................ 55
Figure 35 A-PHY G3–G5 Symmetric Q-Port Architecture ............................................................ 56
Figure 36 Dynamically Modulated, Time Bounded, Local Retransmission .................................. 58
Figure 37 TX RTS Over 8B/10B PCS Block Diagram .................................................................. 59
Figure 38 TX RTS Over PAM-X PCS Block Diagram .................................................................. 60
Figure 39 Single Retransmission Request Sent Over Downlink .................................................... 67
Figure 40 Gap Retransmission Request Sent Over Downlink ....................................................... 67
Figure 41 Header CRC (CRC-8) Bit Level Diagram ..................................................................... 70
Figure 42 Header CRC Bit Assignment ......................................................................................... 70
Figure 43 CRC-32 Calculation Bit Level Diagram ........................................................................ 71
Figure 44 CRC-32 Byte Mapping .................................................................................................. 71
Figure 45 Fully Paced TX Link to TX Phy Interface ..................................................................... 74
Figure 46 RTS Bypass .................................................................................................................... 77
Figure 47 PAM-X Single Lane PCS Block Diagram ..................................................................... 79
Figure 48 PAM-X Dual Lane PCS Block Diagram ........................................................................ 80
Figure 49 PAM16 Sub-Constellations ............................................................................................ 81
Figure 50 A-Packet Partitioning ..................................................................................................... 84
Figure 51 Bit/Symbol/Token Conversion Per Header Sub-Constellation ...................................... 85
Figure 52 Bit/Symbol/Token Conversion Per Payload Data and CRC-32 Bytes ........................... 86
Figure 53 Downlink TX Scrambler LFSR ..................................................................................... 87
Figure 54 PAM-X Single Lane Transition from Training to Idle ................................................... 91
Figure 55 PAM-X Dual Lane Transition from Training to Idle...................................................... 91
Figure 56 PAM-X Single Lane Transition from Idle to Normal..................................................... 92
Figure 57 PAM-X Dual Lane Transition from Idle to Normal ....................................................... 92
Figure 58 PCS Normal Mode Data Example ................................................................................. 94
Figure 59 TX Re-Training Procedure State Machine ..................................................................... 95
Figure 60 Symmetric Q-Port K-Generation/Reflection.................................................................. 97
Figure 61 PCS Block Diagram ....................................................................................................... 99
Figure 62 Uplink / Reverse Downlink TX Scrambler LFSR ....................................................... 101
Figure 63 Training with K-Sequences Example ........................................................................... 104
Figure 64 DHA Startup Control Sequence ................................................................................... 104
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Figure 65 In_Idle Startup Control Sequence ................................................................................ 105

Figure 66 Interrupting Request with Data Packet Continues ....................................................... 106
Figure 67 In Normal Startup Control Sequence ........................................................................... 106
Figure 68 Re-Train Request ......................................................................................................... 107
Figure 69 sCMax Request ............................................................................................................ 107
Figure 70 Single Retransmission Request .................................................................................... 108
Figure 71 Retransmission Gap Request ....................................................................................... 108
Figure 72 Ack Indication .............................................................................................................. 109
Figure 73 Distinct A-Packet 8B/10B Encapsulation .................................................................... 109
Figure 74 Back-to-Back A-Packets: 8B/10B Encapsulation ........................................................ 109
Figure 75 A-Packet 8B/10B Encapsulation with Request Insertion ............................................. 109
Figure 76 RTU PCS Block Diagram ............................................................................................ 110
Figure 77 DRU Scrambler Transition from Training to Idle Mode .............................................. 111
Figure 78 DRU Continues RTR Sequence Sent Over DRU ......................................................... 111
Figure 79 DRU Re-Training Request Sent Over Downlink ......................................................... 111
Figure 80 DRU sCMax Request Sent Over Downlink ................................................................. 112
Figure 81 Typical Startup Procedure ............................................................................................ 116
Figure 82 Unidirectional Startup Procedure ................................................................................. 120
Figure 83 TPA Conformance Point............................................................................................... 121
Figure 84 Test Mode Pattern Generator LFSR ............................................................................. 122
Figure 85 Test Mode 2 .................................................................................................................. 125
Figure 86 NRZ PMD: Upper & Lower PSD Limits ..................................................................... 128
Figure 87 Uplink PMD Upper & Lower PSD Limits: Gears #1–#3 ............................................ 130
Figure 88 PAM-X PMD Upper & Lower PSD Limits ................................................................. 131
Figure 89 Example Matlab Figure #1 ........................................................................................... 134
Figure 90 Example Matlab Figure #2 ........................................................................................... 134
Figure 91 NRZ Downlink Transmitter Eye Diagram ................................................................... 138
Figure 92 A-PHY Port Operation Mode State Machine ............................................................... 146
Figure 93 Sleep Sequence Example, View 1 ................................................................................ 151
Figure 94 Sleep Sequence Example, View 2 ................................................................................ 151
Figure 95 Optional System Architecture ...................................................................................... 155
Figure 96 WUP Directions ........................................................................................................... 156
Figure 97 Wakeup_ind Configuration Signaling .......................................................................... 157
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Figure 98 General Waveform of Main Signals ............................................................................. 157

Figure 99 WUP Handshake ACK/NACK..................................................................................... 159
Figure 100 A-PHY High Level Structure ..................................................................................... 161
Figure 101 Example A-PHY High-Level Layer ........................................................................... 162
Figure 102 A-Packet Format ........................................................................................................ 163
Figure 103 Bad Packet Indication and Propagation Example ...................................................... 168
Figure 104 Many-to-One Target Address Assignment Example .................................................. 170
Figure 105 One-to-Many Target Address Assignment Example .................................................. 170
Figure 106 Basic BIST A-Payload Format ................................................................................... 174
Figure 107 Extended BIST A-Payload Format............................................................................. 174
Figure 108 BIST PRBS Bit Level Diagram ................................................................................. 176
Figure 109 Local Table Example.................................................................................................. 182
Figure 110 Entry-Element Formats .............................................................................................. 183
Figure 111 Local Table Example .................................................................................................. 183
Figure 112 ROUT_TBL Example ................................................................................................ 186
Figure 113 DUP_TBL Example ................................................................................................... 188
Figure 114 CFS A-Packet Payload Format................................................................................... 190
Figure 115 APPI Connectivity...................................................................................................... 194
Figure 116 APPI A-Packet Mapping ............................................................................................ 195
Figure 117 APPI Timing ............................................................................................................... 196
Figure 118 A-PHY Control and Data Planes ................................................................................ 197
Figure 119 Control and Management System Architecture.......................................................... 198
Figure 120 ACMD Register Space ............................................................................................... 202
Figure 121 Ports and AL Instances Register Space Arrangement ................................................ 203
Figure 122 ACMP-M0 Message Format ...................................................................................... 222
Figure 123 ACMP-M0 Message Mapping to I2C ......................................................................... 225
Figure 124 Profile 1 G1–2 Source with Internal Replica ............................................................. 229
Figure 125 Profile 1 G1–2 Source with External Diplexer .......................................................... 229
Figure 126 Profile 1 G1–2 Sink PMD .......................................................................................... 230
Figure 127 G3–5 Source PMD ..................................................................................................... 230
Figure 128 G3–5 Sink PMD ......................................................................................................... 231
Figure 129 Running Disparity (RD) State Diagram ..................................................................... 237
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Tables
Table 1 Q-Port Operation Modes ................................................................................................... 15
Table 2 Per Lane Normative Downlink / Reverse Downlink Gears ............................................... 16
Table 3 Normative-Optional, Downlink / Reverse Downlink Gear Implementations ................... 17
Table 4 Normative Uplink Gears .................................................................................................... 17
Table 5 Dual Lane Downlink Highly Asymmetric Q-Port, Normative Configurations ................. 18
Table 6 Asymmetric Q-Port Normative Configurations ................................................................. 18
Table 7 Symmetric Q-Port Normative Configurations ................................................................... 19
Table 8 Q-Fallback Highly Asymmetric Mode Normative Configurations ................................... 19
Table 9 Q-Port Types Interoperability Matrix ................................................................................ 20
Table 10 Cable TLIS Return Loss .................................................................................................. 28
Table 11 Coupling Attenuation ....................................................................................................... 29
Table 12 Screening Attenuation...................................................................................................... 29
Table 13 Unbalanced Attenuation................................................................................................... 30
Table 14 Alien Cable Bundle Crosstalk.......................................................................................... 31
Table 15 STQ Inter-Pair Crosstalk ................................................................................................. 32
Table 16 STQ Inter-Pair Skew........................................................................................................ 32
Table 17 End Node Insertion Loss ................................................................................................. 34
Table 18 End Node Return Loss ..................................................................................................... 35
Table 19 Receiver ANEXT ............................................................................................................. 36
Table 20 DC Requirements ............................................................................................................ 38
Table 21 Power Ripple Gain........................................................................................................... 39
Table 22 Power Over Coax (PoC) Component Values ................................................................... 40
Table 23 Power Over Differential Line (PoDL) Component Values .............................................. 41
Table 24 Alien Cable Bundle Upper PSD Limit............................................................................. 45
Table 25 Car Noise PSD Limits ..................................................................................................... 46
Table 26 A-Packet Fields Modified by PHY Layer ........................................................................ 57
Table 27 Sub-Constellation Assignment for Original A-Packets ................................................... 62
Table 28 SCI Code Per Assigned Payload Data Sub-Constellation ............................................... 62
Table 29 A-Packet Fields Modified by PHY Layer ........................................................................ 66
Table 30 Downlink/Reverse-Downlink Max RTS Delay & Retransmission Request Wait ........... 68
Table 31 Nominal Downlink/Reverse-Downlink RTS Delay Unit ................................................ 69
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Table 32 Actual Byte Period Consumption Per Gear ..................................................................... 73

Table 33 P1 A-Packet Fields Update .............................................................................................. 76
Table 34 PAM16 Sub-Constellations.............................................................................................. 82
Table 35 Token Data (TD) per Sub-Constellation .......................................................................... 82
Table 36 Symbol / Token Rate and Symbol / Token Period Ratios ................................................ 83
Table 37 Header Sub-Constellation Per sCMax ............................................................................. 84
Table 38 PAM-X Single Lane Token Data Scrambling .................................................................. 88
Table 39 PAM-X Dual Lane Token Data Scrambling .................................................................... 88
Table 40 PAM-X Single Lane Scrambler Output Training Bits ..................................................... 88
Table 41 PAM-X Dual Lane Scrambler Output Training Bits........................................................ 88
Table 42 PAM-X Single Lane "K Sequence" Symbol Mapping vs Training Symbols .................. 90
Table 43 PAM-X Dual Lane "K Sequence" Symbol Mapping vs Training Symbols ..................... 90
Table 44 PAM-X Single Lane Idle Bits Allocation ........................................................................ 92
Table 45 PAM-X Dual Lane Idle Bits Allocation ........................................................................... 92
Table 46 PAM-X Single Lane EOI Symbol Allocation .................................................................. 93
Table 47 PAM-X Dual Lane EOI Symbol Allocation .................................................................... 93
Table 48 TX Re-Training Procedure State Machine Sequence-Length Values .............................. 96
Table 49 NRZ Electrical Levels Mapping .................................................................................... 100
Table 50 8B/10B Encoding .......................................................................................................... 100
Table 51 Startup Control Nibbles ................................................................................................. 102
Table 52 Normal Control Nibbles ................................................................................................ 103
Table 53 PAM4 Electrical Levels Mapping.................................................................................. 111
Table 54 Handshake Indications for Typical Startup (Summary)................................................. 118
Table 55 Time Periods for Startup Procedures ............................................................................. 118
Table 56 Timer Values for Unidirectional Startup Procedure ....................................................... 119
Table 57 PAM-X Test Mode Pattern Generator LFSR Bit Allocation for Sub-Constellation ...... 122
Table 58 LFSR Output of First 5 Symbol Periods........................................................................ 123
Table 59 PAM-X Single Lane sC1616 Coding .............................................................................. 123
Table 60 PAM-X Dual Lane sC1616 Coding................................................................................. 123
Table 61 PAM-X Single Lane sC816 Coding ................................................................................ 124
Table 64 Nominal TX Amplitude Over Coax, Per Gear, Per Direction (Informative) ................. 127
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Table 65 NRZ PMD Upper PSD Limit ........................................................................................ 128

Table 66 NRZ PMD Lower PSD Limit ........................................................................................ 128
Table 67 Uplink PMD Upper PSD Limit ..................................................................................... 129
Table 68 NRZ PMD Lower PSD Limit ........................................................................................ 129
Table 69 Transmitter Timing Jitter Requirements ........................................................................ 136
Table 70 NRZ Downlink Eye Mask Parameters .......................................................................... 137
Table 71 Jitter Components in TM3 and TM4 ............................................................................. 139
Table 72 Selection of RTM6 Sub-Mode via Field TMData ......................................................... 143
Table 73 Transition Appearance Legend ...................................................................................... 146
Table 74 FSM Configuration Parameters ..................................................................................... 153
Table 75 Link Quality Code Levels.............................................................................................. 154
Table 76 WUP Parameters ............................................................................................................ 160
Table 77 A-Packet Fields and Sub-Fields Description ................................................................. 164
Table 78 Adaptation Type Sub-Field Values................................................................................. 165
Table 79 Prio Sub-Field Values (Scheduling-Priority Codes) ...................................................... 166
Table 80 Quality-of-Service Codes .............................................................................................. 166
Table 81 OB (Odd-Bytes) Sub-Field Values ................................................................................ 169
Table 82 Order Sub-Field Values.................................................................................................. 169
Table 83 Target Address Field Values (Pre-Defined T-Address Values)....................................... 170
Table 84 A-Packet Payload Length and OB Sub-Field ................................................................ 171
Table 85 BIST Mode Codes ......................................................................................................... 174
Table 86 Extended BIST Fields Description ................................................................................ 175
Table 87 BIST Payload Pattern Codes ......................................................................................... 176
Table 88 BIST Data Bytes Sequence Example............................................................................. 177
Table 89 BIST Rate Codes ........................................................................................................... 177
Table 90 BIST Burst Codes .......................................................................................................... 177
Table 91 Local Table Entry Descriptor ......................................................................................... 182
Table 92 Duplication Stage Actions ............................................................................................. 184
Table 93 Pre-Defined Port ID Values ........................................................................................... 185
Table 94 DUP_TBL Entry Elements ............................................................................................ 187
Table 95 CFS A-Packet Fields for TBS ........................................................................................ 192
Table 96 APPI Signals .................................................................................................................. 193
Table 97 APPI Clock Frequency Settings..................................................................................... 194
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Table 98 Register Base Address (BA) Alignment ........................................................................ 201

Table 99 Register Data Byte Order............................................................................................... 201
Table 100 A-PHY Common Registers List .................................................................................. 204
Table 101 Port Space Register List............................................................................................... 205
Table 102 Register A-PHY_VER ................................................................................................. 206
Table 103 Register ACMD_ADDRESS ....................................................................................... 206
Table 104 Register PORT_NUM.................................................................................................. 206
Table 105 Register AL_NUM ...................................................................................................... 206
Table 106 Register ID6_HIGH ..................................................................................................... 206
Table 107 Register ID6_LOW ...................................................................................................... 207
Table 108 Register MID ............................................................................................................... 207
Table 109 Register PRODUCT_ID .............................................................................................. 207
Table 110 Register ACMP_IF ...................................................................................................... 207
Table 111 Register ACMD_SECONDADDR .............................................................................. 207
Table 112 Register ACMD_BRDCSTADDR ............................................................................... 207
Table 113 Register FEATURE_CAP ............................................................................................ 208
Table 114 Register FEATURE_CTRL ......................................................................................... 209
Table 115 Register BIST_TX_CTRL1 ......................................................................................... 209
Table 121 Register BIST_RX_CTRL1......................................................................................... 211
Table 122 Register BIST_RX_MON1 ......................................................................................... 211
Table 128 Register INST_DESC .................................................................................................. 213
Table 129 Register PORT_CAP ................................................................................................... 213
Table 130 Register PORT_CAP_2 ............................................................................................... 214
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Table 131 Register PORT_CONFIG ............................................................................................ 214

Table 132 Register PORT_CONFIG_2 ........................................................................................ 215
Table 133 Register TEST_CONFIG............................................................................................. 215
Table 134 Register FSM_CONFIG .............................................................................................. 216
Table 135 Register FSM_STATUS............................................................................................... 216
Table 136 Register WUP_CTRL .................................................................................................. 217
Table 137 Register LinkStatusReport ........................................................................................... 217
Table 138 Register LinkStatusControl ......................................................................................... 217
Table 139 Register DIAG_CTRL ................................................................................................. 218
Table 140 Register DIAG_CNT1 ................................................................................................. 218
Table 149 Register DIAG_CNT10 ............................................................................................... 219
Table 152 ACMP-M0 Message Header Fields ............................................................................. 223
Table 153 ACMP-M0 Message Payload Fields............................................................................ 224
Table 154 5b6b Sub-Block Data Encoding .................................................................................. 234
Table 155 3b4b Sub-Block Data Encoding .................................................................................. 235
Table 156 Control Symbols .......................................................................................................... 236
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Release History
Date Version Description
06-Aug-2020 v1.0 Initial Board adopted release.
08-Dec-2021 v1.1 Board adopted release.
24-May-2023 v1.1.1 Board adopted release.
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xx Copyright © 2020–2023 MIPI Alliance, Inc.

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1 Introduction
1 This document specifies MIPI A-PHY, a serial interface technology with high bandwidth capabilities
2 developed particularly for long reach (e.g., automotive) applications, enabling low pin count and a high level
3 of power efficiency.
4 A-PHY is designed for a wide range of long reach applications, and specifically for automotive market, to
5 carry multiple protocols from MIPI Alliance such as CSI-2 for cameras, and DSI and DSI-2 for displays.
6 Non-MIPI protocols are also supported using a generic Data Link Layer Interface (APPI).
7 A-PHY features include:
8 • Long reach capability – optimized to support cables up to 15 m with up to 4 inline connectors
9 • Multiple speed gears ranging from 2 Gbps up to 16 Gbps
10 • Support for multiple cable types commonly used in automotive
11 • Strong noise immunity for the harsh automotive environment
12 • Generic Data Link Layer, supporting multiple protocols from MIPI Alliance and external entities
1.1 Scope
1.1.1 In Scope
13 This A-PHY Specification document specifies the implementation of the A-PHY, including its layering,
14 electrical characteristics, and its optional features.
15 The A-PHY specification shall always be used in combination with one or more MIPI protocol specifications,
16 such as CSI-2 or DSI-2, plus the associated MIPI Protocol Adaptation Layer (PAL) specification for each
17 MIPI protocol. The A-PHY specification shall not be used in combination with non-MIPI protocols or non-
18 MIPI adaptation layers, unless expressly authorized by the MIPI Alliance Board of Directors. Any other use
19 of the A-PHY specification is strictly prohibited, unless approved in advance by the MIPI Alliance Board of
20 Directors.
1.1.2 Out of Scope
21 Protocol Adaptation Layers (PALs)
22 A single A-PHY can serve multiple protocols at the same time, and each protocol has its own interface to the
23 Data Link Layer, called a Protocol Adaptation Layer (PAL). PALs are not part of this document.
24 • MIPI Developed PALs: MIPI develops PAL specifications for MIPI protocols such as CSI-2 and
25 DSI-2, and publishes them either in the respective protocol specifications or as separate MIPI PAL
26 specifications. MIPI also develops separate MIPI PAL specifications for certain non-MIPI protocols
27 such as I2C and GPIO. MIPI member companies can obtain adopted MIPI specifications via the
28 member website (https://members.mipi.org/wg/All-Members/home/approved-specs) [MIPI14].
29 • Externally Developed PALs: Development of PALs by any non-MIPI party is strictly prohibited,
30 unless approved in advance by the MIPI Alliance Board of Directors.
31 Specific Channel Configurations
32 Different protocols employing A-PHY technology can have different constraints, which can require the use
33 of different approaches for operation control. Therefore, while this document provides the features to enable
34 stable, optimized Link configuration, it does not mandate specific configurations for specific channels.
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1.2 Purpose
35 Long reach devices, and specifically automotive devices, face increasing bandwidth demands for each of
36 their functions, as well as an increase in the number of functions integrated into the system.
37 Addressing this demand requires wide bandwidth, low pin count (serial), highly power-efficient (network)
38 interfaces with sufficient flexibility to be attractive for multiple applications, while employing just a single
39 physical layer technology.
40 A-PHY complements MIPI Alliance’s existing D-PHY and C-PHY interfaces by addressing the long reach
41 automotive channel.

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2 Terminology
2.1 Use of Special Terms

42 The MIPI Alliance has adopted Section 13.1 of the IEEE Standards Style Manual, which dictates use of the
43 words “shall”, “should”, “may”, and “can” in the development of documentation, as follows:
44 The word shall is used to indicate mandatory requirements strictly to be followed in order
45 to conform to the Specification and from which no deviation is permitted (shall equals is
46 required to).
47 The use of the word must is deprecated and shall not be used when stating mandatory
48 requirements; must is used only to describe unavoidable situations.
49 The use of the word will is deprecated and shall not be used when stating mandatory
50 requirements; will is only used in statements of fact.
51 The word should is used to indicate that among several possibilities one is recommended
52 as particularly suitable, without mentioning or excluding others; or that a certain course of
53 action is preferred but not necessarily required; or that (in the negative form) a certain
54 course of action is deprecated but not prohibited (should equals is recommended that).
55 The word may is used to indicate a course of action permissible within the limits of the
56 Specification (may equals is permitted to).
57 The word can is used for statements of possibility and capability, whether material,
58 physical, or causal (can equals is able to).
59 All sections are normative, unless they are explicitly indicated to be informative.
2.2 Definitions
60 A-Packet: A-PHY packet. The A-PHY packet format is defined in Section 11.2 as a group of bytes organized
61 in a specified way to transfer data through the A-PHY interface. A packet consists of a specified set of
62 components: A-Packet Header, A-Packet Payload, and A-Packet Tail (or Footer). The byte is the fundamental
63 unit of data from which the A-Packet is made.
64 A-PHY Network: System of interconnected A-PHY Ports.
65 C-Port: A-PHY Port over Coax Cable.
66 D-Port: A-PHY Port over SDP Cable.
67 Device: Any product that implements at least one A-PHY Port.
68 Downlink: High throughput communication sent from Source to Sink.
69 Downstream-APPI: The traffic direction from the Adaptation Layer to the A-PHY Data Link Layer.
70 Forwarding: Function assigning A-Packet and its attributes to A-PHY Port destination in a Multi-Port
71 A-PHY Device. See Section 11.5.1.
72 Forwarding Element: An entity that applies a Forwarding function (e.g., an A-PHY Device acting as a
73 Forwarding Element).
74 Lane: Point-to-point, single-ended or differential connection between two Ports using an Interconnect
75 Structure.
76 Link: The logical connection between Source and Sink.
77 Multi-Port A-PHY Device: A-PHY Device that implements more than one single A-PHY Port.
78 Native Message: A standardized message in a given Native Protocol.
79 Native Protocol Adaptation Layer: Layer connecting between the Native protocol and A-PHY.
80 Native Protocol: Protocol that is being transferred over the A-PHY, e.g., CSI.
81 Port: An A-PHY Source or Sink with supporting PCB circuitry and interfacing connector.
82 Primary Clock: The Source’s local reference clock.

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83 Note:
84 In previous versions of the A-PHY Specification, a Primary Clock was called a
85 “Master Clock”. MIPI Alliance has deprecated the use of the word “Master” in technical
86 terms, so the A-PHY Specification now uses the updated normative term “Primary Clock”.
87 Please note that the technical definition of the Primary Clock, and its Role in this
88 Specification, are unchanged.
89 Q-Port: A-PHY Port over STQ cable.
90 Reverse Downlink: Q-Port Lane #1 using A-PHY Downlink configuration from Sink to Source.
91 Routing: Part of the Forwarding function that selects destination A-PHY Port for each A-Packet in a
92 Multi-Port A-PHY Device. See Section 11.5.1.
93 RX or Receiver: The Receive function of an A-PHY Port, e.g., Sink Port consists of Downlink RX and
94 Uplink TX.
95 Secondary Clock: The Sink’s locally recovered clock from the Downlink.
96 Note:
97 In previous versions of the A-PHY Specification, a Secondary Clock was called a
98 “Slave Clock” or a "Clock Slave”. MIPI Alliance has deprecated the use of the word “Slave”
99 in technical terms, so the A-PHY Specification now uses the updated normative term
100 “Secondary Clock.” Please note that the technical definition of the Secondary Clock, and its
101 Role in this Specification, are unchanged.
102 Sink: The entity that implements one instance of an A-PHY Link and PHY layers for a Downlink receiver
103 and an Uplink transmitter.
104 Source: The entity that implements one instance of an A-PHY Link and PHY layers for a Downlink
105 transmitter and an Uplink receiver.
106 TX or Transmitter: The transmit function of an A-PHY Port, e.g., Source Port consists of Downlink TX and
107 Uplink RX.
108 Uplink: Low throughput (<500 Mbps) communication sent from Sink to Source.
109 Upstream-APPI: The traffic direction from the A-PHY Data Link Layer to the Adaptation Layer.
2.3 Abbreviations
110 A Ampere (Amp)
111 A-PHY MIPI Alliance A-PHY Interface (this specification)
112 C-PHY MIPI Alliance C-PHY interface [MIPI06]
113 CSI-2 MIPI Alliance Camera Serial Interface 2 [MIPI02]
114 dB Decibel
115 D-PHY MIPI Alliance D-PHY interface [MIPI01]
116 DSI MIPI Alliance Display Serial Interface [MIPI03]
117 DSI-2 MIPI Alliance Display Serial Interface 2 [MIPI04]
118 e.g. For example (Latin: exempli gratia)
119 F Farad (capacitance unit)
120 GHz Gigahertz
121 GND Ground
122 H Henry (induction unit)
123 i.e. That is (Latin: id est)
124 I2C NXP Inter Integrated Circuit interface [NXP01]
125 I3C MIPI Alliance I3C interface [MIPI05]
126 M-PHY MIPI Alliance M-PHY interface [MIPI07]
127 MHz Megahertz
128 MIPI MIPI Alliance, Inc.
129 NAppClk Native Application Clock
130 PHY Physical Layer

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131 RX Receive, Receiver

132 S Second (time unit)
133 STQ Star Quad (shielded dual differential pair)
134 TX Transmit, Transmitter
135 V Volt
136 W Watt
137 Ω Ohm
2.4 Acronyms
138 Ack Acknowledgement
139 ACMD A-PHY Control and Management Database
140 ACMP A-PHY Control and Management Protocol
141 ACMPI ACMP Interrupt
142 ADC Analog-to-Digital Converter
143 AFE Analog Front End
144 APDLL A-PHY Data Link Layer
145 APPI A-PHY Protocol Interface
146 APPL A-PHY Physical Layer
147 BCI Bulk Current Injection
148 BER Bit Error Rate
149 BIST Built in Self-Test
150 BOM Bill of Materials
151 CAL Re-Constructing Adaptation Layer
152 CFS Clock Forwarding Service
153 CRC Cyclical Redundancy Checking
154 DC Direct Current
155 DCD Duty Cycle Distortion
156 DJ Deterministic Jitter
157 DUT Device Under Test
158 ECU Electronic Control Unit
159 eDP embedded Display Port
160 ENIS End Node Interconnect Structure
161 EMC Electromagnetic Compatibility
162 EMI Electromagnetic Interference
163 EOI End-Of-Idle
164 ESD Electrostatic Discharge
165 GBaud Giga Baud
166 Gbps Gigabit Per Second
167 GPIO General Purpose Input/Output
168 HDMI High Definition Media Interface
169 IEC International Electrotechnical Commission
170 IL Insertion Loss
171 IPG Inter-Packet Gap
172 ISO International Organization for Standardization
173 ISS Inverted Scrambler Symbols
174 JITC Just-In-Time Canceller
175 LSB Least Significant Bit
176 MAL Measuring Adaptation Layer

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177 Mbps Megabit Per Second

178 MDI Medium-Dependent Interface
179 MSB Most Significant Bit
180 NPAL Native Protocol Adaptation Layer
181 NRZ Non-Return to Zero
182 OSI Open Systems Interconnection
183 P1 Profile 1
184 P2 Profile 2
185 PAM Pulse Amplitude Modulation
186 PCB Printed Circuit Board
187 PCS Physical Coding Sub-Layer
188 PD Powered Device
189 PER Packet Error Rate
190 PI Power Injection
191 PJ Periodic Jitter
192 PMD Physical Media Dependent
193 POR Power-On Reset
194 PSCR Power Sum Crosstalk Ratio
195 PSD Power Spectral Density
196 PSE Power Sourcing Equipment
197 PSIJ Power Supply Induced Jitter
198 QoS Quality of Service
199 RD Running Disparity
200 RJ Random Jitter
201 RL Return Loss
202 RTD Round Trip Delay
203 RTS Retransmission
204 SCI Sub Constellation Index
205 SDO Standards Developing Organization
206 SDP Shielded Differential Pair
207 SER Symbol Error Rate
208 SoC System on a Chip
209 SPI Serial Peripheral Interface
210 SPP Shielded Parallel Pair
211 STP Shielded Twisted Pair
212 TJ Total Jitter
213 TLIS Transmission Line Interconnect Structure
214 UTP Unshielded Twisted Pair
215 WUP Wake-Up Pattern

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3 References
3.1 Normative References

216 This Specification has no normative references.
3.2 Informative References

217 [IBM01] Widmer, A. X.; Franaszek, P. A., “A DC-Balanced, Partitioned- Block, 8B / 10B
218 Transmission Code”, IBM Journal of Research. Development, VOL. 27, NO. 5,
219 September 1983.
220 [ISO01] ISO Standard 26262-1:2018, Road vehicles — Functional safety — Part 1: Vocabulary,
221 https://www.iso.org/standard/68383.html, International Organization for Standardization
222 TC 22/SC 32, 2018.
223 [ISO02] ISO/CD 7637-2, Road vehicles — Electrical disturbances by conduction and coupling —
224 Part 2: Electrical transient conduction along supply lines,
225 https://www.iso.org/standard/74300.html, International Organization for Standardization
226 TC 22/SC 32, In press.
227 [ISO03] ISO/CD 11452-2: 2019, Road vehicles — Component test methods for electrical
228 disturbances from narrowband radiated electromagnetic energy — Part 2: Absorber-lined
229 shielded enclosure, https://www.iso.org/standard/68557.html, International Organization
230 for Standardization TC 22/SC 32, 2019.
231 Note:
232 MIPI Alliance Member companies can access all adopted MIPI Specifications at
233 https://members.mipi.org/wg/All-Members/home/approved-specs
234 [MIPI01] Specification for D-PHYSM, version 2.1 and above, MIPI Alliance, Inc.
235 [MIPI02] Specification for Camera Serial Interface 2 (CSI-2®), version 2.1 and above,
236 MIPI Alliance, Inc.
237 [MIPI03] Specification for Display Serial Interface (DSI®), version 1.3.1 and above,
239 [MIPI04] Specification for Display Serial Interface 2 (DSI-2SM), version 1.1 and above,
241 [MIPI05] Specification for Improved Inter Integrated Circuit (I3C®), version 1.1.1 and above,
243 [MIPI06] Specification for C-PHYSM, version 2.0 and above, MIPI Alliance, Inc.
244 [MIPI07] Specification for M-PHY®, version 4.1 and above, MIPI Alliance, Inc.
245 [MIPI08] MIPI Alliance, Inc., “MIPI Alliance Manufacturer ID Page”, https://mid.mipi.org,
246 last accessed 24 May 2023.
247 [MIPI09] MIPI A-PHY Protocol Adaptation Layer Specification for CSI-2 (MIPI PAL/CSI-2SM),
248 version 1.0 and above, MIPI Alliance, Inc.
249 [MIPI10] Specification for Camera Service Extensions (CSESM), version 1.0 and above,
251 [MIPI11] MIPI A-PHY Protocol Adaptation Layer Specification for I2C (MIPI PAL/I2C),

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253 [MIPI12] MIPI A-PHY Protocol Adaptation Layer Specification for GPIO (MIPI PAL/GPIO),
255 [MIPI13] MIPI Alliance, Inc., “MIPI A-PHY Adaptation Type Values”, https://www.mipi.org/aphy-
256 adaptation-type-values, last accessed 24 May 2023.
257 [MIPI14] MIPI Alliance, Inc., “Board Approved Specifications”, https://members.mipi.org/wg/All-
258 Members/home/approved-specs, last accessed 24 May 2023.
259 [NXP01] UM10204, I2C Bus Specification and User Manual, Rev. 7 and above, NXP Corporation.

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4 Overview
260 A-PHY addresses the need to move asymmetric, high-throughput data of sensors (e.g., Camera, Lidar, Radar,
261 and others) and display devices located around a vehicle to and from the system CPU over high speed links
262 with optimal wiring, cost, and weight. A-PHY can also be applied to many other non-automotive use cases.
263 A-PHY provides a main uni-directional data stream, and a bi-directional low-throughput command and
264 control data stream, and can optionally also deliver the required power supply to peripheral units (i.e., the
265 sensors and/or displays at the edge of the network) directly via the A-PHY data lines.
266 Figure 1 illustrates the logical structure of the expected Link for sensors or displays. Note that high speed
267 data, control data, and the optional power supply all share the same physical wiring.
Power Power
Sensor Sensor Data (High Speed Uni-Directional)

Processing Display Data (High Speed Uni-Directional)
Display
Unit Command and Control (Bi-Directional)
Unit Command and Control (Bi-Directional)
Unit
268
Figure 1 Data and Power Logical Structure
269 As Figure 2 illustrates, A-PHY includes a generic Data Link Layer that supports a range of Protocol
270 Adaptation Layers for carriage of existing protocols both from MIPI (such as CSI-2 and I3C) and from other
271 sources (such as I2C).
Native Protocol Adaptation Layer

A-PHY Data Link Layer

A-PHY PHY Layer
A-PHY PHY Layer

Native Protocol
Native Protocol
(APDLL)
(APDLL)
(NPAL)
(NPAL)
(APPL)
(APPL)
(NP)
(NP)
Cable
Protocol A-PHY A-PHY Protocol
Uni-Directional High Speed
Bi-Directional Low Speed

272
Figure 2 High Level Layer Structure

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5 Architecture
5.1 High Level Structure

273 An A-PHY system implements a layered solution, as shown in Figure 3.
274 The layers are:
275 • Native Protocol Layer: The Native Protocol Layer implements a specific Native Protocol (and its
276 associated interface) in accordance with that protocol’s specification. This could be either a MIPI
277 protocol (such as CSI-2, DSI, etc.), or an external SDO’s protocol (such as eDP, HDMI, etc.).
278 Note:
279 The Protocol Layer is outside the scope of this specification.
280 • Native Protocol Adaptation Layer: The Native Protocol Adaptation Layer applies conversion of a
281 specific Native Protocol to and from A-Packet structure.
282 Note:
283 The Adaptation Layer is outside the scope of this specification.
284 • APPI: The APPI is the interface between the A-PHY and the upper layers (i.e., the Adaptation Layer
285 for each Native protocol). The APPI definition is part of this specification. All types of Adaptation
286 Layers shall specify the adaptation to that APPI, as shown in Figure 3.
287 • Data Link Layer: The A-PHY Data Link Layer interfaces with one or more Native Protocol
288 Adaptation Layers (each through its own APPI) and performs A-Packet scheduling, prioritization,
289 and forwarding.
290 • Physical Layer: The A-PHY Physical Layer encodes and decodes symbols extracted from A-Packets
291 according to the modulation scheme used per Gear. It handles retransmission of A-Packet, as
292 necessary. The modulated symbols are being transmitted and received over the A-PHY interconnect
293 according to the medium-dependent electrical specifications.

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Native Protocol
Adaptation Layer Adaptation Layer

APPI
Data Link Layer
Link: Multi-Port Oriented Link: Multi-Port Oriented
Link: Port Oriented Link: Port Oriented
PHY Layer PHY Layer PHY Layer

A-PHY
RTS RTS
PCS PCS
PMD PMD
A-PHY Source A-PHY Sink

Medium High Throughput Uni-Directional Data
Low Throughput Bi-Directional Control and Data

294
Figure 3 A-PHY High Level Structure

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5.2 A-PHY Ports

295 An A-PHY link connects a Source port with a Sink port.
296 In this Specification:
297 • The term Downlink represents high throughput communication sent from Source to Sink
298 • Reverse Downlink represents high throughput communication sent from Sink to Source
299 • Uplink represents low throughput (<500 Mbps) communication sent from Sink to Source
300 Interoperability and Gear fallback shall be maintained between Source and Sink ports of the same port type.
5.2.1 C-Port
301 A C-Port is a coaxial (i.e., single conductor) port, using 50 Ω coax connectors and coax cables.
302 A C-Port shall work in Highly Asymmetric operation mode, where Downlink and Uplink communications
303 shall be sent over the same coax channel. There is no Reverse Downlink for this operation mode.
5.2.2 D-Port
304 A D-Port is a differential (i.e., dual conductor) port, using 100 Ω differential pair connectors and single
305 differential pair cables.
306 A D-Port shall work in Highly Asymmetric operation mode, where Downlink and Uplink communications
307 shall be sent over the same single-pair channel. There is no Reverse Downlink for this operation mode.

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5.2.3 Q-Port
308 A Q-Port is a “star quad” (i.e., four conductors arranged as two differential pairs) port, using 100 Ω HSD
309 connectors and Star Quad (STQ) cables, as illustrated in Figure 4.
310 For a Q-Port Downlink:
311 • Pair #0 and Pair #1 “identities” shall be selected by the Source port
312 • The Sink port shall resolve potential inter-pair swap to match the selection made by the Source
313 • Resolved Pair #x is denoted as [Port #x]
314 Example: [Pair #0] for the Sink is the Pair that the Source identifies as Pair #0
315
Figure 4 Star Quad Arrangement of Quad Conductors into Two Differential Pairs
316 • Q-Ports shall have the following operation modes (also summarized in Table 1):
317 • Dual Lane Downlink, Highly Asymmetric mode:
318 • Downlink shall be sent over both Pair #0 and Pair #1
319 • Uplink shall be sent only over Sink’s Pair #0
320 • Asymmetric mode:
321 • Downlink shall be sent only over Source Pair #0
322 • A lower rate Reverse Downlink shall be sent only over the Sink-resolved [Pair #1]
323 • (Uplink is not used in this mode)
324 • Symmetric mode:
326 • An equal rate Reverse Downlink shall be sent only over the Sink-resolved [Pair #1]
327 • (Uplink is not used in this mode)
328 • Single Lane Q-Fallback Highly Asymmetric mode:
330 • Uplink shall be sent only over the Sink-resolved [Pair #0]

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Table 1 Q-Port Operation Modes
Operation Downlink Sent

Description Reverse Downlink Uplink Sent Over
Mode Over
Dual Lane Downlink,
Mode 1 Pair #0 and Pair #1 – Sink’s Pair #0
Highly Asymmetric
Lower Rate over
Mode 2 Asymmetic Source Pair #0 Sink-resolved –
[Pair #1]
Equal Rate over
Mode 3 Symmetric Source Pair #0 Sink-resolved –
[Pair #1]
Single Lane Q-
Sink-resolved
Mode 4 Fallback Highly Source Pair #0 –
[Pair #0]
Asymmetric mode
331 Symmetric Q-Port: A Q-Port supporting Symmetric mode:

332 • Shall be able to be configured both as a Symmetric Source and as a Symmetric Sink
333 • Shall be able to be configured both as an Asymmetric Source and as an Asymmetric Sink.
334 Sink and Source identities shall be pre-configured for such a Symmetric Q-Port.
335 Each Source Q-Port shall support a Single Lane Q-Fallback Highly Asymmetric mode Source
336 configuration.
337 Each Sink Q-Port shall support a Single Lane Q-Fallback Highly Asymmetric mode Sink
338 configuration.

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5.2.4 Gears
5.2.4.1 Normative Downlink and Reverse Downlink Gears
339 A-PHY defines 5 discrete Gears for raw data rates for per-Lane Downlink and Reverse Downlink: G1, G2,
340 G3, G4, and G5 (see Table 2).
341 A-PHY Downlink and Reverse Downlink shall operate at the defined per-Lane data rates shown in Table 2.
342 Reverse Downlink shall be implemented only over a single Lane (i.e., a single Symbol Rate and base
343 Modulation are specified).
344 An A-PHY Device supporting Gear N (i.e., N could be 1–5) shall support all mandatory lower gears per Table
345 2.
346 Table 2 Per Lane Normative Downlink / Reverse Downlink Gears
Gear Symbol Rate Max Net App Data Rate

Modulation
Rate (GBaud) (Gbps)
G1
NRZ-8B/10B 2 1.5
2 Gbps
G2
NRZ-8B/10B 4 3
4 Gbps
G3
PAM4 4 7.2
8 Gbps
G4
PAM8 4 10.8
12 Gbps
G5
PAM16 4 14.4
16 Gbps
347 Note:
348 Max Net Application Data Rate is Computed by reducing from the Raw Rate the combined overheads
349 associated with A-Packet framing, PCS line coding and the pacing done towards the line.

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5.2.4.2 Normative-Optional Gears

350 For G1–G3, Normative-Optional profile Gear implementations are defined (see Table 3). These may be
351 implemented in addition to the Normative Profile Gear implementation. If a Normative-Optional Gear
352 implementation is supported, then it shall be implemented as defined in Table 3.
353 Table 3 Normative-Optional, Downlink / Reverse Downlink Gear Implementations
Gear Symbol Rate Max Net App Data Rate
Modulation
Rate (GBaud) (Gbps)
G1
PAM4 1 1.8
2 Gbps
G2
PAM4 2 3.6
4 Gbps
G3
NRZ-8B/10B 8 6
8 Gbps
354 Note:
355 G3 NRZ-8B/10B shall be used only over C/D-Port (i.e. G3 NRZ-8B/10B shall not be used for Reverse
356 Downlink
5.2.4.3 Normative Uplink Gears

357 A-PHY defines two discrete raw data rate Uplink-Gears: U1 and U2 (see Table 4).
358 Uplink shall be implemented only over a single Lane.
359 An A-PHY Port supporting Uplink-Gear 2 (U2) shall support U1 as well.
360 Per Uplink Gear, a Normative Symbol Rate and base Modulation are specified. An A-PHY Uplink shall
361 operate at the defined data rates shown in Table 4.
362 Table 4 Normative Uplink Gears
Uplink Gear Symbol Rate Max Net App Data Rate
Modulation
Rate (MBaud) (Mbps)
U1
NRZ-8B/10B 100 54
100 Mbps
U2
PAM4-8B/10B 100 125
200 Mbps

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5.2.4.4 Q-Port Configurations Per Gear

363 The Normative Q-Port configurations are defined in Table 5 through Table 8.
364 Table 5 Dual Lane Downlink Highly Asymmetric Q-Port, Normative Configurations
Port Port Net

Lane Rate Per Lane Number of Lanes Application
Rate
Gear (Gbps) per Direction Data Rate
(Gbps) (Gbps)
Dual Lane Downlink (on Pair #0 & Pair #1)
16 G3 8 2 14.4
24 G4 12 2 21.6
32 G5 16 2 28.8
Uplink (on Pair #0)
0.1 U1 0.1 1 0.054
0.2 U2 0.2 1 0.125
365 Table 6 Asymmetric Q-Port Normative Configurations
Port Port Net

Lane Rate Per Lane Number of Lanes per Application
Rate
Gear (Gbps) Direction Data Rate
(Gbps) (Gbps)
Downlink (on Pair #0)
8 G3 8 1 7.2
12 G4 12 1 10.8
16 G5 16 1 14.4
Reverse Downlink (on Pair #1)
2 G1 2 1 1.5
4 G2 4 1 3

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366 Table 7 Symmetric Q-Port Normative Configurations
Port Port Net

Lane Rate Per Lane Number of Lanes Application
Rate
Gear (Gbps) per Direction Data Rate
(Gbps) (Gbps)
Same Gear is Used for Downlink (Pair #0) and Reverse Downlink (Pair #1)
8 G3 8 1 7.2
12 G4 12 1 10.8
16 G5 16 1 14.4
367 Table 8 Q-Fallback Highly Asymmetric Mode Normative Configurations
Port Port Net

Lane Rate Per Lane Number of Lanes per Application
Rate
Gear (Gbps) Direction Data Rate
(Gbps) (Gbps)
Downlink (on Pair #0)
8 G3 8 1 7.2
12 G4 12 1 10.8
16 G5 16 1 14.4
Uplink (on Pair #0)
0.1 U1 0.1 1 0.054
0.2 U2 0.2 1 0.125
5.2.4.4.1 Q-Port Type Interoperability

368 Table 9 shows the interoperability of the Q-Port types with one another.

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369 Table 9 Q-Port Types Interoperability Matrix

Dual Lane Downlink
Q-Port Type Asymmetric Symmetric
Highly Asymmetric
Dual Lane Downlink Dual Lane Downlink Q-Fallback Q-Fallback

Highly Asymmetric Highly Asymmetric Highly Asymmetric Highly Asymmetric
Q-Fallback
Asymmetric Asymmetric Asymmetric
Highly Asymmetric
Q-Fallback Highly
Symmetric Asymmetric Symmetric
Asymmetric

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5.3 Profiles
370 A-PHY supports two profiles to better fit the technical attributes and cost structure of the different automotive
371 market segments.
372 • Profile 1 (P1) is aimed at lower Downlink speeds and lower complexity implementations, with
373 channel attributes and design characteristics enabling lower cost implementations.
374 P1 is based on NRZ 8B/10B technology.
375 • For C-Port/D-Port implementation, P1 is Normative for G1 and G2, and it is Normative-Optional
376 for G3.
377 • P1 shall not be implemented in a Q-Port.
378 • P1 shall provide a Packet Error Rate (PER) of less than 10 -9 under the noise conditions described
379 in Section 7.
380 • Profile 2 (P2) is aimed at solutions requiring superior noise immunity and higher Downlink speeds;
381 it also has a better bandwidth utilization (i.e. net data rate per gear).
382 P2 is based on dynamic PAM scheme, local PHY level retransmission, and noise cancellers.
383 • P2 shall utilize Retransmission (RTS) for all of its Downlink / Reverse Downlink / Uplink
384 Implementations.
385 • For C-Port/D-Port implementation, P2 is Normative for all Gears above G2, while it is Normative-
386 Optional for G1 and G2 using their Normative base modulation of NRZ-8B/10B.
387 • P2 defines an additional optional modulation when operating in G1 and G2. The modulation
388 scheme used for P2 in G1 and G2 shall be selected according to the pre-configured value in the
389 configuration registers (see Section 12.2). An A-PHY Device that supports such optional
390 capability shall support P2 on both modulation schemes for G1 and G2 (NRZ-8B/10B and PAM4).
391 • P2 shall provide a Packet Error Rate (PER) of less than 10-19 under the noise conditions described
392 in Section 7. For G1 and G2, it will provide a PER of less than 10 -18.
393 P1 has lower noise immunity requirements than P2, as detailed in Section 7.
394 P1 and P2 are interoperable at G1 and G2.
395 The Data Link Layer, as described in Section 11, is common for both profiles.

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5.4 Safety
396 Functional safety according to ISO 26262 [ISO01] includes the following measures, given a system-level
397 safety goal and allocated ASIL:
398 • Control and avoidance of systematic failures → Ensured through Robust development process
399 • Control of random hardware failures → Ensured through robust design including mechanisms to
400 detect random HW failures, when they occur.
401 A-PHY packets are end-to-end protected as recommended in ISO-26262:2018:
402 • CRC-32 for each packet, providing a Hamming-Distance of more than 3.
403 • Message Counter that is 8 bits wide.
404 • Timeout monitoring is fulfilled by the Keep-Alive function (see Section 11.3.2)
405 The above measures are necessary to argue a high diagnostic coverage for a communication bus, per
406 Table D.6 in ISO 26262-5:2018.
407 All other functional safety features necessary in order to fulfil the required system-level safety goal with
408 ASIL are expected to be managed by upper layers.

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6 Interconnect
409 The interconnect between an A-PHY Source and an A-PHY Sink carries the high-speed uni-directional data
410 stream, the low-speed bi-directional command and control data and optionally the power supply to an end
411 unit, e.g., an automotive surround sensor. The interconnect can be optimized for reliability, cost, or weight.
412 A-PHY is defined for two cable topologies consisting of potentially multi wire segments of either unbalanced
413 coax cables or balanced cables like a Shielded Twisted Pair (STP) or a Shielded Parallel Pair (SPP). The
414 characteristics of these interconnects are defined within this section. Other cable topologies are outside the
415 scope of this document though they can work as well. The total interconnect may include cable segments,
416 inline connectors, PCB mating connectors, PCB traces along with any related vias, as well as coupling
417 capacitors at both End Nodes.
418 A representative A-PHY interconnect is illustrated in Figure 5. The Power Sourcing Equipment (PSE) and
419 Powered Device (PD) blocks are optional, they can be used in systems employing either balanced or
420 unbalanced interconnects. While Figure 5 shows separated grounds for the End Nodes, there are also
421 common ground use cases to avoid ground loop challenges. Sensor modules may thus have a shared ground
422 with the ECU.
VOUT1, VOUT2, ... VIN

PD PSE
Downstream
Power
e.g. Camera Upstream e.g. Auto ECU
A-PHY Cable TLIS A-PHY

Source (Coax, SDP) Sink
GND1 GND2
GND1 GND2
End Node End Node
423
Figure 5 A-PHY Interconnect
6.1 Lane Configuration

424 The complete physical connection of a Lane consists of two End Nodes with a Transmission-Line-
425 Interconnect-Structure (TLIS) in between. An End Node comprises an A-PHY transceiver and an End-Node
426 Interconnect-Structure (ENIS), and may also include one PD or PSE block. The TLIS between End Nodes
427 may be formed by cable segments (Cable TLIS) or by PCB traces (PCB TLIS). This section defines the
428 required performance of the Transmission-Line-Interconnect-Structure for the signal and power routing as
429 well as interconnect related characteristics of the End Nodes. This, along with the A-PHY transceiver
430 characteristics and noise immunity profile of the Link, ensures the correct overall operation of a Lane.
431 A-PHY is a single or dual Lane, point-to-point, serial communication technology.

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6.2 Cable Topology

432 A-PHY defines two cable topologies, consisting either of unbalanced Coax cables or balanced STP and SPP
433 cables, which are collectively referenced as Shielded Differential Pair (SDP) cables or Dual Differential Pair
434 Shielded (Star Quad or STQ) cables. The Cable TLIS characteristics are defined for the following two
435 topologies, which are also shown in Figure 6:
436 • Coax Topology: Coax cables of total 15 m, with 4 inline connectors and minimum cable segment
437 length of 30 cm.
438 • SDP/STQ Topology: SDP/STQ cables of total 10 m, with 4 inline connectors and minimum cable
439 segment length of 30 cm.
440 The interconnect characteristics are derived for certain cable and connector models. A guidance for the
441 selection of such models is outside the scope of this document. The chosen cables and connectors impact the
442 maximum cable length supported.
443 An A-PHY implementation may support either Coax, SDP, STQ, or all cable topologies. An A-PHY
444 implementation shall support all interconnect characteristics defined within this Interconnect section for the
445 supported cable topology.
Coax Topology
Conn.
Conn.
Conn.
Sensor/Display Conn. ECU

End Node End Node
15 m
SDP Topology
Conn.
Conn.
Conn.
Conn.
Sensor/Display ECU
End Node End Node
10 m
Conn. Inline Connectors
Legend
PCB Mating Connectors
446
Figure 6 Cable Topologies
6.3 Boundary Conditions

447 The reference characteristic impedance level is 100  differential, 50  single-ended, and 25  common-
448 mode if applicable. The 50  impedance level for single-ended operation is also convenient for test and
449 characterization purposes.
450 These typical impedance levels are required for all parts of the interconnect including End Nodes. The
451 tolerances of characteristic impedances of the interconnect and the tolerances of line termination impedances
452 of End Nodes are specified by means of S-parameter templates over the whole operating frequency range.

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6.4 S-Parameter Specifications

453 The characteristics of the physical connection are specified by means of S-parameters for TLIS and End
454 Nodes, specifically Insertion Loss (IL) and Return Loss (RL) parameters. The S-parameter limits are defined
455 up to a maximum frequency of 6 GHz; any A-PHY implementation shall meet the S-parameter limits up to a
456 minimum frequency of 1.5 * FNyquist of the highest gear supported, where FNyquist is the Nyquist frequency.
457 The budgeting of losses, reflections, and mode-conversions beyond what is defined in this standard, as well
458 as their allocation to individual physical parts of the interconnect, is left to the system designer.
6.5 Characterization Conditions

459 All S-parameter definitions are based on a 50 Ω impedance reference level. The characterization of End
460 Nodes and TLIS can be done with a measurement system as shown in Figure 7.
461
Figure 7 Set-up for S-parameter Characterization of End Nodes and TLIS
462 A differential End Node should interface a balanced TLIS through a two-pin connector or two pins in a multi-
463 Port connector.
464 A single-ended End Node should interface an unbalanced TLIS through a one pin connector or one pin in a
465 multi-Port connector.
466 The syntax of S-parameters is:
467 S[measured-mode][driven-mode][measured-port][driven-port]
468 Where:
469 In [measured-mode] and [driven-mode]: d is for differential, c is for common-mode, and blank is for
470 single-ended
471 And [measured-port] and [driven-port] are both port numbers
472 Examples:
473 • Sdd21 is the differential signal at Port 2 due to a differential signal driven at Port 1
474 • Sdc22 is the measured differential reflected signal at Port 2 due to a common-mode signal driven at
475 Port 2
476 • S11 is the measured single-ended reflected signal at Port 1 due to a single-ended signal driven at
477 Port 1

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6.6 Interconnect Specifications

478 The total interconnect is specified by means of S-parameter limits over the relevant frequency range. This
479 includes the insertion and return losses, and mode-conversion limits.
480 The interconnect is further sub-divided into:
481 • Cable Transmission-Line-Interconnect-Structure (TLIS) comprised of Coax/SDP/STQ cable
482 segments as well as inline connectors and two halves of the mating connectors.
483 • End-Node-Interconnect-Structure (ENIS) comprised of half of the mating connector, PCB traces as
484 well as any related vias and supporting circuitry for ESD protection, power feed, diplexer including
485 AC caps, and other signal conditioning functions.
486 The total interconnect along with the set of test points is shown in Figure 8. These test points (TPx) define
487 reference planes for parameters in the Electrical section (Section 9), as well as S-parameter definitions
488 contained within this section.
Interconnect
ENIS Cable TLIS ENIS
End Node End Node
A-PHY PCB Circuitry PCB Circuitry A-PHY

Conn.
Source (CMC, ESD, Filter, (CMC, ESD, Filter,

Sink
TPA TPB
TP3 TP2 TP1 TP4 TP5 TP6
Conn. Inline Connectors
Legend
PCB Mating Connectors
489
Figure 8 Interconnect Test Points Definition
490 The S-parameter characteristics for the Cable TLIS and End Nodes are measured at TPA and TPB. The total
491 interconnect is defined between TP3 and TP6 which identify the signal pins of the A-PHY transceiver chips.
492 PCB circuitry and routing at the End Nodes is delimited by TP2-TP3 and TP5-TP6 with ENIS including the
493 additional mating connectors thus TPA-TP3 and TPB-TP6.
494 Some implementations may use PCB routing only for the interconnect. A PCB TLIS is defined in
495 Section 6.6.4, which replaces all the elements between TP2 and TP5. The overall PCB routing includes
496 contributions from ENIS and PCB TLIS.
6.6.1 Total Interconnect
497 Total interconnect includes two ENIS portions and a Cable TLIS or PCB TLIS whose characteristics are
498 defined in the following sub-sections.
499 The flight time TFLIGHT for signals across the total interconnect shall not exceed 100 ns.

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6.6.2 Cable TLIS (Transmission Line Interconnect Structure)

6.6.2.1 Characteristic Impedance
500 The nominal characteristic impedance of Coax cable is 50 Ω.
501 The nominal differential characteristic impedance of SDP/STQ cable is 100 Ω.
6.6.2.2 Insertion Loss

502 The Coax and SDP Cable TLIS shall meet the Coax Cable Insertion Loss limit and the SDP/STQ Cable
503 Insertion Loss limit, respectively. These limits are defined by the following equations:
504 • Coax Cable Insertion Loss limit:
IL_COAX ≤ 0.15 * ( −1.3 + 0.0115*f+2*√f + 3.79 / √f ) (dB)

where f is Frequency in MHz
505
506 • SDP/STQ Cable Insertion Loss limit:
IL_SDP ≤ 0.0021 * f + 0.315 * √f + 0.36 (dB)

where f is Frequency in MHz
507
508 Insertion Loss limits include all expected degradations due to aging, humidity, temperature, and mechanical
509 stress.
510 Channel impairments resulting from resonance effects of wire lay length or shield stranding in the cable shall
511 not exceed the following limits:
512 • 3 dB within any 10 MHz section in the frequency range up to 100 MHz.
513 • 3 dB within any 100 MHz section above 100 MHz up to the operational frequency.
514 The Insertion Loss limits for both Coax and SDP/STQ cables are graphically shown in Figure 9 as Sddij or
515 Sij limit lines, where i ≠ j.
516
Figure 9 Coax and SDP/STQ Cable Insertion Loss Limits

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6.6.2.3 Return Loss

517 The same Cable TLIS Return Loss (RL) limits apply for Coax and SDP/STQ topologies. The return loss
518 limits include all expected degradations due to aging, humidity, temperature, and mechanical stress.
519 There are two RL limits defined:
520 • RL Limit for a cable with maximum defined IL
521 • Relaxed RL Limit for a cable with up to half of the defined IL limit
522 The Relaxed RL Limit only applies to cables whose IL is equal or better than half the maximum
523 defined IL, as per Section 6.6.2.2 across all relevant operating frequencies.
524 The Cable RL shall meet the values in Table 10.
525 Table 10 Cable TLIS Return Loss
Return Loss
Frequency (dB)
(MHz)
Maximum IL Half IL
5 < f ≤ 500 ≥ 17 ≥ 17
500 < f ≤ 2000 ≥ 17 − ((f−500) / (2000−500)) * 4 ≥ 17 − ((f−500) / (2000−500)) * 7
2000 < f ≤ 3200 ≥ 13 − ((f−2000) / (3200−2000)) * 1.5 ≥ 10 − ((f−2000) / (3200−2000)) * 1.5
3200 < f ≤ 4500 ≥ 11.5 − ((f−3200) / (4500−3200)) * 6.5 ≥ 8.5 − ((f−3200) / (4500−3200)) * 4.5
4500 < f ≤ 6000 ≥5 ≥4
526 The Cable RL limits are graphically shown in Figure 10 as Sddii or Sii limit lines.
0.00
-2.00
-4.00
-6.00
Sddii, Sii (dB)
-8.00
-10.00
-12.00
-14.00
-16.00
-18.00
0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 5500 6000
Frequency (MHz)
Max IL Half IL
527
Figure 10 Cable TLIS Return Loss Limits

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6.6.2.4 Coupling Attenuation

528 The Coupling Attenuation defines both the emission and immunity characteristics of the Cable TLIS and is
529 comprised of Screening Attenuation, a measure of the effectiveness of the cable shielding, and Unbalanced
530 Attenuation, a measure of the mode conversion.
531 Figure 11 shows how Coupling Attenuation is applicable to Coax and SDP/STQ cables. For Coax, the entire
532 Coupling Attenuation is provided by the cable shield alone (i.e., Screening Attenuation), whereas for
533 SDP/STQ cables, it is a combination of the shield and Unbalanced Attenuation.
Coupling Attenuation
Unbalanced
Attenuation
Attenuation
Screening
Attenuation
Screening
Attenuation
Coax SDP
534
Figure 11 Cable TLIS Coupling Attenuation
535 The Coupling Attenuation shall exceed or at a minimum equal the limits shown in Table 11.
536 Table 11 Coupling Attenuation
Frequency Coupling Attenuation
(MHz) (dB)
30 < f ≤ 4000 60
4000 < f ≤ 6000 50
537 The Screening Attenuation shall exceed, or at a minimum equal, the limits shown in Table 12.
538 Table 12 Screening Attenuation
Frequency Screening Attenuation
(MHz) (dB)
f ≤ 6000 45

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539 The Unbalanced Attenuation shall exceed, or at a minimum equal, the limits shown in Table 13.
540 Table 13 Unbalanced Attenuation
Frequency Unbalanced Attenuation
(MHz) (dB)
30 < f ≤ 1265 15
1265 < f ≤ 4000 15 – 20 * log10( f/1265 )
4000 < f ≤ 6000 5
541 The Cable TLIS Attenuation limit lines are graphically shown in Figure 12.
60
50
40
Attenuation (dB)
30
20
10
0
10 100 1000 10000
Frequency (MHz)
Unbalanced Attenuation Screening Attenuation Coupling Attenuation
542
Figure 12 Cable TLIS Attenuation Limits
543 Coax and SDP/STQ cables shall comply with the limits shown in Table 11. SDP/STQ cables shall
544 additionally comply with the limits shown in Table 12 and Table 13.

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6.6.2.5 Alien Cable Bundle Crosstalk

545 The Alien Cable Bundle Crosstalk consists of far-end and near-end crosstalk of alien cables, routed within
546 the same bundle (harness) together with the victim cable. The bundle may include both A-PHY and other
547 aggressors, e.g., 100Base-T1, or 1000Base-T1, which can have different power levels within the same
548 frequency range.
549 The cable bundle crosstalk is constrained through PSCR_BUNDLE(f) parameter, defined as the ratio of the
550 power sum of the individual bundle crosstalk contributions at an A-PHY victim receiver to the aggressor’s
551 Transmitter power as captured in the equation below:
∑𝑁 𝑃(𝑓)𝐵𝑈𝑁𝐷𝐿𝐸𝑋𝑇𝐴𝐿𝐾 ,𝑁
𝑉𝐼𝐶𝑇𝐼𝑀
552 𝑃𝑆𝐶𝑅_𝐵𝑈𝑁𝐷𝐿𝐸(𝑓) = 10 × 𝑙𝑜𝑔10 ( ) (𝑑𝐵)
𝑃(𝑓)𝐴𝐺𝐺𝑅𝐸𝑆𝑆𝑂𝑅
553 where P(f)BUNDLE_XTALK_VICTIM,N represents the power coupled into the A-PHY victim receiver from aggressor
554 N in the presence of the P(f)AGGRESSOR aggressor power.
555 The Alien Cable Bundle Crosstalk should meet the limits shown in Table 14.
556 Table 14 Alien Cable Bundle Crosstalk
Frequency PSCR_BUNDLE
(MHz) (dB)
0 < f ≤ 500 −75
500 < f ≤ 6000 −125.434 + 18.686 * log10(f)
557 The Alien Cable Bundle Crosstalk limit line is graphically shown in Figure 13.
-50
-55
-60
PSCR_BUNDLE (dB)
-65
-70
-75
-80
1 10 100 1000
Frequency (MHz)
558
Figure 13 Alien Cable Bundle Crosstalk Limit

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6.6.2.6 STQ Inter-Pair Crosstalk

559 STQ cables consist of dual differential pairs placed within the same jacket. For STQ cables, the inter-pair
560 crosstalk shall meet the limits specified in Table 15.
561 Table 15 STQ Inter-Pair Crosstalk
Frequency Inter-Pair Crosstalk
(MHz) (dB)
10 ≤ F ≤ 3000 ≤ (-30 + 0.0034 * F)
-18
-20
STQ Inter-Pair Crosstalk (dB)
-22
-24
-26
-28
-30
0 500 1000 1500 2000 2500 3000
Frequency (MHz)
562
Figure 14 STQ Inter-Pair Crosstalk Limit
6.6.2.7 STQ Inter-Pair Skew

563 STQ cables consist of dual differential pairs placed within the same jacket. For STQ cables, the inter-pair
564 skew shall meet the limit specified in Table 16.
565 Table 16 STQ Inter-Pair Skew
Frequency Inter-Pair Skew
(MHz) (nS)
F ≤ 3000 ≤1

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6.6.3 ENIS (End Node Interconnect Structure)

566 Differential End Nodes should use differential coupled traces with a nominal characteristic impedance of
567 100 Ω to optimize signal integrity and minimize the impact of noise on an A-PHY transceiver.
568 Single-ended End Nodes can use a combination of single-ended and differential structures as shown in Figure
569 15. This solution allows using the same A-PHY transceiver as in differential End Nodes while improving
570 EMI effects. Differential traces should be routed with nominal characteristic impedance of Z0′ = 100 Ω
571 differential. In places where differential routing is not possible, impractical, or not advised, such as the
572 connection between the coaxial connector and AC coupling capacitor, single-ended traces with nominal
573 characteristic impedance of Z0 = 50 Ω should be used.
End Node
PD,
PSE
Dp Z0
TLIS (Coax)
A-PHY Z0'
Dn
Z0
574
Figure 15 Single-Ended End Node Routing Example

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575 A-PHY implementations should allow for an End Node Insertion Loss at both ends of the Link as defined in
576 Table 17. The End Node Insertion Loss includes the contributions from ENIS and A-PHY transceiver.
577 Table 17 End Node Insertion Loss
Frequency Insertion Loss

(MHz) (dB)
f<1 6 − 5.5 * log10( f/0.1 )
1 ≤ f < 500 0.5
500 ≤ f < 2000 0.5 − 1.66 * log10( 500/f )
2000 ≤ f < 6000 1.5 − 9.44 * log10( 2000/f )
578 The End Node Insertion Loss limit is graphically shown in Figure 16 as an Sddij or Sij limit line, where i ≠ j.
579
Figure 16 End Node Insertion Loss Limit

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6.6.3.3 Return Loss

580 The End Node Return Loss shall comply with the limits shown in Table 18. The End Node Return Loss
581 includes the contributions from ENIS and A-PHY transceiver.
582 All A-PHY Ports shall comply with the Return Loss A limits. A-PHY Ports operating at the optional Gear 3
583 NRZ 8b10b mode shall additionally comply with the Return Loss B limit.
584 Table 18 End Node Return Loss
Frequency Return Loss A Frequency Return Loss B

(MHz) (dB) (MHz) (dB)
f < 0.5 0 f < 0.5 0
0.5 ≤ f < 5 18 – 18 * log10( 5/f ) 0.5 ≤ f < 5 18 – 18 * log10( 5/f )
5 ≤ f < 100 18 5 ≤ f < 600 18
100 ≤ f < 2750 18 – 11.11 * log10( f/100 ) 600 ≤ f < 2390 18 – 20 * log10( f/600 )
2750 ≤ f < 6000 2 2390 ≤ f < 6000 6
585 The End Node Return Loss limits are graphically shown in Figure 17 as Sddii or Sii limit lines.
586
Figure 17 End Node Return Loss Limits
6.6.3.4 Mode Conversion

587 This specification does not define any limits on differential to common-mode conversion, and vice-versa,
588 however implementers should endeavor to keep differential structures and routing as symmetric as possible
589 for increased robustness of A-PHY applications.

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6.6.3.5 Receiver Alien Near End Crosstalk

590 At the downstream receiver side there may be a need to condense multiple A-PHY links into a compact
591 multi-Port connector and to use very limited PCB space to route the signals to the A-PHY transceiver chip
592 with their additional PoC components, AC capacitors and other supporting circuitry. Such requirements
593 resulted in the definition of Alien Near End crosstalk (ANEXT).
594 Non-A-PHY aggressors shall not share the same multi-Port connector as A-PHY links and should not target
595 the same multi-Port A-PHY receiver, i.e., their PCB crosstalk can be sufficiently mitigated such that the
596 overall crosstalk contribution is dominated by the Alien Cable Bundle Cross talk described in Section 6.6.2.5.
597 The PCB receiver crosstalk is constrained through PSCR_PCB(f) parameter, defined as the ratio of the power
598 sum of the individual PCB crosstalk contributions at an A-PHY victim receiver to the aggressor’s Transmitter
599 power as captured in the equation below:
∑𝑁 𝑃(𝑓)𝑃𝐶𝐵𝑋𝑇𝐴𝐿𝐾 ,𝑁
𝑉𝐼𝐶𝑇𝐼𝑀
600 𝑃𝑆𝐶𝑅_𝑃𝐶𝐵(𝑓) = 10 × 𝑙𝑜𝑔10 ( ) (𝑑𝐵)
𝑃(𝑓)𝐴𝐺𝐺𝑅𝐸𝑆𝑆𝑂𝑅
601 where P(f)PCB_XTALK_VICTIM,N represents the power coupled into the A-PHY victim receiver from aggressor N in
602 the presence of the P(f)AGGRESSOR aggressor power.
603 The Receiver Alien Near End Crosstalk should meet the limits given in Table 19.
604 Table 19 Receiver ANEXT
Frequency PSCR_PCB
(MHz) (dB)
0 < f ≤ 1000 −52
1000 < f ≤ 6000 −52 + 20 * log10( f/1000 )
605 The Receiver Alien Near End Crosstalk limit line is graphically shown in Figure 18.
-30
-35
PSCR_PCB (dB)
-40
-45
-50
-55
1 10 100 1000 10000
Frequency (MHz)
606
Figure 18 Receiver ANEXT Limit

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6.6.4 PCB TLIS (Transmission Line Interconnect Structure) (Informative)

607 It is expected that A-PHY transceiver may be fully-integrated into sensor and SoC chips and that such chips
608 will be interconnected in a variety of topologies including short interconnect structures fully contained within
609 a single PCB. Such a topology is shown in Figure 19 and represents a much less stringent interconnect than
610 the one introduced in Figure 5. A-PHY transceivers should be optimized to handle this type of interconnect
611 with a special focus on lowering the power dissipation and reducing heat in highly confined spaces such as
612 sensor modules.
PCB
End Node End Node
A-PHY Z0
A-PHY
Source Sink
PCB TLIS
613
Figure 19 PCB-Based Interconnect

614 PCB routing should be done differentially using coupled traces with a nominal characteristic impedance of
615 100 Ω.
616 The insertion loss for the PCB TLIS should meet the limits set for the Cable TLIS in Section 6.6.2.2. The
617 expectation is that PCB TLIS IL values are much smaller than Cable TLIS IL and consistent with a typical
618 PCB channel of a few unit inches.
6.6.4.3 Return Loss
619 The return loss for the PCB TLIS should meet the limits set for the Cable TLIS in Section 6.6.2.3. The
620 expectation is that PCB TLIS RL values are much smaller than Cable TLIS RL and consistent with a typical
621 PCB channel of a few unit inches.

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6.6.5 Power Distribution

622 A-PHY Links may include an optional power feed established between a PSE and PD using the same Cable
623 TLIS as the data and control streams. Any other power distribution considerations beyond what is included
624 in this section are implementation specific.
6.6.5.1 DC Requirements
625 DC Requirements are presented in Table 20.
626 A PD can draw PPD power from any A-PHY Link.
627 The voltage at the output of PSE should be VPSEOUT.
628 The TLIS shall be able to support ITLIS current sourced to a PD from a PSE.
629 The total DC loop resistance should be RLOOP so that the maximum DC voltage drop is limited by
630 PPD,Max/VPSEOUT,Min * RLOOP,Max.
631 Table 20 DC Requirements
Parameter Description Min Typ Max Units
PPD PD drawn power – – 6 W
VPSEOUT PSE output voltage 8 12 13 V
ITLIS TLIS current capability 0.75 – – A
RLOOP DC loop resistance – – 4 Ω

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6.6.5.2 AC Requirements
632 Due to switching activity of powered devices and inherent noise in other elements of the power feed, the
633 power signal will exhibit a multi-tone noise profile. A Composite Power Ripple voltage is obtained at the
634 output of a filter with gain function as per Table 21.
635 Table 21 Power Ripple Gain
Frequency Power Ripple Gain

(MHz) (dB)
f ≤ 0.01 −20
0.01 < f ≤ 0.1 20 * log10( f/0.1 )
0.1 < f ≤ 4 0
4 < f ≤ 400 20 * log10( f/4 )
400 < f ≤ 6000 40
636 The Power Ripple gain function is graphically shown in Figure 20.
50
40
30
20
Gain (dB)
10
-10
-20
-30
0.01 0.1 1 10 100 1000 10000
Frequency (MHz)
Power Ripple Gain

637
Figure 20 Power Ripple Gain Function
638 To avoid interfering with the normal operation of the A-PHY Link, the Composite Power Ripple voltage shall
639 not exceed a peak-peak value of 100 mVpp.

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6.6.5.3 Power Over Coax

640 A typical A-PHY Power Over Coax (POC) configuration is illustrated in Figure 21 with recommended
641 parameter values shown in Table 22.
642 If the power feed is not required, then the PSE, PD, and inductive element L should be removed.
End Node e.g. Camera End Node e.g. ECU

Downstream
VOUT1, VOUT2, ... Power PSE VIN
PD
Upstream L
L
C C
Dp Dp
A-PHY
TLIS (Coax)
A-PHY
Source Z0 R R Z0
Dn Dn Sink
GND1 C/2 C/2 GND2

GND 1 GND2
643
Figure 21 Power Over Coax (PoC) Configuration
644 Both End Nodes may share the same ground reference however, due to return currents and non-negligible
645 Coax shield resistance, different ground potentials are experienced by the A-PHY transceivers. The maximum
646 Ground Voltage Offset is defined in Section 6.6.6.
647 Table 22 Power Over Coax (PoC) Component Values
Component Min Typ Max Comment
R – 50 Ω – Load balancing on Dn line.
AC coupling capacitors. C/2 is the equivalent of the
C 10 nF – 100 nF
two C capacitors in series on Dp line.
Ideal inductor is shown in the diagram. Actual
circuit may be more complex and include inductors,
L 10 µH – 100 µH
ferrite beads and parallel resistors to comply with
End Node return loss limits.
648 The tolerance of the different parameters shall be such that ENIS limits in Section 6.6.3 can be met.

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6.6.5.4 Power Over Differential Line

649 A typical A-PHY Power over Differential Line (PoDL) configuration is illustrated in Figure 22 with
650 recommended parameter values shown in Table 23.
651 If the power feed is not required, then the PSE, PD, and inductive element L should be removed.
End Node e.g. Camera End Node e.g. ECU

Downstream
VOUT1, VOUT2, ...
Power PSE VIN
PD
Upstream
L L
L L
C C
Dp Dp
A-PHY A-PHY
Source Z0 Z0 TLIS (SDP) Z0 Z0
Dn Dn Sink
GND1 C C GND2
GND 1 GND2
652
Figure 22 Power Over Differential Line (PoDL) Configuration
653 Both End Nodes may share the same ground reference however, due to return currents and non-negligible
654 SDP shield resistance, different ground potentials are experienced by the A-PHY transceivers. The maximum
655 Ground Voltage Offset is defined in Section 6.6.6.
656 Table 23 Power Over Differential Line (PoDL) Component Values
Component Min Typ Max Comment
C 10 nF – 100 nF AC coupling capacitors.
Ideal inductor is shown in the diagram. Actual circuit
may be more complex and include inductors, ferrite
L 10 µH – 100 µH
beads and parallel resistors to comply with End
Node return loss limits.
657 The tolerance of the different parameters shall be such that ENIS limits in Section 6.6.3 can be met.
6.6.6 Ground Voltage Offset
658 The Ground Voltage Offset VGNDOFF is defined as the voltage difference of the ground potentials of the End
659 Nodes in an A-PHY Link (i.e., GND1 and GND2 in Figure 21 and Figure 22). A-PHY End Nodes shall be
660 fully operational for VGNDOFF within and including the limits of ±1.0 V.

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7 EMC Environmental Conditions

661 A-PHY is specified to provide high levels of electromagnetic immunity while operating over the challenging
662 channels as defined in Section 6.
663 Key environmental stresses include:
664 • 300 V/m RF Ingress at Multi-GHz
665 • 200 mA BCI (Bulk Current Injection)
666 • Large electrical transients, both in amplitude and in frequency
7.1 RF Ingress
667 RF Ingress is the radiated electromagnetic immunity model based on the ALSE method (ISO 11452-2
668 [ISO03]), using multiple modulation schemes (i.e., CW, AM, PM; see Figure 23) testing instant attacks over
669 15 m cable.
Continuous Wave
(CW)
Pulse
Modulation
Amplitude
Modulation
670
Figure 23 Examples of Applicable Pulses
671 A-PHY shall support two RF Ingress noise limits, inserted at TPA/TPB on the data line, one per profile:
672 • Profile 1: 5 mV Peak up to 6 GHz, scaled up according to the per-frequency ENIS Insertion Loss
673 (IL) as specified in Section 6.6.3.2
674 • Profile 2: 40 mV Peak up to 6 GHz, scaled up according to the per-frequency ENIS Insertion Loss
675 (IL) as specified in Section 6.6.3.2

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7.2 Bulk Current Injection (BCI)

676 BCI is the conducted electromagnetic immunity model based on ISO 11452-4 [ISO03], using multiple
677 modulation schemes (i.e., CW and AM; see Figure 23) testing instant attacks over 15 m cable.
678 A-PHY shall support two BCI noise limits, inserted at TPA/TPB on the data line, one per profile:
679 • Profile 1: 21 mV Peak up to 400 MHz, scaled up according to the per-frequency ENIS Insertion
680 Loss (IL) as specified in Section 6.6.3.2
681 • Profile 2: 40 mV Peak up to 400 MHz, scaled up according to the per-frequency ENIS Insertion
682 Loss (IL) as specified in Section 6.6.3.2
7.3 Fast Transient

683 Fast Transient is the transient immunity to fast and slow pulses based on ISO7637-2/3 [ISO02], with
684 modifications attributed to various OEM inputs to extend pulse frequency up to 40 MHz using crosstalk from
685 power cable transients into the data line.
686 A-PHY shall support two Fast Transient noise limits, inserted at TPA/TPB on the data line, one per profile:
687 • Profile 1: 15 mV < |Peak| < 20 mV for 150 ns up to 40 MHz fundamental pulse frequency
688 • Profile 2: 15 mV < |Peak| < 150 mV for 150 ns up to 40 MHz fundamental pulse frequency
nS
689
Figure 24 P2 Decaying Sawtooth Model at 40 MHz / 4 nS Tr / 150 mV to 15 mV in 150 nS

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7.4 Alien Cable Bundle Max PSD Level

690 A-PHY shall tolerate Alien-Cable-Bundle-related Xtalk broadband noise, inserted at TPA/TPB, with
691 maximum PSD as specified in Table 24 and as shown in Figure 25.
692 Table 24 Alien Cable Bundle Upper PSD Limit
Frequency Upper PSD Limit
(MHz) (dBm/Hz)
0.2 ≤ f ≤ 20 −138
20 < f ≤ 500 -138 - 20.3871 * log10(f/20)
500 < f ≤ 4000 -166.5 + 18.1322 * log10(f/500)
693
Figure 25 Alien Bundle PSD Limit Line

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7.5 Car Noise (PSD)

694 The “Car Noise” Power Spectral Density (PSD) is assumed not to exceed the limits shown in Table 25.
695 Table 25 Car Noise PSD Limits
Frequency PSD
(MHz) (dBm / Hz)
f ≤ 10 −130
10 < f ≤ 100 −140
100 < f ≤ 4000 −160
4000 < f ≤ 6000 −150

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8 PHY Layer
8.1 Architecture
8.1.1 High Level Structure
696 The A-PHY has unified architecture to support both Profile 1 (P1) and Profile 2 (P2).
8.1.1.1 Single-Lane Highly Asymmetric
A-PHY - Source A-PHY - Sink
Link Layer Link Layer
RTS RTS
PAM-X 8b10b PAM-X 8b10b

PCS PCS PCS PCS
Downlink Downlink Downlink Downlink

Uplink Uplink
PAM-X NRZ PAM-X NRZ
PMD PMD
PMD PMD PMD PMD
697
Figure 26 A-PHY Single Lane Highly Asymmetric Unified Architecture
698 • For G1–G5 Uplink, both the P1 Port and the P2 Port use the same 8B/10B PCS, and the Uplink
699 PMD
700 • For G1 & G2 Downlink, both the P1 Port and the P2 Port (when PORT_CONFIG.GL3P2OPT=0)
701 use the same 8B/10B PCS, and the NRZ PMD
702 • For G1–G3, the P1 Port implements RTS-Bypass
703 • For G1–G5, the P2 Port implements RTS
704 The RTS Sub-Layer handles the PHY related fields of the A-Packet and specifies the retransmission process
705 for A-Packets that are erroneous or that are not received (see Section 8.2).
706 The Physical Coding Sub-Layer (PCS) specifies the conversion of Data Link Layer A-Packets into PHY
707 Symbols. For P2, PCS also handles the JITC Re-Training (see Section 8.3).
708 The PMD Sub-Layer defines the electrical specifications and the physical medium (see Section 9).

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8.1.1.2 Dual Downlink Lane Highly Asymmetric Q-Port
RTS RTS
Dual Lane PAM-X Dual Lane PAM-X

8b10b PCS 8b10b PCS
Lane #0 PCS Lane #1 Lane #0 PCS Lane #1
Downlink Downlink Uplink Downlink Downlink Uplink

PAM-X PAM-X PMD PAM-X PAM-X PMD
PMD PMD PMD PMD
Pair #0 Pair #1 [Pair #0] [Pair #0] [Pair #1] Pair #0
709
Figure 27 A-PHY Dual Lane Downlink Highly Asymmetric Q-Port Architecture
710 Note:
711 • [Pair #x] indicates that the Sink/Source side shall resolve inter-pair swap, if one exists.
8.1.1.3 Asymmetric Q-Port
Link Layer
Link Layer
RTS RTS
PAM-X PCS 8B/10B PCS PAM-X PCS 8B/10B PCS
Downlink Reverse Downlink Reverse

PAM-X Uplink Downlink PAM-X Uplink Downlink
PMD PMD NRZ PMD PMD PMD NRZ PMD
Pair #0 Pair #0 Pair #1 [Pair #0] [Pair #0] [Pair #1]
712
Figure 28 A-PHY Asymmetric Q-Port Architecture

713 Note:
714 [Pair #x] indicates that the Sink side shall resolve inter-pair swap, if one exists.

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8.1.1.4 Symmetric Q-Port
RTS RTS
PAM-X PCS 8B10B PCS PAM-X PCS PAM-X PCS 8B10B PCS PAM-X PCS
Downlink Reverse Downlink Reverse

PAM-X Uplink Downlink PAM-X Uplink Downlink
PMD PMD PAM-X PMD PMD PMD PAM-X PMD
Pair #0 Pair #0 Pair #1 [Pair #0] [Pair #0] [Pair #1]
715
Figure 29 A-PHY Symmetric Q-Port Architecture

716 Note:
717 [Pair #x] indicates that the Sink side shall resolve inter-pair swap, if one exists.

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8.1.2 Port Specification Generalization

718 The A-PHY Port specification is generalized to define a Port that can optionally operate using multiple
719 Symbol Rates (GBaud).
720 An A-PHY Port shall be preconfigured to operate using one of the following Symbol Rates: 1 Gbaud,
721 2 GBaud, 4 GBaud, or 8 GBaud.
722 The A-PHY Port specification is generalized to specify a Port that can optionally operate using multiple
723 multi-level modulations.
724 An A-PHY Port working in PAM-X shall be preconfigured to operate in a specific maximum PAM16
725 Sub-Constellation (denoted as sCMax) from: { sC1616, sC816, sC416 } (see Section 8.3.1.1), as defined in
726 Table 2.
8.1.3 Primary-Secondary Clocking Schemes
727 A-PHY implements a Primary-Secondary clocking scheme.
728 A Source Port shall act as the Primary Clock, and a Sink Port shall act as the Secondary Clock:
729 • A Source Port shall transmit using a Downlink symbol rate derived from its local reference clock.
730 • A Sink Port shall transmit using an Uplink symbol rate derived from the recovered Downlink symbol
731 rate, locally generated by its receiver.
8.1.4 PHY Layer Implementation Guidelines
8.1.4.1 A-PHY P1 G1/G2 Architecture
732 The P1 G1/G2 architecture is shown in Figure 30, and is based on the following main blocks:
733 • RTS Bypass (Retransmission Bypass, see Section 8.2.8)
734 • 8B/10B PCS (Physical Coding Sub-Layer, see Section 8.3.1.9)
735 • PMD (Physical Media Dependent, see Section 9)

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Source Sink
RTS Bypass RTS Bypass RTS Bypass RTS Bypass
PMD s Reception PMD s Reception

Quality Quality
A-Packet A-Packet A-Packet A-Packet
Link Startup Link Startup

Encapsulation Decapsulation Decapsulation Encapsulation
InTrain/InIdle/ InTrain/InIdle/
Byte Stream Controller InNormal Byte Stream Controller Byte Stream Controller InNormal Byte Stream Controller
[Local / Remote] [Local / Remote]
data/control byte data/control byte data/control byte data/control byte
B[7:0] B[7:0] B[7:0] B[7:0]
Scrambler Descrambler descrambler Scrambler

Enable K-Sequence K-Sequence Enable
K-Sequences S[7:0] Detected S[7:0] Detected S[7:0] K-Sequences S[7:0]
Control Mark Control Mark Control Mark Control Mark
CM CM CM CM
Scrambled data/control byte Scrambled data/control byte Scrambled data/control byte Scrambled data/control byte
SB[7:0] SB[7:0] SB[7:0] SB[7:0]
K-Reflection
8b10b encoder 8b10b Decoder 8b10b decoder 8b10b encoder
10b symbol 10b symbol 10b symbol 10b symbol
10b Symbols NRZ to 10b NRZ to 10b 10b Symbols

to NRZ Symbols Symbols to NRZ
736
Figure 30 A-PHY P1 G1/G2 Architecture

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8.1.4.2 A-PHY P2 G1/G2 Architecture

737 The P2 G1/G2 architecture is shown in Figure 31, and is based on the following main blocks:
738 • RTS for Downlink and Uplink (see Section 8.2)
739 • 8B/10B PCS. No Re-Training is used with 8B/10B (see Section 8.3.1.9)
740 • PMD (see Section 9)
741 Note:
742 This architecture also applies to A-PHY Devices supporting optional PAM4 in G1 and G2, when configured to operate in NRZ8B10B.
Source Sink
Ret. Ret.
Ret. Req Req
Ret.
Requests Requests Ret.
Ret.
Local Request Req Remote Request Req
RTS Ret. Remote Request Manager RTS RTS Ret.
Local Request Generator RTS
Generator Generator
Ack Ack
PMD s Reception PMD s Reception

Quality Ret. Ret. Quality Ret. Ret.
Req Ack Req Ack
Link Startup Link Startup
Encapsulation Uplink Request Extraction Decapsulation Decapsulation Uplink Request Insertion Encapsulation
InTrain/InIdle/ InTrain/InIdle/
Byte Stream Controller InNormal Byte Stream Controller Byte Stream Controller InNormal Byte Stream Controller
[Local / Remote] [Local / Remote]
data/control byte data/control byte data/control byte data/control byte
B[7:0] B[7:0] B[7:0] B[7:0]
Scrambler Descrambler descrambler Scrambler

Enable K-Sequence K-Sequence Enable
K-Sequences S[7:0] Detected S[7:0] Detected S[7:0] K-Sequences S[7:0]
Control Mark Control Mark Control Mark Control Mark
CM CM CM CM
Scrambled data/control byte Scrambled data/control byte Scrambled data/control byte Scrambled data/control byte
SB[7:0] SB[7:0] SB[7:0] SB[7:0]
K-Reflection
8b10b encoder 8b10b Decoder 8b10b decoder 8b10b encoder
10b symbol 10b symbol 10b symbol 10b symbol
10b Symbols NRZ to 10b NRZ to 10b 10b Symbols

to NRZ Symbols Symbols to NRZ
743
Figure 31 A-PHY P2 G1/G2 Architecture

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8.1.4.3 A-PHY PAM-X Single-Lane Architecture

744 ThePAM-X single Lane architecture is shown in Figure 32, and is based on the following main blocks:
745 • Uplink:
746 • RTS: RTS requests are sent over the Downlink, no Acks are used (see Section 8.2)
747 • 8B/10B PCS: No Re-Training is used with 8B/10B (Section 8.3.1.9)
748 • Downlink:
749 • RTS: RTS requests and Acks are sent over the Uplink (see Section 8.2)
750 • PAM-X PCS: Re-Train/sCMax requests are sent over the Uplink (see Section 8.3.1)
Source Ret.
Requests Sink Ret.
Requests
Re-Train_EN Ret. Re-Train_REQ/SCMax_REQ

Ret. Requests
Requests
sCMax sCMax/2_EN Remote
Local Request Remote Request Local Request
RTS Ret.
Manager
RTS Request RTS Ret.
Generator
RTS
Generator Req Req
Manager
Ret. Ret.
Ack Ack
A-Packet A-Packet
sCMax Re-Train
Req Req
sCMax Re-Train
Req Req Ret.
Req
Ret. Ret. Ret.
A-Packet
Req Ack Ack A-Packet
Re-Train_EN
Re-Train Packet to Token sCxx_Header Uplink PMD s Re-Train Token to Packet sCxx_Header Downlink PMD s
Reception Quality Reception Quality
Token Type
Token Type
Token Data
Token Data
IDLE/ISS
Downlink PMD s
Link Startup Uplink Request Extraction Decapsulation Reception Quality

Link Startup InTrain/InIdle/
Uplink Request insertion Encapsulation
Ret. InNormal
InTrain/InIdle/ Byte Stream Controller Requests Byte Stream Controller

InNormal / DHA DHA
[Local / Remote] data/control byte data/control byte
Token Type
Token Data
B[7:0] B[7:0]
IDLE/ISS IDLE/ISS
Mode Mode
Descrambler Scrambler
S[7:0] S[7:0]
Normal_EN K-Sequence Enable
Detected K-Sequences
Control Mark Control Mark
Training_EN
Training_EN
CM CM
Token Type Token Data (TD) Token Type Token Data (TD)
Scrambled data/control byte Scrambled data/control byte
• sC16/8/4/2 When type is IDLE/ISS/EOI, SB[7:0] • sC16/8/4/2 When type is IDLE/ISS/EOI, SB[7:0]
• IDLE/ISS/EOI Data is ignored... • IDLE/ISS/EOI Data is ignored...
Scrambler Descrambler
K-Reflection
8b10b Decoder 8b10b Encoder
Lane 0 Lane 0
Scrambled Scrambled
10b symbol 10b symbol
sCxx bits for one sCxx bits for one
symbol symbol
NRZ to 10b 10b to NRZ

Bits to
Symbols Symbol to bit Symbols
Symbol
752
Figure 32 A-PHY P2 G3-G5 Single Lane Architecture
753 For C-Ports and C-Ports supporting G3-G5, PAM-X PCS/PMD shall be implemented. 8B/10B PCS/NRZ-PMD shall also be implemented on the Downlink
754 direction, in order to support interoperability at G1/G2.
755 The P2 PAM-X architecture is applied to G3-G5 and to G1-G2 when the PAM4 option is selected for those Gears.

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8.1.4.4 A-PHY G3–G5 Dual Lane Downlink Highly Asymmetric Architecture

756 The G3–G5 Dual Lane Downlink architecture is shown in Figure 32, and is based on the following main blocks:
757 • Uplink:
760 • Downlink:
Source SINK
Retransmission REQ
Local Retransmission REQ
Remote
Retransmission REQ Retransmission REQ
Request Request
Manager Manager
A-Packet
Retransmission ACK Retransmission REQ Retransmission ACK
sCMax TX Remote RX RX Local TX
Retransmission ACK
RTS Request RTS RTS Request RTS
Manager Manager
A-Packet
sCMax/2_EN
Re-Train REQ RE-TRAIN ACTIVE
Request sCMax REQ Re-Train Request Re-Train REQ (DRU) Re-Train Re-Train REQ (DRU)
Insertion IDLE/ISS Manager Extraction sCMax REQ (DRU) Manager sCMax REQ (DRU)
RE-TRAIN ACTIVE
A-Packet
A-Packet
A-Packet A-Packet
Retransmission REQ
Retransmission ACK
SCxx Uplink PMD s SCxx Downlink PMD s
Packet To Token Packet To Token
Header Reception Quality Header Reception Quality
Re-Train REQ
sCMax REQ
Token Data
Token Type
InTrain/InIdle/
Uplink Request Extraction Decapsulation Uplink Request Insertion Encapsulation
InNormal
IDLE/ISS
Link Link
BYTE Stream Controller BYTE Stream Controller
StartUp StartUp DHA
IDLE/ISS
MODE InTrain/InIdle/ MODE
Data/Control
InNormal / DHA
Data/Control
Token Type
Token Type
Token Data
Token Data
Byte/s
Byte/s
[Local / Remote]
K-Sequence Detected
K-Sequence Detected
Control Mark CM
Control Mark CM
NORMAL_EN Descrambler Scrambler
Scrambled data/
Token Type
Token Type
Token Type
Token Data
Token Data
control byte/s
Scrambled data/
• sC16/8/4/2 Token Type

control byte/s
Token Data (TD) Token Data (TD)
• IDLE/ISS/EOI When type is IDLE/ISS/EOI, • sC16/8/4/2 When type is IDLE/ISS/EOI,
Data is ignored... • IDLE/ISS/EOI Data is ignored...
TRAINING_EN
TRAINING_EN
Scrambler 8b10b Decoder/s Descrambler 8b10b Encoder/s

K Refelections
LANE 0 LANE 1 LANE 0 LANE 1
SCxx
SCxx
SCxx
SCxx
Scrambled
Scrambled bits for one
bits for one 10b symbol/s symbol
symbol
10b Symbol/S
Bits to Bits to NRZ/PAM4 to Symbol to Symbol to
to NRZ/PAM4
Symbol Symbol 10b Symbol/s Bit Bit
764
Figure 33 A-PHY P2 G3-G5 Dual Lane Downlink Highly Asymmetric Architecture
765 For Q-Ports supporting G3-G5, Dual Lane Downlink Highly Asymmetric, a Dual Lane PAM-X PCS/PMD shall be implemented.
766 Note:
767 [Pair #x] indicates that the Sink/Source side shall resolve inter-pair swap, if it exists.

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8.1.4.5 A-PHY G3–G5 A-Symmetric Q-Port Architecture

768 The G3–G5 A-Symmetric Q-Port Architecture is shown in Figure 34 and is based on the following main blocks:
769 • Reverse Downlink:
773 • Downlink:
Source SINK
Retransmission ACQ Retransmission ACQ Retransmission ACQ Retransmission ACQ
Local Remote
Retransmission REQ Retransmission REQ Retransmission REQ Retransmission REQ
Request Request
Manager Manager
Retransmission REQ
A-Packet
Retransmission ACK Retransmission REQ Retransmission REQ Retransmission REQ
sCMax TX Remote RX RX Local TX
Retransmission ACK Retransmission ACK Retransmission ACK
Manager Manager
A-Packet
sCMax/2_EN
A-Packet A-Packet A-Packet
Request Re-Train sCMax REQ Request Request Re-Train Re-Train REQ Request
Insertion IDLE/ISS Manager Re-Train REQ
Extraction Extraction Manager sCMax REQ Insertion
RE-TRAIN ACTIVE
A-Packet A-Packet
A-Packet
Reverse Downlink
A-Packet
SCxx SCxx Downlink PMD s
Header
Packet To Token PMD s
Header
Packet To Token Reception Quality
Reception Quality
Token Data
Token Type
InTrain/InIdle/
Decapsulation Encapsulation
InNormal
IDLE/ISS
Link BYTE Stream Controller Link
BYTE Stream Controller
StartUp StartUp DHA
MODE InTrain/InIdle/ MODE
Data/Control
InNormal / DHA
Data/Control
IDLE/ISS
Token Type
Token Type
Token Data
Token Data
Byte/s
Byte/s
[Local / Remote]
K-Sequence Detected
K-Sequence Detected
Control Mark CM
Control Mark CM
NORMAL_EN Descrambler Scrambler
Scrambled data/
Token Type
Token Type
Token Type
Token Data
Token Data
control byte/s
Scrambled data/
• sC16/8/4/2 Token Type

control byte/s
Token Data (TD) Token Data (TD)

• IDLE/ISS/EOI When type is IDLE/ISS/EOI, • sC16/8/4/2 When type is IDLE/ISS/EOI,
Data is ignored... • IDLE/ISS/EOI Data is ignored...
TRAINING_EN
TRAINING_EN
Scrambler 8b10b Decoder/s Descrambler 8b10b Encoder/s

K Refelections
LANE 0 LANE 0
SCxx
Scrambled Scrambled
SCxx
bits for one bits for one
symbol 10b symbol/s symbol
10b Symbol/S
Bits to NRZ/PAM4 to Symbol to
to NRZ/PAM4
Symbol 10b Symbol/s Bit
777
Figure 34 A-PHY G3–G5 A-Symmetric Q-Port Architecture

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8.1.4.6 A-PHY G3–G5 Symmetric Q-Port Architecture

778 The G3–G5 Symmetric Q-Port Architecture is shown in Figure 35 and is based on the following main blocks:
779 • Reverse Downlink:
783 • Downlink:
Source SINK
Retransmission ACK Retransmission ACK Retransmission ACK Retransmission ACK
Local Local
Retransmission REQ Retransmission REQ Retransmission REQ Retransmission REQ
Request Request
Manager Manager

Retransmission ACK Retransmission REQ Retransmission ACK
TX Remote RX RX Remote TX
sCMax Retransmission ACK sCMax
Manager Retransmission REQ
Manager
Retransmission ACK
sCMax/2_EN sCMax/2_EN
Re-Train REQ
Request sCMax REQ Re-Train Request Request Re-Train sCMax REQ Request
Insertion IDLE/ISS Manager sCMax REQ Extraction Extraction sCMax REQ Manager IDLE/ISS Insertion
RE-TRAIN ACTIVE RE-TRAIN ACTIVE
SCxx Uplink PMD s SCxx SCxx Uplink PMD s SCxx

Header
Packet To Token Reception Quality Header
Packet To Token Packet To Token Header Reception Quality
Packet To Token Header
Token Data
Token Data
Token Type
Token Type
Link IDLE/ISS IDLE/ISS Link
StartUp StartUp IDLE/ISS
MODE MODE
IDLE/ISS
Token Type
Token Type
Token Type
Token Type
Token Data
Token Data
Token Data
NORMAL_EN Token Data NORMAL_EN
Token Type
Token Type
Token Type
Token Type
Token Type
Token Data
Token Data
Token Data
Token Data
• sC16/8/4/2 Token Data (TD)

• IDLE/ISS/EOI When type is IDLE/ISS/EOI,
Data is ignored...
TRAINING_EN TRAINING_EN TRAINING_EN TRAINING_EN
Scrambler Descrambler Descrambler Scrambler

K Refelections K Refelections
LANE 0 LANE 0 LANE 0
SCxx
SCxx
Scrambled Scrambled Scrambled Scrambled
SCxx
SCxx
bits for one bits for one bits for one bits for one
symbol symbol symbol symbol
Bits to Symbol to Symbol to Bits to

Symbol Bit Bit Symbol
787
Figure 35 A-PHY G3–G5 Symmetric Q-Port Architecture

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8.1.5 PHY-Related A-Packet Fields

788 The A-Packet format is defined in Section 11.2 and Figure 102.
789 The following A-Packet fields are modified (i.e., are used differently) by the PHY:
790 A-Packet Header:
791 • Link’s PHY1: SCI (2-bit sub-field in Service Descriptor field)
792 • Link’s PHY2: TX-Delay: Delay Value (7-bit field) and Original indication (1-bit field)
793 • Link’s PHY3: Message Counter (8-bit field)
794 • A-Header CRC (8-bit field)
795 A-Packet Tail:
796 • A-Payload CRC-32 (32-bit field)
797 The rest of the A-Packet fields are not modified by the PHY layer.
798 The PHY layer modifies the fields described in Table 26.
799 Table 26 A-Packet Fields Modified by PHY Layer
Field Sub-Field Bits Description
Link’s PHY1: 2 Payload Data Sub Constellation Indication

SCI at PHY1 b1:b0 See Section 8.2.1 (PAM-X) or Section 8.2.8 (NRZ)
Link’s PHY2: Delay 7

Conveys the TX_Delay_Val, as defined in
TX Delay & Value at b6:b0
Section 8.2.5.1 (P2) or Section 8.2.8 (P1)
Original Indication PHY2
Original 1 Conveys an indication whether this A-Packet is an

Indication b7 Original or a Retransmitted A-Packet,
bit at PHY2 per Section 8.2.5.2 (P2) or Section 8.2.8 (P1)
Link’s PHY3: Message 8

Message Counter Counter b7:b0 Conveys the message counter, per Section 8.2.5.2
(MC)
A-Header CRC-8 8 See Section 8.2.5.3

b7:b0
A-Payload CRC-32 32 See Section 8.2.5.4

b31:b0

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8.2 RTS
800 An A-PHY Profile 2 PHY Port utilizes a Dynamically modulated, Time Bounded, Local Retransmission
801 mechanism (RTS). See Figure 36.
802 The RTS is:
803 • Dynamically Modulated: When sent over PAM-X, retransmitted packets utilize a better error
804 resistant payload sub-Constellation than the originally transmitted packets.
805 • Time Bounded: Retransmission is attempted as long as the total ‘Overall Delay’ that an A-Packet
806 suffers at the A-PHY transmitter, over the interconnect and at the A-PHY receiver, is limited
807 (see Section 8.2.4).
808 • Local: The RTS mechanism is local to a single-hop A-PHY, such that the Link Layer is not aware of
809 it.
Protocol CSI/DSI/I3C Protocol

Max Application BW (net) is 90% of PHY Rate

10-19 Post-RTS PER
Overall Delay
RX Delay
TX Delay
RTS RTS
PCS Interconnect Delay PCS
PMD Original/Retransmitted Packets PMD

-3
< 10 Pre-RTS PER
<10-6 Pre-RTS SER
TX PHY RX PHY
Overall Delay = TX Delay + Interconnect Delay + RX Delay
810
Figure 36 Dynamically Modulated, Time Bounded, Local Retransmission
811 Note:
812 1. The PER numbers in Figure 36 refer to G3–5 implementation.
813 2. For G1–2 the Pre-RTS PER is 10-9 and the Post-RTS PER is 10-18.

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814 The RTS operates over both the 8B/10B PCS (block diagram in Figure 37) and the PAM-X PCS (block
815 diagram in Figure 38).
Link Layer
Original
Ready
A-Packet
Pacer TX RTS
at 97.5%
MC Original
Ready A-Packet
Ack (over Downlink only) Active MC

Window Handler
Original
A-Packet
Remote Request Fill-up Level

TX RTS Buffer
Manager Rem-Ret-Request
Retransmitted Original
A-Packet A-Packet
Scheduler
A-Packet
Update
TX Delay Field
A-Packet
Update Header
CRC and CRC-32
A-Packet
8b10b
PCS
816
Figure 37 TX RTS Over 8B/10B PCS Block Diagram

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Link Layer
Original
Ready
A-Packet
Pacer TX RTS
At 96%
MC Original
Ready A-Packet
Ack Active MC
Window Handler
Original
A-Packet
Re-Train_EN Fill-up Level

Remote Request TX RTS Buffer
Manager
Rem-Ret-Request
Retransmitted Original
A-Packet A-Packet
Request
Generator
Request for Uplink
Retransmission
(G4/5 Only) Scheduler
A-Packet
sCMax/2_EN Update SCI and

TX Delay Fields
A-Packet
Update Header
CRC and CRC-32
A-Packet
PAM-X
PCS
817
Figure 38 TX RTS Over PAM-X PCS Block Diagram

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818 RTS utilizes the following procedure:

819 The TX RTS shall fetch for transmission A-Packets from the TX Data Link Layer using a 97.5% (when
820 operating over 8B/10B Downlink PCS) / 96% (when operating over PAM-X PCS) / 95% (when operating
821 over 8B/10B Uplink PCS), fully paced interface as specified in Section 8.2.6, and only when it has a valid
822 Message Counter (MC) available to assign per each fetched A-Packet as specified in Section 8.2.2.
823 • The TX RTS shall assign each A-Packet a data payload sub-Constellation by setting the SCI Header
824 field value, as specified in Section 8.2.1.
825 • The TX RTS shall assign each A-Packet a TX Delay Header field value, as specified in
826 Section 8.2.5.1.
827 • The TX RTS shall assign each A-Packet a Message Counter (MC) field as specified in
828 Section 8.2.5.2.
829 • The TX RTS shall compute and assign each A-Packet a Header CRC-8 field as specified in
830 Section 8.2.5.3 and a CRC-32 field as specified in Section 8.2.5.4.
831 • A-Packet retransmissions shall be triggered by retransmission requests sent by the receiving Port to
832 the transmitting Port as specified in Section 8.2.3.
833 • Upon reception of a valid retransmission request, the TX RTS shall retransmit the proper A-Packet/s
834 (carrying the requested MC/s) as specified in Section 8.2.3.2.
835 • While Re-Train_EN is set (see Figure 38 in Section 8.2), the TX RTS shall stop sending A-Packets
836 to the TX PCS. When Re-Train_EN is subsequentially cleared, the RTS shall not resume sending an
837 A-Packet which was interrupted, but rather shall send complete A-Packets.
838 The TX RTS shall store A-Packets, received from the Data Link Layer, for potential retransmissions, until
839 their MC is released as specified in Section 8.2.2.
840 The RX RTS shall try to recover bad CRC32 A-Packets and missing A-Packets using retransmission requests.
841 The RX RTS shall use a buffer (RX RTS Buffer) to store subsequent A-Packets received while the RX RTS
842 is still waiting for a retransmission to recover a previous erroneous or missing A-Packet. When such a
843 retransmitted A-Packet arrives, it shall be inserted to its proper location in the buffer, as indicated by its MC,
844 to maintain the A-Packets order.
845 A-PHY provides a fixed delay retransmission service (FixRD), aiming to implement retransmission while
846 introducing minimal Latency Variation. A-Packets which use the FixRD service indicated by their
847 Latency_QoS header sub-field set to one (1’b1) (see Table 80) and are called FD A-Packets.
848 The RX RTS shall forward all received, non-discarded, FD A-Packets (with good or bad CRC32), according
849 to their original order, to its Data Link Layer, only when their ‘Overall Delay’ (i.e., the sum of delays at the
850 TX, interconnect and RX) reaches ‘Max RTS Delay’ (see Section 8.2.4 and Section 8.2.2).
851 A-PHY provides a minimum delay retransmission service (MinRD), aiming to implement retransmission
852 while introducing minimal Latency. A-Packets which use the MinRD service indicated by their Latency_QoS
853 header sub-field cleared to zero (1’b0) (see Table 80) are called MD A-Packets.
854 The Receiver shall try to recover bad CRC32 MD A-Packets and missing A-Packets (which might be MD)
855 using retransmission requests.
856 The RX RTS shall forward good MD A-Packets to its Data Link Layer as soon as possible, without violating
857 the original MD A-Packet order. E.g., a good MD A-Packet shall wait until all preceding MD A-Packets have
858 been forwarded.
859 The RX RTS shall forward to its Data Link Layer any MD A-Packets (with good or bad CRC32), according
860 to their original order when one of these conditions are met:
861 • A-Packet ‘Overall Delay’ reaches ‘Max RTS Delay’ (see Section 8.2.4 and Section 8.2.2).
862 • A-Packet MC was released from the RX RTS MCW as specified in Section 8.2.2.
863 Note:
864 At the Receiver, when A-Packets are forwarded by the PHY to the local Link layer, the order is
865 separately maintained for FD A-Packets and MD A-Packets.

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8.2.1 PAM-X Payload Data Modulation Assignment by Source

866 The TX RTS shall assign each original A-Packet a proper SCI Header field value that indicates the A-Packet’s
867 payload data (and CRC-32) sub-constellation (see Section 8.1.5), based on the Link’s preconfigured sCMax
868 and the current sCMax/2_EN indication, as indicated by the Remote Request Manager (see the PCS block
869 diagram, Figure 47) and the EResistance_QoS Header sub-field bit value (see Table 27):
870 • When EResistance _QoS bit equals zero (‘0’) AND the current sCMax/2_EN is not set, the RTS
871 shall set the A-Packet’s SCI field value to indicate sCMax.
872 • When EResistance _QoS bit equals one (‘1’) OR the current sCMax/2_EN is set, the RTS shall set
873 the A-Packet’s SCI field value to indicate sCMax/2.
874 Table 27 Sub-Constellation Assignment for Original A-Packets
sCMax sCMax/2_EN EResistance _QoS Assigned sC
False sC1616
0
sC1616 True sC816
– 1 sC816
False sC816
0
sC816 True sC416
– 1 sC416
False sC416
0
sC416 True sC216
– 1 sC216
sC216 – – sC216
875 For Retransmitted A-Packets the RTS shall assign the sCMax/2 sub-Constellation.
876 For both Original and Retransmitted A-Packets, the RTS shall assign the sub-Constellation, just before
877 handing the A-Packet to the TX PCS (to properly take into account the current sCMax/2_EN indication),
878 using the SCI encoding shown in Table 28.
879 Table 28 SCI Code Per Assigned Payload Data Sub-Constellation
Assigned sC SCI[1:0]
sC1616 00
sC816 01
sC416 10
sC216 11
880 The Downlink Receiver shall discard good Header CRC-8 A-Packets with SCI code indicating sC216 on a
881 Link which uses sC416 as its header sub-constellation.
882 The Downlink Receiver shall decode all other, good Header CRC-8, A-Packets payload and CRC-32 tokens,
883 solely according to their Header’s SCI code (Note that this means that the Downlink Receiver shall properly
884 decode a good CRC, sC416 payload A-Packet on a Link with sCMax = sC1616).

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8.2.2 Active Message Counter Window

885 Message Counters (MC) use 8-bit values with wrap-around at 256 (i.e., 0 is the next MC value after MC
886 value 255).
887 Both TX and RX RTS shall maintain an Active Message Counter Window (Active MCW) of up to ‘Active
888 MCW Max Size’ consecutive (with wrap around) MCs.
889 For each A-Packet newly fetched from the Link Layer, the TX RTS shall assign an MC as specified in
890 Section 8.2.5.2 and shall set its Active MCW’s higher limit to that MC.
891 The TX RTS shall not fetch a new A-Packet from its Link Layer when its current Active MCW size has
892 already reached ‘Active MCW Max Size’.
893 TX RTS shall release an MC (called ‘this MC’ below) from its Active MCW:
894 • Either after ‘Max RTS Delay’ of storage time at the TX RTS buffer has passed
895 • Or when an ‘Ack’ message is received from the RX RTS for an MC ≥ ‘this MC’, per
896 Section 8.3.2.8.5.
897 When the TX RTS releases an MC from its Active MCW, it shall adjust its Active MCW’s lower limit
898 accordingly.
899 For each good CRC-32 Original A-Packet received, the RX RTS shall set its Active MCW’s higher limit to
900 that A-Packet MC.
901 The RX RTS shall release an MC (called ‘this MC’ below), from its Active MCW upon the occurrence of at
902 least one of the following conditions:
903 • ‘This MC’, is the “oldest” MC in the RX RTS Active MCW and its A-Packet was forwarded to the
904 Link Layer;
905 • And/or the RX RTS sent an ‘Ack’ for a MC ≥ ‘this MC’;
906 • And/or reception of a good CRC-32 Original A-Packet with MC value equal or larger than ‘this MC’
907 + ‘Active MCW Max Size’ with wrap around.
908 When the RX RTS releases an MC from its Active MCW, it shall adjust its Active MCW’s lower limit
909 accordingly.
910 The RX RTS shall discard Retransmitted A-Packet arriving with an MC value which is not in its Active MCW
911 The ‘Active MCW Max Size’ value for the Uplink RTS shall be 16. As a result, no more than 16 MCs are
912 still available for retransmission at any time.
913 The ‘Active MCW Max Size’ value for the Downlink RTS shall be 128. As a result, no more than 128 MCs
914 are still available for retransmission at any time.
Informative Implementation Note

915 Both the Downlink TX and the RX RTS may implement just 128 entries in the A-Packet descriptor array,
916 using the lower 7 bits of the MC value as the index to the proper descriptor entry.

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8.2.3 Retransmission Request / Ack Types

917 There are two types of Retransmission Requests, and one Ack Indication:
918 1. Single Retransmission Request: The Receiver requests the Retransmission of a single A-Packet,
919 that arrived with a bad CRC-32, or was missing and still was not recovered.
920 A Single Retransmission Request shall convey the MC value of the requested A-Packet as specified
921 in Section 8.3.2.8.3 when sent over the Uplink and as specified in Section 8.2.3.3 when sent over the
922 Downlink.
923 2. Retransmission Gap Request: The Receiver requests the retransmission of a missing range of
924 A-Packets.
925 A Retransmission Gap Request shall convey:
926 A. Last Matched MC: The MC value of the A-Packet immediately before the first missing
927 A-Packet in the missing A-Packet range
928 B. Post Gap MC: The MC value of the A-Packet immediately after the last missing A-Packet in
929 the missing A-Packet range. Note that the missing MC range could be as small as a single
930 missing MC value.
931 3. Ack Indication: The Receiver may indicate to the transmitter that all Active MCs up to and
932 including ‘this MC’ can be released, as Retransmissions are no longer needed for them. An Ack
933 Indication shall convey the ‘this MC’ value, per Section 8.3.2.8.5 on the Uplink. Ack Indications
934 shall not be sent over the Downlink.
935 Note that per Section 8.2, any FD A-Packets at the RX RTS whose MCs were released due to Ack
936 Indications that were sent still need to wait to reach their ‘Max RTS Delay’ (by contrast, MD
937 A-Packets are forwarded to the Link Layer as soon as their MC is released). If more than 32 FD
938 A-Packets with released MCs are waiting to be forwarded to the Link Layer, then the oldest MC may
939 be forwarded before its time.
Informative Note
940 Ack Indications may be needed in cases where large bursts of short Downlink A-Packets can consume more
941 than 128 MCs within a single ‘Max RTS Delay’ period. In such situations the transmitter cannot continue to
942 send A-Packets until either MCs are released by Ack indications sent by the Sink, or the ‘Max RTS Delay’
943 period passes. For End Node Sink ports, the incoming A-Packet length distribution is determined by the type
944 and the number of Adaptation Layers supported on that End Node. As high-throughput Adaptation Layers
945 such as CSI-2, DSI, and DP use maximum-sized A-Packets (in order to reduce framing overhead and improve
946 Link utilization), a typical End Node Sink would not need to implement Ack Indications. Sink Ports of
947 forwarding elements that are unable to accurately estimate the number of different incoming A-Packet
948 streams should consider implementing Ack Indication with proper FD A-Packet handling, as specified above.
8.2.3.1 Retransmission Request Triggering by the Receiver
949 Upon reception of an A-Packet with good Header CRC-8 and good CRC-32 fields, the Receiver:
950 • Shall store this A-Packet in its RX RTS Buffer associated with ‘this’ MC.
951 • Shall set this MC status to ‘Good’.
952 • If this A-Packet is non-retransmitted (Original) with non-matching MC value and with an ‘Overall
953 Delay’ that is still valid, then it shall generate a Retransmission Gap Request for the missing MC
954 values, with the ‘Last Matched MC’ field in the Request Packet equal to the ‘Last MC’, and with the
955 ‘Post Gap MC’ field equal to ‘this MC’ (see Section 8.2.3.3 and Section 8.3.2.8.4) and shall set the
956 status of each missing MC (all MC values, with wrap around, from ‘Last MC’ + 1 to ‘this MC’ – 1)
957 to ‘Missing’.
958 • If this A-Packet is non-retransmitted (Original), then it shall set ‘Last MC’ to ‘this’ MC.
959 Upon reception of a non-retransmitted (Original) A-Packet with good Header CRC-8, matching MC value
960 (value = ‘Last MC’ + 1 with wrap around), and a bad CRC-32 field, the Receiver:

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961 • Shall store this A-Packet in its RX RTS Buffer after setting its ‘Bad’ indication
962 (see Section 11.2.1.2.4).
963 • Shall set this MC status to ‘Bad CRC-32’.
964 • Shall set ‘Last MC’ to the value of ‘this’ MC.
965 • If the A-Packet still has a valid ‘Overall Delay’, then it shall generate a Single Retransmission
966 Request for that MC value (see Section 8.2.3 and Section 8.3.2.8.3).
967 The Receiver shall discard any original A-Packets received with both a bad CRC-32 and non-matching MC.
968 Upon reception of a retransmitted A-Packet with good Header CRC-8, MC value matching a currently ‘Bad
969 CRC-32/Missing’ MC, and a bad CRC-32 field value, the Downlink Receiver:
970 • Shall store this A-Packet in its RX RTS Buffer after setting its ‘Bad’ indication (Section 11.2.1.2.4)
971 • Shall set this MC status to ‘Bad CRC-32’.
972 • If the A-Packet still has a valid ‘Overall Delay’, and if the number of retransmission requests sent for
973 that MC is still below the ‘Max RTS Request Num’, then the Receiver shall generate an additional
974 retransmission request for that MC value (see Section 8.3.2.8.3).
975 The Receiver shall discard any retransmitted A-Packet with bad CRC-32 and any MC status other than ‘Bad
976 CRC-32 /Missing’ MC.
977 Upon detection of an MC with ‘Bad CRC-32/Missing’ status, for which a retransmission request has already
978 been sent, but no retransmitted A-Packet with good CRC-32 has been received yet, after the ‘Retransmission
979 Request Wait’ period, with a still-valid ‘Overall Delay’, and if the number of retransmission requests sent for
980 that MC is still below the ‘Max RTS Request Num’, and if the ‘Retransmission Request Wait’ period has
981 elapsed, then the Receiver shall generate an additional retransmission request for that MC value (see the
982 informative example below).
983 The Receiver shall support a ‘Max RTS Request Num’ value of at least 3.
Example: Recurrent, Unsatisfied Retransmission, Request Generation (Informative)

984 To efficiently identify unsatisfied retransmission requests in order to generate recurrent requests, the Receiver
985 may implement a ‘Request Timeout FIFO’. Each time the Receiver generates a retransmission request, other
986 than the last request allowed for ‘this’ MC, it can put an entry into the FIFO with the number of retransmission
987 requests for ‘this’ MC, the time of request + ‘Retransmission Request Wait’ period (the ‘Recurrent Request
988 Time’) and ‘this’ MC value.
989 At each cycle/s the Receiver examines only the oldest FIFO entry’s Recurrent Request Time, waiting until it
990 reached/passed, then removes this entry from the FIFO and examine its MC value. If this MC is still in the
991 ‘BAD CRC-32/Missing’ state, its number of retransmission requests is still as written in the entry, and its
992 ‘Overall Delay’ + ‘Min Link RTD’ is still ≤ ‘Max RTS Delay’, then the Receiver generates an additional
993 retransmission request for that MC value (which may result in inserting a new entry into the FIFO with a new
994 ‘Recurrent Request Time’ associated with the same MC).
8.2.3.2 Retransmission Request Handling at TX RTS
995 The TX RTS shall discard Retransmission Requests for MC values that are not in its current Active MCW.
996 When a Gap Retransmission Request is received for more than 32 MCs, only the 32 higher (i.e., most recent)
997 MC values shall be considered as valid requests (Gap Requests are always “First Time Requests”).
998 “First time Requests” shall be serviced by their arrival order
999 “Recurrent Requests” (second or third request for the same MC) shall also be serviced by their arrival order,
1000 but with higher priority than the “First time Requests”.
8.2.3.3 Format of Single/Gap Retransmission Request Sent Over Downlink
1001 In modes that use RTS over the Uplink, the Source shall send Single/Gap Retransmission Requests over the
1002 Downlink to signal the Sink to re-transmit a Single/Range-of-Missing A-Packet/s.

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1003 The Single/Gap Retransmission Requests shall use the A-Header fields settings shown in Table 29.
1004 Table 29 A-Packet Fields Modified by PHY Layer
Field Sub-Field [bits] Description
Adaptation Descriptor: Adaptation Type [3:0] 0
Link’s PHY1: SCI at PHY1 [1:0] When in G3: 11 (sC216)

When in G4 & G5: 10 (sC416)
Link’s PHY2: Delay Value at PHY2 [6:0] 0

TX Delay & Original Indication
Original Indication bit at PHY2 [7] 0
Link’s PHY3:
Message Counter (MC) [7:0] 0
Message Counter
Header CRC [7:0] See Section 8.2.5.3
CRC-32 [31:0] See Section 8.2.5.4
1005 The Single/Gap Retransmission Requests shall not be sent as part of the Active MCW (as in Section 8.2.2),
1006 as they shall always use MC = 0.
1007 On the Downlink TX RTS they are inserted by the (Local) Request Generator and the Scheduler, directly into
1008 the A-Packet stream after the TX RTS Buffer (see Figure 38), and at the Downlink RX RTS they are extracted
1009 into the Remote Request Manager from the A-Packet stream before the RX RTS Buffer.
1010 These Request A-Packets themselves shall not be re-transmitted at the TX and shall not generate RTS requests
1011 at the RX upon their reception.
1012 A Single/Gap Retransmission Request sent over the Downlink shall be discarded if its CRC-32 value is bad.
1013 The first Payload byte of a Single/Gap Retransmission Request sent over the Downlink shall use the same
1014 Control Byte format as specified for the Uplink requests (see Section 8.3.2.5.2), with CN1 and CN2 encoded
1015 per Table 52.

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1016 The Payload of a Single Retransmission Request, sent over the Downlink shall consist of:
1017 • A first Control Byte with Null CN1 and an RRS CN2
1018 • A Data Byte carrying the MC of the requested A-Packet to be re-transmitted over the Uplink
CN1: Null
A-Header [8-Bytes] MC CRC-32 [4-Bytes]
1019
CN2: RRS
Figure 39 Single Retransmission Request Sent Over Downlink
1020 The Payload of a Gap Retransmission Request sent over Downlink, shall consist of:
1021 • A first Control Byte with Null CN1 and a GRS CN2
1022 • A first Data Byte containing MC1, the ‘Last Matched MC’ per Section 8.2.3
1023 • A second Data Byte containing MC2, the ‘Post Gap MC’ per Section 8.2.3
CN1: Null
A-Header [8-Bytes] MC1 MC2 CRC-32 [4-Bytes]
1024
CN2: GRS
Figure 40 Gap Retransmission Request Sent Over Downlink

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8.2.4 Time Bounded RTS

1025 An A-Packet at the TX RTS module may experience a variable delay, denoted as ‘TX RTS Delay’, before
1026 being transmitted into the Link.
1027 ‘TX RTS Delay’ shall be measured as the time between the A-Packet’s start-of-reception by the TX RTS
1028 module, from the Data Link Layer, until the start-of-transmission-or-retransmission over the physical Link.
1029 The ‘Overall Delay’ per A-Packet is the sum of the delay at the Transmitter (as recorded in the TX Delay
1030 field in the A-Packet’s header, see Section 8.2.5.1), delay on the Cable (interconnect), and delay at the
1031 Receiver as estimated by the Receiver from the start-of-transmission-or-retransmission over the physical
1032 Link (the Receiver estimates the interconnect delay and adds to it the time period passed since the start-of
1033 reception for this A-Packet).
1034 ‘Max RTS Delay’ is the max value for ‘Overall Delay’ and ‘TX RTS Delay’.
1035 ‘Max RTS Delay’ shall be configured to the same value for both Link partners, based on link
1036 Downlink/Reverse-Downlink throughput.
1037 ‘Retransmission Request Wait’ is the minimum time the Downlink/Reverse-Downlink Receiver shall wait
1038 before issuing an additional retransmission request for the same packet (i.e., the same MC).
1039 The Receiver shall support the nominal Downlink/Reverse-Downlink ‘Max RTS Delay’ and ‘Retransmission
1040 Request Wait’ values given in Table 30.
1041 Table 30 Downlink/Reverse-Downlink Max RTS Delay & Retransmission Request Wait
Link Throughput Max RTS Delay Retransmission Request Wait

(Gbps) (nS) (nS)
2 12288 4096
4 12288 4096
8 10240 3413
12 8192 2730
16 6144 2048
1042 Note:
1043 In Dual Downlink mode, "Max RTS Delay" is the same as for 16 Gbps Link throughput.
1044 When RTS is used over the Uplink, ‘Max RTS Delay’ shall be equal to 16 µS and ‘Retransmission Request
1045 Wait’ shall be equal to 5.5 µS.

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8.2.5 A-Packet – PHY Related Header/Tail Modifications

1046 In addition to modifying the SCI field as specified in Section 8.2.1, the RTS module modifies the following
1047 A-Header/Tail fields:
1048 • Tx Delay (see Section 8.2.5.1)
1049 • Message Counter and Original indication bit (see Section 8.2.5.2)
1050 • Header CRC (CRC-8) (see Section 8.2.5.3)
1051 • A-Packet Tail CRC (CRC-32) (see Section 8.2.5.4)
8.2.5.1 Tx Delay
1052 Per each A-Packet transmission, the transmitter shall assign a 7-bit TX_Delay_Val and place it in the TX
1053 Delay A-Header field. The TX_Delay_Val shall contain the integer part of ‘TX RTS Delay’ (per
1054 Section 8.2.4) divided by ‘RTS Delay Unit’:
TX RTS Delay
1055 ⌊RTS Delay Unit⌋ (“floor” operation of the division result when both values are in nS).
1056 Since TX_Delay_Val is written into the header before several lower functions on the way to the actual first
1057 symbol transmission over the Link are executed with their associated delays (i.e., CRC-8/CRC-32
1058 computation, PCS operations, TX path to the AFE, etc.), the ‘TX RTS Delay’ value shall also take into
1059 account the additional fixed delay of these lower functions, based on the implementation.
1060 The transmitter shall not send an A-Packet when its ‘TX RTS Delay’ is equal or larger than ‘Max RTS Delay’.
1061 ‘RTS Delay Unit’ shall be configured to the same value for both Link partners, based on link
1062 Downlink/Reverse-Downlink throughput. Each A-PHY P2 Port shall support the nominal ‘RTS Delay Unit’
1063 values listed in Table 31.
1064 Table 31 Nominal Downlink/Reverse-Downlink RTS Delay Unit
Link Throughput RTS Delay Unit Nominal Max RTS Delay
(Gbps) (nS) (nominal RTS Delay Units)
2 128 96
4 128 96
8 128 80
12 64 128
16 64 96
1065 Note:
1066 In Dual Downlink mode, "RTS Delay Unit" and "Nominal Max RTS Delay" are the same as for
1067 16 Gbps Link throughput.
1068 When RTS is used over the Uplink, ‘RTS Delay Unit’ shall be equal to 128 nS.
8.2.5.2 Message Counter and Original Indication Bit

1069 For each A-Packet, the TX RTS shall assign an 8-bit Message Counter (MC) and place it in the Message
1070 Counter field, as specified in Section 11.2. New, original, A-Packets shall use MCs in sequential order with
1071 wrap-around (that is, MC value 255 is followed by MC value 0), and their Original Indication bit shall be set
1072 to one (‘1’). Re-transmitted A-Packets shall re-use their original MC, but shall have their Original Indication
1073 bit cleared to zero (‘0’).

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8.2.5.3 Header CRC (CRC-8)

1074 The Header CRC is an 8-bit CRC (CRC-8) calculated over the A-Packet Header (A-Header) fields (i.e., the
1075 A-Header fields from the Adaptation Type sub-field through the Payload Length field, inclusive, but not
1076 including the Header CRC field itself).
1077 The A-Header bits shall be fed into the CRC-8 calculator starting from the Adaptation Type sub-field’s LSB
1078 and ending with the Payload Length field’s MSB.
1079 The CRC-8 is calculated according to the bit-level diagram in Figure 41.
A-Header Bit
In
+ S0 + S1 S2 S3 S4 + S5 + S6 S7
1080
Figure 41 Header CRC (CRC-8) Bit Level Diagram
1081 Figure 41 can also be expressed as the polynomial:
1082 𝐺(𝑥) = 𝑋 8 + 𝑋 6 + 𝑋 5 + 𝑋 + 1
1083 Note:
1084 In the event of any difference in interpretation between the polynomial and the Figure, treat the Figure
1085 as correct.
1086 The CRC-8 states (S0 through S7) shall be zeroed prior to the start of each A-Header CRC-8 calculation.
1087 After the CRC-8 calculation is completed, all states (S0 through S7) shall be stored in the Header CRC field
1088 as shown in Figure 42.
LSB
S7 S6 S5 S4 S3 S2 S1 S0
1089
Header CRC Field Data
Figure 42 Header CRC Bit Assignment
1090 The Receiver shall discard any A-Packet received with a bad (i.e., incorrect) value in the Header CRC-8 field.
1091

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1092
8.2.5.4 A-Packet Tail CRC (CRC-32)

1093 The CRC-32 in the A-Packet Tail is a 32-bit CRC (CRC-32) calculated over all of the A-Packet’s bytes (i.e., from the first byte of the A-Header through the last
1094 byte of the A-Payload, inclusive), but not including the Header CRC (CRC-8) field.
1095 Per each byte, the bits shall be fed into the CRC-32 calculator, starting from its LSB to its MSB where the first bit inserted per new A-Packet shall be the A-Header’s
1096 Adaptation Type sub-field LSB and the last bit per A-Packet, fed into the CRC32 calculator, shall be the MSB of the last A-Payload byte.
1097 The CRC-32 is calculated according to the polynomial:
1098 𝑃 = 𝑥 32 + 𝑥 26 + 𝑥 23 + 𝑥 22 + 𝑥 16 + 𝑥 12 + 𝑥 11 + 𝑥 10 + 𝑥 8 + 𝑥 7 + 𝑥 5 + 𝑥 4 + 𝑥 2 + 𝑥 + 1
1099 See also the bit-level diagram in Figure 43.
S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16
DataIn S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15
1100
Figure 43 CRC-32 Calculation Bit Level Diagram
1101 The CRC-32 states (S0 through S31) shall be set to one before the CRC calculation starts, per each A-Packet.
1102 After the CRC-32 calculation is completed, all states (S0 through S31) shall be XORed with 1 (i.e., the complete CRC-32 value is XORed with a constant
1103 0xFFFFFFFF value) and then mapped into four bytes as shown in Figure 44.
MSB LSB MSB LSB MSB LSB MSB LSB
S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
Byte N Byte N+1 Byte N+2 Byte N+3

1104
Figure 44 CRC-32 Byte Mapping

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8.2.6 Fully Paced A-Packet Stream from TX Data Link Layer to TX RTS
1105 The TX RTS shall fetch A-Packets from the Data Link Layer at a Fully Paced Rate, ensuring that effective
1106 utilization of the Physical Link does not exceed 96%/97.5%/95% for PAM-x/NRZ/Uplink, respectively.
8.2.6.1 Max Net Link Rate for 8B/10B PCS
1107 The A-Packet format defines a maximum payload size of:
1108 • Downlink: 380 bytes
1109 • Uplink: 32 bytes
1110 • Double Rate Uplink (DRU): 76 bytes
1111 When operating over 8B/10B PCS, the additional overhead is:
1112 • 8-Byte A-Header
1113 • 4-Byte A-Tail (CRC-32)
1114 • At least 2 Bytes framing overhead (CM + CB) of 8B/10B PCS
1115 • All bytes are then subject to 8B/10B encoding
1116 P2 uses RTS which requires, over the 8B/10B PCS, at least 2.5% of the Phy Rate to be kept free for RTS. As
1117 a result, a maximum of 97.5% of the Phy Rate can be used for Original A-Packets flow. In order to unify the
1118 net application data rate per Gear for both profiles, P1 also uses the 97.5% pacing.
1119 • For Downlink the 8B/10B PCS Max Net Link Rate (using the maximum size A-Packet payload) is:
1120 0.975 * 380 * 8 / ((8+4+2+380) * 10) = 75% of Phy Rate

1121 • For Uplink the Max Net Link Rate (using the maximum size A-Packet payload) is:
1122 • For NRZ:
1123 0.95 * 32 * 8 / ((8+4+2+32) * 10) = 52.87% of Phy Rate

1124 • For PAM4:
1125 0.95 * 76 * 8 / ((8+4+2*2+76) * 10) = 62.78% of Phy Rate
8.2.6.2 Max Net Link Rate for PAM-X PCS

1126 The A-Packet format defines a maximum payload size of 380 Bytes over the Downlink.
1127 When operating over PAM-X PCS, the overhead is:
1128 • 8-Byte A-Header. In the worst case, the first byte is modulated as sC216, while the rest are modulated
1129 using half the number of bits per symbol (compared to the payload bytes modulation)
1130 • 4-Byte A-Tail (CRC-32), modulated in the same manner as the payload
1131 • At least two IPG tokens, modulated as sC216
1132 Since for A-Header, the first byte is modulated using sC216 hence 1 bit per symbols, compare with max of 4
1133 bit per symbol for sC1616 payload modulation, while the rest of the 7 A-Header bytes, in the worst case, are
1134 modulated at half the bits per symbol vs the payload symbols, the 8 A-Header bytes, in the worst case,
1135 consume Link time of 1 (first byte) * 4 + 7 (rest of the A-Header bytes) * 2 = 18 payload byte time.
1136 The minimum IPG is defined as two sC216 tokens; at worst, this consumes the time of 4 Payload Bytes with
1137 sC1616 modulation.
1138 P2 uses RTS which requires at least 4% of the Phy Rate to be kept free for RTS and JITC Re-Train events.
1139 As a result, a maximum of 96% of the Phy Rate can be used for Original A-Packets flow.
1140 Therefore, P2’s Max Net Link Rate (using the maximum size A-Packets’ payload) is:

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1141 0.96 * 380 / (18 + 4 + 4 + 380) = 90% of Phy Rate

8.2.6.3 8B/10B PCS Fully Paced, A-Packets Stream from Link to TX RTS
1142 Over 8B/10B PCS, the TX RTS shall fetch a fully paced A-Packet stream from the TX Data Link, with up to
1143 97.5% (Downlink) / 95% (Uplink) effective utilization of the Physical Link.
1144 To measure effective utilization, the TX RTS must take into account, for each A-Packet fetched from the Link
1145 into the Phy, its Actual Physical Link consumption in terms of time, based on the A-Payload size in bytes.
1146 Physical Link consumption is measured in terms of Physical Link Byte Periods (BPeriods), where one
1147 BPeriod is defined as the time taken to transmit one data byte over the physical Link after its conversion to a
1148 10b symbol; hence, 10/GearBW[bps].
1149 Example:
1150 For Gear #2, GearBW is 4 Gbps, resulting in a BPeriod of 10/4 Gbps = 2.5 nS
1151 Actual Byte Period consumption per A-Packet over 8B/10B PCS shall be computed as:
1152 (A-PayloadSizeInBytes + 2 [CM + CB] + 8 [A-Header] + 4 [CRC-32]) BPeriods
8.2.6.4 PAM-X PCS Fully Paced, A-Packets Stream from Link to TX RTS
1153 The TX RTS shall fetch a fully paced A-Packet stream from the TX Data Link, with up to 96% effective
1154 utilization of the Physical Link.
1155 To measure effective utilization, the TX RTS must take into account, for each A-Packet fetched from the Link
1156 into the Phy, its Actual Physical Link consumption in terms of time, based on the A-Payload size in bytes and
1157 the different modulation used to transmit it. This relates to the Link’s sCMax and the A-Packet’s
1158 EResistance_QoS bit value.
1159 Physical Link consumption is measured in terms of Physical Link Byte Periods (BPeriods), where one
1160 BPeriod is defined as the minimal period it takes to transmit one data byte over the physical Link; hence,
1161 8/GearBW[bps].
1162 Example:
1163 For Gear #3, GearBW is 8 Gbps, resulting in a BPeriod of 8/8 Gbps = 1 nS
1164 Actual Byte Period consumption per A-Packet, per Gear at its associated sCMax, shall be calculated per Table
1165 32.
1166 Table 32 Actual Byte Period Consumption Per Gear
Gear sCMax Actual Byte Period Consumption per A-Packet [BPeriod]
(2*‘Payload Length’ field + 4 [CRC32]) * (1 + EResistance_QoS/1)

3 sC416
+ 16 [sC216 A-Header] + 2 [MinIPG]

4 sC816
+ 14 [one byte as sC216 with 7-byte as sC416 A-Header] + 3 [MinIPG]

5 sC1616
+ 18 [one byte as sC216 with 7-byte as sC416 A-Header] + 4 [MinIPG]
1167 A 96% fully paced A-Packet stream means that, for a fully utilized Link, the first Byte of A-Packet ‘N+1’
1168 shall be fetched from the Link Layer to the TX RTS module, after the nominal average spacing period of
1169 (Actual Byte Period Consumption of A-Packet ‘N’) / 0.96 BPeriods has passed since the first Byte of
1170 A-Packet ‘N’ was fetched into the TX RTS (see the informative example below).

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1171
Figure 45 Fully Paced TX Link to TX Phy Interface
PAM-X Pacing Implementation Example (Informative)

1172 A 96% Link utilization rate indicates a 24/25 ratio between the actual Original A-Packets flow rate and the
1173 Raw Phy Rate. This means that, in addition to the Actual Byte Period Consumption (ABPC) associated with
1174 the transfer of a given A-Packet, the Pacer must add an additional ABPC * (25/24−1), or ABPC/24, BPeriods
1175 before a new A-Packet transfer can start, to avoid exceeding the 96% utilization limit.
1176 Let’s assume we implement the Pacer using a zero-initialized “Debt/Credit Byte Period Counter” (BPCnt),
1177 in which, for each BPeriod, we subtract 25 from BPCnt only if this BPeriod is part of an ABPC associated
1178 with a certain A-Packet, and we add 24 to BPCnt (i.e., for the 96% of the whole Physical Link Rate) only if
1179 BPCnt < 0.
1180 As long as BPCnt ≥ 0, we can start transferring a new A-Packet. In this way, we maintain the average nominal
1181 rate required with a maximum deviation of just ±1 BPeriod from the nominal A-Packet start-of-transfer
1182 pacing.

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8.2.7 Scheduling Priority for A-Packets at TX RTS

1183 The TX RTS scheduler shall apply the following scheduling priorities when sending outgoing A-Packets into
1184 the physical Link (see Figure 38):
1185 • Highest Priority: Locally-generated Single/Gap Retransmission Requests (i.e., generated by the
1186 local RX RTS, see Section 8.2.3.1).
1187 • Second Priority: Delayed Original A-Packets pending in the TX RTS Buffer (as defined in
1188 Section 8.2.7.1).
1189 • Third Priority: Pending Retransmitted A-Packets associated with Remote-generated Single/Gap
1190 Retransmission Requests (i.e., generated by the Remote link partner RX RTS).
1191 • Lowest Priority: Original A-Packets pending in the TX RTS Buffer (i.e., non-Delayed).
1192 Per the above scheduling scheme, when the TX RTS scheduler prioritizes a pending Delayed Original
1193 A-Packet over a pending Retransmitted A-Packet, it shall also discard the current retransmission attempt of
1194 the pending Retransmitted A-Packet, and shall discard its associated Remote-generated Retransmission
1195 Request. Note that the Retransmitted A-Packet shall be still stored in the TX RTS Buffer, and therefore may
1196 be retransmitted as result of a future Remote-generated Retransmission Request (2nd/3rd RTS attempt).
1197 The TX RTS shall not discard Original A-Packets due to retransmissions.
1198 Note that the TX RTS does not modify the A-Header’s Priority sub-field.
8.2.7.1 Delayed Original A-Packet
1199 A Delayed Original A-Packet is an Original A-Packet for which the current wait time in BPeriods plus its
1200 effective size (in terms of Actual Byte Period Consumption, per Section 8.2.6.3 and Section 8.2.6.4) exceeds:
1201 ( 0.8 × ‘Max RTS Delay’ / BPeriod )
1202 where ‘Max RTS Delay’ is defined as per Section 8.2.4 and BPeriod is defined as per Section 8.2.6.3 and
1203 Section 8.2.6.4.

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8.2.8 RTS Bypass

1204 While working in P1, there is no use for the full RTS mechanism. However, several functionalities still
1205 needed.
1206 The RTS Bypass implementation over 8B/10B PCS is shown in Figure 46.
1207 The RTS Bypass shall include the following blocks:
1208 • Pacer: Ensures that no more than 97.5% (Downlink) / 95% (Uplink) of the Raw Phy Rate is
1209 allocated to Original A-Packets
1210 • MC Assignment: Assigns a Message Counter value to the A-Packet
1211 • TX Buffer: Small FIFO for ensuring proper activities
1212 • CRC and Header CRC: Updates the A-Packet CRC fields
1213 P1 RTS Bypass block updates the PHY related A-Packet fields as described in Section 8.2.8.
1214 Table 33 P1 A-Packet Fields Update
Field Sub-Field Bits Data
Link’s PHY1: 2
(Any value)
SCI at PHY1 b1:b0
7
Delay Value at PHY2 00
Link’s PHY2: b6:b0
TX Delay &
Original Indication Original Indication bit 1
1
at PHY2 b7
Link’s PHY3: Message Counter 8 Conveys the message counter,

Message Counter (MC) b7:b0 per Section 8.2.5.2
8
Header CRC See Section 8.2.5.3
b7:b0
8
CRC-32 See Section 8.2.5.4
b7:b0

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Link Layer
Ready A-Packet
Pacer TX RTS
at 97.5%
A-Packet
MC Assignment
A-Packet
TX Buffer
A-Packet
Update Header
CRC and CRC-32
A-Packet
8b10b
PCS
1215
Figure 46 RTS Bypass

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8.3 Physical Coding Sub-Layer (PCS)

8.3.1 PAM-X PCS
1216 The PAM-X Physical Coding Sub-Layer (PCS) is pre-configure to operate either as a Single Lane PAM-X,
1217 or as a Dual Lane PAM-X.
1218 Per each such pre-configuration, the PAM-X PCS operates in three modes:
1219 1. Training Mode
1220 During Link startup, Training Mode is used to enable fast convergence of the Receiver’s equalizer,
1221 cancellers, and timing recovery by sending the content of the scrambler bit by bit.
1222 2. Idle Mode
1223 During Link startup, Idle Mode is an intermediate mode moving out of Training Mode, in which the
1224 scrambler moves to producing 16 bits per symbol period, while transmitting only Idle Symbols.
1225 3. Normal Mode
1226 This is normal operation with data packets transmission. During Normal Mode, the Receiver may
1227 request a JITC Re-Training sequence. If it does so, then a fixed length Re-Training sequence is
1228 generated, preempting any data packet if needed.

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Link Layer ACMP

A-Packet
Byte Stream
Re-Train_EN
Remote Request
Manager sCMax/2_EN RTS sCMax
A-Packet
Normal Mode PCS

Re-Train_EN
Re-Train Packet to Token sCxx_Header
Token Data
Token Type
IDLE/ISS
Link Startup
Token Data
Token Type
IDLE/ISS
A -PHY
PHY Layer
Mode
PCS Layer
Token Stream
Normal_EN
Training_EN
Token Type Token Data (TD)
• sC16/8/4/2 When type is IDLE/ISS/EOI,
• IDLE/ISS/EOI Data is ignored...
Scrambler
Lane 0
Scrambled
sCxx bits for one
symbol
Bits to
Symbol
Symbol Stream
Symbol
PMD
1229
Figure 47 PAM-X Single Lane PCS Block Diagram

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Link Layer ACMP

A-Packet
Byte Stream
Re-Train_EN
Remote Request
Manager sCMax/2_EN RTS sCMax
A-Packet
Normal Mode PCS

Re-Train_EN
Re-Train Packet to Token sCxx_Header
Token Data
Token Type
IDLE/ISS
Link Startup
Token Data
Token Type
IDLE/ISS
A -PHY
PHY Layer
Mode
PCS Layer
Token Stream
Normal_EN
Training_EN
Token Type Token Data (TD)
• sC16/8/4/2 When type is IDLE/ISS/EOI,
• IDLE/ISS/EOI Data is ignored...
Scrambler
Lane 0 Lane 1
Scrambled Scrambled
Same Same
bits for one bits for one
sCxx sCxx
symbol symbol
Bits to Bits to
Symbol Symbol
Symbol Stream
Symbol
Symbol
PMD PMD
1230
Figure 48 PAM-X Dual Lane PCS Block Diagram
8.3.1.1 PAM16 Sub-Constellation Bit to Symbol mapping

1231 The A-PHY PAM-X transmitter shall comply with the PAM16 symbol set (constellation) and its Sub-
1232 Constellations as defined in this section, to enable trade-offs of error-resistance vs. bits-per-symbol.
1233 As shown in Figure 49, each Sub-Constellation is labelled using the format sCXn, where X is the number of
1234 sub-constellation levels and n is the number of full constellation levels (i.e., 16).
1235 In the basic PAM16 set, each symbol is transmitted using one of 16 discrete voltage levels, each of which
1236 represents one bit-to-symbol mapping, as shown in Table 34.

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sC1616 sC816 sC416 sC216 (G4-5) sC216 (G3)

15 15 15 15
13
11 11 11
7 7
5 5
3 3
-1
-3 -3
-5 -5
-7 -7
-9
-11 -11 -11
-13
-15 -15 -15 -15

1237
Figure 49 PAM16 Sub-Constellations

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1238 Table 34 PAM16 Sub-Constellations
sC1616 sC816 sC416 sC216 at Gear >3 sC216 at Gear 3
4-bit Symbol 3-bit Symbol 2-bit Symbol 1-bit Symbol 1-bit Symbol
0000 15 000 15 00 15 – – 0 15
0001 13 – – – – – – – –
0011 11 001 11 – – 0 11 – –
0010 9 – – – – – – – –
0110 7 011 7 – – – – – –
0111 5 – – 01 5 – – – –
0101 3 010 3 – – – – – –
0100 1 – – – – – – – –
1100 −1 – – – – – – – –
1101 −3 110 −3 – – – – – –
1111 −5 – – 11 −5 – – – –
1110 −7 111 −7 – – – – – –
1010 −9 – – – – – – – –
1011 −11 101 −11 – – 1 −11 – –
1001 −13 – – – – – – – –
1000 −15 100 −15 10 −15 – – 1 −15
1239 The levels shown are relative to the currently used TX Amplitude, where level ‘15’ represents positive TX
1240 Peak level. Note that sC216 levels are Gear-dependent, whereas the other sub-Constellations are Gear-
1241 independent.
8.3.1.2 Symbol and Token Rate/Period
1242 A Token is defined as a group of 4 Symbols. All transmission shall be done with full Tokens.
1243 All Symbols within one Token shall use the same Sub-Constellation, with the number of Token Data (TD)
1244 bits varied per the Sub-Constellation used.
1245 Table 35 Token Data (TD) per Sub-Constellation
Sub-Constellation Number of TD bits Denoted as
sC1616 4 * 4 = 16 TD[15:0]
sC816 4 * 3 = 12 TD[11:0]
sC416 4*2=8 TD[7:0]
sC216 4*1=4 TD[3:0]

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1246 For a Dual Lane PAM-X, each Token shall be transmitted using the two Lanes within two symbol periods:
1247 • In the first Symbol Period, the first Token’s Symbol shall be transmitted over Lane0 and the second
1248 Token’s Symbol shall be transmitted over Lane1.
1249 • In the second Symbol Period, the Third Token’s Symbol shall be transmitted over Lane0 and the last
1250 Token’s Symbol shall be transmitted over Lane1.
1251 The ratios between Symbol and Token Rate, and between Symbol and Token Period, are shown in Table 36.
1252 Table 36 Symbol / Token Rate and Symbol / Token Period Ratios
Per Lane
Number of Symbol Period /
Symbol Rate Comment
Lanes Token Period
/ Token Rate
4 Symbol periods are needed to transmit the

1 4 1/4
4 Tokens’ symbols over the same Lane
2 Symbol periods are needed to transmit the

2 2 1/2
4 Tokens’ symbols over the two Lanes

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8.3.1.3 A-Packet to Token Conversion

1253 The A-Packet received from the Data Link Layer (see Section 11) and the updated information from the RTS block (see Section 8.2) are moved into the lower PHY
1254 layer, which operates in terms of Symbol/Token units.
1255 Figure 50 describes the A-Packet partitioning. Figure 51 and Figure 52 describe the conversion to bits/Symbols/Tokens for each Sub-Constellation for Header
1256 bytes (H), for Payload Data, and for CRC-32 bytes (D).
Older Newer
8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit Variable Length Byte 32-bit
Adapt. Service Placem. TX Target Payload Header
A-Packet Desc. Desc. Desc. Delay Address
RTS Hdr
Length CRC
Payload Data Bytes CRC-32
Byte Stream
Packet Partioning
MSB
MSB
H0 H1 H2 H3 H4 H5 H6 H7 D0 D1 D2 Dn-5 Dn-4 Dn-3 Dn-2 Dn-1 Dn

LSB
LSB
Fixed Sub-Constellation Per Link Same Sub-Constellation for payload data and CRC-32 bytes based on Header carried
information
1257
Figure 50 A-Packet Partitioning
1258 The first Header byte shall be transmitted using the sC2 16 Sub-Constellation. The rest of the Header bytes shall be transmitted using a fixed Sub-Constellation
1259 derived from the fixed, preconfigured sCMax, per Table 37.
1260 Table 37 Header Sub-Constellation Per sCMax
Max Sub-Constellation Header Sub-Constellation
sC1616 sC416
sC816 sC416
sC416 sC216

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1261 All Payload data and CRC-32 bytes within a given A-Packet shall use the same Sub-Constellation. This Sub-
1262 Constellation may be dynamically changed from one A-Packet to the next A-Packet.
1263 The Sub-Constellation for the payload data and the CRC-32 bytes shall be selected from the set:
1264 { sC216, sC416, sC816, sC1616 }

1265 and shall be indicated in the packet header SCI field.
1266 The transmitter shall not send an A-Packet whose Sub-Constellation for payload data and CRC-32 bytes is
1267 lower than the Sub-Constellation used for the Header.
1268 The transmitter shall not send an A-Packet whose Sub-Constellation for payload data and CRC-32 bytes is
1269 higher than the maximum Sub-Constellation (i.e., no greater than sCMax).
1270 When the last bytes of an A-Packet (i.e., of the CRC-32) do not align with the Token boundaries, the minimum
1271 number of all-zero padding nibbles (Padding) shall be added in order to align with the Token boundaries (as
1272 shown in Figure 52).
Newer Older
MSB
MSB
MSB
LSB
LSB
LSB
H2 H1 H0
H2[7] H2[6] H2[5] H2[4] H2[3] H2[2] H2[1] H2[0] H1[7] H1[6] H1[5] H1[4] H1[3] H1[2] H1[1] H1[0] H0[7] H0[6] H0[5] H0[4] H0[3] H0[2] H0[1] H0[0]
S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 sC216
Tok5 Tok4 Tok3 Tok2 Tok1 Tok0
Newer Older
MSB
MSB
MSB
LSB
LSB
LSB
H2 H1 H0
H2[7] H2[6] H2[5] H2[4] H2[3] H2[2] H2[1] H2[0] H1[7] H1[6] H1[5] H1[4] H1[3] H1[2] H1[1] H1[0] H0[7] H0[6] H0[5] H0[4] H0[3] H0[2] H0[1] H0[0]
S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 sC416

Tok3 Tok2 Tok1 Tok0
1273
Figure 51 Bit/Symbol/Token Conversion Per Header Sub-Constellation

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Newer Older
MSB
MSB
MSB
LSB
LSB
LSB
D2 D1 D0
D2[7] D2[6] D2[5] D2[4] D2[3] D2[2] D2[1] D2[0] D1[7] D1[6] D1[5] D1[4] D1[3] D1[2] D1[1] D1[0] D0[7] D0[6] D0[5] D0[4] D0[3] D0[2] D0[1] D0[0]
S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 sC216
Tok5 Tok4 Tok3 Tok2 Tok1 Tok0
Newer Older
MSB
MSB
MSB
LSB
LSB
LSB
D2 D1 D0
S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 sC416

Tok2 Tok1 Tok0
Newer Older
MSB
LSB
Padding D0
0 0 0 0 D0[7] D0[6] D0[5] D0[4] D0[3] D0[2] D0[1] D0[0]
S3 S2 S1 S0 sC816
Tok0
Newer Older
MSB
MSB
LSB
LSB
Padding D1 D0
0 0 0 0 0 0 0 0 D1[7] D1[6] D1[5] D1[4] D1[3] D1[2] D1[1] D1[0] D0[7] D0[6] D0[5] D0[4] D0[3] D0[2] D0[1] D0[0]
S7 S6 S5 S4 S3 S2 S1 S0 sC816
Tok1 Tok0
Newer Older
MSB
MSB
MSB
LSB
LSB
LSB
D2 D1 D0
S7 S6 S5 S4 S3 S2 S1 S0 sC816
Tok1 Tok0
Newer Older
MSB
LSB
Padding D0
0 0 0 0 0 0 0 0 D0[7] D0[6] D0[5] D0[4] D0[3] D0[2] D0[1] D0[0]
S3 S2 S1 S0 sC1616
Tok0
Newer Older
MSB
MSB
LSB
LSB
D1 D0
D1[7] D1[6] D1[5] D1[4] D1[3] D1[2] D1[1] D1[0] D0[7] D0[6] D0[5] D0[4] D0[3] D0[2] D0[1] D0[0]
S3 S2 S1 S0 sC1616
Tok0
1274
Figure 52 Bit/Symbol/Token Conversion Per Payload Data and CRC-32 Bytes

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8.3.1.4 Downlink Scrambler

1275 The Downlink Scrambler shall be implemented using the LFSR shown in Figure 53.
XOR
S00 S01 S02 ... S37 S38 S39 ... S57
58 bit Scrambler Structure

Scrambler Output (SN)
1276
Figure 53 Downlink TX Scrambler LFSR
1277 The Figure 53 LFSR can also be expressed as the polynomial:

1278 𝐺(𝑋) = 1 + 𝑋 𝟑9 + 𝑋 58
1279 Note:
1281 as correct.
1282 The Scrambler’s 58-bit seed shall be initialized by the TX PCS to an arbitrary value with at least one bit set
1283 to 1.
1284 The TX PCS Scrambler shall operate according to one of the following two stages:
1285 • In Training Mode: For each Token period T, the scrambler produces 4 bits, ST[3:0].
1286 • ST[0] denotes the first bit produced during Token period T.
1287 • In Idle and Normal Modes: For each Symbol period N, the scrambler produces 16 bits, denoted as
1288 SN[15:0].
1289 • SN[0] denotes the first bit produced during Symbol period N. At the end of the Nth Symbol period,
1290 this bit will reside in S15 in the LFSR.
1291 • For PAM-X Single Lane: Per Symbol period, only the 4 LSB (out of the 16 bits the scrambler
1292 produced), i.e., SN[3:0], are used to scramble its data.
1293 • For PAM-X Dual Lane: Per Symbol period, the 4 LSB, of the 16 bits the scrambler produced,
1294 SN[3:0], are used to scramble Lane0 data and SN[7:4], are used to scramble Lane1 data.
1295 • At each Symbol period N, the four per-Lane scrambler output bits, i.e. [sb3:sb0], shall be used
1296 according to the Symbol Type used for that Symbol Period, for Idle/ISS symbols encoding, only
1297 the sb0 bit value shall be used (as data bits are ignored), to be encoded as an sC216 symbol, while
1298 for data, the TX PCS shall scramble (i.e., XOR - ) the proper Token Data (TD) bits with the
1299 scrambler output bits to generate the scrambled token data as shown in Table 38 and Table 39.

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1300 Table 38 PAM-X Single Lane Token Data Scrambling

Symbol
sC1616 sC816 sC416 sC216
Period
N TD[3:0]  SN[3:0] TD[2:0]  SN[2:0] TD[1:0]  SN[1:0] TD[0]  SN[3]
N+1 TD[7:4]  SN+1[3:0] TD[5:3]  SN+1[2:0] TD[3:2]  SN+1[1:0] TD[1]  SN+1[3]
N+2 TD[11:8]  SN+2[3:0] TD[8:6]  SN+2[2:0] TD[5:4]  SN+2[1:0] TD[2]  SN+2[3]
TD[15:12]  TD[11:9] 
N+3 TD[7:6]  SN+3[1:0] TD[3]  SN+3[3]
SN+3[3:0] SN+3[2:0]
Table 39 PAM-X Dual Lane Token Data Scrambling
Symbol
Lane sC1616 sC816 sC416 sC216
Period
Lane1 TD[7:4]  SN[7:4] TD[5:3]  SN[6:4] TD[3:2]  SN[5:4] TD[1]  SN[7]
N
Lane0 TD[3:0]  SN[3:0] TD[2:0]  SN[2:0] TD[1:0]  SN[1:0] TD[0]  SN[3]
Lane1 TD[15:12]  SN+1[7:4] TD[11:9]  SN+1[6:4] TD[7:6]  SN+1[5:4] TD[3]  SN+1[7]
N+1
Lane0 TD[11:8]  SN+1[3:0] TD[8:6]  SN+1[2:0] TD[5:4]  SN+1[1:0] TD[2]  SN+1[3]
8.3.1.5 Downlink Training Mode

1301 During Training, the TX PCS transmits the scrambler’s output bits (TD are assumed as all zero) using sC216.
1302 During each Token period T, the scrambler generates 4 bits, denoted as ST[0] to ST[3]. These bits shall be
1303 assigned according to Table 40 and Table 41.
1304 Table 40 PAM-X Single Lane Scrambler Output Training Bits
Symbol Training Symbols
Period Assigned Scrambler Bit
N ST[0]
N+1 ST[1]
N+2 ST[2]
N+3 ST[3]
Table 41 PAM-X Dual Lane Scrambler Output Training Bits
Symbol
Lane1 Lane0
Period
N ST[1] ST[0]
N+1 ST[3] ST[2]
1305 The scrambler output Training bits are mapped to an sC216 symbol, as shown in Table 34.

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1306 Inverted Scrambler Symbols (ISS) during training shall use the ones-complement of the Training bits mapped
1307 to a sC216 symbol as in Table 34.
1308 The PAM-X Source PCS shall transmit the scrambler output bits interleaved with Reflected K-Sequences,
1309 where each Reflected K-Sequence shall be sent whenever it detects one K-Sequence received over the Uplink
1310 / Reverse Downlink. This process is also referred to as ‘K-Reflection’.
1311 ‘K-Reflection Delay” is the time from last bit of Uplink’s K-Sequence arrival time to first symbol of PAM-X
1312 K-Sequence transmit time. The ‘K-Reflection Delay’ shall be chosen such that the requirements from ‘ISS
1313 Generation Delay’, as specified in Section 8.3.1.8, could be met.

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1314 Each K Sequence shall be 8 symbols long, where the first K Sequence’s symbol shall be aligned with the
1315 start of a Token period T, as shown in Table 42 and Table 43.
1316 Table 42 PAM-X Single Lane "K Sequence" Symbol Mapping vs Training Symbols
Symbol Period K Sequence Normal Training
N −5 @ G3, −3 @ G4/5 sC216( ST[0] )
N+1 5 @ G3, 3 @ G4/5 sC216( ST[1] )
N+2 sC216( 1 ) sC216( ST[2] )
N+3 sC216( 0 ) sC216( ST[3] )
N+4 −5 @ G3, −3 @ G4/5 sC216( ST+1[0] )
N+5 sC216( ST+1[1] ) sC216( ST+1[1] )
N+6 sC216( ST+1[2] ) sC216( ST+1[2] )
N+7 sC216( ST+1[3] ) sC216( ST+1[3] )
Table 43 PAM-X Dual Lane "K Sequence" Symbol Mapping vs Training Symbols
Symbol Lane1 K Lane0 K Lane1 Normal Lane0 Normal

Period Sequence Sequence Training Training
5 @ G3, −5 @ G3,
N sC216( ST[1] ) sC216( ST[0] )
3 @ G4/5 −3 @ G4/5
5 @ G3,
N+1 sC216( 1 ) sC216( ST[3] ) sC216( ST[2] )
3 @ G4/5
-5 @ G3, sC216( 1 )
N+2 sC216( ST+1[1] ) sC216( ST+1[0] )
-3 @ G4/5
N+3 sC216( 0 ) sC216( 0 ) sC216( ST+1[3] ) sC216( ST+1[2] )
5 @ G3, −5 @ G3,
N+4 sC216( ST+2[1] ) sC216( ST+2[0] )
3 @ G4/5 −3 @ G4/5
N+5 sC216( ST+2[3] ) sC216( ST+2[2] ) sC216( ST+2[3] ) sC216( ST+2[2] )
1317 Note that sC216(ST) denotes the normal training symbol modulation for that Token period.
1318 K sequences are used by the Receiver to resolve Token boundaries, Lane Swap/De-Skew (for Dual Lane
1319 PAM-X), and channel Polarity (when channel is differential), and to allow the Sink’s Downlink / Reverse
1320 Downlink receiver to compute the ‘Min Link RTD’ using the K-Reflection done by the transmitter.
1321 Since the minimum distance between K sequences, as generated by the Sink and reflected by the PAM-X
1322 Source over the Downlink, is much larger than 58-bit Downlink duration, the Receiver has more than enough
1323 incoming scrambler output bits to load its 58-bit de-scrambler and lock it to the TX scrambler.

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8.3.1.5.1 Mode Transition from Training to Idle

1324 At the Sink side, when the PAM-X Downlink receiver is ready to move into Idle mode, the Uplink transmitter starts to send In_idle Startup Control Sequences.
1325 At the Source side, the PAM-X Downlink / Reverse Downlink transmitter shall indicate a transition into Idle mode whenever it is ready to move into Idle mode
1326 and is currently detecting an In_idle Startup Control Sequence being received over the Uplink.
1327 To indicate the transition out of Training Mode and into Idle Mode, the PAM-X TX PCS shall transmit, per Lane, 8 Inverted Scrambler Symbols (ISSs) followed
1328 by 16 normal training symbols as shown in Figure 54.
Older Newer
16 Symbols Per Lane N Tokens
L0 Training ISS ISS ISS ISS ISS ISS ISS ISS Training IDLE
Scrambler advances 16 bits every

Scrambler advances 4 bits every Token Period
1329 Symbol Period
Figure 54 PAM-X Single Lane Transition from Training to Idle
16 Symbols Per Lane N Tokens (N/2 Per Lane)
Scrambler advances 16 bits every

Scrambler advances 4 bits every Token Period
1330 Symbol Period
Figure 55 PAM-X Dual Lane Transition from Training to Idle

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8.3.1.6 Downlink Idle Mode

1331 During the Idle mode and in the gap between data packets (IPG) in the normal mode, Idle Tokens shall be
1332 transmitted.
1333 Each Idle Token shall map 4 scrambler output bits (“Idle bits”) to sC216 symbols as shown in Table 44 and
1334 Table 45. Note that for Idle/ISS symbol encoding SN[0] shall be used, and not SN[3] which shall be used to
1335 scramble sC216 data tokens).
1336 Table 44 PAM-X Single Lane Idle Bits Allocation
Symbol Period Idle Bit
N SN[0]
N+1 SN+1[0]
N+2 SN+2[0]
N+3 SN+3[0]
Table 45 PAM-X Dual Lane Idle Bits Allocation
Symbol Period Lane Idle Bit

Lane1 SN[4]
N
Lane0 SN[0]
Lane1 SN+1[4]
N+1
Lane0 SN+1[0]
1337 While not in training, Inverted Scrambler Symbols (ISS) shall use the one’s-complement of the Idle bits
1338 mapped to an sC216 symbol: sC216(~SN).
1339 To indicate transitioning into Normal mode, the PCS shall transmit, per Lane, four Inverted Scrambler
1340 Symbols (ISSs) followed by four regular Idle symbols, as shown in Figure 56 and Figure 57.
N link tokens 4 symbols
Idle ISS ISS ISS ISS I I I I Normal
1341
Figure 56 PAM-X Single Lane Transition from Idle to Normal
N link tokens 4 symbols
Idle ISS ISS ISS ISS I I I I

Normal
Idle ISS ISS ISS ISS I I I I
1342
Figure 57 PAM-X Dual Lane Transition from Idle to Normal

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8.3.1.7 Downlink Normal Mode

1343 In Normal Mode the PCS transmits data packets interleaved by Inter Packet Gaps (IPG).
1344 An IPG shall consist of one or more Idle Tokens, followed by a single End-Of-Idle (EOI) token.
1345 EOI tokens shall convey two ISSs and two Idle symbols.
1346 EOI symbols shall be allocated as shown in Table 46 and Table 47.
1347 Table 46 PAM-X Single Lane EOI Symbol Allocation
Symbol Period EOI Symbol
N ISS
N+1 ISS
N+2 Idle
N+3 Idle
Table 47 PAM-X Dual Lane EOI Symbol Allocation
Symbol Period Lane EOI Symbol

Lane1 ISS
N
Lane0 ISS
Lane1 Idle
N+1
Lane0 Idle
1348 An example of Normal Mode PCS data is shown in Figure 58. The minimal IPG period has IDLE Token and
1349 EOI Token as shown in the upper example. The IPG period may include more IDLE Tokens, as shown in the
1350 lower diagram.

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Header Tokens (G3: H=15, G4/5: H=8) Payload Data and CRC-32 Tokens Min. IPG Header Tokens (G3: H=15, G4/5: H=8) Payload Data and CRC-32 Tokens
Tok Tok Tok Tok Tok Tok Tok Tok Tok Tok Tok Tok Tok Tok Tok Tok Tok Tok Tok Tok Tok Tok
IDLE EOI
0 1 H-2 H-1 H 0 1 2 N-2 N-1 N 0 1 H-2 H-1 H 0 1 2 K-2 K-1 K
Packet (n) Packet (n+1)
Header Tokens (G3: H=15, G4/5: H=8) Payload Data and CRC-32 Tokens IPG Header Tokens (G3: H=15, G4/5: H=8) Payload Data and CRC-32 Tokens
Tok Tok Tok Tok Tok Tok Tok Tok Tok Tok Tok Tok Tok Tok Tok Tok Tok Tok Tok Tok Tok Tok
IDLE IDLE EOI
0 1 H-2 H-1 H 0 1 2 N-2 N-1 N 0 1 H-2 H-1 H 0 1 2 K-2 K-1 K
Packet (n) Packet (n+1)

1351
Figure 58 PCS Normal Mode Data Example

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8.3.1.8 Highly Asymmetric Downlink JITC Re-Training

1352 When working in Normal Mode, the Sink may request the Source to transmit the Re-Training sequence:
1353 • The Re-Training request shall be transmitted by Sink over the Uplink as described in
1354 Section 8.3.2.8.1
1355 • Upon detection of such a request, the Source’s Downlink Transmitter shall transmit, starting on the
1356 next Token boundary (and interrupting a packet if necessary), the Re-Training Sequence.
1357 • The Re-Training Sequence consists of TX_ReTRAIN_ISS_NUM ISS symbols followed by
1358 TX_ReTRAIN_IDLE_NUM idle symbols sent per Lane.
1359 • ISS Generation Delay is the time from last bit of a valid Re-Training request arrival time to the first
1360 ISS symbol of the Re-Training Sequence transmit time. ISS Generation Delay shall be selected to
1361 satisfy:
1362 [K-Reflection Delay – 64 Downlink Symbol Periods] ≤
1363 ISS Generation Delay ≤
1364 [K-Reflection Delay + 64 Downlink Symbol Periods]
1365 (See Section 8.3.1.5 for the definition of K-Reflection Delay.)
1366 • After completing the Re-Training Sequence, the Downlink Transmitter may send data packets, but it
1367 shall limit the actual max Sub-Constellation used to sCMax/2. (e.g., for a Link with sCMax = sC1616
1368 it shall use a maximum Sub-Constellation of sC816).
1369 • When the Downlink Transmitter detects that an sCMax Request has been transmitted over the Uplink
1370 (per Section 8.3.2.8.2), then it may startTX
sending data again,
Re-Train using the sCMax Sub-Constellation.
Procedure
1371 The Downlink Transmitter shall operate according toSM
the Re-Train Procedure State Machine as illustrated in
1372 Figure 59.
sCMax Request Detected
0: TX
Normal
(sCMax)
Re-Training Request detected

-1: TX Normal
(sCMax/2)
Re-Training Request detected
1: TX ISS
(reset TX_ReTRAIN_ISS_NUM
counter )
TX_ReTRAIN_ISS_NUM Expired
2: TX IDLE
(reset
TX_ReTRAIN_IDLE_NUM
counter )
TX_ReTRAIN_IDLE_NUM Expired
1373
Figure 59 TX Re-Training Procedure State Machine

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1374 Table 48 TX Re-Training Procedure State Machine Sequence-Length Values

Value
Name Description
(Symbols)
Per Lane, ISS symbols number in the
TX_ReTRAIN_ISS_NUM 1280
Re-Training Sequence
Per Lane IDLE symbols number in the
TX_ReTRAIN_IDLE_NUM 96
Re-Training Sequence
8.3.1.9 PAM-X Reverse Downlink For Symmetric Q-Port

1375 PAM-X Reverse Downlink shall operate similar to the regular Single Lane PAM-X Downlink, except as
1376 stated in the following sub-sections.
8.3.1.9.1 PAM-X Reverse Downlink Scrambler
1377 When using the PAM-X PCS to implement the Reverse Downlink, the Scrambler shall be implemented as
1378 specified in Section 8.3.1.4, but with the orthogonal LFSR as shown in Section 8.3.2.3 (i.e., the same LFSR
1379 as used for the Uplink Scrambler)
8.3.1.9.2 PAM-X Reverse Downlink K-Sequences Generation and Sink K-Reflection
1380 In Symmetric Q-Port, During Training with K Sequences:
1381 • At the Sink side, the Reverse Downlink PAM-X TX PCS shall transmit training symbols as specified
1382 in Section 8.3.1.5 while improving its Downlink reception quality at the presence of its own
1383 transmission. After reaching a sufficient reception quality, but not earlier than 10 mS after its start of
1384 transmission and when its Downlink Receiver is ready to receive K-Sequences from the Source, the
1385 Reverse Downlink TX PCS shall start to periodically interleave the training symbols with Sink-
1386 Generated K-Sequences, separated by intervals of ‘K-Sequence Variable Periods’ as specified in
1387 Section 8.3.2.6, but with the PAM-X K-Sequences as specified in Section 8.3.1.5.
1388 • At the Source side, after its Reverse Downlink receiver has reached a good reception quality, its
1389 Downlink PAM-X TX PCS shall Reflect received Sink-Generated K-Sequences as specified in
1390 Section 8.3.1.5.
1391 • The Sink’s downlink receiver then shall use these Source-Reflected K-Sequences (as in
1392 Section 8.3.1.5), and its TX PCS shall again reflect each received Source-Reflected K-Sequence
1393 towards the Source by generating a single Sink-Reflected K-Sequence over the Reverse Downlink.
1394 • At the Source side, the Reverse Downlink receiver shall use these Sink-Reflected K-Sequences to
1395 resolve ‘Min Link RTD’. The Source Downlink PAM-X TX PCS shall not reflect received Sink-
1396 reflected K-Sequences. Sink-reflected K-Sequences can be identified by the Source, as they will be
1397 received by the Source less than 100 µS after the source transmitted its Source-reflected K-
1398 Sequence.

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1399
Figure 60 Symmetric Q-Port K-Generation/Reflection
8.3.1.9.3 Symmetric Q-Port JITC Re-Training

1400 In a Symmetric Q-Port, when working in Normal Mode, each link partner may request the other link partner
1401 to transmit the Re-Training sequence:
1402 • The Re-Training request shall be initiated by the “Initiating Partner” by transmitting, starting on the
1403 next Token boundary (and interrupting a packet if necessary), a Re-Training Sequence towards its
1404 partner.
1405 • Upon detection of such a Re-Training Sequence, a “Responding Partner”, which is not already
1406 transmitting such sequence, shall transmit, starting on the next Token boundary (and interrupting a
1407 packet if necessary), the Re-Training Sequence.
1408 • The Re-Training Sequence consists of TX_ReTRAIN_ISS_NUM ISS symbols followed by
1409 TX_ReTRAIN_IDLE_NUM idle symbols as specified in Table 48. Note that since Downlink Scrambler
1410 is orthogonal to the Reverse Downlink scrambler, the two Re-Training sequences are also
1411 orthogonal.
1412 • After completing the Re-Training Sequence, each Partner’s transmitter may send data packets, but it
1413 shall limit the actual max Sub-Constellation used to sCMax/2. (e.g., for a Link with sCMax = sC1616
1414 it shall use a maximum Sub-Constellation of sC816).
1415 When a Partner detects that an sCMax Request has been transmitted over the other direction using the format
1416 shown in Figure 80), then it may start sending data again, using the sCMax Sub-Constellation.
1417 The “Responding Partner” Transmitter shall operate according to the Re-Train Procedure State Machine as
1418 illustrated in Figure 59, starting from State 0 of this State Machine. The “Initiating Partner” Transmitter shall
1419 operate according to the same State Machine, moving directly to State 1 upon initiation of the Re-Training
1420 Request. Note that it is common for both partners to act as an “Initiator Partner”, since noise may impact
1421 both same-Gear partners.

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8.3.2 8B/10B PCS

1422 8B/10B PCS (Figure 61) is used over the Uplink, for all Gears, for both Profiles. It is used over the
1423 Downlink/Reverse Downlink for Gears #1 and #2. For profile 1, 8B/10B PCS is also used over the Downlink
1424 for Gear #3.
1425 The 8B/10B TX PCS encapsulates A-Packets, using the ‘A-P Encapsulation’ module (see Section 8.3.2.8.6),
1426 converting A-Packets Byte by Byte to 10b symbols (8B/10B encoding), which are then sent bit by bit (LSB
1427 to MSB) over the Link.
1428 When operating over the Uplink, the 8B/10B TX PCS also inserts several Requests / Ack-Indications into
1429 the byte stream using the ‘Uplink Request Insertion’ module. When sending Requests / Ack-Indications over
1430 the Reverse Downlink, they shall be sent using A-Packet encapsulation with similar format and A-Packet
1431 Header, as detailed in Section 8.2.3.3.
1432 The 8B/10B TX PCS operates in three modes:
1433 1. Training Mode
1434 During Link startup, Training mode is used to enable the Receiver to synchronize to the 10b word
1435 boundaries and lock its descrambler.
1436 2. Idle Mode
1437 During Link startup, an intermediate mode moving out of Training mode transmitting only scrambler
1438 contents (data is zero).
1439 3. Normal Mode
1440 Normal operation with data packets transmission.

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Request Generator Link Startup
A-Packet
Re-Train sCMax Ret. Ret.
Req Req Ack Req
Uplink Request Insertion A-P Encapsulation

DHA
InTrain/InIdle/
Byte Stream Controller InNormal
data/control byte
B[7:0]
Scrambler
Enable
K-Sequences S[7:0]
Control Mark
CM
Scrambled data/control byte
SB[7:0]
8b10b encoder
10b symbol
10b Symbols
to NRZ
1441
Figure 61 PCS Block Diagram

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8.3.2.1 10b Symbols to NRZ Mapping

1442 The notation for 8B/10B symbols is “abcdeifghj”, where the “a” bit is transmitted first. Each bit shall be
1443 transmitted according to Table 49.
1444 Table 49 NRZ Electrical Levels Mapping
Bit Value TX Level
0 + (peak TX amplitude)
1 − (peak TX amplitude)
8.3.2.2 8B/10B Encoding

1445 All information communicated shall be 8B/10B encoded according to the data and control symbol
1446 assignments specified in Annex B.
1447 When encoding a data/control byte (CM=0), 10b Data symbols shall be transmitted.
1448 When encoding a control mark (CM=1), B[7:0] shall be zeroed to make sure that SB[7:0] will reflect the
1449 scrambler content, and a 10b Control symbol shall be transmitted according to the 3 LSBs of the current
1450 scrambler output, SB[2:0], as shown in Table 50.
1451 Table 50 8B/10B Encoding
S[2:0] 10b Control Symbol
000 K28.1
001 K28.3
010 K28.5
011 K28.6
100 K23.7
101 K27.7
110 K29.7
111 K30.7

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8.3.2.3 Uplink / Reverse Downlink Scrambler

1452 When using the 8B/10B PCS to implement the Uplink / Reverse Downlink, the Scrambler shall be
1453 implemented using the LFSR shown in Figure 62.
XOR
S00 S01 S02 ... S17 S18 S19 ... S57
58 bit Scrambler Structure

Scrambler Output (SN)
1454
Figure 62 Uplink / Reverse Downlink TX Scrambler LFSR
1455 The Figure 62 LFSR can also be expressed as the polynomial:

1456 𝐺(𝑋) = 1 + 𝑋19 + 𝑋 58
1457 Note:
1459 as correct.
1460 The Scrambler’s 58-bit seed shall be initialized by the TX PCS to an arbitrary value with at least one 1 bit.
1461 For each 10b symbol period, the scrambler produces 8 bits, i.e., S[7:0] where S[0] denotes the first bit
1462 produced during the period.
1463 The Uplink / Reverse Downlink TX shall use this Scrambler to produce a scrambled data/control byte
1464 SB[7:0] which shall equal B [7:0] XOR S[7:0].
8.3.2.4 Downlink Scrambler

1465 When using the 8B/10B PCS to implement the Downlink, the Scrambler shall be implemented using the
1466 LFSR described in Figure 53.
1467 The Scrambler’s 58-bit seed shall be initialized by the TX PCS to an arbitrary value with at least one 1 bit.
1468 For each 10b symbol period, the scrambler shall produce 8 bits, i.e., S[7:0], where S[0] denotes the first bit
1469 produced during the period.
1470 The Downlink TX shall use this Scrambler to produce a scrambled data/control byte SB[7:0] which shall
1471 equal B[7:0] XOR S[7:0].

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8.3.2.5 Byte Stream Controller
8.3.2.5.1 Data Bytes

1472 Data bytes carry the contents of A-Packets or Requests/Acks, as detailed below.
1473 When having nothing else to transmit, the 8B/10B TX PCS shall transmit zero bytes carrying the scrambler’s
1474 output bits (i.e., CM=0 and B[7:0]=0). The Receiver can continuously check the content of these zero bytes
1475 (i.e., 0, as known to the Receiver) to verify that it is still in good sync with the Transmitter.
8.3.2.5.2 Control Byte
1476 Control bytes carry control information and shall consist of two control nibbles: CN1 (the least significant
1477 control nibble) and CN2 (the most significant control nibble).
8.3.2.5.3 Startup Control Sequence
1478 Startup Control Sequences are used during Link startup to mark operation mode transitions and other
1479 indications needed during the startup procedure, see Section 8.3.3.
1480 Startup Control Sequences shall not be sent during the period after startup was completed but before the first
1481 A-Packet has been sent.
1482 A Startup Control Sequence shall consist of a Control Mark (i.e., CM=1 and B[7:0]=0) followed by two
1483 identical Control Bytes as defined in Table 51.
1484 A Startup Control Sequence shall be valid only if the two received Control Bytes contain the same value.
1485 Table 51 Startup Control Nibbles
Used in Used in
Control Nibble Code Usage Restrictions
CN1 CN2
Startup Sequence (STS) 0110 + − –
In Idle (IDLE) 1001 − + –
In Normal (NML) 1110 − + –
Downlink Half Amplitude (DHA) 0111 − + Shall not use over 8B/10B Downlink
1486 During a given mode of operation, after generating a Startup Control Sequence, no additional Startup Control
1487 Sequence shall be sent until at least 256 µS has elapsed. When changing an operation mode, a new Startup
1488 Control Sequence marking the change may be sent immediately.

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8.3.2.5.4 Normal Control Sequence

1489 A Normal Control Sequence shall consist of a Control Mark (CM=1 and B[7:0]=0) followed by a single
1490 Control Byte. A Normal Control sequence shall be used in normal mode to mark Packet boundaries and
1491 Request/Ack boundaries, as detailed in Table 52.
1492 A single Normal Control byte may combine the end of a previous packet or request (in CN1) and the beginning
1493 or continuation of a new packet or request (in CN2); this is indicated with the wildcard notation (i.e., the
1494 asterisk character: *) in subsequent Sections.
1495 Table 52 Normal Control Nibbles
Used Used
Control Nibble Code Usage Restrictions
in CN1 in CN2
Null 0000 + + –
Packet Start (PS) 1000 − + –
Packet End (PE) 0100 + − –
Ret. Req. Start (RRS) 0010 − +
Req. End (RE) 0001 + −
Gap Req. Start (GRS) 0011 − +
Shall not use over
Re-Train Req. (RTR) 1111 − +
P1 8B/10B Downlink
sCMax Req. (CMR) 0101 − +
Interrupt (INT)/Packet Continue (PC) 1100 + (INT) + (PC)
Ack Indication (ACK) 1010 − +

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8.3.2.6 Training Mode

1496 During Training without K Sequences:
1497 • The 8B/10B TX PCS shall transmit only Zero bytes.
1498 During Training with K Sequences:
1499 • At the Sink side, the 8B/10B Uplink / Reverse Downlink TX PCS shall transmit zero bytes while
1500 improving its Downlink reception quality at the presence of its own transmission. After reaching a
1501 sufficient reception quality, and when the Downlink Receiver is ready to receive K-Sequences from the
1502 Source, the Uplink / Reverse Downlink TX PCS shall start to periodically interleave the zero Bytes with
1503 the K-Sequences, separated by intervals of ‘K-Sequence Variable Periods’.
1504 • At the Source side, the 8B/10B Downlink TX PCS shall transmit zero bytes interleaved with Reflected
1505 K-Sequences. Each Reflected K-Sequence shall be sent whenever the Source detects a K-Sequence
1506 received over the Uplink. The Source shall only use this process (also referred to as ‘K-Reflection’) after
1507 its Uplink Receiver’s de-scrambler is well locked.
1508 Each K-Sequence shall consist of the K28.5 (comma) control 10b-Symbol, sent when RD=−1 (K28.5 Pos:
1509 ‘001111 1010’) without violating the 8B/10B running disparity rules (i.e., the exact location of the K28.5 Pos
1510 within the byte stream shall be adjusted accordingly), followed by at least two zero bytes.
1511 Each time a K-Sequence is sent, the next K-Sequence Variable Period shall be computed; its value shall be
1512 between 256 and 400 µS.
1513 Note: (Informative)
1514 One way to implement a pseudo-randomly selected K-Sequence Variable Period is to use 7 bits of
1515 the scrambler output to compute the value:
1516 Period Value = 256 + S[6:0] µS
1517 This method produces values in the range 256–383. In addition, it will wait until the 8B/10B running
1518 disparity is consistent with the insertion of the K28.5 Pos.
K-Sequence Variable Period µS) K-Sequence Variable Period µS)
Zero Byte K28.5 Pos Zero Byte Zero Byte Zero Byte Zero Byte K28.5 Pos Zero Byte Zero Byte Zero Byte Zero Byte K28.5 Pos Zero Byte Zero Byte Zero Byte
... ... ...
1519
Figure 63 Training with K-Sequences Example
1520 A receiver uses received K-Sequences to resolve 10b-Symbol boundaries and channel Polarity (when channel
1521 is differential), which are then used to lock the Receiver’s de-scrambler.
1522 Since the minimum distance between the K28.5 10b-Symbols is much larger than the 58-bit scrambler size,
1523 the Receiver has more than enough incoming TX Scrambler bits to load its 58-bit de-scrambler and lock it to
1524 the TX Scrambler.
1525 After successfully receiving the reflected K-Sequences and locking its own de-scrambler, the Sink shall stop
1526 sending K-Sequences. It may then generate Half Amplitude Startup Control Sequences, which consist of a
1527 Control Mark (CM=1 and B[7:0]=0) followed by two Downlink Half Amplitude Control Bytes (CN1=STS,
1528 CN2=DHA); see Figure 64.
CN1: STS CN1: STS

Zero Byte CM CN2: DHA
Zero Byte
CN2: DHA ...
1529
Figure 64 DHA Startup Control Sequence

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8.3.2.7 Idle Mode

1530 During Idle mode, the 8B/10B TX PCS shall transmit zero bytes interleaved with In_idle Startup Control
1531 Sequences (see Figure 65).
1532 Per Figure 65, an In_idle Startup Control Sequence shall consist of a Control Mark (CM=1 and B[7:0]=0)
1533 followed by two In_idle Control Bytes (CN1=STS, CN2=IDLE).
CN1: STS CN1: STS

Zero Byte CM CN2: IDLE
Zero Byte
CN2: IDLE ...
1534
Figure 65 In_Idle Startup Control Sequence
1535 At the Sink side, when ready to move to Idle mode, the first In_idle Startup Control Sequence shall be
1536 transmitted immediately upon entering the Idle Mode. Additional In_idle Startup Control Sequences may
1537 follow (with the proper spacing between them), as long as no “In Idle” indication is received from the Source.
1538 Note that the Downlink may also be a PAM-X Downlink.
1539 At the Source side, the 8B/10B Downlink TX PCS shall transmit Reflected In_idle Startup Control
1540 Sequences. Each Reflected In_idle Startup Control Sequence shall be sent whenever the Source is ready to
1541 move to Idle mode, or is already in Idle mode and detects an In_idle Startup Control Sequence received over
1542 the Uplink.
1543 The Sink’s 8B/10B Downlink Receiver shall use these Reflected In_idle Startup Control Sequences to
1544 compute the Min Link RTD.

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8.3.2.8 Normal Mode

1545 In Normal Mode over the Uplink / Reverse Downlink, the Byte Stream Controller shall convey requests, Ack
1546 Indications, and data packets according to the following priorities, listed in descending order:
1547 1. Re-Train Requests
1548 2. sCMax Requests
1549 3. Single and Gap Retransmission Requests (in a first-come, first-served order) as specified in
1550 Section 8.2.3 and Section 8.2.4.
1551 4. Ack Indications
1552 5. Data Packets
1553 Requests and/or Ack Indications presented to the Uplink Transmitter during a data packet transmission shall
1554 not wait for its completion; they shall be transmitted immediately, interrupting transmission of the data
1555 packet, as detailed below. Interrupting Requests and/or Acks shall start with an INT CN1 in their Control Byte.
1556 Requests/Ack-Indications sent over the Reverse Downlink shall be sent using A-Packet encapsulation, with
1557 similar format and A-Packet Header as detailed in Section 8.2.3.3, and shall not interrupt any other A-Packet.
1558 Requests / Ack Indications received at the Uplink / Reverse Downlink Receiver shall be discarded if their
1559 CRC field is bad, OR if one of their 10b-Symbols was detected by the 8B/10B decoder as a non-valid 10b-
1560 Symbol (i.e., as a 10b-Symbol which is not one of the 10b-Symbols used on RD+ or RD− disparity symbol
1561 lists regardless of the current disparity). This additional condition is added to reduce the probability for
1562 “False-Positive”, Request / Ack Indication, detection.
1563 An interrupted data packet shall continue when all requests / indications have been transmitted. CN1: RE and
1564 CN2: PC shall be used in the Control Byte ending the Request and continuing the data packet.
A-Packet s first N Bytes Interrupting RTS Request A-Packet s Continues Bytes

CN1: * A-Header A-Packet CN1: INT CN1: RE A-Packet A-Tail CN1: PE
CM CM MC CRC CM CM
CN2: PS 1st Byte ... Byte (N) CN2: RRS CN2: PC Byte(N+1) ... Last Byte CN2: *
1565
Figure 66 Interrupting Request with Data Packet Continues
1566 Re-Train Requests presented to the Uplink Transmitter during the transmission of other requests/indications
1567 shall also interrupt them.
1568 In Normal Mode over the Downlink, the Byte Stream Controller shall not send Requests/Ack-Indications.
1569 When transitioning from Idle to Normal mode, before transmitting the first A-Packet, the 8B/10B TX PCS
1570 shall transmit zero bytes interleaved with In_Normal Startup Control Sequences. Per Figure 67, the
1571 In_Normal Startup Control Sequence shall consist of a Control Mark (CM=1 and B[7:0]=0), followed by two
1572 In_Normal Control Bytes (CN1=STS, CN2=NML).
1573 The first In_Normal Startup Control Sequence shall be transmitted immediately upon entering the Normal
1574 Mode.
CN1: STS CN1: STS

Zero Byte CM CN2: NML
Zero Byte
CN2: NML ...
1575
Figure 67 In Normal Startup Control Sequence

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8.3.2.8.1 Re-Train Request

1576 A Re-Train Request signals the Downlink Transmitter to start transmitting the JITC Re-Training sequence
1577 (see Section 8.3.1.8).
1578 Per Figure 68, a Re-Train Request shall consist of:
1579 • A Control Mark
1580 • A Control Byte with an RTR CN2
1581 • A Data Byte carrying the CRC of the first Control Byte, calculated as specified in Section 8.2.5.3.
1582 • Another Control Mark
1583 • Another Control Byte, with an RE CN1 and an RTR CN2
1584 • Another Data Byte, containing the CRC of the second Control Byte, calculated as specified in
1585 Section 8.2.5.3.
1587 • A third Control Byte, with a RE CN1
1588 For discarding purposes, a Re-train Request shall be treated as two separate back-to-back Requests which
1589 shall be independently inspected for discard conditions.
CN1: * CN1: RE CN1: RE

CM CRC1 CM CRC2 CM
1590 CN2: RTR CN2: RTR CN2: *
Figure 68 Re-Train Request
8.3.2.8.2 sCMax Request

1591 An sCMax Request signals the Downlink Transmitter that it may start transmitting sCMax symbols after
1592 transmitting lower sub-constellation symbols per a previous Re-train request (see Section 8.3.1.8).
1593 Per Figure 69, an sCMax request shall consist of:
1595 • A Control Byte with a CMR CN2
1596 • Another Data Byte, containing the CRC of the first Control Byte, calculated according to
1597 Section 8.2.5.3.
1599 • Another Control Byte, with a RE CN1
CN1: * CN1: RE
CM CN2: CMR
CRC CM
1600 CN2: *
Figure 69 sCMax Request
1601 An interrupted sCMax request shall be abandoned by both the Uplink TX and the RX.

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8.3.2.8.3 Single Retransmission Request

1602 A Single Retransmission Request signals the Downlink Transmitter to re-transmit a single A-Packet.
1603 Per Figure 70, a Single Retransmission Request shall consist of:
1605 • A Control Byte with an RRS CN2
1606 • A Data Byte carrying the MC of the requested Downlink A-Packet
1607 • Another Data Byte, containing the CRC of the two previous bytes
CN1: * CN1: RE
CM MC CRC CM
1610 CN2: RRS CN2: *
Figure 70 Single Retransmission Request
1611 An interrupted Single Retransmission Request shall be repeated after completion of that interruption.
8.3.2.8.4 Retransmission Gap Request
1612 Gap Retransmission Requests signals the Downlink Transmitter to retransmit a series of consecutive
1613 Downlink packets.
1614 Per Figure 71, a Gap Retransmission Request shall consist of:
1616 • A Control Byte with a GRS CN2
1617 • A Data Byte containing MC1, the Last Matched MC as specified in Section 8.2.3.
1618 • Another Data Byte, containing MC2, the Post Gap MC as specified in Section 8.2.3.
1619 • A third Data Byte, containing the CRC of the three previous bytes
CN1: * CN1: RE
CM MC1 MC2 CRC CM
1622 CN2: GRS CN2: *
Figure 71 Retransmission Gap Request
1623 An interrupted Gap Retransmission Request shall be repeated after interruption completion.

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8.3.2.8.5 Ack Indication

1624 An Ack Indication signals the Downlink Transmitter to release all Active MCs, up to and including ‘this MC’.
1625 Per Figure 72, an Ack Indication shall consist of:
1627 • A Control Byte with an ACK CN2
1628 • A Data Byte containing the ‘this MC’ value
1629 • Another Data Byte, containing the CRC of the two previous bytes
CN1: * CN1: RE
CM MC CRC CM
1632 CN2: ACK CN2: *
Figure 72 Ack Indication
1633 An interrupted Ack Indication shall be repeated after completion of that interruption.
8.3.2.8.6 Data Packet
1634 Per Figure 73, a Data Packet shall consist of:
1636 • A Control Byte with a PS CN2
1637 • Data Bytes containing the A-Packet bytes, in order
1639 • Another Control Byte, with a PE CN1
A-Packet Bytes
CN1: NULL A-Header A-Tail CN1: PE
Zero Byte CM CM Zero Byte
1640 CN2: PS 1st Byte ... Last Byte CN2: NULL
Figure 73 Distinct A-Packet 8B/10B Encapsulation
1641 Data Packets can be efficiently encapsulated back-to-back, as shown in Figure 74:
First A-Packet Bytes Second A-Packet Bytes

CN1: * A-Header A-Tail CN1: PE A-Header A-Tail CN1: PE
CM CM CM
CN2: PS 1st Byte ... Last Byte CN2: PS 1st Byte ... Last Byte CN2: *
1642
Figure 74 Back-to-Back A-Packets: 8B/10B Encapsulation
1643 When operating over Uplink, Data Packets may be interrupted by Requests /Acks. Interrupted Data Packets
1644 shall continue with:
1646 • A Control Byte with a PC CN2, and RE CN1 belonging to the interrupting request
1647 • Data Bytes containing the remaining A-Packet bytes, in order
1649 • Another Control Byte, with a PE CN1
A-Packet s first N Bytes Interrupting RTS Request A-Packet s Continues Bytes

CN1: * A-Header A-Packet CN1: INT CN1: RE A-Packet A-Tail CN1: PE
CM CM MC CRC CM CM
CN2: PS 1st Byte Byte (N) CN2: RRS CN2: PC Byte(N+1) Last Byte CN2: *
1650 ... ...
Figure 75 A-Packet 8B/10B Encapsulation with Request Insertion

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8.3.2.9 Double Rate Uplink

1651 The Double Rate Uplink (DRU) 8B/10B PCS is used over the Uplink to transmit A-Packets at up to twice
1652 the normal Uplink data rate. Figure 76 shows the additional functionality in red, and augmented functionality
1653 blocks in red dashed lines.
1654 DRU shall operate similarly to the regular 8B/10B Uplink, except as stated below in this Section.
1655 The DRU 8B/10B TX PCS shall transmit A-Packet Header, Payload, and Tail bytes using PAM4 symbols by
1656 asserting the En_DR indication, with the result that the following procedure is performed once for every 10b
1657 (i.e., 100 nS) symbol period:
1658 • The Byte Stream Controller collects two consecutive A-Packet bytes to form a byte pair {B, B2}.
1659 • The Scrambler scrambles this byte pair to generate the scrambled byte pair {SB, SB2}.
1660 • The default 8b10b encoder generates the first 10b symbol from SB, and the second 8b10b encoder
1661 generates the second 10b symbol from SB2, together forming the resulting 10b symbol pair.
1662 • For transmission, the PAM4 encoder maps the10b symbol pair into 10 PAM4 symbols.
1663 If the number of A-Packet Payload bytes is odd, then in order to complete the last byte pair a zero data byte
1664 (i.e., with value 0x00) shall be added after the last A-Packet CRC32 byte. This additional zero byte shall be
1665 treated as part of the A-Packet Tail (transmitted with En_DR asserted).
1666 At all other byte instances that are not part of an A-Packet Header, Payload, or Tail, En_DR shall be set to
1667 zero, and the NRZ symbols shall be transmitted using the default 8b10b encoder.
1668 The second 8b10b encoder shall only operate (i.e., shall only update its running disparity) when En_DR is
1669 asserted. The second 8b10b encoder shall operate as an independent 8b10b encoder, i.e., it shall have no
1670 dependency on the default 8b10b encoder disparity.
1671 The scrambler shall transit to producing 16 bits per 10b Symbol period (100 nS) at the beginning of the Idle
1672 Mode (i.e., by asserting scr16), as detailed in 8.3.2.9.2Section 8.3.2.9.2.
Request Generator Link Startup
A-Packet
Re-Train Ret. sCMax Ret.
Req Req Req Ack
Uplink Request Insertion A-P Encapsulation DHA

InTrain/InIdle/
InNormal
Byte Stream Controller En_DR
data/control 2nd
byte data byte scr16
B[7:0] B2[7:0]
Enable
K-Sequences
Scrambler
Control Mark
CM
Scrambled data/control byte 2nd scrambled data byte
SB[7:0] SB2[7:0]
8b10b encoder 2nd 8b10b encoder
10b symbol 2nd 10b symbol
10b Symbol
10b Symbols
Pair
to NRZ
to PAM4
0 1
1673
Figure 76 RTU PCS Block Diagram
8.3.2.9.1 10b Symbol Pair to PAM4 Mapping

1674 The notation for 10b symbols is “abcdeifghj”, where the “a” bit is transmitted first. A 10b Symbol Pair
1675 comprises a first 10b symbol “a1b1c1d1e1i1f1g1h1j1” and a second 10b symbol “a2b2c2d2e2i2f2g2h2j2”. Each bit
1676 pair ({a1,a2} to {j1,j2}) shall be transmitted according to Table 53.

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1677 Table 53 PAM4 Electrical Levels Mapping

Bit Pair Value TX Level
{0,0} + (peak TX amplitude)
{0,1} +1/3 (peak TX amplitude)
{1,0} -1/3 (peak TX amplitude)
{1,1} − (peak TX amplitude)
8.3.2.9.2 DRU Scrambler

1678 The Scrambler shall use the regular Uplink LFSR as shown in Figure 62.
1679 The scrambler shall begin operating as detailed in Section 8.3.2.3. At the beginning of the Idle Mode it shall
1680 transition to producing 16 bits for each 10b symbol period (indicated by asserting scr16). (That is, for each
1681 10b symbol period the scrambler shall produce S[15:0], where S[0] denotes the first bit produced during the
1682 period.) The DR Uplink TX shall use these bits to produce:
1683 • A first, scrambled data byte SB[7:0] which shall be equal to B[7:0] XOR S[7:0], and
1684 • A second, scrambled, data byte SB2[7:0] which shall be equal to B2[7:0] XOR S[15:8].
1685 As shown in Figure 77, the transition shall occur on the first symbol after the first In_idle Startup Control
1686 Sequence transmitted.
Scrambler produces 8 bits (scr16=0) Scrambler produces 16 bits (scr16=1)
CN1: STS CN1: STS

Zero Byte CM CN2: IDLE
Zero Byte
CN2: IDLE ...
1687
Figure 77 DRU Scrambler Transition from Training to Idle Mode
8.3.2.9.3 DRU JITC Re-Training

1688 Because a P2 PAM4 DRU receiver would need more time to recover from an NBI attack, a DRU Re-Training
1689 procedure shall be used in conjunction with the Downlink Re-Training specified in Section 8.3.1.8.
1690 DRU Re-Training shall use the following TX stages (Sink side is the DRU TX):
1691 • Stage 1: Continuous NRZ modulated Re-Training Request (RTR) sequences are sent until a
1692 Downlink ISS sequence or Idle is detected.
1693 • Stage 2: NRZ Only Requests & Idle can be sent until an sCMax Request arrives from the Source, or
1694 until an NRZ period of 2 µS (over all from the procedure start) elapses.
1695 • Stage 3: Back to Normal. PAM4 modulated Data packets can be now sent.
1696 When the Sink (Downlink RX function) requires a Downlink Re-Training, it shall trigger a Re-Training
1697 procedure on both the Downlink direction and the DRU direction by sending the Continuous NRZ modulated
1698 RTR sequence until it detects an ISS sequence or a good Idle. The continuous NRZ modulated RTR sequence
1699 shall use the format shown in Figure 84.
CN1: * CN1: RE CN1: RE CN1: RE CN1: RE

CM CRC 1 CM CRC 2 CM CRC 3 CM CRC N CM
CN2: RTR CN2: RTR CN2: RTR ... CN2: RTR CN2: *
1700
Figure 78 DRU Continues RTR Sequence Sent Over DRU
1701 When the Source (DRU RX function) requires a Re-Training, it shall trigger a Re-Training procedure for just
1702 the DRU direction by sending a Re-Training Request over the Downlink, using the same convention and A-
1703 Header format as specified in Section 8.2.3.3, but with the payload format shown in Figure 79.
CN1: Null
A-Header [8-Bytes] CRC-32 [4-Bytes]
CN2: RTR
1704
Figure 79 DRU Re-Training Request Sent Over Downlink

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1705 Once such RTR is received by the Sink, which is in normal mode (i.e., DRU Re-Training procedure Stage
1706 3), it shall abort any data packet it is currently transmitting and shall move directly to DRU Re-Training
1707 procedure Stage 2; as a result, no Downlink Re-Training is triggered. If the Sink receiving this RTR over the
1708 Downlink has already triggered its own RTR over DRU in Stage 1, and is now on Stage 1 or Stage 2, then
1709 the received RTR shall be ignored.
1710 If the Source has already triggered a DRU Re-Training, and/or if it has already begun Downlink Re-Training
1711 (due to RTR sent over the DRU by the Sink), and its PAM4 reception capability has been restored, then it
1712 shall generate an sCMax request via the Downlink in order to shorten the duration of the Sink TX’s Stage 2.
1713 The DRU sCMax Request shall be sent over the Downlink using the same convention and A-Header format
1714 as specified in Section 8.2.3.3, but with the Payload format shown in Figure 80.
CN1: Null
A-Header [8-Bytes] CRC-32 [4-Bytes]
CN2:CMR
1715
Figure 80 DRU sCMax Request Sent Over Downlink

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8.3.2.10 8B/10B Reverse Downlink for Asymmetric Q-Port

1716 8B/10B Reverse Downlink for an Asymmetric Q-Port shall operate similarly to the regular 8B/10B Downlink
1717 for an Asymmetric Q-Port, except as stated below in this Section.
8.3.2.10.1 Reverse Downlink Scrambler for Asymmetric Q-Port
1718 When using the 8B/10B PCS to implement the Reverse Downlink, the Scrambler shall be implemented using
1719 the Uplink Scrambler LFSR specified in Section 8.3.2.3.
8.3.2.10.2 “Reverse Downlink” JITC Re-Training
1720 A Reverse Downlink receiver (i.e., the RX function located at the Source side) shall not initiate Re-Training
1721 requests towards the Sink.
1722 When the Sink (i.e., the Downlink RX function) requires a Downlink Re-Training, it shall trigger a
1723 Continuous Re-Training Request (RTR) sequence, sent over the Reverse Downlink until it detects a
1724 Downlink ISS sequence or an Idle.
1725 The continuous Re-Training Request (RTR) sequence shall include back to back transmission of A-Packets
1726 using the format shown in Figure 79.
1727 When the Sink recovers its ability to receive the sCMax sub-Constellation over the Downlink, it shall send
1728 an sCMax Request over the Reverse Downlink using the format shown in Figure 80.

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8.3.3 Repetitive Scrambler Reset for Test (RSRT) Mode

1729 The Repetitive Scrambler Reset for Test (RSRT) mode is intended to assist with compliance tests. It defines
1730 well-synchronized reset points for the scrambler, which makes it easier to prepare and store a fixed pattern
1731 and transmit it repeatedly during the test (58-bit scrambler repetition will take too long).
1732 In RSRT mode, the scrambler shall reset to all-ones (i.e., all 58 bits are set to one) at the following points:
1733 • First Reset Point: On the transition from Idle to Normal modes of the Startup sequence.
1734 • Next Reset Point: On every 2N symbols counted from the First Reset Point.
1735 These reset points are detailed in the following sub-sections.
1736 RSRT mode may only be selected if the RSRT_ST in the Register FEATURE_CAP is set to 1 (see Table 113).
1737 If field RSRT_ST is set to 1, then setting field RSRT_EN in Register FEATURE_CTRL shall enable the RTRS
1738 mode (see Table 114).
8.3.3.1 First Reset Point
1739 The First Reset Point where the scrambler shall be reset during RSRT mode is the transition point from Idle
1740 Mode to Normal Mode during the Startup sequence:
1741 • For PAM-X (Downlink): Upon detection of four Inverted-Idle Symbol and four Idle Symbol
1742 sequence (see Figure 56 and Figure 57) at the last Idle Symbol.
1743 • For NRZ (Uplink / Downlink): Upon detecting the First In-Normal Startup Control Sequence, after
1744 the second CN2: NML (see Figure 67).
1745 The First Reset Point shall also be used for symbol counting reference. The symbol count shall reset to zero
1746 at this point and incremented with each symbol from this point and on.
8.3.3.2 Next Reset Point
1747 The Next Reset Points where the scrambler shall be reset during RSRT mode are every 2 N symbols from the
1748 First Reset Point. The scrambler shall be reset at the last symbol of the 2N symbol sequence so the first symbol
1749 of the next 2N symbol sequence is scrambled with the seed value. The default value of N is 21, and is
1750 configured with field RSRT_NVAL in Register FEATURE_CTRL.

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8.3.4 Startup Procedure

1751 Two types of Startup procedures are defined:
1752 • “Mission Mode” Startup: A connection-oriented startup procedure where every successful state
1753 transition is triggered by a response from the Link partner. This startup type is used for the actual
1754 operation. See Section 8.3.4.1.
1755 • Unidirectional Startup: A connectionless startup procedure where all transitions are time-based,
1756 triggered by the Source without relying on the Sink’s responses. The Sink shall keep up with the
1757 startup sequence, with or without its own transmission. This type of startup is used for special test
1758 modes that aim to test Receiver PMD performance. See Section 8.3.4.2.
1759 The Downlink direction (Source to Sink) may be implemented using either 8B/10B PAM-X Single Lane PCS
1760 or PAM-X Dual Lane PCS.
1761 The Uplink direction (Sink to Source) shall be implemented:
1762 • For Single Lane ports: Using 8B/10B Uplink PCS
1763 • For Q-Ports with Dual Lane Highly Asymmetric modes: Using 8B/10B Uplink PCS over Lane 0
1764 • For Q-Ports with Asymmetric modes: Using Uni-directional Reverse Downlink 8B/10B PCS over
1765 Lane #1
1766 • For Q-Ports with Symmetric modes: Using Uni-directional Reverse Downlink PAM-X Single
1767 Lane PCS over Lane #1
1768 In this section, the meaning of the term K-Sequence depends upon the coding:
1769 • For 8B/10B PCS Uplink / Downlink / Reverse Downlink, the definition in Section 8.3.1.9 applies
1770 • For PAM-X, the definition from Section 8.3.1.5 applies
1771 A Port or Lane is considered to be in a Silent State when not transmitting any signal.

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8.3.4.1 “Mission Mode” Startup Procedure
Source Sink
S S S Silent
Channel Solved &

T Clock Recovered Training
T without K
sequences
Channel
Solved &
Descrambler
T*
Locked
Training
T* with K
sequences
T* Token/10b-Symbol Boundaries &

Descrambler
Locked
I Idle
Idle Detected
I
N Normal
I Idle Detected
Normal
Detected
N
N
1772
Figure 81 Typical Startup Procedure
1773 In a typical startup procedure, the Source acts as the Primary Clock and the Sink acts as the Secondary Clock.
1774 The typical startup procedure, illustrated in Figure 81, consists of the following steps:
1775 1. While in Silent State, the Source shall verify that the Sink is also in Silent state.
1776 2. Using its own reference clock, the Source shall start transmission of the Downlink training
1777 sequence without K-Sequences.
1778 3. The Sink’s Downlink receiver shall detect the received signal, recover the clock, and solve the
1779 channel for sufficient quality. Then, using the recovered clock, it shall start transmission of the
1780 Uplink / Reverse Downlink training sequence with K-Sequences.
1781 4. The Source’s Uplink / Reverse Downlink receiver shall detect the received signal, solve the
1782 channel for sufficient quality, and then lock its Uplink descrambler by resolving polarity if needed.
1783 Then it shall reflect the Downlink K-Sequences into the Downlink training sequence it is already
1784 transmitting. One reflected K-Sequence shall be sent each time the Source’s Uplink / Reverse
1785 Downlink receiver detects a K-Sequence.

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1786 5. The Sink’s Downlink receiver:

1787 A. Shall use these incoming reflected K-Sequences to resolve token/10b-Symbol boundaries and
1788 polarity swaps, shall compute ‘Min Link RTD’, and shall lock its descrambler;
1789 B. At this stage the Sink’s descrambler is locked, so it can predict all data arriving from the
1790 Source (if Sink doesn’t transmit K-Sequences, then the Source will also not reflect them), the
1791 Sink’s Downlink receiver may now request the Source to reduce its nominal TX amplitude to
1792 half (using the DHA Uplink Startup Control Sequence per Section 8.3.2.6).
1793 C. In such a case, the Source upon reception of the DHA Startup Control Sequence shall reduce
1794 its amplitude to half while continuing with its training sequence transmission. The Source
1795 shall complete such amplitude reduction, reaching a stable half amplitude, within 250 µS
1796 from the DHA Startup Control Sequence reception.
1797 D. If the Sink fails to recover its good operating point after such change in Source amplitude,
1798 then it shall reset the start-up procedure. Otherwise, the Sink’s Uplink / Reverse Downlink
1799 transmitter shall transition from Training Mode to Idle Mode as specified in Section 8.3.2.7.
1800 6. The Source’s Uplink / Reverse Downlink receiver shall detect the Uplink / Reverse Downlink Idle
1801 sequence, and then its Downlink transmitter shall transition from Training Mode to Idle Mode as
1802 specified in Section 8.3.2.7 for 8B/10B and in Section 8.3.1.5 for PAM-X.
1803 7. The Sink’s Downlink receiver shall detect the transition into Idle Mode, and then its Uplink /
1804 Reverse Downlink transmitter shall transition from Idle Mode to Normal Mode as specified in
1805 Section 8.3.2.8. A Port transitioning into Normal Mode means that the Port is now ready to receive
1806 data packets.
1807 8. The Source’s Uplink / Reverse Downlink receiver shall detect the Sink’s transition into Normal
1808 Mode, and then its Downlink transmitter shall transition from Idle Mode to Normal Mode as
1809 specified in Section 8.3.2.8 for 8B/10B and in Section 8.3.1.6 for PAM-X, concluding successful
1810 startup. The Source shall not send data packets towards the Sink before concluding successful
1811 startup.
1812 9. The Sink’s Downlink receiver shall detect the Source’s transition to Normal Mode, which
1813 concludes successful startup. The Sink shall not send Data Packets to the Source until and unless
1814 startup concludes successfully.
1815 Table 54 summarizes Handshake Indications between the Link partners:
1816 • Starting at Step 3, where both partners are transmitting, the absence of the receive signal for
1817 SILENTDETT shall be considered as an indication that the Link partner has entered a Silent State.
1818 • If the Source detects that the Sink entered Silent State, then the Source shall first enter Silent State
1819 for a period of at least MINSILENTT, and then start over. If the Sink detects that the Source entered
1820 Silent State, then the Sink shall also enter Silent State and then wait for the Source to start over.
1821 • If the Source did not reach completion of step 4 within a period of MAX4COMP T after its start of
1822 transmission in step 2, then the Source shall restart the procedure by entering Silent State.
1823 • If the Source did not reach completion of step 8 within a period of MAX8COMPT after its start of
1824 transmission in step 2, then the Source shall restart the procedure by entering Silent State.
1825 • If a Link partner identifies a non-recoverable error condition during startup or normal operation, then
1826 it shall restart the startup procedure by entering Silent State and then waiting for its Link partner to
1827 also enter Silent State.

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1828 Table 54 Handshake Indications for Typical Startup (Summary)

Direction
Step Indication’s Meaning Comment
Source to Sink Sink to Source
2 Start of Transmission – Startup Procedure started –
Start of K-Sequence Reception is good, ready

3 – –
Transmission to receive K-Sequence
Reception is good, de-

PAM-X Sink measures
4 K-Sequence Reflection – scrambler is locked, ready
Link RTD
for Idle mode
Sink may use

Optional: For Downlink, Half of
Source shall
5 – DHA Startup Control nominal Amplitude is
accommodate when
Sequences requested by the Sink
requested
De-scrambler is locked,
In Idle Startup Control Token Boundaries solved,
5 – –
Sequences ready for the transition into
Idle mode
Transition into Idle Mode Moved into Idle mode

sequence (moved to 16b per 8b10B Sink measures Link
6 –
(“Reflected” when Sink’s scrambler period in RTD
“In Idle” detected) PAM-X)
Successfully moved to Idle

In Normal Startup Control
7 – Mode, ready to receive –
Sequences
A-Packets
Transition into Normal Ready to receive

8 – –
Mode sequence A-Packets
1829 Table 55 Time Periods for Startup Procedures

Period Value
Name Description
(mS)
SILENTDETT Silent State detection period 0.1
MINSILENTT Minimum time in Silent State 0.5
MAX4COMPT Maximum Time for Step 4 Completion 50
MAX8COMPT Maximum Time for Step 8 Completion 100

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8.3.4.2 Unidirectional Startup Procedure

1830 The Unidirectional startup procedure illustrated in Figure 82 consists of the following steps:
1831 1. While in Silent State, the Source shall verify that the Sink is also in Silent state.
1832 2. Using its own reference clock, the Source shall start transmission of the Downlink training
1833 sequence without K-sequences, and reset its T2KT timer to the value in Table 56.
1834 3. When the T2KT timer expires, the Source shall add the Downlink K-Sequences to the Downlink
1835 training sequence that it is already transmitting, and shall reset its T2IT timer to the value in Table
1836 56.
1837 4. When the T2IT timer expires, the Source Transmitter shall transition from Training Mode to Idle
1838 Mode, followed by the Idle sequence, and shall then reset its T2NT timer to the value in Table 56.
1839 5. When the T2NT timer expires, the Source Transmitter shall transition from Idle Mode to Normal
1840 Mode, which concludes a successful startup.
1841 Table 56 Timer Values for Unidirectional Startup Procedure
Timer Value
Name Description
(mS)
T2KT Time to K 50
T2IT Time to Idle 30
T2NT Time to Normal 10
1842 During the above procedure, the Sink Receiver shall follow the sequence and reach successful normal
1843 operation.
1844 If the Sink was instructed (per Section 9.1.2.6) to perform Unidirectional startup with Sink transmission, then
1845 it shall add its own Uplink transmission as specified in the Mission Mode Startup Procedure (Section 8.3.4.1).
1846 If the Sink was instructed to perform Unidirectional startup without Sink transmission, then it shall be in
1847 Silent State at all times.
1848 If the Sink detects that the Source entered Silent State, then the Sink shall also enter Silent state and then wait
1849 for the Source to start over.
1850 In the case of a Unidirectional Startup with Sink transmission (per step 3), if the Source detects that the Sink
1851 entered Silent State, then the Source shall first enter Silent State for a period of at least MINSILENTT, and
1852 shall then start over.

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Source Sink
S S S Silent
T Channel Solved
Training
T without K
sequences
Time to K
Passed
T*
Training
T* with K
sequences
T* Token Boundaries &

Descrambler
Locked
I Idle
Time to Idle
Passed I
N Normal
I Idle Detected
Time to Normal
Passed
N
N
1853
Figure 82 Unidirectional Startup Procedure

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9 PMD Electrical Specification

1854 This section contains the electrical specifications for A-PHY’s three Physical Media Dependents (PMDs):
1855 1. PAM-X PMD: Downlink operates at 4 GBaud.
1856 2. NRZ PMD: Downlink operates with NRZ modulation and 8B/10B encoding (10b symbols) at
1857 2 Gbps, 4 Gbps, and optionally 8 Gbps.
1858 3. Uplink PMD: Operates at 100 Mbps NRZ or 200 Mbps PAM4 modulated 8B/10B encoding (10b
1859 symbols).
1860 Each PMD implementation shall comply both with all general requirements in each sub-section, and with
1861 any special consideration(s) relevant for that particular PMD (e.g., LFSR output usage for PAM-X PMD).
9.1 TX Electrical Specification

1862 The Transmitter electrical specifications are defined at the TPA conformance point as shown in Figure 83,
1863 and shall be measured using the normative Test Modes, Test Fixture, Test Procedures, and post-processing
1864 routines contained in this section.
TX DUT
A-PHY PCB Circuitry

Capturing Device
Source (CMC, ESD, Filter,
1865 TPA
Figure 83 TPA Conformance Point
1866 In this section, the term SRG is the Transmitter’s symbol rate divided by 109. For example, for the Downlink,
1867 the SRG of G1 is 2, SRG of G2 is 4, and SRG of G5 is 4. For the Uplink, SRG is 0.1 for all Gears.

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9.1.1 Test Mode Pattern Generator (TMPG)

1868 The Test Mode Pattern Generator (TMPG) shall continuously use the LFSR shown in Figure 84 to generate
1869 a repeating pseudo-random sequence of TMP_LEN TMPG_Periods.
𝐺(𝑥) = 1 + 𝑥17 + 𝑥 20
+
S00 S01 S02 S16 S17 S18 S19

1870
Figure 84 Test Mode Pattern Generator LFSR
1871 In using the LFSR:

1872 • The initial seed value shall be 20’hFFFFF (i.e., all ones)
1873 • The TMPG_Period is defined as a ‘Symbol period’ for PAM-X PMD, and as a ‘10b Symbol period’
1874 for the other PMDs.
1875 • The LFSR shall be reset to the initial seed value (i.e., all ones, 20’hFFFFF) after TMP_LEN
1876 TMPG_Periods.
1877 • For NRZ/Uplink PMD: For each TMPG_Period (n), the first 8 bits of the LFSR S[00:07] (note, S[07]
1878 is the LSB of this 8-bit value) shall be used to encode the 10b symbol, via 8B/10B encoding, and
1879 then the LFSR shall produce the next 8 bits, to be stored in S[00:07] for use in the next 10b symbol
1880 period.
1881 • For PAM-X PMD: For each TMPG_Period (n), bits S[12:15] of the LFSR seed (note, S[15] is the LSB
1882 of this 4-bit value) shall be used to encode the sub-constellation symbol for Lane 0 as shown in
1883 Table 57. For Dual Lane PAM-X, bits S[08:11] of the LFSR seed shall be used to encode the sub-
1884 constellation symbol for Lane 1, and then the LFSR shall produce the next 16 bits, to be stored in
1885 S[00:15], for use in the next symbol period. (Note that only the LSBs of these 16 bits will be actually
1886 used: the 4 LSBs for Single Lane, or the 8 LSBs for Dual Lane.)
1887 • For PAM-X PMD: The TMPG shall generate a cycle comprising two TMP_LEN TMPG_Periods
1888 sequences, where in the first TMP_LEN TMPG_Periods sequence the TMPG shall encode
1889 sub-constellation symbols using normal polarity, while for the second TMP_LEN TMPG_Periods
1890 sequence the TMPG shall encode sub-constellation symbols using reverse polarity (i.e., ensuring the
1891 cycle’s zero DC).
1892 For PAM-X PMD: LFSR output usage:

1893 • The PHY shall use the symbols shown in Table 57 per symbol period
1894 • The bit sequences shown in Table 57 shall be used to generate the constellation symbols.
1895 Table 57 PAM-X Test Mode Pattern Generator LFSR Bit Allocation for Sub-Constellation
LFSR Bits for Lane 1 LFSR Bits for Lane 0
S08 S09 S10 S11 S12 S13 S14 S15
SC1616 b3 b2 b1 b0 b3 b2 b1 b0
SC816 – b2 b1 b0 – b2 b1 b0
SC416 – – b1 b0 – – b1 b0
SC216 – – – b0 – – – b0

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9.1.1.1 LFSR Usage Example

1896 The following example demonstrates the usage of the LFSR.
1897 • The LFSR output for the first 5 symbols periods is shown in Table 58.
1898 Table 58 LFSR Output of First 5 Symbol Periods
LFSR S00 S01 S02 S03 S04 S05 S06 S07 S08 S09 S10 S11 S12 S13 S14 S15
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
3 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0
4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0
5 0 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0
1899 • sC1616 coding is shown in Table 59 and Table 60.

1900 Table 59 PAM-X Single Lane sC1616 Coding
Symbol Level
LFSR / During During

S12–S15 Cycle’s 1st Cycle’s 2nd
Period
TMP_LEN TMP_LEN
Period Period
1 1111 −5 5
2 0000 15 −15
3 1110 −7 7
4 1100 −1 1
5 1000 −15 15
Table 60 PAM-X Dual Lane sC1616 Coding
Lane 1 Lane 0
Symbol Level Symbol Level

During
LFSR / During During During
S08–S11 S12–S15 Cycle’s
Period Cycle’s 1st Cycle’s 2nd Cycle’s 1st
2nd
TMP_LEN TMP_LEN TMP_LEN
TMP_LEN
Period Period Period
Period
1 1111 −5 5 1111 −5 5
2 0000 15 −15 0000 15 −15
3 0000 15 −15 1110 −7 7
4 1111 −5 5 1100 −1 1
5 0011 11 −11 1000 −15 15

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1901 • sC816 coding is shown in Table 61.

Symbol Level
LFSR / During During

S13–S15 Cycle’s 1st Cycle’s 2nd
Period
TMP_LEN TMP_LEN
Period Period
1 111 −7 7
2 000 15 −15
3 110 −3 3
4 100 −15 15
5 000 15 −15

Symbol Level
During During
LFSR S14–S15 Cycle’s 1st Cycle’s 2nd
TMP_LEN TMP_LEN
Period Period
1 11 −5 5
2 00 15 −15
3 10 −15 15
4 00 15 −15
5 00 15 −15

Symbol Level
During During
LFSR S15 Cycle’s Cycle’s
1st 2nd
TMP_LEN TMP_LEN
Period Period
1 1 −sC2Lvl sC2Lvl
2 0 sC2Lvl −sC2Lvl
1907 Note that sC2Lvl is Gear-dependent, as shown in Table 34.

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9.1.2 Test Modes

9.1.2.1 TM1: Test Mode 1: Transmit PSD
1908 This test shall be used to validate a Transmitter is conforming with the transmit PSD mask.
1909 When TM1 is enabled, the PHY shall continuously transmit the test mode pattern generator sequence, with:
1910 NRZ/Uplink: TMP_LEN = 217
1911 PAM-X PMD: TMP_LEN = 220, at sC216
9.1.2.2 TM2: Test Mode 2: Droop

1912 This test shall be used to validate Transmitter droop.
1913 When TM2 is enabled, the PHY shall continuously transmit a pattern of 128 nS of ‘+(peak TX amplitude)’
1914 symbols followed by 128 nS of ‘−(peak TX amplitude)’ symbols.
1915 The amplitude is measured at 20 ns after zero crossing and at 100 ns after zero crossing (see Figure 85).
128ns 128ns
VH20 VH100
VL20 VL100
1916
Figure 85 Test Mode 2
9.1.2.3 TM3: Test Mode 3: Transmit Jitter

1917 This test shall be used to validate Transmitter jitter.
1918 When TM3 is enabled, the PHY shall continuously transmit a pattern of one ‘+(peak TX amplitude)’ symbol
1919 followed by one ‘–(peak TX amplitude)’ symbol.
9.1.2.4 TM4: Test Mode 4: Transmit Linearity

1920 This test shall be used to validate Transmitter linearity.
1921 When TM4 is enabled, the PHY shall continuously transmit the test mode pattern generator sequence, with:
1922 NRZ/Uplink: TMP_LEN = 212
1923 PAM-X PMD: TMP_LEN = 215, at the highest supported sub-constellation

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9.1.2.5 TM5: Test Mode 5: In Silent State

1924 This test shall be used to validate End Node’s RL/XTalk/etc. for limit lines conformance testing as in
1925 Section 6.6.3, primarily to ensure that the PHY‘s “mission mode” Complex Impedance (i.e., the combined
1926 effect of resistive, inductive, and capacitive impedance components) is presented during the test.
1927 When TM5 is enabled, the PHY shall be powered on, presenting its “mission mode” Complex Impedance
1928 towards the data line, without transmitting any signal (i.e., Silent State).
9.1.2.6 TM6: Test Mode 6: Unidirectional Startup

1929 When TM6 is enabled, the Source shall initiate the Unidirectional Startup Procedure as specified in
1930 Section 8.3.4.2, during which it shall ignore any transmission sent over the Uplink by its Link partner.

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9.1.3 Transmitter Power Spectral Density Mask

9.1.3.1 Requirement
1931 When working in TM1, capturing the TX signal and calculating its PSD, per the processing procedure listed
1932 below, the “max hold power spectral density” of the Transmitter shall be between the Upper and Lower PSD
1933 limits for the selected PMD per sub-section below. The same PSD limits are used for both 50 Ω Coax and
1934 100 Ω Differential channels.
1935 Informative:
1936 Table 64 shows the nominal TX Amplitudes to meet these PSD limits over 50 Ω Coax channel, per
1937 Gear and per Direction.
1938 Table 64 Nominal TX Amplitude Over Coax, Per Gear, Per Direction (Informative)
Nominal Downlink Amplitude Nominal Uplink Amplitude
Gear
(mVpp) (mVpp)
1 250 500
2 350 500
3 250 500
4 500 250
5 500 250
Exception case for Optional mode G3, 8 Gbps, 8B/10B NRZ:
3 500 500
1939 When operating over 100 Ω Differential channel, 3 dB higher (than the Coax’s amplitude) amplitude
1940 is used to meet the same PSD limits.
1941 In DHA (Downlink Half Amplitude) mode the amplitude is 6 dB lower compared to nominal
1942 amplitude.
1943 Normative:
1944 Common Mode PSD Limit: For differential channels, both Differential and Common modes of the
1945 TX signal shall be captured and processed in the same manner. The “max hold power spectral
1946 density” per PSD point of the common mode signal shall be below the specified Upper PSD limit (in
1947 dBm/Hz) of the differential signal, at least by the Unbalanced Attenuation limit (UA in dB).
1948 The PSD mask is defined for the nominal amplitude; for DHA mode, the PSD mask shall be 6 dB
1949 lower.
1950 For Q-Port, the Downlink / Reverse Downlink TX differential and common PSD per Pair, per
1951 PMD/Gear, shall comply with the Nominal PSD limits for the selected PMD/Gear when reducing
1952 3 dB from the nominal limits for G1, G2, G4, and G5 (no change for G3 PSD limits).

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9.1.3.1.1 NRZ PMD PSD Limits

1953 SRG-normalized upper and lower PSD limits for NRZ PMD are specified in Table 65 and Table 66.
1954 Table 65 NRZ PMD Upper PSD Limit
(MHz) (dBm/Hz)
10 * SRG / 4 −108
100 * SRG / 4 −97.5
350 * SRG / 4 −93
800 * SRG / 4 −92
1250 * SRG / 4 −92
4000 * SRG / 4 −104
1955 Table 66 NRZ PMD Lower PSD Limit

(MHz) (dBm/Hz)
400 * SRG / 4 −100
1400 * SRG / 4 −100
1956 To compute Limit values for intermediate frequencies, linear interpolation with linear frequency axis shall
1957 be done (i.e., vertices are connected with straight lines at a linear frequency axis).
1958 Per-Gear upper and lower PSD limits for NRZ PMD are shown in Figure 86.
1959
Figure 86 NRZ PMD: Upper & Lower PSD Limits

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9.1.3.1.2 Uplink PMD PSD Limits

1960 Upper and lower PSD limits for Uplink PMD are specified in Table 67 and Table 68.
1961 Table 67 Uplink PMD Upper PSD Limit
(MHz) (dBm/Hz)
0.25 −89
2.5 −78.5
10 −74
20 −73
31.25 −73
62.5 −80
100 −100
1962 Table 68 NRZ PMD Lower PSD Limit

(MHz) (dBm/Hz)
10 −81
35 −81
1963 To compute Limit values for intermediate frequencies, linear interpolation with linear frequency axis shall
1964 be done (i.e., Vertices are connected with straight lines at a linear frequency axis)
1965 For G4 and G5, PSD limit lines shall be 6 dB lower than specified in Table 67 and Table 68.
1966 Upper and Lower PSD limits for Uplink PMD for G1, G2, and G3 are shown in Figure 87.

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1967
Figure 87 Uplink PMD Upper & Lower PSD Limits: Gears #1–#3

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9.1.3.1.3 PAM-X PMD PSD Limits

1968 Upper and lower PSD limits for PAM-X PMD are given by the following equations:
1969 FCORNER_MHZ = 1000 * SRG/4
−92 dBm/Hz 0 < F ≤ FCORNER_MHZ

1970 Upper PSD (FMHz) ≤ { FMHZ−FCORNER_MHZ
−92 − (4 ∗ ) dBm/Hz FCORNER_MHZ < F ≤ 4000
FCORNER_MHZ
1971 Lower PSD (FMHz) ≤ −98 dBm/Hz 4 < F ≤ FCORNER_MHZ
1972 For G3 to G5, SRG = 4. Upper and Lower PSD limits are Gear-dependent: for G3, both of the limit lines
1973 specified by the equations above shall be further reduced by 3.5 dB, as shown in Figure 88.
1974
Figure 88 PAM-X PMD Upper & Lower PSD Limits
1975 When using the Normative-Optional operating mode of PAM-X sC4 for G1 / G2, PSD limits shall be
1976 computed per the equations above, with SRG = 1 for G1, and SRG = 2 for G2.

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9.1.3.2 Processing Procedure

1977 Steps:
1978 1. Capture a 512 µS block of consecutive symbols with at least 8-times oversampling.
1979 2. Compute the transmit PSD (Power Spectral Density) using RBW of 120 kHz.
1980 3. Perform steps #1 and #2 an additional 7 times (for a total of 8 times) and perform “Max Hold”
1981 function per PSD point (i.e., select the maximum value per PSD point, out of the 8 PSD results).
9.1.3.2.1 Matlab Example Code (Informative)
1982 The following example Matlab code illustrates PAM-X TM1 pattern generation and PSD computation on a
1983 per-Gear basis.
1984 %Generate Test Mode 1 Per Gear, 2^21-2 sC2 balanced sequence
1985 clear all
1986 sc2Gear123=[15,-15];
1987 sc2Gear45=[11,-11];
1988
1989 Gear = 5; %Select Gear: 3 to 5
1990
1991 %select sC2 levels, amp and Baud per selected Gear
1992 if(Gear > 3),
1993 sc2 = sc2Gear45;
1994 AmpPeak = 0.25; % 500mV peak to peak, nominal for Gears #4 and #5
1995 Baud = 4;
1996 else
1997 sc2 = sc2Gear123;
1998 AmpPeak = 0.125; % 250mV peak to peak, nominal for Gears #1, #2 and #3
1999 Baud = 4;
2000 end
2001
2002 %2^20-1 symbol sequence used once at positive polarity and then in negative polarity to
2003 ensure zero DC
2004 scr=ones(1,20);
2005 TMP_LEN=2^20-1;
2006 scrN=zeros(TMP_LEN,20);
2007 for nn=1:TMP_LEN,
2008 scrN(nn,:)=scr;
2009 scr = [mod(scr([1:16]+4)+scr([1:16]+1),2),scr(1:4)];
2010 end
2011 sc2Ai = scrN(:,[4]+12);
2012 sc2Asymb = sc2(sc2Ai+1);
2013 Aseq21 = [sc2Asymb';-sc2Asymb'];
2014 %End of Test Mode 1 Generation
2015
2016 %calc PSD
2017 Fs=32;
2018 Imped=50;
2019 NBIN=32*8192; % to match 122kHz BIN width
2020 NLen=4*128*Baud*1000;% 4*128 µS of symbols per Baud
2021 %TX Lowpas generation
2022 [b,a]=butter(1,2.5/(Fs/2));
2023
2024 %TX PSD Limits
2025 FMask = [0,1e9,4e9];
2026 VMask = [-92,-92,-104];
2027
2028 FLowMask = [4e6,1e9];
2029 VLowMask = [-98,-98];
2030
2031 %for Gears #1, #2 and #3 reduce PSD limits by 3.5dB
2032 if(Gear < 4),
2033 VMask = VMask - 3.5;
2034 VLowMask = VLowMask - 3.5;
2035 end

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2036
2037 PP=zeros(1,(NBIN/2+1));
2038 for nn=1:8,
2039 nn,
2040
2041 %TM1 2^21 sC2 pattern
2042 rr = 1/15*AmpPeak*repmat(circshift(Aseq21,round(rand(1,1)*(2^20-1))),...
2043 ceil(NLen/length(Aseq21)),1);
2044 rr = rr(1:NLen);
2045 rr4=repmat(rr,1,Fs/Baud);rr4=rr4';rr4=rr4(:);
2046 [Pt21,F]=psdBmHz_pwelch(filter(b,a,rr4),NBIN,Fs*1e9,Imped);
2047
2048 PP=max([PP(:)';Pt21']); % "Max Hold"
2049 end
2050 figure(1);clf;
2051 plot(F/1e9,10*log10([PP]),FMask/1e9,VMask,'r-',FLowMask/1e9,VLowMask,'k-');
2052 xlabel('F [GHz]');ylabel('PSD [dBm/Hz]')
2053 legend(['TM1 Gear #',num2str(Gear),' TX PSD'],'PSD Mask Upper Limit',...
2054 'PSD Mask Lower Limit','Location','NE');
2055 axis([0 8 -140 -80]);grid on;
2056 title(['TM1 over Coax at ',num2str(Baud),'GBaud Gear #',num2str(Gear),...
2057 ', Amp: ',num2str(AmpPeak*2*1e3),'mVpp, TX PSD']);shg
2058 The above Matlab code uses the function psdBmHz_pwelch, which is not a native Matlab function. It is
2059 provided below:
2060 function [P,F]= psdBmHz_pwelch(Sig,N,WFS,Zohm);

2061
2062 nfft=N;
2063
2064 w=hann(round(min(nfft/2,length(Sig)/2)));
2065
2066 [P,F]=pwelch(Sig,w,[],nfft,WFS);
2067
2068 P=P/sum(P)*mean(Sig.^2)/Zohm/0.001/mean(diff(F));
2069 The resulting figures should resemble the examples shown in Figure 89 and Figure 90.

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2070
Figure 89 Example Matlab Figure #1
2071
Figure 90 Example Matlab Figure #2

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9.1.4 Transmitter Maximum Output Droop

9.1.4.1 Requirement
2072 When working in TM2, capturing and calculating the droop per the Processing Procedure listed below, the
2073 magnitude of both the positive and negative droop shall be less than 22%.
2074 For Q-Port, the Droop limit shall be met for each pair separately.
2075 Steps:
2076 1. Find the rising-edge zero-crossing in the waveform (Vhigh reference zero-crossing).
2077 2. Measure the amplitude at 20 nS after the reference zero-crossing (V20).
2078 3. Measure the amplitude at 100 nS after the reference zero-crossing (V100).
2079 4. Compute the positive droop as: (1 − V100/V20) * 100
2080 5. Repeat using the falling edge zero-crossing reference to calculate the negative droop.

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9.1.5 Transmitter Timing Jitter

9.1.5.1 Requirement
2081 When working in TM3, capturing the “Clock Patterned” TM3 Signal and calculating its jitter per the
2082 Processing Procedure listed in Section 9.1.5.2, the average P2P Tj of 10 x [1MJSamples (1M Jitter Samples)
2083 captures] shall be less than the per-Gear limit shown in Table 69.
2084 Table 69 Transmitter Timing Jitter Requirements
Average P2P Tj Equivalent RMS
Out of 10 Captures of a Tj Comprising Only
Gear of 1MJSamples Each Pure RJ (P2P / 9.75)
(pS) (pS)
Normative Informative
1 64 6.56
2 32 3.28
3 19.5 2
4 13.8 1.41
5 9.75 1
Uplink
3500 359
(All Gears)
2085 For Q-Port, the Timing Jitter limit shall be met for each pair separately. When operating with a Dual Lane
2086 transmitter, the pair under test shall transmit TM3 and the untested Pair shall transmit TM1.
2087 Steps:
2088 1. Capture 10 captures of the transmitted clock pattern, with 10 times oversampling each, that would
2089 allow for a calculation of 1M (106) Jitter Samples per capture.
2090 2. For each such capture, perform the following:
2091 A. Pass the captured signal through a single-pole High-Pass Filter at:
2092 i. For PAM-X Gears: Use pole frequency of Baud/20.
2093 E.g., for 4 GBaud, HPF is at 200 MHz.
2094 ii. For 8B10B Gears: Use pole frequency of Baud/160.
2095 E.g., for 4 GBaud, HPF is at 25 MHz.
2096 B. Compute the Time series (Ts) of the High-Pass filtered signal, 1M zero crossings locations
2097 (use linear interpolation between captured samples for accurate computation of zero-crossing
2098 times)
2099 C. Compute the Average UI as the average of the 1M−1 differences between two adjacent Ts
2100 locations (Ts(n+1) − Ts(n))
2101 D. Compute Nominal Ts (NomTs) by starting from NomTs(1) = Ts(1) with constant difference,
2102 between adjacent locations of Average UI (NomTs(n+1) − NomTs(n) = Average UI)
2103 E. Compute the jitter vector, Tj, as the difference vector of (Ts(n) − NomTs(n))
2104 F. Pass the resulted Tj jitter vector through a single-pole High-Pass filter at Baud/2500 to
2105 account for CDR tracking BW. E.g., for 4 GBaud, HPF is at 1.6 MHz.
2106 G. Compute the Peak-to-Peak of the resulted Tj jitter as P2P = max(Tj) − min(Tj)
2107 3. Average the 10 P2P results computed for the ten captures.

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9.1.6 Transmitter Symbol Rate Accuracy

2108 The Transmitter long term average symbol rate accuracy shall be ±100 ppm of its nominal symbol rate.
9.1.7 NRZ Downlink Transmitter Eye Opening

9.1.7.1 Requirement
2109 When working in TM4, 1M Symbols (i.e., 106) of the pseudo-random signal are acquired and post-processed
2110 per the procedure listed in Section 9.1.7.2. The Eye Opening shall meet the per-Gear octagonal mask limits
2111 shown in Table 70.
2112 Table 70 NRZ Downlink Eye Mask Parameters
NRZ EW EH ERW ERH
Downlink (UI) (mV) (UI) (mV)
Gear 1 0.80 215 0.33 200
Gear 2 0.80 280 0.40 220
Gear 3
0.65 290 0.42 200
(optional)

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2113 Steps:
2114 1. Capture 1M Symbols (106) of the transmitted pseudo-random pattern, with a sufficient
2115 oversampling rate per Gear so that the acquired signal is a true representation of the real signal.
2116 2. Compute the Eye Diagram by superimposing multiple time slices of the captured pattern with
2117 which slicing a multiple of the average unit interval (UI) while accounting for a reference, first
2118 order CDR tracking BW With corner frequency at Baud/2500.
2119 3. Check that the Eye Diagram does not touch the mask, except for a single violating transition
2120 which is allowed.
Level
One
EH
ERH
EW ERW
Level
Zero
2121
Figure 91 NRZ Downlink Transmitter Eye Diagram
2122 In the Figure 91 Eye Diagram:
2123 • EW is a representation of the horizontal opening of an eye diagram, and is measured at the voltage
2124 level that maximizes the reading. For a differential signal, that level is usually the differential zero
2125 crossing.
2126 • EH is a representation of the vertical opening of an eye diagram, and is measured between the
2127 minimum One Level and maximum Zero Level at a time instant that maximizes the reading.
2128 • ERW is a representation of the horizontal width of the embedded rectangle in the octagon mask.
2129 • ERH is a representation of the vertical height of the embedded rectangle in the octagon mask.

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9.1.7.3 NRZ Jitter (Informative)

2130 A-PHY Tx requirements for jitter in Gear 1 and 2 are defined for both transmitter timing jitter
2131 (see Section 9.1.5) and the NRZ transmitter eye opening (see Section 9.1.7). For both definitions,
2132 implementers can allocate Deterministic Jitter (DJ) and Random Jitter (RJ) components according to their
2133 needs. In this section, the examples of what components are included in each jitter definition are informative.
2134 While TM3 captures the clock pattern, which removes Data-Dependent Jitter contribution and additionally
2135 uses a Baud/160 highpass filter (HPF) which attenuates lower-frequency contribution, there may still be
2136 residual DJ components, such as Duty-Cycle Distortion (DCD), Power Supply Induced Jitter (PSIJ), and
2137 Periodic Jitter (PJ).
2138 In TM4 the PHY generates a Pseudo-Random pattern, and the Total Jitter is often associated with this pattern.
2139 All DJ components are included in this mode. As described in Section 9.1.5 on transmitter timing jitter, the
2140 Total Jitter (TJ) of TM4 is also subjected to post-processing with a Baud/160 HPF, thus removing lower-
2141 frequency jitter contribution.
2142 Table 71 Jitter Components in TM3 and TM4
TM4
TM3
Block Jitter Type (Pseudo-Random
(Clock Pattern)
Pattern)
Reference Clock RJ X X
RJ X X
PLL DJ (DDJ) X X
DJ (PJ) X X
RJ X X
PHY DJ (DDJ) X (partially) X
DJ (PJ) X (partially) X
DJ (DDJ) – X
ENIS
DJ (PJ) X X
TJ in Gear 1 64 ps1 140 ps2
ALL TJ in Gear 2 32 ps1 70 ps2
TJ in Gear 3 – 35 ps2
2143 Note:
2144 1. Normative requirement described in Section 9.1.5.
2145 2. Informative number. BER target is 10-12. Normative requirements for TM4 eye mask are described
2146 in Section 9.1.7.
2147 3. “X” indicates that the component contributes to the jitter budget

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9.1.8 PAM-X Transmitter Linearity

9.1.8.1 Requirement
2148 When working in TM4, capturing the signal and calculating its residual distortion per the Processing
2149 Procedure detailed in Section 9.1.8.2 for at least 4 consecutive UI phases, the residual distortion’s RMS shall
2150 satisfy the equation:
𝐷𝑖𝑠𝑡𝑜𝑟𝑡𝑖𝑜𝑛𝑅𝑀𝑆
2151 𝑑𝐵 ( ) ≤ (−44 + 6 ∗ (4 − log 2 (𝑀))) 𝑑𝐵
𝐶𝑎𝑝𝑡𝑢𝑟𝑒𝑑𝑆𝑖𝑔𝑛𝑎𝑙𝑅𝑀𝑆
2152 where M is the PAM level used.
2153 In addition, the residual distortion’s Peak per phase, of these at least 4 consecutive UI phases, shall satisfy
2154 the equation:
𝐷𝑖𝑠𝑡𝑜𝑟𝑡𝑖𝑜𝑛𝑃𝑒𝑎𝑘
2155 𝑑𝐵 ( ) ≤ (−30 + 6 ∗ (4 − log 2 (𝑀))) 𝑑𝐵
𝐶𝑎𝑝𝑡𝑢𝑟𝑒𝑑𝑆𝑖𝑔𝑛𝑎𝑙𝑅𝑀𝑆
2156 where M is the PAM level used.
2157 For Q-Port, the Linearity limit shall be met for each pair separately. When operating with a Dual Lane
2158 transmitter, both pairs shall simultaneously transmit TM4 and each pair shall separately meet the Linearity
2159 limit.
2160 Steps:
2161 1. Capture at least 32 durations of TM4 cycle (i.e., 2 * TMP_LEN TMPG_Periods) of consecutive
2162 symbols with 10 times oversampling
2163 2. Pass the captured signal through a band-pass filter consisting of a first order high-pass filter at
2164 Baud/20 and a second order, anti-aliasing, low-pass filter at Baud/2 (see informative Matlab code
2165 in Section 9.1.8.2.1).
2166 3. Average the filtered signal, creating a single, averaged TM4 cycle (TM4Avg)
2167 4. Per each one of TM4Avg’s 10 UI phases (Phase N), perform the following steps:
2168 • Starting from Phase N, sample TM4Avg in UI spacing, creating TM4AvgPhaseN signal
2169 • Find the correlation between TM4 cycle data (known sequence, as defined by this
2170 specification) and TM4AvgPhaseN, and align (via circular shift) TM4 cycle data to
2171 TM4AvgPhaseN
2172 • Compute an ‘ideal’ linear canceller, trying to estimate TM4AvgPhaseN by filtering the
2173 aligned TM4 Cycle Data via a linear filter selected to minimize the mean square of the
2174 estimation error,
2175 where estimation error signal = TM4AvgPhaseN − TM4AvgPhaseNEstimation
2176 • Set ‘Residual Distortion’ signal to be equal to the estimation error signal using the best
2177 estimating linear filter, and calculate both the RMS of this signal (‘DistortionRMS’) and the
2178 Peak of this signal (‘DistortionPeak’)
2179 • Compute the ‘CapturedSignalRMS’ as equal to the RMS of TM4AvgPhaseN
2180 See informative Matlab code in Section 9.1.8.2.1.

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9.1.8.2.1 Matlab Example Code (Informative)

2181 The following example Matlab code illustrates Synthetic TX signal generation using nonlinear components,
2182 to demonstrate the operation of this post-processing function. The code assumes that the processed samples
2183 are frequency-locked to the transmit signal frequency.
2184 clear all

2185 %Generate test mode 4 for PAM16 4GSPS channel A (Lane0)
2186 %2^15 symbol sequence used ones at positive polarity and then in negative polarity to
2187 ensure zero DC
2188 sc16=[15,13,9,11,1,3,7,5,-15,-13,-9,-11,-1,-3,-7,-5];
2189
2190 scr=ones(1,20);
2191 LEN=2^15;
2192 scrN=zeros(LEN,20);
2193 for nn=1:LEN,
2194 scrN(nn,:)=scr;
2195 scr = [mod(scr([1:16]+4)+scr([1:16]+1),2),scr(1:4)];
2196 end
2197
2198 sc16A = scrN(:,[1:4]+12);
2199 sc16Ai=sc16A*(2.^[3:-1:0]');
2200 sc16Asymb = sc16(sc16Ai+1);
2201
2202
2203 tm4 = [sc16Asymb';-sc16Asymb'];
2204 Ns=length(tm4);
2205 Nc=50; % Canceller length
2206
2207 % Test mode4 matrix
2208 clear X0;
2209 for i=1:Nc
2210 X0(i,:)=circshift(tm4,1-i);
2211 end
2212
2213 %Read captured data file, high resolution capture at x10 Baud
2214 % fid=fopen('RawData.bin','r');
2215 % tx = fread(fid,inf,'double');
2216 % fclose(fid);
2217
2218 %Replacement of captured data using TX signal model with nonlinear and
2219 %Normal Noise
2220 %------------- Start of “Synthetic TX signal” Model --------------
2221 %add 10 phases;
2222 tm = repmat(tm4(:)',10,1);tm=tm(:);
2223 %Norm Amp to 0.25V
2224 tm=0.25*tm/max(tm);
2225
2226 %rep for 32 periods
2227 tx = repmat(tm(:),32,1);
2228
2229 %tx internal BW first order Low pass
2230 [B,A]=butter(1,3/10);
2231 tx=filter(B,A,tx);
2232
2233 %Static non-linear
2234 NL2 = 28; % second harmonic [dB]
2235 NL3 = 20 ; % third harmonic [dB]
2236 sNL = 10^(-NL2/20)*tx.^2 + 10^(-NL3/20)*tx.^3;
2237
2238 %Dynamic non-linear
2239 NL2 = 28; % second harmonic [dB]
2240 NL3 = 20 ; % third harmonic [dB]
2241 dNL=10^(-NL2/20)*[filter([1,0,0,0,0,-1]/2,1,tx)].^2 + 10^(-NL3/20)*[filter([1,0,0,0,0,-
2242 1]/2,1,tx)].^3 ;

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2243
2244
2245 %add Normal Noise to NL products
2246 NN = 10^(-54/20)*randn(length(tx),1) + sNL + dNL;
2247 clear sNL dNL
2248
2249 %Add all noises to tx
2250 tx = tx + NN;
2251
2252 %tx output first order Low pass at x1.5 Nyquist
2253 [B,A]=butter(1,1.5/10);
2255
2256 %----- End of “Synthetic TX signal” Model------------
2257
2258 %tx signal captured / modelled analysis starts here...
2259
2260 % (RX) "Receiver's" second order LPF at Nyquist,
2261 [B,A]=butter(2,1/10,'low');
2263
2264 % (RX) "Receiver's" first order HPF at 1/10 Nyquist
2265 [B,A]=butter(1,0.1/10,'high');
2267
2268 % Average Input to remove random noise and remove filter transitions, resulted tx is
2269 % row vector
2270 tx=mean(reshape(tx([1:length(tm4)*10*31]+2e3),length(tm4)*10,31)');
2271
2272 DistArr = []; %Save Distortions
2273
2274 % Compute distortion for 10 clock phases
2275 for n=1:10
2276 tx1=tx(n:10:end);
2277 % Align data and test pattern
2278 [val,index]=max(xcorr(tx1,tm4));
2279 X=circshift(X0, [0, mod(index+Nc/2,Ns)]);
2280 % Compute coefficients that minimize squared error
2281 coef=tx1/X;
2282 % Linear canceller
2283 err=tx1-coef*X;
2284 % Peak distortion
2285 dist(n) = max(abs(err));
2286
2287 DistArr = [DistArr,err(:)] ; %Save Distortions
2288 end
2289 % Print distortion in mV for 10 sampling phases
2290 format bank
2291 peakDistortion_mV = 1000*dist'
2292
2293 %Per phase: Distortion RMS and Distortion Peak to Signal RMS ratio
2294 DistortionRMSToSignalRMSPerPhase_dB = 20*log10(rms(DistArr)./rms(reshape(tx(:),10,length(tx)/10)'))
2295 DistortionPeakToSignalRMSPerPhase_dB = 20*log10(max(abs(DistArr))./rms(reshape(tx(:),10,length(tx)/10)'))
9.1.9 PAM-X Transmitter Dual Lane, Inter-Pair Skew

9.1.9.1 Requirement
2296 For Q-Port Dual Lane, when working in TM4 on both pairs, simultaneously capturing both Pair #0 and Pair
2297 #1 signals and calculating their inter-pair skew, the resulting Inter-Pair Skew shall be below 1 nS.

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9.2 RX Electrical Specification

9.2.1 Profile 1 Receiver Bit Error Rate
2298 The Profile 1 Downlink/Uplink Receiver shall receive NRZ symbols transmitted by an A-PHY Profile 1
2299 compliant Transmitter via a compliant A-PHY channel under alien noise conditions within the A-PHY
2300 Profile 1 noise limits at an overall Bit Error Rate (BER) of < 10-12 (i.e., equivalent to Packet Error Rate [PER]
2301 of < 10-9 for Downlink, and PER of <10-10 for Uplink).
9.2.2 Profile 2 Downlink Receiver Pre-RTS Packet Error Rate
2302 The Profile 2 Downlink Receiver shall receive symbols transmitted by a compliant Profile 2 compliant
2303 Transmitter via a compliant A-PHY channel under alien noise conditions within the Profile 2 noise limits at
2304 an overall, Pre-RTS Packet Error Rate (PER) of < 10-3 for G3–G5, and PER < 10-9 for G1–G2.
9.2.3 Profile 2 Uplink Receiver Bit Error Rate
2305 The Profile 2 Uplink Receiver shall receive symbols transmitted by an A-PHY Profile 2 compliant
2306 Transmitter via a compliant A-PHY channel under alien noise conditions within the A-PHY Profile 2 noise
2307 limits at an overall Pre-RTS Bit Error Rate (BER) of < 10-12 (i.e., equivalent to Pre-RTS Packet Error Rate
2308 [PER] of < 10-10).
9.2.4 Receiver Symbol Rate Frequency Tolerance
2309 The Receiver shall properly receive transmitted symbols with a long-term average rate accuracy of ±100 ppm
2310 of its Nominal Symbol Rate.
9.2.5 Receiver Test Modes
9.2.5.1 RTM6: Receiver Test Mode 6: Unidirectional Startup
2311 When RTM6 is selected and enabled, the Sink shall go into Silent State and wait for the Source to initiate the
2312 Unidirectional Startup Procedure as specified in Section 8.3.4.2. The sub-modes RTM6A and RTM6B are
2313 selected with field TMData field in Register TEST_CONFIG (see Table 133), using the values defined in
2314 Table 72.
2315 Table 72 Selection of RTM6 Sub-Mode via Field TMData
Value of Bitfield
RTM6 Sub-Mode
TMData
0 RTM6A
1 RTM6B
2316 The Sink shall follow the requirements as specified in the Unidirectional Startup according to the following
2317 sub Modes:
2318 • RTM6A: When this sub mode is enabled, the Sink shall cease to transmit its Uplink transmission
2319 • RTM6B: When this sub mode is enabled, the Sink shall transmit its Uplink transmission as specified
2320 during the Unidirectional Startup, with the expectation that its Link partner will completely ignore
2321 this Uplink transmission (i.e., no RTS/ReTrain requests can be sent, RTS is not operating, etc.).

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10 Modes of Operation
2322 The A-PHY Port has two Operation Modes: Active and Non-Active. Within each Operation Mode there are
2323 some States, and a set of Transitions between the States, that together define the Operation Mode State
2324 Machine detailed in Section 10.3.
10.1 Non-Active Mode

2325 During Non-Active Mode (i.e., during all the Non-Active states), the A-PHY Port shall not transmit any data
2326 into the A-PHY Channel/Interconnect, and shall ignore any data received from the A-PHY
2327 Channel/Interconnect, other than the request to move out of the Non-Active operation mode (i.e., the Wakeup
2328 Signal as defined in Section 10.5).
10.2 Active Mode

2329 During Active Mode (i.e., during all the Active states), the A-PHY Port shall act to sustain a data
2330 communication Link with its partner A-PHY Port, and shall act to provide the required data transmission
2331 quality, per the selected operation Profile and Gear (see Section 5.2).

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10.3 Operation Mode State Machine

2332 The Operation Mode State Machine (see Figure 92) is the major state machine controlling A-PHY Port
2333 operation.
Active Mode
Normal
State
Sleep
Transition Link- Link-
Down Establish
Trans. Transition
Stop
Start-Up Test Mode
Transition
State
Wakeup
Transition
Test Test Mode
State Transition
Sleep
State
Power-Up
State
Non-Active Mode
2334
Figure 92 A-PHY Port Operation Mode State Machine
2335 The same state machine is defined for both A-PHY Source Ports and A-PHY Sink Ports. Unless otherwise
2336 specified, the same definitions of states and transitions apply to both A-PHY Source Ports and A-PHY Sink
2337 Ports. In Figure 92, transitions are color-coded by type per the Table 73 legend.
2338 Table 73 Transition Appearance Legend
Transition Appearance Transition Description
Transitions from Any State into a particular other state
Red Arrow
(e.g., Reset Transition)
Transitions that are the result of a local or remote (on the A-PHY Link)
Purple Arrow Control/Command/Sequence
(e.g., Sleep Transition)
Transitions that are the result of a local only Control/Command/Sequence
Green Arrow
(e.g., Ready Transition)
Transitions that are the result of Link Establishment process
Blue Arrow
(e.g., Link Establish Transition)
Transitions that are the result of Link Down conditions
Orange Arrow
(e.g. Link-Down Transition)

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10.3.1 General Operation

2339 When two A-PHY Ports are connected, some states and transitions by their nature are not synchronized (e.g.,
2340 power supply can be independent for each A-PHY, so entering and leaving the Power-Up State cannot be
2341 synchronized), whereas other states and transitions will have some level of synchronization (e.g., both
2342 A-PHY Ports must be in their Normal State in order to exchange data).
2343 There are three mechanisms to achieve synchronization between the two A-PHY Ports Link partners:
2344 • Commands Exchange: When the Link is established, commands traversing the Link in both
2345 directions are used to notify and synchronize the state and transitions between the two A-PHY Ports.
2346 The specific commands are specified in the ACMP section (Section 12.3).
2347 • Signal Detection: Signal detection shall be used in both A-PHY Ports to detect the following
2348 signals:
2349 • Wake-Up Pattern (WUP) signal detection, while in Sleep State
2350 • Link Startup Signal Patterns (per selected Profile), while in Start-Up State
2351 • No-Signal, Link-Down (per selected Profile), while in Normal State
2352 • Internal Events: Time Outs, Error Counters, Link Quality Indicators, etc.
2353 In addition, the A-PHY Port receives instructions from its local system (e.g., Host, CPU, MCU, SoC). These
2354 are referred to as Local Events and can be presented to the A-PHY Port in the form of:
2355 • Local System Signals
2356 • Local Commands (i.e., Local Register Writes)
2357 The A-PHY Port acts upon the remote/local signals/commands and according to the Operation Mode State
2358 Machine and, as a result, may change its states automatically. The A-PHY Port is also required to notify the
2359 Local System (e.g., Host, CPU, MCU, SoC) about changes that it makes and/or detects. This approach allows
2360 the Local System to receive all necessary information, take necessary decisions, and instruct the A-PHY Port
2361 to operate accordingly.
2362 Some of the operations of the A-PHY Port are defined to be “automatic”, meaning that the operation shall be
2363 accomplished without requiring the Local System to intervene.

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10.3.2 States
2364 This specification defines the four States detailed in this section: Power-Up, Start-Up, Normal, and Sleep.
10.3.2.1 Power-Up State
2365 The A-PHY Port shall be in Non-Active Operation Mode while in Power-Up State.
2366 Possible reasons for an A-PHY Port to enter the Power-Up State are:
2367 • Power is not applied/not sufficient.
2368 • Reset is asserted.
2369 The A-PHY will exit the Power-Up State upon Ready_ind assertion.
2370 Ready_ind is asserted when Power is meeting working conditions and RESET is de-asserted.
10.3.2.2 Start-Up State
2371 The A-PHY Port shall be in Active Operation Mode while in Start-Up State.
2372 The Start-Up State may be entered as a result of a Link-Down Transition (Section 10.3.3.6), Wakeup
2373 Transition (Section 10.3.3.8), or Ready Transition (Section 10.3.3.3), as depicted in Figure 92.
2374 The Start-Up State is the state of the A-PHY Port during its process of establishing a Link with the remote
2375 A-PHY partner (its ‘Link partner’). Within the Interconnect conditions defined in Section 6, the process of
2376 Link establishment (measured from the time of entering the Start-Up State until the time of entering the
2377 Normal State) shall not exceed a time period of SUPT.
2378 The Start-Up Sub-State-Machine is described in Section 8.3.3.
2379 Upon successful completion of the Start-Up Sub-State-Machine, the Link is considered to be established and
2380 the Start-Up State shall be exited, taking the Link-Establish Transition, and the Normal State shall be entered.
2381 Upon unsuccessful completion of the Start-Up Sub-State-Machine, another attempt shall be made as long as
2382 the StartUpFail_cnt number of successive iterations (see Register FSM_CONFIG, Table 134) is not
2383 exceeded. If during any attempt to complete the Start-Up sequence, there is no response from the other side
2384 other than Silent, the next attempt shall be preceded with WUP (the Wake-Up Protocol, see Section 10.5).
2385 In the event of StartUpFail_cnt continuous failures to complete the Link Start-Up Sub-State-Machine
2386 successfully, the A-PHY Port shall take the Stop Transition, exiting the Start-Up State and entering the Sleep
2387 State. The Stop Transition shall result in notifying the Local System by activating the AutoStop_ind. In this
2388 event, the upper layer should take the correct measures to resolve the issue (e.g., change Configuration,
2389 activate the Reset or Power, or both, in order to cause the A-PHY to re-start, etc.).

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10.3.2.3 Normal State

2390 The A-PHY shall be in Active Mode of Operation while in Normal State.
2391 The Normal State is entered from Start-Up State upon Link-Establish event.
2392 The Normal State is the state of the A-PHY when it is fully operational, transmitting and receiving data, up
2393 to the maximal throughput, to and from its remote A-PHY Port partner (Link partner). The A-PHY Port shall
2394 be able to transmit and receive data at the minimal throughput [ DSTTPR , USTTPR ].
2395 While in Normal State, the A-PHY keeps monitoring the quality of the Link. The A-PHY Port shall stay in
2396 Normal State as long as the Link conditions provide a sustained PER according to Table 2 on the transferred
2397 data.
2398 When these conditions cannot be achieved, the Link Down transition shall be taken. The A-PHY Port reports
2399 the LNKQUALLEVEL to the Local System.
2400 While in Normal State, the A-PHY Port may receive a request to move to Sleep State from a remote A-PHY
2401 Port. In such cases, the A-PHY Port shall notify its Local System by activating the SleepRequestOut_ind.
2402 On the event of SleepRequestIn_ind activation, the A-PHY Port shall trigger the Sleep Sequence (per
2403 Section 10.3.3.7).
10.3.2.4 Sleep State
2404 The A-PHY Port shall be in Non-Active Mode of Operation while in Sleep State.
2405 The Sleep State can be entered either from Start-Up State as a result of the AutoStop_ind activation, or from
2406 Normal State as a result of the SleepRequestIn_ind activation.
2407 The Sleep State is the state of the A-PHY Port when it has no data to be exchanged with the remote A-PHY
2408 Port for long periods of time (i.e., for power saving).
2409 While in Sleep State the A-PHY Port minimizes its power consumption, e.g., by shutting down all of its high-
2410 performance functions and maintaining only the basic functions needed to generate and/or detect the request
2411 to move out of the Non-Active operation mode (see Section 10.5).
2412 In cases where the Sleep State was entered by the Stop Transition, the Local System should take the correct
2413 measures to resolve the issue (e.g., change Configuration, activate the Reset or Power, or both, to cause the
2414 A-PHY to re-start, etc.).
2415 Upon the event of WakeupIn_ind activation the Sleep Sub-State shall be exited, taking the Wake-Up
2416 Transition and entering the Start-Up State. The Wake-Up Protocol is specified in Section 10.5.

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10.3.3 Transitions
2417 The Operation Mode State Machine defines eight Transitions as detailed in the following sub-sections:
2418 • Power-Off Transition
2419 • Reset Transition
2420 • Ready Transition
2421 • Stop Transition
2422 • Link Establish Transition
2423 • Link Down Transition
2424 • Sleep Transition
2425 • Wakeup Transition
10.3.3.1 Power-Off Transition
2426 <from Any-State to Power-Up State>
2427 Upon a Power-Off Transition, the A-PHY Port shall automatically enter the Power-Up State, regardless of its
2428 current state (i.e., from Any-State).
10.3.3.2 Reset Transition

2429 <from Any-State to Power-Up State>
2430 Upon a Reset Transition, the A-PHY Port shall automatically enter the Power-Up State, regardless of its
2431 current state (i.e., from Any-State).
10.3.3.3 Ready Transition

2432 <from Power-Up State to Start-Up State>
2433 The A-PHY Port shall automatically exit the Power-Up State and enter the Start-Up State.
10.3.3.4 Stop Transition

2434 <from Start-Up State to Sleep State>
2435 When the Start-Up process does not succeed for StartUpFail_cnt consecutive iterations (see Register
2436 FSM_CONFIG, Table 134), the A-PHY Port shall automatically activate the AutoStop_ind indication and
2437 move from Start-Up State to Sleep State. The remote A-PHY Port is expected to move to Sleep State,
2438 eventually, because of the same Stop Transition conditions (i.e., non-synchronized transition into Sleep State
2439 doesn’t require the Sleep Sequence as described in Section 10.3.3.7).
2440 There is an optional ManualStop_ind indication that can be sent to the A-PHY Port by the Local System to
2441 direct the A-PHY Port to stop its Start-Up tries, move out of the Start-Up State, and enter the Sleep State.
10.3.3.5 Link Establish Transition

2442 <from Start-Up State to Normal State>
2443 See Section 8.3.3.

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10.3.3.6 Link Down Transition

2444 <from Normal State to Start-Up State>
2445 Either one of the following conditions shall trigger the Link Down Transition:
2446 • No packet was received (pre-RTS) for more than NOTRNST
2447 • LNKQUALLEVEL = 0
10.3.3.7 Sleep Transition
2448 <from Normal State to Sleep State>
2449 The Sleep Transition shall occur on a successful completion of the Sleep Sequence. The Sleep Sequence shall
2450 be triggered by either local or remote sleep request. An example of a Sleep Sequence is depicted in Figure
2451 93.
1. To move to Sleep State, the 2. On activation of 3. On reception of
System shall activate the SleepRequestIn_ind indication, SleepRequest_cmd , the A-
SleepRequestIn_ind indication the A-PHY Port shall start PHY Port shall activate the
sending the SleepRequest_cmd SleepRequestOut_ind
periodically every SLPT indication
System System
Sleep / Wake SleepReqIn SleepReqOut Sleep / Wake
A-PHY A-PHY
Control Control
Port Port
Function SleepReqOut SleepReqIn Function
6. Same as (3) above 5. Same as (2) above 4. As result, the System may
activate the
2452 SleepRequestIn_ind indication
Figure 93 Sleep Sequence Example, View 1
2453 Figure 94 presents the same Sleep sequence in a second way, i.e., as a waveform diagram. Steps 1–6 are the
2454 same in both Figures.
SLPONGOT
Sleep
1) If Link Down is detected or

SleepRequestIn_ind SLPACKT elapse, move to
Sleep State
2)
SleepRequestOut_ind 6) Side A
SLP T
A to B SlpCmd SlpCmd SlpCmd

APHY Channel A-PHY Channel
B to A
3)
SlpCmd SlpCmd
SleepRequestOut_ind 5) Side B
4)
SleepRequestIn_ind
Move to Sleep State
2455 SLPACKT
Figure 94 Sleep Sequence Example, View 2

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2456 In order to synchronize the transition into Sleep State at both A-PHY Ports (i.e., both Link partners), the
2457 A-PHY Ports shall use the indications RemoteSleep_cmd (see Section 11.3.3), SleepRequestIn_ind
2458 (see Table 134), and SleepRequestOut_ind (see Table 135), and the following set of rules; together, these are
2459 referred to as the Sleep Sequence:
2460 • Rule 1: On activation of the SleepRequestIn_ind indication, the A-PHY Port shall start sending the
2461 RemoteSleep_cmd periodically every SLPT.
2462 • Rule 2: On reception of the RemoteSleep_cmd, the A-PHY Port shall activate the
2463 SleepRequestOut_ind indication.
2464 • Rule 3: If no RemoteSleep_cmd is received for a time period of more than NOSLPT, the A-PHY
2465 Port shall deactivate the SleepRequestOut_ind indication.
2466 • Rule 4: When the SleepRequestIn_ind and the SleepRequestOut_ind are both asserted for a time
2467 period of at least SLPACKT, the A-PHY Port shall move to Sleep State.
2468 • Rule 5: When the SleepRequestIn_ind and the SleepRequestOut_ind are both asserted for a time
2469 period of at least SLPONGOT, the A-PHY Port shall consider any “Link Down” event as a
2470 SLPACKT expired event, and shall accordingly move to the Sleep State.
10.3.3.8 Wakeup Transition

2471 <from Sleep State to Start-Up State>
2472 The Wakeup Transition shall be generated by either the A-PHY-Sink or the A-PHY-Source (while in Sleep
2473 State) on the A-PHY Interconnect, towards the other A-PHY (also in Sleep State).
2474 The A-PHY Port shall be able to receive and correctly detect the Wakeup pattern while in Sleep State. Upon
2475 receiving the Wakeup pattern, the A-PHY Port shall automatically operate according to the WUP Protocol
2476 (see Section 10.5), and if completed successfully, shall move out of Sleep State and enter its Start-Up State.
10.3.4 Test Mode
2477 Test Mode and its Test State shall be entered from any other State upon setting the TMEnable bit in Register
2478 TEST_CONFIG to 1 (i.e., 1’b1) (see Table 133 in Section 12.2.5.2).
2479 The Test Mode and its Test State are exited upon clearing the TMEnable bit in Register TEST_CONFIG to
2480 zero (i.e., 1’b0). Test State shall always be exited to Power-Up State (see Section 10.3.2.1).

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10.4 FSM Parameters

2481 This section describes Configuration parameters and programming.
2482 Table 74 lists all FSM Configuration parameters.
2483 Table 75 defines all Link Quality Code Levels used in the LNKQUALLEVEL configuration parameter to
2484 quantify the quality of a Link.
2485 Table 74 FSM Configuration Parameters
Parameter
Min Max Units Description
Name
Start-Up Time.
SUPT – 100 mS Measured from entering the Start-Up
State until entering the Normal State
Target Throughput of the A-Port
0.9 * Downlink.
Max Net % of
Max Net
DSTTPR Link PHY Max Net Link Rate is defined in
Link
Rate Rate Section 8.2.6.1 and Section 8.2.6.2 for
Rate
Downlink.
0.9 *
Max Net % of Target Throughput of the A-Port Uplink.
Max Net
USTTPR Link PHY Max Net Link Rate is defined in
Link
Rate Rate Section 8.2.6.1 for Uplink
Rate
A-PHY Link Quality Code Levels, set
per Profile (see Section 7 and Table
75).
Values:
0: No Link
LNKQUALLEVEL 0 5 Levels 1: Bad Link
2: Marginal Bad Link
3: Marginal Good Link
4: Good Link
5: Excellent Link
6 – 7: Reserved
Max Maximum Time between A-Packet
KEPALVT – RTS µS transmission.
Delay / 2
Maximum Time without A-Packet
NOTRNST – 5 mS
transmission.
Period between two consecutive
SLPT – 100 µS
Remote Sleep Commands.
10 x Period to identify disruption of the Sleep
NOSLPT – µS
SLPT Sequence.
20 x Period to identify a successful Sleep
SLPACKT – µS
SLPT Sequence.
15 x Period to identify that a Sleep
SLPONGOT – µS
SLPT Sequence is ongoing.

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2486 Table 75 Link Quality Code Levels

Link Quality
Name Description
Code Level
The receiver cannot complete the StartUp function within the
Level-0 No Link Start-Up State successfully and cannot sustain a Normal
Operation within the Normal State.
Too many errors are propagated from the A-PHY Port to the upper
Level-1 Bad Link
layers (Adaptation Layer and Application).
Small amount of errors is propagated from the A-PHY Port to the
Level-2 Marginal Bad Link
upper layers (Adaptation Layer and Application).
No errors are propagated from the A-PHY Port to the upper layers
Level-3 Marginal Good Link (Adaptation Layer and Application) but the Link conditions are not
good (e.g., Retransmission Rate is high).
Level-4 Good Link (Adaptation Layer and Application) and the Link conditions are
good (e.g., Retransmission Rate is low).
Level-5 Excellent Link (Adaptation Layer and Application) and the Link conditions are
excellent (e.g. Retransmission Rate is zero).

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10.5 Wake-Up Protocol

10.5.1 General
2487 This section specifies the wake-up communication protocol and the Wake-Up Pattern (WUP) signal that is
2488 used during the Wake-Up Protocol. It also provides a generic and informative view of the wake-up process.
10.5.1.1 System Architecture (Informative)
2489 In systems that are designed for power saving modes, there are (at least) two power domains: the Working
2490 Power (VDD) and the Standby Power (VSTBY). The WUP is used to signal a remote device that it needs to
2491 wake up (i.e., to move from its power-saving mode to its normal operation mode). Within such devices there
2492 is a module (STBY_module) that is responsible for detection and generation of the WUP signal and for
2493 starting the wake-up procedure. That module needs to be fed by the V STBY power source.
2494 An optional description of such a system is depicted in Figure 95.
VDD VSTBY VSTBY VDD
Standby Power Standby Power

Domain (VSTBY ) Domain (VSTBY )
A-PHY A-PHY
STBY_module STBY_module
Port Port
Main Power Main Power

Domain (VDD) Domain (VDD)
Local System Remote System

2495 E.g. ECU E.g. Sensor
Figure 95 Optional System Architecture
2496 The WUP signal may be initiated by any one of the Remote or Local systems. The initiating entity is referred
2497 to as the WUP_Initiator, and the other partner entity is referred to as the WUP_Follower. The WUP_Initiator
2498 generates and transmits the WUP signal. The WUP_Follower receives and detects the WUP signal, as shown
2499 in Figure 96.

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VDD VSTBY VSTBY VDD

A-PHY A-PHY
Port Port
Main Power WUP Signal Main Power


E.g. ECU E.g. Sensor
VDD VSTBY VSTBY VDD

A-PHY A-PHY
Port Port


Figure 96 WUP Directions
2501 The WUP signal is sent and received on the A-PHY Interconnect.
2502 When the device is set as the WUP_Initiator, the WakeupIn_ind is used as an input signal indicating to the
2503 WUP_Initiator to start the generation of the WUP signal.
2504 When the device is set as the WUP_Follower, it uses the WakeupOut_ind as an output signal indicating that
2505 a WUP signal was detected, per Figure 97.

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VSTBY VSTBY

Domain (VSTBY ) Domain (VSTBY ) WakeupIn_ind
WakeupOut_ind A-PHY A-PHY signal indicating
signal indicating Port Port that WUP
that WUP signal signal needs to
was detected be generated

Figure 97 Wakeup_ind Configuration Signaling
2507 As a result of receiving the WakeupOut_ind signal, the WUP_Follower’s Local System performs its power-
2508 up procedures to supply VDD.
2509 For efficiency, the WUP_Initiator can start its own power-up procedure to provide VDD in parallel or prior to
2510 the generation of the WUP signal.
10.5.2 Wake-Up Pattern (WUP) Signal
2511 The waveform shown in Figure 98 describes in general the main signaling associated with the Wake-up
2512 procedure. The following sub-sections describe it in greater detail.
WakeupIn_ind
at the WUP_Initiator ...
Bit Rate
GENT
A-PHY Channel PRBS9

Word
(511-bit)
PRBS9
Word
(511-bit)
PRBS9
Word
(511-bit)
PRBS9
Word
(511-bit)
PRBS9
Word
(511-bit)
PRBS9
Word
(511-bit)
WUP
Amplitude ...
WUP Duration
DETT
2513
WakeupOut_ind
at the WUP_Follower ...
Figure 98 General Waveform of Main Signals
10.5.2.1 PRBS9 Pattern

2514 PRBS9 is a randomization pattern, used as the data of the WUP signal. The polynomial used for the WUP
2515 PRBS9 is:
2516 𝑥9 + 𝑥5 + 1
2517 A full randomization cycle of PRBS9 is 511 bits, which is defined as the PRBS9 Word.
2518 For DC balancing, PRBS9 Words shall be sent in pairs in which the first PRBS9 Word shall have negative
2519 polarity and the second PRBS9 Word shall have positive polarity.
2520 The PRBS9 data is used to control disparity for DC balancing and to control transition density for activity
2521 detection. The receiver of the PRBS9 is not required to parse and retrieve the data. An incorrect PRBS9
2522 sequence shall not disqualify a WUP signal.

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10.5.2.2 WUP Amplitude

2523 The WUP Amplitude WUP_AMP_par is set for robustness (noise resistance) and EMI considerations.
10.5.2.3 WUP Bit Rate
2524 The WUP Bit Rate WUP_RATE_par is set to minimize the power while maintaining frequency beyond the
2525 droop of the HPF at both sides of the transmission lines.
10.5.2.4 WUP Duration
2526 The WUP Duration WUP_DUR_par allows fast response but also allows secured detection.
2527 The WUP Duration should be an even integer of PRBS9 Words.
10.5.2.5 WUP Generation
2528 The WUP_Initiator should be capable of generating and transmitting the WUP signal, as result of the
2529 WakeupIn_ind signal indication.
2530 The maximum time from WakeupIn_ind input activation to first WUP signal symbol transmission shall not
2531 exceed GENT.
10.5.2.6 WUP Detection
2532 The WUP_Follower shall be capable of receiving and detecting the WUP signal and generating the
2533 WakeupOut_ind indication, respectively, while operating on the standby power source (i.e., V STBY).
2534 Any WUP signal compliant with the above specifications shall be detected. The latency from the start of the
2535 transmitted symbol in the WUP_Initiator to the activation of WakeupOut_ind in the WUP_Follower shall
2536 not exceed DETT.

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10.5.3 WUP Handshake Procedure

2537 The WUP_Follower shall detect the WUP signal as specified in Section 10.5.2, and on positive detection
2538 shall activate the WakeupOut_ind output signal. The activation of the WakeupOut_ind output signal shall
2539 automatically trigger the Wake-up Transition, resulting in moving out of Sleep State and entering the Start-Up
2540 State (see Section 10.3.2.2).
2541 The WUP_Initiator shall complete the transmission of the WUP signal and automatically trigger the Wake-
2542 up Transition, resulting in moving out of Sleep State and entering the Start-Up State (see Section 10.3.3.8).
2543 There are two cases of WUP Handshake Procedures: One is when the WUP_Initiator is the Primary Clock,
2544 and the second is when the WUP_Initiator is the Secondary Clock (see Section 8.1.3).
2545 In both cases the Link Start-Up Sub-State Machine (see Section 8.3.3) is used as handshake indication for
2546 WUP_ACK or WUP_NACK:
2547 • WUP_ACK if Link Start-Up proceeds within WUP_ACK_TimeOut
2548 • WUP_NACK if Link Start-Up doesn’t proceed within WUP_ACK_TimeOut
2549 An example of the major signal waveform in handshake process is presented in Figure 99.
WakeupIn_ind
at the WUP_Initiator
WUP_ACK_TimeOut
PRBS9 PRBS9 PRBS9 PRBS9 PRBS9 PRBS9

A-PHY Channel Word Word Word Word Word Word
(511-bit) (511-bit) (511-bit) (511-bit) (511-bit) (511-bit) Link Start-Up Signaling
(e.g. Training)
WakeupOut_ind
at the WUP_Follower
VDD_Enb / VSTBY_Dis
2550
Figure 99 WUP Handshake ACK/NACK
2551 When the WUP Handshake Procedure results in a NACK, the A-PHY Port shall follow the unsuccessful
2552 completion of the Start-Up sequence as described in Section 10.3.2.2.

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10.5.4 WUP Parameters
2553 Table 76 WUP Parameters

Parameter Name Min Max Units Description
WUP signal duration.
The WUP signal is constructed from the right
WUP_DUR_par 1 2 mS
number of PRBS9 Words that shall last for this
duration.
WUP signal bit rate.
WUP_RATE_par 3 5 Mbps
Can also be described as Nominal 4 Mbps ± 25%.
WUP signal TX amplitude, measured as Single-
WUP_AMP_par 400 600 mV
Ended, Peak-To-Peak
Maximum time from the activation of
GENT – 1 mS WakeupIn_ind until the transmission of the first
WUP signal symbol, all at the WUP_Initiator
Maximum time from the first transmitted WUP
signal symbol at the WUP_Initiator until the
DETT – 2 mS
activation of WakeupOut_ind at the
WUP_Follower
WUP_ACK_TimeOut – 200 mS –

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11 Data Link Layer
11.1 Architecture Overview

2554 The A-PHY Data Link Layer (APDLL) is the layer between the Native Protocol Adaptation Layer (NPAL)
2555 and the A-PHY Physical Layer.
2556 Figure 100 illustrates the layering structure of the A-PHY connectivity with the Native Protocol (NP).
A-PHY Protocol Interface

(APPI)

A-PHY PHY Layer
A-PHY PHY Layer

Native Protocol
Native Protocol
(APDLL)
(APDLL)
(NPAL)
(NPAL)
(APPL)
(APPL)
(NP)
(NP)
Cable
Protocol A-PHY A-PHY Protocol
Uni-Directional High Speed
Bi-Directional Low Speed

2557
Figure 100 A-PHY High Level Structure
2558 The A-PHY Data Link Layer interfaces with the Native Protocol Adaptation Layer via the A-PHY Protocol
2559 Interface (APPI) (see Section 11.7).
2560 Each Native Protocol Adaptation Layer has at least one APPI connection to the A-PHY Data Link Layer.
2561 Each Native Protocol Adaptation Layer serves at least one Native Protocol (NP) and has all relevant Native
2562 Interfaces (NI) for that.
2563 A-PHY Data Link Layer may be connected to multiple Native Protocols Adaptation Layers using a single
2564 Local Function (see Section 11.4).
2565 The A-PHY Data Link Layer may have a single A-PHY Network Function connected to it, or multiple A-PHY
2566 Network Functions (see Section 11.6).

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2567 Figure 101 provides an example of a possible A-PHY implementation structure.
Native Video
Native CSI-2
Native DSI
Interface
Interface
Interface
Native
Interfaces
CSI-2
I2C
CSI-2 DSI Non MIPI Video
Combo GPIO
Adaptation Layer Adaptation Layer Adaptation Layer
Adaptation Layer
APPI
APPI
APPI
APPI
Local Function (ID=1)
Multi Port Function

Data Link Layer
Network Function (ID=2) Network Function (ID=3) Network Function (ID=N)
Data Link Layer Data Link Layer Data Link Layer
PHY Layer PHY Layer PHY Layer

...
A-PHY Port A-PHY Port A-PHY Port
A-PHY
2568
Figure 101 Example A-PHY High-Level Layer
2569 The Native Protocol Adaptation Layer is responsible for translating the incoming Native Protocol data
2570 streams into the A-PHY representation. In the opposite direction, it is responsible for translating from the
2571 A-PHY representation back to the Native Protocol representation.
2572 The A-PHY Data Link Layer representation is in the form of packets, referred to as A-Packets
2573 (see Section 11.2).
2574 The A-Packet is structured to carry the native protocol data (i.e., the payload) and all information that the
2575 A-PHY Data Link Layer requires to perform its functions efficiently, such as the packet’s Target Address,
2576 required QoS, etc.
2577 The A-PHY Data Link Layer is responsible for:
2578 • Routing of A-Packets:
2579 • If there are multiple Native Protocol Adaptation Layers, then the distribution of A-Packets to their
2580 respective Native Protocol Adaptation Layer is done by the Local Function of the APDLL
2582 • If there are multiple A-PHY ports, then the routing and forwarding of all A-Packets (from
2583 Adaptation Layers and/or A-PHY Ports) is done by the Multi-Port Function of the APDLL
2585 • Scheduling of A-Packets forwarded to the same A-PHY Port is done by the Network Function
2586 (see Section11.6).
2587 The A-PHY Protocol Interface (APPI) is a bi-directional, asymmetric, parallel, digital, packet-based
2588 interface.

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11.2 A-Packet Format

2589 The A-Packet shall use the same packet format for Downstream and Upstream directions.
2590 The A-Packet shall use the format shown in Figure 102. The A-Packet fields shall be structured as shown in Table 77. The fields in Figure 102 are ordered from
2591 left to right; i.e., the first field is the Adaptation Descriptor and the last field is the CRC-32. In a multi-byte field (e.g., CRC-32 or Payload), the bytes are ordered
2592 from most significant byte (left) to least significant byte (right).
2593 Figure 102 shows the A-Packet fields with color coding:
2594 • White with crossing stripes: Native Protocol Adaptation Layer payload
2595 • White: Fields under the control of the Native Protocol Adaptation Layer
2596 • Black: Fields under the control of the A-PHY Port
2597 • Light Grey: Fields reserved for future use
2598 • Grey with White Text: Fields under mutual control of both the Native Protocol Adaptation Layer and the A-PHY Port
2599 PHY Related Fields: The fields controlled by the A-PHY Port (A-Header fields PHY1, PHY2, PHY3, and PHY Header CRC; and the A-Tail CRC-32) shall be sent
2600 with zeros, and shall be ignored on reception by the A-PHY Data Link Layer (see Section 8.1.5).
A-Packet
A-Packet Header A-Packet Payload A-Packet Tail
8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit

PHY
Adaptation Service Placement Target Payload PHY Tail
PHY2 PHY3 Header Payload (K Payload Bytes)
Descriptor Descriptor Descriptor Address Length (N) CRC-32
CRC
Adaptation
BAD
RES
Res QoS Prio PHY1 ALEI

OB
Type RES Order

b7
b6
b5
b4
b3
b2
b1
b0
b7
b6
b5
b4
b3
b2
b1
b0
b7
b6
b5
b4
b3
b2
b1
b0
2601
Figure 102 A-Packet Format

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2602 Table 77 A-Packet Fields and Sub-Fields Description

A-Packet Size
Field Sub-Field Bits Description See Section
Section (Bits)
A-Header Adaptation Adaptation 4 b3:b0 Type of Native Protocol

Descriptor Type Adaptation Layer
11.2.1.1.1
communication with the A-PHY
Data Link Layer
Reserved 4 b7:b4 Reserved for future use Value: 0x0
Service PHY1 2 b1:b0 Reserved for PHY Usage 11.2.1.2.1

Descriptor
Prio 2 b3:b2 Indicates the A-Packet’s
11.2.1.2.2
Priority
QoS 2 b5:b4 Indicates the A-Packet’s

11.2.1.2.3
Quality of Service
BAD 1 b6 Value 1’b1 indicates

11.2.1.2.4
a Bad A-Packet
Reserved 1 b7 Reserved for future use Value: 1’b0
Placement ALEI 3 b2:b0 Adaptation Layer specific See relevant Adaptation

Descriptor information Layer Specification
for more details
OB 1 b3 Value 1’b1 indicates that the

(Odd-Bytes) A-Payload contains an odd 11.2.1.3.2
number of Bytes
Order 2 b5:b4 Indicates the order of this

A-Packet within a stream 11.2.1.3.3
sequence of A-Packets
Reserved 2 b7:b6 Reserved for future use Value: 2’b00
PHY2 8 b7:b0 Reserved for PHY Usage 11.2.1.4
Target Address 8 b7:b0 Indicates the A-Packet’s Target

11.2.1.5
destination Address
PHY3 8 b7:b0 Reserved for PHY Usage 11.2.1.6
Payload Length (N) 8 b7:b0 Indicates the number N of

16-bit Payload Words (not
11.2.1.7
bytes) contained in the
A-Payload
PHY Header-CRC 8 b7:b0 Reserved for PHY Usage 11.2.1.8
A- Payload 8*K – The Native Adaptation Layer's

Payload payload. A-Payload length is K 11.2.2
bytes (not 16-bit words).
A-Tail CRC-32 32 b31:b0 Reserved for PHY Usage 11.2.3

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11.2.1 A-Packet Header (A-Header) Fields

2603 The A-Packet Header (also known as A-Header) shall consist of eight (8) Header Bytes as depicted in Figure
2604 102, Table 77, and as defined in the following sub-sections.
11.2.1.1 Adaptation Descriptor Field
2605 The 8-bit Adaptation Descriptor field shall consist of the Adaptation Type sub-field as defined below, and a
2606 Reserved 4-bit sub-field at b7:b4 which should be set to 4’b0000.
11.2.1.1.1 Adaptation Type Sub-Field
2607 The 4-bit sub-field Adaptation Type (b3:b0 of the Adaptation Descriptor field) shall be set according to Table
2608 78.
2609 Table 78 Adaptation Type Sub-Field Values
Adaptation
Description Remarks
Type Value
0 PHY Service See Section 8.2.3.3
1 Link Service See Section 11.3
2 Clock Forwarding Service See Section 11.6.2
3–15 Type of Native Adaptation Layer Reserved for allocation
communication with the A-PHY solely by MIPI Alliance
Data Link Layer
2610 Adaptation Type values shall be allocated solely by MIPI Alliance:

2611 • Values 0–2 are fully defined in this Specification.
2612 • Values 3–15 shall identify A-PHY Protocol Adaptation Layers (PALs), and shall be specified in
2613 separate MIPI Specifications (e.g., MIPI PAL/I2C [MIPI11], MIPI PAL/GPIO [MIPI12], MIPI
2614 PAL/CSI-2 [MIPI09], etc.).
2615 Because new Adaptation Type values are expected to be introduced from time to time as new PALs are
2616 specified, MIPI Alliance maintains the current list of all allocated Adaptation Type values on a web page in
2617 the MIPI Alliance public web site [MIPI13].
11.2.1.2 Service Descriptor Field
2618 The 8-bit Service Descriptor Field shall consist of sub-fields PHY1, Prio, QoS, and BAD as defined below,
2619 and one Reserved bit at b7 which should be set to 1’b0.
11.2.1.2.1 PHY1 Sub-Field
2620 The 2-bit PHY1 sub-field (b1:b0 of the Service Descriptor field) is PHY-related, and is described in
2621 Section 8.1.5. The APDLL sets this sub-field to zero when sending, and ignores it when receiving.

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11.2.1.2.2 Prio Sub-Field

2622 The 2-bit Prio sub-field (b3:b2 of the Service Descriptor field) shall indicate the scheduling priority of the
2623 A-Packet, using the Scheduling Priority Codes defined in Table 79. For more details on the Scheduling and
2624 Priority functionality, please refer to Section 11.6.1.
2625 Table 79 Prio Sub-Field Values (Scheduling-Priority Codes)
Prio Value Throughput /
Description
(Priority Code) Packet-Size
0 Reserved Reserved for future use
Normal Priority
1 Large Provides low latency-variation for high-bandwidth traffic such
as Camera data, Video, etc.
2 Reserved Reserved for future use
Highest Priority
3 Small Provides low latency for low-bandwidth, time-critical traffic
such as I3C, I2C, GPIO, Controls, etc.
11.2.1.2.3 QoS Sub-Field

2626 The 2-bit QoS (Quality of Service) sub-field (b5:b4 of the Service Descriptor field) shall indicate the
2627 A-Packet’s quality-of-service requirements, using the encoding defined in Table 80. For more details on QoS
2628 functionality, see Section 8.2.
2629 Table 80 Quality-of-Service Codes
Sub-
QoS Bit Value Traffic Type Description
Field
Reduce average/min Latency at
Latency_QoS Time Critical:
0 the expense of
Bit Minimum RTS Delay (MinRD)
Latency-Variation
Flow Sensitive: Reduce Latency-Variation at the
QoS[0] 1
QoS Fixed RTS Delay (FixRD) expense of average/min Latency
[2-bit] Regular Error Resistance while
EResistance _QoS 0 Regular Content
optimized for utilization
Bit
Improved Error Resistance at
1 Important Content the expense of utilization
QoS[1]
optimization

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11.2.1.2.4 BAD Sub-Field

2630 The 1-bit BAD sub-field (b6 of the Service Descriptor field) shall indicate whether the data in the delivered
2631 A-Packet is damaged; A-Packets with damaged data should be handled accordingly by the application layer.
2632 The value 1’b0 in the BAD sub-field shall indicate undamaged data, and the value 1’b1 shall indicate damaged
2633 data.
2634 If all of the A-PHY Port’s error detection and correction mechanisms could not resolve the errors for a
2635 received A-Packet that needs to be forwarded, then that A-Packet shall be marked as “Bad” by setting this
2636 sub-field to the value 1’b1. Such an A-Packet shall be forwarded over the A-PHY network, even though it is
2637 identified as Bad, in order to make sure that the application receives all of the sent data, and takes corrective
2638 actions when necessary.
2639 Note that the BAD sub-field may be set by the Native Protocol Adaptation Layer.
2640 The A-PHY Port shall not clear this sub-field value.
2641 Figure 103 illustrates an example of indication and propagation of a “Bad” A-Packet.

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Add/Drop Add/Drop Add/Drop

Daisy-Chain Device Daisy-Chain Device Daisy-Chain Device
CSI-2 CSI-2 CSI-2

I2C I2C I2C
GPIO GPIO GPIO
APPI
APPI
Local Function (ID=1) Local Function (ID=1) Local Function (ID=1)
Multi Port Function Multi Port Function Multi Port Function

Data Link Layer Data Link Layer Data Link Layer
Network Function (ID=2) Network Function (ID=3) Network Function (ID=2) Network Function (ID=3) Network Function (ID=2) Network Function (ID=3)
Data Link Layer Data Link Layer Data Link Layer Data Link Layer Data Link Layer Data Link Layer
PHY Layer PHY Layer PHY Layer PHY Layer PHY Layer PHY Layer
A-PHY Port A-PHY Port A-PHY Port A-PHY Port A-PHY Port A-PHY Port
6. Nth A-Packet
can still be
identified as
1. Send Nth A-Packet Bad packet
5. Receive Nth A-Packet without error
(i.e. detected with CRC and MC fields)
4. Send Nth A-Packet
2. Receive Nth A-Packet 3. Nth A-Packet

with error (i.e. detected forwarded to next port
with CRC and MC fields) and marked as Bad
and all the PHY s Error packet
Handling mechanisms
could not solve
2642
Figure 103 Bad Packet Indication and Propagation Example

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11.2.1.3 Placement Descriptor Field

2643 The 8-bit Placement Descriptor Field shall consist of the sub-fields ALEI (Adaptation Layer Extended Info),
2644 OB (Odd-Bytes), Order, and a Reserved sub-field at b7:b6 (which should be set to 2’b00).
11.2.1.3.1 ALEI (Adaptation Layer Extended Info) Sub-Field
2645 The 3-bit ALEI sub-field (b2:b0 of the Placement Descriptor field) may be used by the specific Adaptation
2646 Layer for purposes specified in the relevant Adaptation Layer Specifications.
11.2.1.3.2 OB (Odd-Bytes) Sub-Field
2647 The 1-bit OB sub-field (b3 of the Placement Descriptor field) shall be used to indicate whether the byte length
2648 of the Payload is odd or even, using the values shown in Table 81.
2649 Table 81 OB (Odd-Bytes) Sub-Field Values
Sub-Field Name Bits OB Values
OB 1 0: Payload contains an even number of bytes (2, 4, 6, etc.)

(Odd-Bytes) b3 1: Payload contains an odd number of bytes (1, 3, 5, etc.)
11.2.1.3.3 Order Sub-Field

2650 In cases where the Native Protocol Adaptation Layer uses framed data structures for transfers (for example,
2651 the CSI-2 Adaptation Layer uses the Low-Level Long Packet structure), such a frame can be represented as
2652 a sequence of A-Packets in which each A-Packet carries a portion of the frame. Each such portion is referred
2653 to as a Chunk.
2654 The 2-bit Order sub-field (b5:b4 of the Placement Descriptor field) shall indicate the order (or position) of
2655 the Chunk represented by this A-Packet within the NPAL frame, using the values shown in Table 82.
2656 Table 82 Order Sub-Field Values
Sub-Field Name Bits Order Values
0: A Middle (not the first and not the last) Chunk
2 1: The First Chunk
Order
b5:b4 2: The Last Chunk
3: The Only (both the first and the last) Chunk
2657 The use of the Order sub-field is specified separately for each Adaptation Layer, together with its Chunk size
2658 and ordering.
11.2.1.4 PHY2 Field
2659 The 8-bit PHY2 field is PHY-related, and is described in Section 8.1.5. The APDLL sets this field to zero
2660 when sending, and ignores it when receiving.

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11.2.1.5 Target Address Field

2661 The 8-bit Target Address field (also known as the T-Address field) shall indicate the destination of the
2662 A-Packet, using the T-Address values defined in Table 83.
2663 Table 83 Target Address Field Values (Pre-Defined T-Address Values)
Target Address
Value Target Description
(T-Address)
Link Partner: The Target Entity is the Link Partner
0
i.e., is the A-PHY Port that is connected via Interconnect to this A-PHY Port
1 Reserved
2–254 Specific Target Entity

255 Broadcast
2664 The Target Entity is the consumer of the A-Packet stream tagged with its assigned Target Address.
2665 This addressing mechanism supports multiple methods of Target Address assignment:
2666 • One-to-One Target Address Assignment: One Target Entity is assigned with a single, unique
2667 Target Address
2668 • One-to-Many Target Address Assignment: Several Target Entities are assigned with the same
2669 single and unique Target Address
2670 • Many-to-One Target Address Assignment: One Target Entity is assigned with multiple different,
2671 unique Target Addresses
2672 A Target Entity is typically associated with an Adaptation Layer ID, which identifies a specific instance of
2673 the Adaptation Layer. In more advanced cases, a single instance of the Adaptation Layer can be assigned
2674 multiple Target Entities, where each Entity handles a specific stream of A-Packets targeted to that Target
2675 Entity.
2676 An example with multiple Target Addresses Entities (Many-to-One) is shown in Figure 104. An example of
2677 One-to-Many is shown in Figure 105.
2678
Figure 104 Many-to-One Target Address Assignment Example
2679
Figure 105 One-to-Many Target Address Assignment Example

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11.2.1.6 PHY3 Field

2680 The 8-bit PHY3 field is PHY-related, and is described in Section 8.1.5. The APDLL sets this field to zero
2681 when sending, and ignores it when receiving.
11.2.1.7 Payload Length Field
2682 The 8-bit Payload Length field indicates the number of 16-bit Payload Words (not the number of 8-bit payload
2683 bytes) in the payload. Its value shall be greater than 0 (Zero), and shall not exceed the following values:
2684 • For Downlink: 190
2685 • For Uplink: 16
2686 • For Double Rate Uplink (DRU): 38
2687 The number of bytes in the Payload of the A-Packet can be calculated from the Payload Length field and the
2688 OB (Odd Bytes) sub-field of the Placement Descriptor field (see Section 11.2.1.3.2). The total number of
2689 Bytes (K) in the payload is calculated as: K = N * 2 – OB, where N is the value of this Payload Length field
2690 and OB is the value of the OB sub-field.
2691 Example: For a Payload containing three payload bytes (i.e., K=3), the Payload Length field will
2692 contain 2 (i.e., N=2), and the OB sub-field of the Placement Descriptor field will contain 1’b1 (i.e.,
2693 Odd).
2694 Table 84 illustrates the relationship between the payload length in bytes (K), the value of this Payload Length
2695 field (N), and the value of the OB sub-field, for even-length payloads and odd-length payloads.
2696 Table 84 A-Packet Payload Length and OB Sub-Field
Payload Length Payload Length OB Sub-Field
in Bytes Field Value Value
(K) (Length in Words, N) (bit)
K
If K is Even 𝑁= 0
2
K+1
If K is Odd 𝑁= 1
2
11.2.1.8 PHY Header CRC Field

2697 The 8-bit PHY Header CRC field is PHY-related, and is described in Section 8.1.5. The APDLL sets this
2698 field to zero when sending, and ignores it when receiving.

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11.2.2 A-Packet Payload (A-Payload)

2699 The A-Packet Payload (also known as A-Payload) is a variable-length area containing the A-Packet’s payload
2700 bytes. The number of bytes in the A-Payload is determined by the values of the A-Header’s Payload Length
2701 field and OB sub-field, as detailed in Section 11.2.1.3.2.
2702 The mapping of any given native payload format to the 16-bit Payload Words in the A-Packet Payload is
2703 defined by the particular Adaptation Layer specification (e.g., MIPI PAL/CSI-2 [MIPI09]). All such
2704 mappings shall comply with the payload length encoding convention given in Table 84.
2705 The length of the A-Packet Payload (i.e., the number of bytes of payload data) shall not exceed:
2706 • For Downlink: 380 bytes
2707 • For Uplink: 32 bytes
2708 • For Double Rate Uplink (DRU): 76 bytes
11.2.3 A-Packet Tail (A-Tail) (CRC-32 Field)
2709 The 32-bit A-Packet Tail (also known as A-Tail) field immediately follows the A-Payload and contains the
2710 CRC-32 field.
2711 The value of the CRC-32 field shall be calculated by the PHY sub-layer as a CRC-32 for the entire A-Packet
2712 before the A-Tail (i.e., including all Header bytes and all Payload bytes), as specified in Section 8.2.5.4.

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11.3 Link Service

11.3.1 BIST
2713 Part of the Link Services is the ability to generate and send BIST A-Packets (BIST Generator) for purposes
2714 of receiver tests at the remote side Link Partner (BIST Monitor), both on the Downlink and on the Uplink.
2715 BIST Generator and BIST Monitor (see Section 11.3.1.5) services are provided through the following register
2716 sets:
2717 • TX: For the generation and transmission of BIST A-Packets, a set of BIST-TX registers are specified
2718 (see Table 115 through Table 120).
2719 • RX: For the monitoring of received BIST A-Packets, a set of BIST-RX registers are specified (see
2720 Table 121 through Table 127).
2721 In a BIST A-Packet:
2722 • The Adaptation Type sub-field shall contain 0x1
2723 • The BAD sub-field shall contain the value of field bistBAD in register BIST_TX_CTRL5 (see Table
2724 119)
2725 • The QoS sub-field shall contain the value of field bistQ in register BIST_TX_CTRL1 (see Table 115)
2726 • The Prio (Priority) sub-field shall contain the value of field bistP in register BIST_TX_CTRL1
2727 (see Table 115)
2728 • The Target Address (T-Address) field shall contain the value of field bistT field in register
2729 BIST_TX_CTRL3 (see Table 117)
2730 • The Payload Length field shall contain the value of field bistL in register BIST_TX_CTRL2
2732 • The Order sub-field shall contain the value of field bistORDR in register BIST_TX_CTRL5
2734 • The OB sub-field shall contain the value of field bistO in register BIST_TX_CTRL5 (see Table 119)
2735 • The ALEI sub-field shall contain either 0 (3’b000) for basic BIST, or 1 (3’b001) for BIST
2736 Extension-1 (see Table 85)
2737 • The Payload bytes shall contain the value pattern specified in Section 11.3.1.2

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11.3.1.1 BIST Modes

2738 The BIST Mode shall be set according to field bistMode in register BIST_TX_CTRL4 (see Table 118), using
2739 the BIST Mode Code values defined in Table 85.
2740 Table 85 BIST Mode Codes
BIST Mode Code
As set in Register Description
BIST_TX_CTRL4
0 Reserved
Basic BIST Mode
1 BIST A-Packets are generated with ALEI=0, according to settings of the BIST-TX
registers and following the A-Payload structure as described in Figure 106.
Extended BIST Mode
2 BIST A-Packets are generated with ALEI=1, according to settings of the BIST-TX
registers and following the A-Payload structure as described in Figure 107 and
Table 86.
3 – 15 Reserved
2741 The Basic BIST A-Payload format is depicted in Figure 106.
A-Payload
Data Byte
#0 ... Data Byte
#N
1 byt e 1 byt e
2742
Figure 106 Basic BIST A-Payload Format
2743 The Extended BIST A-Payload format is depicted in Figure 107, and its fields and sub-fields are specified
2744 in Table 86.
A-Payload
b31 b0 b31 b0 b31 b0

Extension
Mode
Field
Bitmap
Reserved Reserved Message Counter Timestamp
Data Byte
#0 ... Data Byte
#N
CRC
2745 1 byte 1 byte 1 byte 1 byte 4 bytes 4 bytes 1 byte 1 byte 4 bytes
Figure 107 Extended BIST A-Payload Format

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Table 86 Extended BIST Fields Description
Size Values Description

Field Name Sub-Field Name
(bits)
Extension Mode 2 0–2: Reserved
Mode
[b1:b0] 3: BIST_EXT1
6
Reserved –
[b7:b2]
Field Bitmap 0: Message Counter does not exist
1 1: Message Counter exists
MC
[b0] See field bistEXT_MC in register
BIST_TX_CTRL6, Table 120
0: Timestamp does not exist
1 1: Timestamp exists
TS
[b1] See field bistEXT_TS in register
4
DATA See field bistPATT in Table 87
[b5:b2]
1
Reserved –
[b6]
0: CRC does not exist
1 1: CRC exists
CR
[b7] See field bistEXT_CRC in register
Reserved – 8 –
Reserved – 8 –
Message Counter – 32 This field shall only exist if field MC is set to 1.
See Section 11.3.1.1.1.
Timestamp – 32 This field shall only exist if field TS is set to 1.
Data Bytes #[0:N] – 8 See Section 11.3.1.1.3.
CRC – 32 This field shall only exist if field CR is set to 1.
11.3.1.1.1 Message Counter Field

2746 The Message Counter shall be a 32-bit wrap-around counter of BIST packets. It shall increment with each
2747 BIST packet. The bytes of the Message Counter value shall be ordered from the most significant byte
2748 (MSByte) to the least significant byte (LSByte), with the most significant byte located in the A-Payload
2749 closer to A-Header. The Message Counter field shall only exist if the MC sub-field of Field Bitmap is set to
2750 1.
11.3.1.1.2 Timestamp Field
2751 The Timestamp shall represent the creation time (in nanoseconds) of the first bit of this BIST_EXT1 first Data
2752 Byte (i.e., Data Byte 0).
2753 The Timestamp is represented as a 32-bit wrap-around counter of nanoseconds. This counter shall
2754 continuously count, and will wrap around every approximately 4 seconds.

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2755 The bytes of the Timestamp value shall be ordered from the most significant byte (MSByte) to the least
2756 significant byte (LSByte), with the most significant byte located in the A-Payload closer to A-Header. The
2757 Timestamp field shall only exist if the TS sub-field of Field Bitmap is set to 1.
2758 One option is to use the TBS (see 11.6.2.1.5) to share and synchronize the RTBC (see Section 11.3.4) of both
2759 link partners and use the RTBC as the Timestamp values.
11.3.1.1.3 Data Bytes
2760 The number of Data Bytes shall be:
2761 • Number of Data Bytes (N) = Number of A-Payload Bytes (K) – MC*4 – TS*4 – CR*4 – 4
2762 Please refer to Section 11.2.1.7 for a description of K.
2763 The value of the Data Bytes shall be:
2764 • Zero (0) if DATA sub-field of Field Bitmap is set to 0 (4’b0000)
2765 • PRBS if DATA sub-field of Field Bitmap is set to 1 (4’b0001)
11.3.1.1.4 CRC Field
2766 Field CRC shall be a 32-bit CRC with polynomial and rules according to Section 8.2.5.4. The CRC value
2767 shall be calculated over all the bytes comprising the A-Payload, by their order, up to the CRC field (not
2768 including the CRC field itself). The bytes of the CRC value shall be ordered from the most significant byte
2769 (MSByte) to the least significant byte (LSByte) with the most significant byte is located in the A-Payload
2770 closer to A-Header. The CRC field shall only exist if the CR sub-field of Field Bitmap is set to 1.
11.3.1.2 BIST Payload Patterns
2771 The BIST Payload Pattern shall be set according to field bistPATT in Register BIST_TX_CTRL4 (see Table
2772 118), using the BIST Payload Pattern Code values defined in Table 87.
2773 Table 87 BIST Payload Pattern Codes
BIST Payload Pattern Code
BIST_TX_CTRL4
0 All Payload bytes contain 0x00
1 PRBS as described below.
2 – 15 Reserved
11.3.1.2.1 PRBS Pattern

2774 When bistPATT is set to one (PRBS), the Data Bytes of the BIST A-Packets payload shall convey the PRBS
2775 sequence of the polynomial:
2776 P(x) = x32 + x30 + x29 + x23 + 1
2777 The PRBS shall be calculated according to the bit level diagram in Figure 108.
XOR XOR XOR
+ + +
S0 S1 ... S7 S8 ... S22 S23 ... S28 S29 S30 S31
msb Data Byte #n lsb

S7 S6 S5 S4 S3 S2 S1 S0
2778
Figure 108 BIST PRBS Bit Level Diagram

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2779 The PRBS shall be updated in steps of 8 bits, after which the value of states S0:S7 is considered as the Data
2780 Byte value (S0 as the LSB), ordered in sequential order into the BIST Payload such that Data Byte 0 conveys
2781 the result of the first step, Data Byte 1 conveys the result of the second step, and Data Byte #N conveys the
2782 result of the last step.
2783 The initial value of the BIST PRBS states S0 through S31 shall be all ones (0xFFFFFFFF).
2784 Table 88 illustrates an example.
2785 Table 88 BIST Data Bytes Sequence Example
Data Data Data Data
8-bit 8-bit 8-bit 8-bit
Byte Byte Byte Byte
Step Step Step Step
Value Value Value Value
1 0x00 9 0x07 17 0x00 25 0xD2
2 0x00 10 0xEC 18 0x21 26 0x7A
3 0x01 11 0x60 19 0xB6 27 0x5F
4 0xFB 12 0x84 20 0x0B 28 0x74
5 0x00 13 0xFF 21 0x42 29 0xFC
6 0x03 14 0xFF 22 0xC6 30 0xFF
7 0xFF 15 0xEF 23 0xC8 31 0x30
8 0xCF 16 0x4F 24 0xF9 32 0xF9
11.3.1.3 BIST Rate

2786 The BIST Rate is the rate at which BIST A-Packets are generated. The BIST Rate shall be controlled by the
2787 value of field bistR in register BIST_TX_CTRL1 (see Table 115) which defines the minimum number of
2788 BPeriods (as defined in Section 8.2.6) between two consecutive BIST A-Packets according to Table 89.
2789 Table 89 BIST Rate Codes
BIST Rate Code
BIST_TX_CTRL1
0 Reserved
1 – 15 (R) 2(R+1) BPeriods between consecutive BIST A-Packets
11.3.1.4 BIST Burst

2790 The BIST Burst is the number of consecutive BIST A-Packets that are generated. The BIST Burst shall be
2791 controlled by the value of field bistB in register BIST_TX_CTRL5 (see Table 119) which defines the exact
2792 number of BIST A-Packet that are generated, according to the code defined in Table 90.
2793 Table 90 BIST Burst Codes
BIST Burst Code
BIST_CTRL5
0 Generate an unlimited number of BIST A-Packets per burst
1 – 15 (B) Generate 2(B+1) BIST A-Packets per burst

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11.3.1.5 BIST Generator and BIST Monitor

2794 To enable the BIST Generator, set field bistENB in register BIST_TX_CTRL5 (see Table 119) to 1. When the
2795 BIST Generator is enabled, BIST A-Packet transmission is controlled by setting and clearing the field
2796 bistACTV in register BIST_TX_CTRL5 (see Table 119).
2797 To enable the BIST Monitor, set field bistENB in register BIST_RX_CTRL1 (see Table 121) to 1. When the
2798 BIST Monitor is enabled, all the Read-Only BIST Monitor Results registers (see Table 122 through Table
2799 127) shall be active and operational. Upon setting field bistENB or field bistCLR (i.e., upon changing its value
2800 from 0 to 1) in register BIST_RX_CTRL1 (see Table 121), all the Read-Only BIST Monitor Results registers
2801 shall be reset to 0. While field bistLTCH in register BIST_RX_CTRL1 (see Table 121) is set to 1, all the Read-
2802 Only BIST Monitor Results registers shall be latched.

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11.3.2 Keep-Alive
2803 The Network Function shall monitor its packet scheduling over time. If no packets are scheduled for
2804 transmission in a given direction (whether Downlink or Uplink) for a time period longer than KEPALVT
2805 (defined in Table 74), then the Network Function shall send a Keep-Alive Packet. Both directions shall use
2806 the same value of KEPALVT. The KEPALVT period is renewed with any A-Packet transmission.
2807 At the receiver Port, if no A-Packets are received and delivered to the relevant Network Port’s Link Layer
2808 for a period larger than (KEPALVT * N, N>1), then it shall be considered as an error. The value of N shall
2809 be decided on a system level, depending on system-level fault tolerance time for relevant safety goals. Such
2810 an error event should be detected by monitoring the following fields in the Diagnostic Counter Registers
2811 (see Section 12.2.5.2):
2812 • Field GoodOriginalReceived in register DIAG_CNT5
2813 • Field BadOriginalReceived in register DIAG_CNT7
2814 • Field GoodDelivered in register DIAG_CNT1
2815 • Field BadDelivered in register DIAG_CNT3
2816 In a Keep-Alive A-Packet for any Port (i.e., Source or Sink):
2818 • The QoS sub-field shall contain 2’b00
2819 • The Prio (Priority) sub-field shall contain 2’b01
2820 • The Target Address (T-Address) field shall contain 0x00 (Link Partner)
2821 • The Payload shall consist of a single byte, set to 0x00
11.3.3 Remote Sleep Command
2822 To support the Sleep Transition specified in Section 10.3.3.7, the RemoteSleep_cmd indication shall be
2823 passed by using the Remote Sleep Command.
2824 In a Remote Sleep Command A-Packet:
2826 • The QoS sub-field shall contain 2’b00
2827 • The Prio (Priority) sub-field shall contain 2’b01
2828 • The Target Address (T-Address) shall contain 0x00 (Link Partner)
2829 • The Payload shall consist of a single byte, set to 0x0E

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11.3.4 Running Time-Base Count (RTBC)

2830 The Running Time-Base Count (RTBC) link service enables a generic way to easily add timestamp
2831 information on tunneled traffic. Examples of such use cases can be found in the respective MIPI PAL
2832 specifications for PAL/GPIO and PAL/ETH, or in the Extended BIST (see Section 11.3.1.1). The RTBC
2833 service is based on a simple counter that increments at the same rate, and has the same value, at both Session
2834 Partners. The RTBC service is based on the Clock Forwarding Service (CFS) detailed in Section 11.6.2, and
2835 in particular the Time-Base Service (TBS) detailed in Section 11.6.2.1.5.
2836 The RTBC counter:
2837 • Shall be a 32-bit, wrap-around counter.
2838 • Shall represent nanoseconds, counted in the Initiator’s reference clock (e.g., counter value 1234
2839 represents 1234 nanoseconds).
2840 • Shall reset to zero at the transition from Idle to Normal modes of the Downlink Startup sequence
2841 (see First Reset Point as described in Section 8.3.3.1).
2842 When using TBS, the Initiator-To-Follower-Delay-ns is measured by the ACC_DELAY field of each CFS
2843 A-Packet used for TBS, and should be added to the counter value at the Follower side.

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11.4 Local Functions

2844 An A-PHY Device shall implement the Local Function when it has one or more Native Protocol Adaptation
2845 Layers.
2846 An A-PHY Device with Local Function (i.e., with Port-ID=1) shall implement the following functions for all
2847 A-Packets destined for this A-PHY Device (i.e., for all A-Packets forwarded to Port-ID=1):
2848 1. Parse the A-Packet fields:
2849 • Use the A-Packet’s Adaptation Type sub-field to determine the target Native Protocol Adaptation
2850 Layer
2851 • If needed, use the A-Packet’s Target Address (T-Address) field to determine the target Native
2852 Protocol Adaptation Layer (i.e., if there is more than one Adaptation Layer instance with the same
2853 Adaptation Type value)
2854 2. Determine what target Native Protocol Adaptation Layer to forward the A-Packet to, according to
2855 the LOC_TBL (see Section 11.4.1)
2856 3. Deliver the A-Packet to the selected Native Protocol Adaptation Layer

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11.4.1 Local Table (LOC_TBL) Recommendations (Informative)

2857 This is an informative section describing a recommended efficient Local Table implementation.
2858 Consider the following Local Function steps:
2859 • Use the A-Packet’s Adaptation Type sub-field as the Entry-Index to the LOC_TBL
2860 • Read the Entry-Descriptor and decide on its Format and Length
2861 • Use the A-Packet’s T-Address (if needed) and the relevant Entry-Element to retrieve the Adaptation
2862 Layer ID
2863 • Deliver the A-Packet to the selected Adaptation Layer.
2864 Each entry in the Local Table represent an Adaptation Type. For example, entry 13 represent all the CSI-2
2865 Adaptation Layer instances of this A-PHY Device.
2866 Figure 109 illustrates that the content of each entry begins with the Entry Descriptor byte, followed by a list
2867 of the Entry Elements.
...
LOC_TBL Entry
12
...
LOC_TBL Entry
13
Entry
Descriptor
Entry-Element#1 Entry-Element#2 ...
LOC_TBL Entry
14
...
...
2868
Figure 109 Local Table Example
2869 The Entry Descriptor is described in Table 91.

2870 Table 91 Local Table Entry Descriptor
Entry Descriptor
Bits Values
Sub-Fields
Reserved [7:6] Reserved for future use
The Entry-Element Format:
0: Reserved
1: Direct Assignment: one T-Address to one AL-ID
Format [5:4]
2: Range Assignment: T-Address sequence starting from First and
ending at End, to a single AL-ID
3: Reserved
The number of Entry-Elements in this Entry:
0: Empty Entry
Length [3:0]
1: Single Entry-Element
2 to 15: Number of Entry-Elements

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2871 The Entry Element Format is shown in Figure 110.
Single Assignment Format Range Assignment Format
Entry-Element#n Entry-Element#n
Adaptation From To Adaptation

T-Address
Layer ID T-Address T-Address Layer ID
2872
Figure 110 Entry-Element Formats
2873 In Direct Assignment Format, A-Packets with a designated Adaptation Layer Type and with matching
2874 T-Address are distributed to the Adaptation Later specified by its Adaptation Layer ID.
2875 In Range Assignment Format, A-Packets with designated Adaptation Layer Type and with T-Address value
2876 within the range defined between the From T-Address and the To T-Address are distributed to the Adaptation
2877 Later specified by its Adaptation Layer ID.
2878 An Entry that is defined as Direct Assignment Format, has only one Entry-Element (i.e., with Length=1), and
2879 where the T-Address field of its single Entry-Element is set to zero, is considered as “All T-Addresses”. In
2880 this case, all A-Packets with the designated Adaptation Layer Type are distributed to the Adaptation Layer
2881 specified by its Adaptation Layer ID, ignoring the T-Address value.
2882 When a Local Table Entry consists of more than one Entry-Element where the Adaptation Layer ID values
2883 are not all the same, this is considered as an “Adaptation Layer Cluster Type”, meaning that this A-PHY
2884 Device implements multiple Adaptation Layers of the same type (e.g., three CSI-2 Adaptation Layer
2885 instances).
2886 Figure 111 depicts examples of the different cases.
A-Packets with AL-Type=12

with All T-Address values are
...
distributed to AL-ID=1 A-Packets with Cluster AL-Type=13

with T-Address values 20 and 22
Entry-Element#1 are distributed to AL-ID=2,
T-Address AL-ID and with T-Address value 23 to AL-ID=3
LOC_TBL Entry 0x11
12 0 1
Entry-Element#1 Entry-Element#2 Entry-Element#3

T-Address AL-ID T-Address AL-ID T-Address AL-ID
LOC_TBL Entry 0x13
13 20 2 22 2 23 3
Entry-Element#1
T-Address Range AL-ID
LOC_TBL Entry 0x21
14 30 39 4 A-Packets with AL-Type=14
with T-Address values in the
Range between 30–39
...
are distributed to AL-ID=4

2887
Figure 111 Local Table Example

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11.5 Multi-Port Functions

2888 When an A-PHY device has several PHY Ports, it is considered to be a Multi-Port A-PHY Device.
2889 A Multi-Port-A-PHY-Device shall implement the Multi-Port Routing Function as specified in Section 11.5.1.
11.5.1 Multi-Port Routing Function
2890 The Routing Function shall have two stages:
2891 • A-Packet Duplication Stage, according to the DUP_TBL (see Section 11.5.1.1)
2892 • A-Packet Forwarding Stage, according to the ROUT_TBL (see Section 11.5.1.2)
2893 As result of the Forwarding Function, A-Packets shall be forwarded either to Adaptation Layer(s), where they
2894 are treated according to the Local Function (see Section 11.4), or to A-PHY Port(s), where they are treated
2895 according to the Network Function (see Section 11.6).
11.5.1.1 Packet Duplication Stage
2896 An A-PHY Device acting as a Forwarding Element shall apply the Packet Duplication Stage on all received
2897 packets from all A-PHY Ports and from all Adaptation Layers.
2898 The A-Packet’s Target Address shall be searched in the DUP_TBL, and shall be handled according to the
2899 conditions shown in Table 92.
2900 Table 92 Duplication Stage Actions
Condition Description Action Output
Received T-Address is not DUP_TBL

Error:
present in the DUP_TBL Entry does not NULL
Corrupted DUP_TBL
(as Entry T-Address) exist
DUP_TBL
Error:
DUP_TBL Entry is Empty Entry exists, NULL
Corrupted DUP_TBL
but is empty
DUP_TBL Entry contains a
One A-Packet similar to
single value which is equal No duplication No Action
the received one (reused)
to the received T-Address
DUP_TBL Entry contains a One A-Packet similar to
single value which is T-Address the received one
Replace T-Address
different from the received Replacement (reused), but with a
T-Address different T-Address
Generate N−1 A-Packets. N A-Packets similar to the
Set T-Address to the N received one, each with a
DUP_TBL Entry contains N
Duplication A-Packets according to the different T-Address,
values, where N > 1
values contained in the according to the
DUP_TBL Entry DUP_TBL Entry

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11.5.1.2 Packet Forwarding Stage

2901 The Packet Forwarding Stage shall be operated by any A-PHY Device acting as a Forwarding Element, after
2902 the Duplication Stage.
2903 The A-Packet’s Target Address shall be searched in the ROUT_TBL and shall be forwarded to the Port ID
2904 listed in the ROUT_TBL Entry for that Target Address.
2905 The Port ID field in a ROUT_TBL entry shall use the values shown in Table 93.
2906 Table 93 Pre-Defined Port ID Values
Port ID Value Function Description
A-Packets that are directed to the Trash Function are wasted

0 Trash Function
(through, disregard, discard)
A-Packets that are directed to the Local Function are aimed to
1 Local Function
one of the local Adaptation Layer instances
A-Packets that are directed to a Network Function are aimed to
2 to 254 Network Function be forwarded to another A-PHY Device via one of the A-PHY
Ports
255 Reserved Reserved
2907 Each A-Packet is forwarded according to the value in the Target Address field in its A-Header
2908 (see Section 11.2.1.5).

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11.5.1.3 Routing Table (ROUT_TBL) Recommendations (Informative)

2909 This is an informative section describing a recommended efficient Routing Table implementation.
2910 The Routing Table (ROUT_TBL) describes, per Target Address, which Port to forward the A-Packet to.
2911 Any A-PHY Device acting as a Forwarding Element will have one Routing Table (ROUT_TBL) for each of
2912 its A-PHY Ports. Each ROUT_TBL contains up to 256 entries, with one entry for each Target Address
2913 (referred to as the Entry T-Address). Each entry contains a single Port ID.
2914 For the proposed efficient configuration, the Port ID value of a A-PHY Port will not appear in any of its
2915 ROUT_TBL Entries.
2916 Figure 112 illustrates a ROUT_TBL example.
Network Port ID = 4
ROUT_TBL
...
ROUT_TBL Entry Port-ID A-Packets with T-Address = 12

are forwarded to the Local Port
12 1 (also T-Address = 14)

are forwarded to the Trash
13 0 Port (also T-Address = 16)
ROUT_TBL Entry Port-ID

14 1

are forwarded to Network Port
15 3 ID=3
ROUT_TBL Entry Port-ID

16 0

are forwarded to Network Port
17 2 ID=2
...
2917
Figure 112 ROUT_TBL Example

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11.5.1.4 Duplication Table (DUP_TBL) Recommendations (Informative)

2918 This is an informative section describing a recommended efficient Duplication Table implementation.
2919 The Duplication Table (DUP_TBL) describes, for each received T-Address, how many duplications to make
2920 for the A-Packet and what Target Address value to use for each such instance of duplication.
2921 Any A-PHY Device acting as a Forwarding Element will have one Duplication Table (DUP_TBL) for each
2922 of its A-PHY Ports.
2923 A DUP_TBL contains up to 256 entries, with one entry for each T-Address (referred to as the Entry
2924 T-Address), but no more than MaxPortsCNT entries (where MaxPortsCNT is the maximum number of
2925 A-PHY Ports that the A-PHY Device implements).
2926 Each DUP_TBL Entry includes an Entry Descriptor that describes how many Entry-Elements it contains.
2927 The number of Entry-Elements could be as shown in Table 94.
2928 Table 94 DUP_TBL Entry Elements
DUP_TBL Entry
Name Description
Descriptor Value
An Empty Entry is used when no operation is required.
0 Empty Entry These A-Packets are just handed to the next stage (i.e., to
the Forwarding Stage)
A Replacing Entry is used to replace the T-Address value
1 Replacing Entry
of matching A-Packets.
A Duplicating Entry is used to duplicate matching
2 – MaxPortsCNT Duplicating Entry A-Packets, creating the required number of duplication
instances and assigning each one the required T-Address
2929 Any T-Address value may appear in the Entry-Element list, providing that a given T-Address value does not
2930 appear in more than one Entry-Element of the same DUP_TBL Entry.
2931 Figure 113 illustrates a DUP_TBL example.

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Network Port ID = 4
DUP_TBL
...
DUP_TBL Entry Descriptor Entry-Element A-Packets with T-Address = 12
12 =1 = 12 are not changed
DUP_TBL Entry Descriptor A-Packets with T-Address = 13

13 =0 are also not changed
DUP_TBL Entry Descriptor Entry-Element A-Packets with T-Address = 14

have their T-Address replaced
14 =1 = 22 with 22
A-Packets with T-Address = 15
are duplicated to three duplication
DUP_TBL Entry Descriptor Entry-Element Entry-Element Entry-Element instances:
15 =3 = 15 = 35 = 45 - The first keeps T-Address 15
- The second gets T-Address 35
- The third gets T-Address 45
DUP_TBL Entry Descriptor
16 =0
A-Packets with T-Address = 17

DUP_TBL Entry Descriptor Entry-Element Entry-Element are duplicated to two duplication
instances:
17 =2 = 37 = 47 - The first gets T-Address 37
- The second gets T-Address 47
...
2932
Figure 113 DUP_TBL Example

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11.6 Network Functions

11.6.1 Scheduling and Priorities
2933 When multiple A-Packets are handed to an A-PHY Port for transmission, they need to be ordered and
2934 prioritized according to the value in the Prio field.
2935 A-Packets with higher priority shall be scheduled for transmission over the A-PHY Link before packets with
2936 lower priorities.
2937 A-Packets of the same priority shall be scheduled for transmission according to their arrival/reception order
2938 (first-in, first-out).
2939 The order of A-Packets shall be preserved per priority, such that A-Packets transmitted with the same priority
2940 will arrive at their destination in the same order in which they were transmitted.
2941 There are two levels of packet Scheduling-Priority over the A-PHY Network, translating into different latency
2942 and latency variation figures per priority level.
2943 The QoS field is used by the PHY Layer to set the transmission and reception properties accordingly
2944 (see Section 8.3.1).

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11.6.2 Clock Forwarding Service

2945 The Clock Forwarding Service (CFS) is intended to improve the performance of a re-constructed clock that
2946 was transferred over the A-PHY Network.
2947 Typically, a Native Application Clock is measured at one Adaptation Layer with its own reference clock and
2948 its information is passed to the peer Adaptation Layer for it to reconstruct, with its own reference clock, the
2949 Native Application Clock accurately and synchronously to the origin Native Clock (e.g., DSI’s pixel clock,
2950 etc.). Both reference clocks’ rates shall be set to the same value, but they are not synchronized and have
2951 inherent differences (drift and jitter) allowed within the specification of Section 9. Since the measuring and
2952 re-constructing clocks are not the same, and since a general A-PHY Network may consist of intermediate
2953 devices, some compensations are required.
2954 The information needed to support the Clock Forwarding Service is sent between the two Adaptation Layer
2955 peers using a specialized A-Packet, called a CFS A-Packet.
11.6.2.1 CFS A-Packet Format
2956 The Native Application Clock information is sent from the Adaptation Layer that measures it, to the
2957 Adaptation Layer responsible for the reconstruction of the clock, using the CFS A-Packet format.
2958 In the CFS A-Packet Header:
2959 • The Adaptation Type sub-field shall be set to 2 (4’b0010)
2960 • The Prio (Priority) sub-field shall be set to 1 (2’b01)
2961 • The QoS sub-field (i.e., the Latency_QoS bit and the Err_Resistance_QoS bit) shall be set according
2962 to the specific relevant Native Protocol Adaptation Layer specification
2963 • The Order sub-field shall be set to 0 (2’b00) (i.e., Middle Chunk)
2964 • The OB (Odd Byte) sub-field shall be set according to the payload length (see Section 11.2.1.3.2).
2965 The payload of the CFS A-Packet is formatted according to Figure 114, with the following color coding:
2966 • White with crossing stripes: Native Protocol Adaptation Layer payload
2967 • White: Fields that are under the Native Protocol Adaptation Layer’s control
2968 • Black: Fields that are under the A-PHY Port’s control
2 Bytes 1 Byte Variable Length 3 Bytes
FreqOffset AL_TYPE Measurement ACC_DELAY
2969
Figure 114 CFS A-Packet Payload Format
2970 The fields of the CFS A-Packet payload are described in the following sub-sections.
11.6.2.1.1 Frequency Offset (FreqOffset) Field
2971 Each CFS A-Packet shall have a Frequency Offset field (see Figure 114) which is handled by each forwarding
2972 A-PHY Port along the A-PHY Network path.
2973 The FreqOffset field shall carry the relative difference between the origin MAL reference clock (Forc,
2974 normalized to its nominal value) and the reference clock (Ftxc normalized to its nominal value) of the A-PHY
2975 Port that is transmitting the CFS A-Packet in 2-25 units (e.g., a FreqOffset value of 32 means 1 PPM).
2976 The FreqOffset field is a two’s-complement signed value in the range of (−215 to (215 – 1)) x 2-25 ≈
2977 (−977 to 977) PPM.
2978 Each A-PHY Port transmitting the CFS A-Packet shall update the FreqOffset field accordingly. For example,
2979 if an intermediate device needs to forward a CFS A-Packet and the received CFS A-Packet's FreqOffset is
2980 set to V1 (that represents the difference between Forc to the transmitted device Ftx1), then it needs to add to
2981 that value the difference between its receiving Refence Clock (Frvc), on which it must be locked, and its own
2982 transmitting Reference Clock (Ftxc2). The new value of FreqOffset V2 should be: V2 = V1 + (Frvc − Ftxc2).

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11.6.2.1.2 Adaptation Layer Type (AL_Type) Field

2983 The AL_Type field of the CFS A-Packet payload contains the Adaptation Type code of the Adaptation Layer
2984 that uses the service. Each Adaptation Layer that uses CFS A-Packets shall assign its Adaptation Layer Type
2985 code (see Table 78) to any CFS A-Packet that it generates. The Adaptation Layer Type code shall be set in
2986 the AL_Type field of the CFS A-Packet payload format (see Figure 114).
2987 For example, if a DSI-2 Adaptation Layer makes use of the Clock Forwarding Service, then its generated
2988 CFS A-Packets shall contain the value 12 in their AL_Type payload field, per Figure 114.
2989 To clarify: The Adaptation Type subfield within the Adaptation Descriptor field within the A-Packet Header
2990 shall always be set to 2, whereas the AL_Type field shall be set to the type of the Adaptation Layer that uses
2991 the packet (which varies depending upon the particular Adaptation Layer in use).
11.6.2.1.3 Measurement Field
2992 The meaning and format of the Measurement field within the CFS A-Packet payload shall be specified by
2993 the particular Adaptation Layer specification in use (e.g., DSI-2 Adaptation Layer).
2994 For example, the Native Application Clock could be the Video Pixel Clock (with some frequency) and the
2995 Measurement could be a field composed of a 64-bit value that represents a Fixed-Point division of the Native
2996 Application Clock and the local Reference Clock. It could also be some other format, for example a counter
2997 of clock edges.
2998 The Measurement field within the CFS A-Packet payload shall not be changed by the A-PHY Data Link
2999 Layer.
11.6.2.1.4 Accumulated Delay (ACC_DELAY) Field
3000 To allow phase-synchronized distribution of the Native Application Clock, the delay of each CFS A-Packet
3001 is measured over the A-PHY Network.
3002 This measurement shall be present in the ACC_DELAY field (see Figure 114) of a CFS A-Packet payload.
3003 The ACC_DELAY field shall carry the time in nS units (24-bit value) from its generation until its presentation
3004 on the physical Link carrying it (interconnect). This field is accumulated over the entire topology.

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11.6.2.1.5 Time-Base Service

3005 The Time-Base Service (TBS) is a sub-service of the generic CFS. In TBS, instead of sharing the Native
3006 Application Clock, the reference clock of one A-PHY Port is shared with another A-PHY Port. It can then be
3007 used for timestamping services of many Adaption Layers’ traffic tunneling as described in Section 11.3.4.
3008 When two A-PHY Port wish to share a common Time-Base between them, they use the TBS. In such a case,
3009 one A-PHY Port is designated the TBS-Initiator and the other A-PHY Port is designated the TBS-Follower.
3010 The CFS A-Packet used for TBS shall set the A-Packet fields as described in
3011 Table 95.
3012 Table 95 CFS A-Packet Fields for TBS
Sub-Field Name Size
Field Name Value in TBS Description
(bits)
Indicates “Link Service” as described

AL_Type – 8 1
in Table 78
Time-Base Measurement Window

TBWIND 4 0 – 15 Period (MWP) in nanoseconds:
MWPns = 2TBWIND+10
Measurement
Reserved 4 – –
Running Time-Base Count as in

TBCOUNT 32 0 – (232 − 1)
Section 11.3.4
3013 All A-PHY Ports shall update fields FreqOffset and ACC_DELAY in the CFS A-Packets used for TBS,
3014 according to Section 11.6.2.1.1 and Section 11.6.2.1.4, respectively.

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11.7 APPI Signal Interface

3015 The A-PHY Protocol Interface (APPI) is used to make a connection between the A-PHY Link Layer and
3016 higher protocol adaptation layers.
3017 The APPI signal interface described here is intended to be generic and application independent.
3018 The interface described here is defined as an on-chip connection and does not attempt to minimize signal
3019 count or define timing parameters or voltage levels for the APPI signals.
11.7.1 Signals Description
3020 The APPI has two independent symmetrical interfaces:
3021 • The DO (Data Out) path describes the data flow from the Data Link Layer to the Native Protocol
3022 Adaptation Layer
3023 • The DI (Data In) path describes the data flow from the Native Protocol Adaptation Layer to the Data
3024 Link Layer
3025 The APPI Clock source shall be from the Data Link Layer to the Native Protocol Adaptation Layer.
11.7.1.1 APPI Signals
3026 The A-PHY APPI signals are described in Table 96 and the high-level connectivity is shown in Figure 115.
3027 APPI timing diagrams are shown in Section 11.7.4.
3028 Table 96 APPI Signals
Direction
Signal Name Description
O = Out / I = In
N-bit parallel data output from APDLL to NPAL

DO_DAT [N−1:0] O
(where N = 16, 32, or 64 bits)
DO_RDY I Ready to receive data indication from NPAL to APDLL
DO_REQ O Request to send data from APDLL to NPAL
DO_PSTRT O Packet start indication from APDLL to NPAL
APPI_CLK O Synchronous Clock of the APPI (Section 11.7.2)
N-bit parallel data input from NPAL to APDLL

DI_DAT [N−1:0] I
(where N = 16, 32, or 64 bits)
DI_RDY O Ready to receive data indication from APDLL to NPAL
DI_REQ I Request to send data from NPAL to APDLL
DI_PSTRT I Packet start indication from NPAL to APDLL
3029 Note:
3030 The data bus width (‘N’) shall be the same for both interfaces (DI_DAT and DO_DAT)

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DI_REQ
DI_RDY
DI_PSTRT
DI_DAT[N-1:0]
Data Link Layer

APPI CLOCK
DO_REQ
DO_RDY
DO_PSTRT
DO_DAT[N-1:0]
3031
Figure 115 APPI Connectivity
11.7.2 APPI Clock

3032 The APPI Clock shall be a Synchronous clock input to the Adaptation Layer.
3033 The clock frequency shall be defined by the PHY speed and the APPI bus width, per Table 97.
3034 The APPI Clock shall not exceed 500 MHz.
3035 TCLK = 1 / APPI clock frequency
3036 Table 97 APPI Clock Frequency Settings
APPI Bus Width
Link Rate (Bits)
(Gbps)
16 32 64
2 125 MHz 62.5 MHz 31.25 MHz
4 250 MHz 125 MHz 62.5 MHz
8 500 MHz 250 MHz 125 MHz
12 NA 375 MHz 187.5 MHz
16 NA 500 MHz 250 MHz
24 NA NA 375 MHz
32 NA NA 500 MHz

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11.7.3 APPI A-Packet Mapping

3037 Figure 116 illustrates APPI byte mapping, based on the A-Packet partitioning shown in Figure 50.
Newer Older
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
Dn Dn-1 Dn-2 Dn-3 Dn-4 D3 D2 D1 D0 H7 H6 H5 H4 H3 H2 H1 H0
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
MSB
MSB
MSB
MSB
MSB
MSB
APPI 16b Bus
LSB
APPI3 APPI2 APPI1 APPI0
LSB
LSB
LSB
LSB
APPI5 APPI4
LSB
MSB
MSB
MSB
APPI2 APPI1 APPI0 APPI 32b Bus
LSB
LSB
LSB
MSB
APPI0 APPI 64b Bus
LSB
3038
Figure 116 APPI A-Packet Mapping

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11.7.4 APPI Timing Diagrams

3039 The APPI timing (see Figure 117) is the same for A-PHY Source and Sink.
DI_REQ
DI_RDY
DI_DAT [N-1:0] DI_DATA
DI_PSTRT
APPI CLOCK
DO_REQ
DO_RDY
DO_DAT [N-1:0] DO_DATA
DO_PSTRT
3040
Figure 117 APPI Timing
3041 Note:
3042 i) APPI Clock is defined in Section 11.7.2
3043 ii) DI_DAT and DO_DAT shall have the same N bus width
3044 iii) Dx_RDY can be asserted regardless of Dx_REQ status
3045 iv) Data is valid be transmitted upon asserting both Dx_REQ and Dx_RDY
3046 v) Dx_PSTRT is asserted at the start of packet transmission

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12 A-PHY Control and Management Database (ACMD) and

Protocol (ACMP)
3047 The A-PHY Control and Management Database (ACMD) specifies the set of registers that are used to control
3048 and manage all the A-PHY Layers as specified in this specification.
3049 The A-PHY Control and Management Protocol (ACMP) is used to access ACMD registers. It is an
3050 interface-independent protocol that may be implemented with any native control and management interface
3051 listed in and selected by Table 110. A specific ACMP Mapper is used to map between the native interface
3052 being used and the ACMP. An A-PHY Device shall support the ACMD and ACMP as described in
3053 Section 12.2 and Section 12.3, respectively.
3054 The ACMD and ACMP are used to control and manage the A-PHY entity via its local Host (e.g., on the same
3055 board). To control and manage a remote A-PHY entity, the native control and management interface in use
3056 shall be tunneled over the A-PHY Data Plane using the respective Adaptation Layer. The A-PHY’s Control
3057 Plane, which includes the ACMD and ACMP, has no direct communication with the A-PHY’s Data Plane.
3058 The current version of this specification (A-PHY v1.1) only supports the I2C protocol as the native control
3059 and management interface for tunneling the ACMP. Future versions of the specification may support other
3060 protocols for ACMP tunneling.
3061 This is depicted in Figure 118.
To Host /
Peripheral
External Opt.
Mapper
Internal Adaptation Layer ... Adaptation Layer
Opt. LEGEND
ACMP Local Function Native Interface

Spec Layer
Multi-Port Link Layer APPI
ACMD Link Port (virtual)
Data Plane
Network Network
Function Function
Control Plane
Link Link Database

Mapper
PHY PHY
A-PHY Specification Document Borders

3062
Figure 118 A-PHY Control and Data Planes
3063 The Internal Native Option (marked as a dotted line between Adaptation Layer and Mapper) is the option
3064 that allows ACMD to be accessed without an external interface (e.g., connector), typically used in integrated
3065 devices. An A-PHY Device shall implement at least one of the options (External Option, Internal Option, or
3066 both).

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12.1 Control and Management System Architecture (Informative)

3067 The Control and Management scheme for A-PHY is designed to allow ease of integration with systems from
3068 A-PHY’s target marketplaces (e.g., Automotive). Several of MIPI’s Specifications are targeting the same goal
3069 and are typically based on Controller/Target protocols and interfaces (e.g., CCI, I3C, etc.).
3070 Note:
3071 In previous versions of the A-PHY Specification, a Controller was called a “Master” and a
3072 Target was called a “Slave”. MIPI Alliance has deprecated the use of the words “Master”
3073 and “Slave” in technical terms, so the A-PHY Specification now uses the updated normative
3074 terms “Controller” and “Target”, respectively. Please note that the technical definitions of
3075 Controller and Target, and their Roles in this Specification, are unchanged.
3076 The major update required from such system architectures is to move from a close-proximity Native System
3077 to a long-distance distributed A-PHY based system, but still provide minor changes (or no changes at all)
3078 from the perspective of the control and management Host. In a close-proximity system, side-band interfaces
3079 such as I2C or I3C may be used. When applied on longer-distance A-PHY interconnect systems, the control
3080 and management is achieved in-band (within the A-PHY traffic itself). This is achieved by sharing and
3081 reusing the same Controller/Target and Host/Peripheral concepts, as depicted in Figure 119.
1. DedicatedCM
APP Peripheral From Native Systems

Data (close proximity)
(HOST) (e.g. SNS)
CTRL
Single Control & Control &

Point of Mgmt. Mgmt.
Control Controller Target
To A-PHY Based Systems
(long-distance, distributed)
1a. Non-Integrated
Adaptation Adaptation
Layer Layer
APP A-PHY A-PHY Peripheral
Data Data
(HOST) Port Port (e.g. SNS)
CTRL
CTRL
Control & From Non-Integrated era Control &

Single ACMP ACMP
Point of Mgmt. Mgmt.
Control Controller Target
To Integrated era
1b. Integrated
Adaptation Adaptation
Layer Layer
APP A-PHY A-PHY Peripheral
Data Data
(HOST) Port Port (e.g. SNS)
CTRL
CTRL
Single ACMP ACMP

Control & Control &
Point of
Mgmt. Controller Mgmt. Target
3082 Control
Figure 119 Control and Management System Architecture

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3083 Typically, in Automotive, the A-PHY network will be deployed in a fixed topology where all the network
3084 information is known in advance (pre-configuration). Such networks are typically relatively small and require
3085 relatively simple control and management efforts, but at the same time have demanding requirements for
3086 bring-up and response times, and/or optimized utilization and/or performance.

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3087 In Figure 119, an evolution of solution is presented, from the legacy systems that were designed and limited
3088 for “close proximity” solutions with a dedicated control and management channel (“1. DedicatedCM” in the
3089 figure), through a distributed solution that is based on A-PHY technology but uses A-PHY bridges which are
3090 not integrated within the application device (“1a. Non-Integrated”), and on to the case where A-PHY
3091 technology is integrated into the application device providing a single-device solution (“1b. Integrated”). All
3092 of these solutions still use the same control and management channel concepts known to the legacy systems.
3093 Fixed-topology networks allow dynamic and real-time events like selection of active session, duplication and
3094 termination of sessions, changing session properties, changing Adaptation Layer behavior, etc., and can
3095 support several configuration models like per-element configuration, single-point-of-configuration, change
3096 of configuration, etc.

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12.2 ACMD
3097 The A-PHY Control and Management Database (ACMD) is built from a collection of Registers. The Register
3098 address is a 16-bit value referred to as the Base Address (BA) and the Register data is an 8-bit, 16-bit, or
3099 32-bit value referred to as Register Data.
12.2.1 Register Base Address Alignment
3100 The Register’s Base Address shall be aligned according to Table 98.
3101 Table 98 Register Base Address (BA) Alignment
Register Base Address (BA)
Register Data Size Example
Alignment
8-bit 8-bit aligned 0x0001, 0x0002, 0x0057
12.2.2 Register Data Byte Order

3102 The most significant data byte of a Register is mapped to the lower-ordered relative byte address, as depicted
3103 in Table 99.
3104 Table 99 Register Data Byte Order
+3 +2 +1 +0 Base Address
…
REG_SIXT REG_SIXT REG_EIGHT 0x0010
REG_THIRTYT REG_THIRTYT REG_THIRTYT REG_THIRTYT 0x0014
0x0018
0x001C
…
3105 The Table 99 example shows example data byte layouts for 8-bit, 16-bit, and 32-bit Registers:
3106 • Register REG_EIGHT (orange background) is an 8-bit Register with BA = 0x0010
3107 • Its single data byte is located at the same BA, 0x0010
3108 • Register REG_SIXT (purple background) is a 16-bit Register with BA = 0x0012.
3109 • Its most significant data byte is located at the same BA, 0x0012
3110 • Its least significant data byte is located at BA 0x0013
3111 • Register REG_THIRTYT (green background) is a 32-bit Register with BA = 0x0014
3112 • Its most significant data byte is located at the same BA, 0x0014
3113 • Its second most significant data byte (MH) is located at BA 0x0015
3114 • Its third most significant data byte (ML) is located at BA 0x0016
3115 • Its least significant data byte is located at BA 0x0017

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12.2.3 Register Space

3116 Figure 120 depicts the ACMD Register Space.
0x0000
Example:
CCS Registers 0x1000
0x0000–0x1FFF
0x2000
Example:
Image Statistics Registers
0x2000–0x2FFF
0x3000
Application-Specific
Registers 0x4000
0x0000– 0x7FFF
Example: 0x5000
Manufacturer-Specific
Registers (MSR)
0x3000–0x7FFF 0x6000
0x7000
0x8000
A-PHY Common Registers
0x8000–0x8FFF
0x9000
0xA000
0xB000
Registers for 0xC000

A-PHY Ports and
Adaptation Layer Instances
0xD000
0x9000–0xFFFF
0xE000
0xF000
3117 0xFFFF
Figure 120 ACMD Register Space
3118 Each instance in the A-PHY Ports and Adaptation Layer Instances Register Space (from 0x9000 to 0xFFFF)
3119 shall start with INST_DESC Registers, which shall have the format defined in Table 128.

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3120 The A-PHY Ports and Adaptation Layer Instances Register Space shall be constructed according to Figure
3121 121.
Instance Instance
INST_DESC Reg Next Instance Ptr
Type Index/ID
...
Instance Instance
Type Index/ID
...
Instance Instance
...
Type Index/ID
...
3122
Figure 121 Ports and AL Instances Register Space Arrangement
3123 The A-PHY Ports and Adaptation Layer Instances Register Space shall be arranged so that the first instances
3124 are A-PHY Port instances and the rest are Adaptation Layer instances. The number of A-PHY Port instances
3125 shall be located in Register PORT_NUM (see Table 104), and the number of Adaptation Layer instances shall
3126 be located in Register AL_NUM (see Table 105).

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12.2.4 Register List

3127 Table 100 lists all Registers defined for the A-PHY Common Registers.
3128 Table 101 lists all Registers defined for the Ports and AL Instances Register Space.
3129 Table 100 A-PHY Common Registers List
Register Size Detailed
Register Name Description
Offset (Bytes) In
0x8000 A-PHY_VER 1 The version of A-PHY Table 102
+ 0x01 ACMD_ADDRESS 1 E.g., 7-bit Target Address in I2C Table 103
+ 0x02 PORT_NUM 1 Number of A-PHY Ports Table 104
+ 0x03 AL_NUM 1 Number of Adaptation Layers Table 105
The most significant 4 bytes of the 6-byte
+ 0x04 ID6_HIGH 4 ID E.g., Provisioned ID as specified in the Table 106
MIPI I3C Specification [MIPI05]
The least significant 2-bytes of the 6-byte
+ 0x08 ID6_LOW 2 ID E.g., Provisioned ID as specified in the Table 107
MIPI I3C Specification [MIPI05]
+ 0x0C MID 2 MIPI Alliance Manufacturer ID [MIPI08] Table 108
+ 0x0E PRODUCT_ID 2 Vendor-specific product identifier Table 109
+ 0x10 ACMP_IF 1 The native interface in use for ACMP Table 110
2
+ 0x11 ACMD_SECONRADDR 1 E.g., 7-bit Target Address in I C Table 111
+ 0x12 ACMD_BRDCSTADDR 1 E.g., 7-bit Target Address in I2C Table 112
+ 0x13 FEATURE_CAP 1 Feature Capabilities Table 113
+ 0x14 FEATURE_CTRL 1 Feature Control Table 114
… – – – –
+ 0x30 BIST_TX_CTRL1 1 BIST Generator Control

Table 115
+ 0x31 BIST_TX_CTRL2 1 BIST Generator Control Table 116
… – – – –
+ 0x40 BIST_RX_CTRL1 1 BIST Monitor Control Table 121
+ 0x44 BIST_RX_MON1 4 BIST Monitor Results Table 122
+ 0x4C BIST_RX_MON3 4 BIST Monitor Results Table 124
… – – – –
+ 0x100
Vendor_Specific – – –
and Higher

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3130 Table 101 Port Space Register List

Register Size
Register Name Remarks / Description Detailed In
Offset (Bytes)
PORT_INST = Next Instance pointer
0x9000 (or as
Instance Index used as ID of this
indicated by INST_DESC 4 Table 128
A-Port
previous
Instance) Instance Type used as A-Port Type
+ 0x04 PORT_CAP 1 Port Capabilities Table 129
+ 0x05 PORT_CONFIG 1 Port Configuration Table 131
+ 0x06 TEST_CONFIG 1 Test-Mode Configuration Table 133

Extended Port Capabilities
+ 0x07 PORT_CAP_2 1 Table 130
New in A-PHY v1.1
Extended Port Configuration
+ 0x08 PORT_CONFIG_2 1 Table 132
New in A-PHY v1.1
… – – – –
+ 0x10 FSM_CONFIG 1 FSM Configuration Table 134
+ 0x11 FSM_STATUS 1 FSM Status Table 135
+ 0x12 – – – –
+ 0x13 WUP_CTRL 1 Wake-Up Protocol Control Table 136
+ 0x14 LINK_STAT_REP 1 Link Status Report Table 137
… – – – –
+ 0x18 LINK_STAT_CTRL 1 Link Status Control Table 138
… – – – –
+ 0x20 DIAG_CTRL 1 Diagnostics Control Table 139

Set of 32-bit Registers to retrieve
diagnostics counters.
Table 140
All counters are saturated, and shall
+ 0x24 DIAG_CNT[1-12] 4 through
be wrap around.
Table 151
All counters are controlled with
Register DIAG_CTRL simultaneously.
… – – – –
+ 0x100
to Vendor_Specific – – –
+ 0x7FF

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12.2.5 Detailed Register Description

12.2.5.1 ACMD Programming
3131 This section provides detailed Register descriptions for all A-PHY Common Registers defined for the ACMD
3132 Register Space.
3133 Table 102 Register A-PHY_VER
Remarks /
Field Bits Values Attribute
Description
0x01: A-PHY
Specification
Version 1.0
Version 8 RO –
0x02: A-PHY
Specification
Version 1.1
3134 Table 103 Register ACMD_ADDRESS

Remarks /
Description
E.g., Target Address
Address 8 0 – 255 WR
in I2C
3135 Table 104 Register PORT_NUM

Remarks /
Description
4 0: Reserved
NumberOfPorts RO –
b3:b0 1 – 15: Ports
4
Reserved 0 – –
b7:b4
3136 Table 105 Register AL_NUM

Remarks /
Description
4
NumberOfAdaptationLayers 0 – 15: ALs RO –
b3:b0
4
Reserved 0 – –
b7:b4
3137 Table 106 Register ID6_HIGH

Remarks /
Description
The most significant
ID_High 32 0 – (232−1) RO 32 bits of the 48-bit ID
value

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3138 Table 107 Register ID6_LOW
Field Bits Values Attribute Remarks / Description
The least significant 16 bits

ID_Low 16 0 – (216−1) RO
of the 48-bit ID value
3139 Table 108 Register MID
MIPI Manufacturer ID
ManufacturerID 16 0 – (216−1) RO
[MIPI08]
3140 Table 109 Register PRODUCT_ID
Vendor-specific product
ProductID 16 0 – (216−1) RO
identifier
3141 Table 110 Register ACMP_IF
0: SW
Value 0 (SW) represents an
4 1: I2C
InterfaceCode RO internal, software-based
b3:b0 2: I3C
interface
3 – 15: Reserved
0: None
4
InterruptCode 1: GPIO – –
b7:b4
2 – 15: Reserved
3142 Table 111 Register ACMD_SECONDADDR
E.g., Secondary Target

Address in I2C
3143 Table 112 Register ACMD_BRDCSTADDR
E.g., Broadcast Target

Address in I2C

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3144 Table 113 Register FEATURE_CAP
Field Bits Values Attr Remarks / Description
BIST is defined at A-PHY Common

register area, therefore per device.
When this bit is set, the device
1 0: BIST per Port not used
BIST_PORT_ST RO uses BIST per Port, mapped to the
b0 1: BIST per Port is used
Port register area, at the same
specified offsets from the Port’s
Base Address.
0: Time-Base is not supported
1: Time-Base is supported on
TX
2
TIME_BASE_ST 2: Time-Base is supported on RO Time-Base support
b2:b1
RX
3: Time-Base is supported on
both TX and RX
1 0: RSRT is not supported Repetitive Scrambler Reset for Test
RSRT_ST RO
b3 1: RSRT is supported (RSRT) support
2
Reserved Reserved RO Reserved
b5:b4
1 0: ACMP-M0 is not supported See Section 12.3.1 and
ACMP-M0_ST RO
b6 1: ACMP-M0 is supported Section 12.3.2.
1 0: ACMP-MN is not supported At least one of these bits shall be
ACMP-MN_ST RO set to 1.
b7 1: ACMP-MN is supported
3145 A Device supporting ACMP-MN shall support and map to the ACMD register space all required registers as
3146 defined in the respective ACMP-MN specification.

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3147 Table 114 Register FEATURE_CTRL
Field Bits Values Attr Remarks / Description
1
Reserved Reserved WR Reserved
b0
0: Time-Base is disabled
1: Time-Base is enabled on
2 TX
TIME_BASE_EN WR Time-Base enable
b2:b1 2: Time-Base is disabled on
RX
3: Reserved
Repetitive Scrambler Reset for Test
1 0: RSRT is disabled
RSRT_EN WR (RSRT) shall only be enabled for
b3 1: RSRT is enabled tests
3 When RSRT is enabled, the

RSRT_NVAL 0-7: N = (21 + RSRT_NVAL) WR scrambler is reset every 2N
b6:b4
symbols (N = [21..28])
1 0: ACMP-M0 is selected
ACMP_MOD WR –
b7 1: ACMP-MN is selected
3148 Table 115 Register BIST_TX_CTRL1
2 QoS for generated BIST

bistQ See Section 11.3.1 WR
b1:b0 A-Packets
2 Priority for generated
bistP See Section 11.3.1 WR
b3:b2 BIST A-Packets
Inter Packet Gap (IPG)
4
bistR See Section 11.3.1.3 WR for generated BIST
b7:b4
A-Packets
Payload length (number

of 16-bit Words, not
8
bistL See Section 11.3.1 WR number of 8-bit bytes)
b7:b0
for generated BIST
A-Packets

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Target Address
8 (T-Address) for
bistT See Section 11.3.1 WR
b7:b0 generated BIST
A-Packets
WR BIST Mode for

4
bistMode See Section 11.3.1.1 generated BIST
b3:b0
A-Packets
WR Pattern for payload
4
bistPATT See Section 11.3.1.2 bytes for generated
b7:b4
BIST A-Packets
See Section 11.3.1 Odd Byte indication for

1
bistO WR generated BIST
b0
A-Packets
See Section 11.3.1 BAD indication for
1
bistBAD WR generated BIST
b1
A-Packets
See Section 11.3.1.4 Burst length for
4
bistB WR generated BIST
b2:b5
A-Packets
0: BIST Generator not
1 Active
bistACTV WR BIST Activation
b6 1: BIST Generator
Active
1 0: BIST Disabled BIST Enable
bistENB WR
b7 1: BIST Enabled

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Order indication for

2
bistORDR See Section 11.3.1 WR generated BIST
b1:b0
A-Packets
2
Reserved Reserved WR –
b3:b2
Extended BIST format
1 includes the BIST
bistEXT_MC See Table 86 WR
b4 Message Counter
(see Figure 107)
1 includes the BIST Time
bistEXT_TS See Table 86 WR
b5 Stamp
(see Figure 107)
1
bistEXT_CRC See Table 86 WR includes the BIST CRC
b6
(see Figure 107)
Reserved 1 –
Reserved WR
b7
3154 Table 121 Register BIST_RX_CTRL1
5
Reserved – – –
b4:b0
1 Clear/Reset all the BIST

0: Results not cleared
bistCLR WR Monitor Results
b5 1: Results cleared
Registers
Latch all the BIST
1 0: Results not Latched
bistLTCH WR Monitor Results
b6 1: Results Latched
Registers
1 0: BIST Monitor Disabled
bistENB WR BIST Monitor Enable
b7 1: BIST Monitor Enabled
3155 Table 122 Register BIST_RX_MON1
Number of received
BIST A-Packets with
good payload (e.g. good
pattern of zeros or
rcvGOOD 32 Packet Number WR PRBS, good Extended
BIST CRC field, good
Extended BIST
Message Counter field,
etc.)

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Number of received
BIST A-Packets with a
wrong payload (e.g.
wrong pattern of zeros
rcvWRONG 32 Packet Number WR or PRBS, wrong
Extended BIST CRC
field, wrong Extended
BIST Message Counter
field, etc.)
Number of received
rcvBAD 32 Packet Number WR BIST A-Packets with
their BAD bit set to one
Number of missing
BIST A-Packets, based
rcvMISS 32 Packet Number WR on received Extended
BIST Message Counter
fields
Maximal delay time (in

nSec) that a BIST A-
delayMAX 32 Nanoseconds WR Packet suffered, based
on its Extended BIST
Timestamp field
Minimal delay time (in

nSec) that a BIST A-
delayMIN 32 Nanoseconds WR Packet suffered, based
on its Extended BIST
Timestamp field

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12.2.5.2 Port Programming

3161 This section provides detailed Register descriptions for all Registers defined for the Ports and AL Instances
3162 Register Space.
3163 Table 128 Register INST_DESC
Remarks /
Description
16 Base Address (BA)
NextInstancePtr 0 – (216−1): 0x9000 RO
b15:b0 of the next Instance
Index of Instance
8
InstanceIndex 0 – 255 RO used as the ID of the
b23:b16
instance
For Adaptation
Layer Instance:
0: A-PHY Source Port
4 15:0 – According to
InstanceType SubType 1: A-PHY Sink Port RO
b27:b24 Adaptation Type
2 – 15: Reserved
Code (see Table
78).
2
InstanceTypeRes 0 RO –
b29:b28
0: Port Instance
2
InstanceTypeType 1: Adaptation Layer Instance RO –
b31:b30
2 – 3: Reserved
3164 Table 129 Register PORT_CAP

Remarks /
Description
0: Reserved All Gears up to and
4
MaxGear 1 – 5: GearX RO including this Gear
b3:b0
6 – 7: Reserved are supported
Profile 2 is
1 0: Not Supported supported for Gears
GL3P2 RO
b4 1: Supported lower than Gear3
(G2 and G1)
1 0: Not Supported Profile 1 is
G3P1 RO
b5 1: Supported supported for Gear3
2
b7:b6

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Table 130 Register PORT_CAP_2
Profile 2 supports Optional

PAM4 modulation for G1 and G2
1 0: Not Supported
GL3P2OPT RO Note:
b0 1: Supported
Applicable only if GL3P2 is set
to ‘1’
1 0: Not Supported
DRU RO Support for Dual Rate Uplink
b1 1: Supported
1 0: Not Supported Support for Q-Port Dual Lane
QPDDL RO
b2 1: Supported Downlink
1 0: Not Supported
QPAL RO Support for Asymmetric Q-Port
b3 1: Supported
1 0: Not Supported
QPSL RO Support for Symmetric Q-Port
b4 1: Supported
3
b7:b5
3165 Table 131 Register PORT_CONFIG
0: Reserved
4
GearSelect 1 – 5: Selected GearX RW –
b3:b0
6 – 7: Reserved
1 0: Not Enabled
GL3P2 RW –
b4 1: Enabled
1 0: Not Enabled
G3P1 RW –
b5 1: Enabled
2
b6:b7

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Table 132 Register PORT_CONFIG_2
1 0: Not Enabled Note:

GL3P2OPT RW
b0 1: Enabled Applicable only if GL3P2 is enabled
1 0: Not Enabled
DRU RW –
b1 1: Enabled
1 0: Not Enabled
QPDDL RW –
b2 1: Enabled
1 0: Not Enabled
QPAL RW –
b3 1: Enabled
1 0: Not Enabled
QPSL RW –
b4 1: Enabled
3
b7:b5
3166 Table 133 Register TEST_CONFIG
Field Bits Value Attribute Remarks / Description
0: Reserved
1: TM1
2: TM2
4 3: TM3 Test Mode select according to
TMSelect RW
b3:b0 4: TM4 Section 9.1.2.
5: TM5
6: TM6
7 – 15: Reserved
1
Reserved 0 – –
b4
2
TMData 0–3 RW Per Test Mode Selection
b6:b5
1 0: Normal Mode While this bit is set, the device is in
TMEnable RW
b7 1: Test Mode Test Mode

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3167 Table 134 Register FSM_CONFIG

Remarks /
Description
0: Infinite
4
StartUpFail_cnt 1 – 15: Maximum number of WR –
b3:b0
Start Up failures
1
b4
0: ManualStop_ind
1 See
ManualStopRequest is de-asserted RW
b5 Section 10.3.3.4.
1: ManualStop_ind is asserted
0: SleepRequestIn_ind
1 is de-asserted
SleepRequestLocal RW See Section 10.3.
b6 1: SleepRequestIn_ind
is asserted
1
b7
3168 Table 135 Register FSM_STATUS

Remarks /
Description
0: Unknown/Error
1: Power-Up State
2: Start-Up State FSM State
3
CurrentState 3: Sleep State RO according to
b2:b0
4: Normal State Section 10.3.2.
5 – 6: Reserved
7: Test State
0: Ready_ind
1 is de-asserted See
Ready RO
b3 1: Ready_ind Section 10.3.2.
is asserted
1
Reserved 0 – –
b4
0: AutoStop_ind
AutoStop RO
b5 1: AutoStop_ind Section 10.3.2.
is asserted
0: SleepRequestOut_ind
SleepRequestRemote RO
b6 1: SleepRequestOut_ind Section 10.3.2.
is asserted
1
b7

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3169 Table 136 Register WUP_CTRL

4
b3:b0
0: WakeupIn_ind
1 not asserted
SigGenRequest RW See Section 10.5.
b4 1: WakeupIn_ind
asserted
0: WakeupOut_ind
1 not asserted
SigDetectIndication RO See Section 10.5.
b5 1: WakeupOut_ind
asserted
2
b7:b6
3170 Table 137 Register LinkStatusReport

3 Indicates the Link Quality Level
LNKQUALLEVEL 0–7 RO
b2:b0 defined in the A-PHY Spec.
When set, indicates that no A-
1 Packet was delivered over the
NoKpAlvErr 0/1 RO
b3 A-PHY Link during the last
KEPITR x KEPALVT period.
4
b7:b4
3171 Table 138 Register LinkStatusControl

Defines the number of
4
KEPITR 0 – 15 RW KEPALVT periods before error
b3:b0
indication (NoKpAlvErr).
4
b7:b4

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3172 Table 139 Register DIAG_CTRL
0: Counting While this bit is set, all DIAG_CNTx

1
StopCounting RW counters shall hold their values and
b0 1: Stop Counting
shall not continue to count.
When this bit is set, all DIAG_CNTx
1 0: Normal
ClearCounters RW1C counters shall be reset to zero.
b1 1: Reset Counters
This bit is cleared-on-write.
1 0: Run When this bit is set, all DIAG_CNTx
LatchCount RW
b2 1: Latch counters shall latch their values.
6
(b7:b3)
3173 Table 140 Register DIAG_CNT1
Number of packets without error

indication (i.e., with A-Header sub-
32
GoodDelivered 0 – (232−1) RO field BAD cleared to 1’b0) that were
b31:b0
delivered to the Upper Layers (i.e., to
the APDLL)
32 Number of packets that were received

GoodReceived 0 – (232−1) RO
b31:b0 with good (correct) CRC-32 value
Number of packets with error

indication due to local reception of
32
BadDelivered 0 – (232−1) RO wrong CRC-32 errors, that were
b31:b0
delivered to the Upper Layers (i.e., to
the APDLL)
32 Number of packets that were received

BadReceived 0 – (232−1) RO
b31:b0 with bad (incorrect) CRC-32 value

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Number of Original packets

32 (see Table 26 and Section 8.2) that
GoodOriginalReceived 0– (232−1) RO
b31:b0 were received with good (correct)
CRC-32 value
32 Number of Good Retransmitted

GoodRtsReceived 0 – (232−1) RO
b31:b0 packets that were received
32 Number of Erroneous Original packets

BadOriginalReceived 0 – (232−1) RO
b31:b0 that were received
32 Number of Erroneous Retransmitted

BadRtsReceived 0 – (232−1) RO
b31:b0 packets that were received
Field Bits Value Attribute Remarks / Description
32 Number of Retransmission Requests

RtsRequestsSent 0 – (232−1) RO
b31:b0 that were sent
Number of packets with correct

32
Gaps 0 – (232−1) RO CRC32 value but wrong MC.
b31:b0
Only Original packets.

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32 Number of received packets with

Drops 0 – (232−1) RO
b31:b0 incorrect Header CRC (Dropped)
32 Number of MCs RTS requested (total,

RtsMCRequested 0 – (232−1) RO
b31:b0 including single and gap)

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12.3 ACMP
3185 The A-PHY Control and Management Protocol (ACMP) is designed for Controller/Target systems where the
3186 A-PHY device is a Target. The initiation of ACMP Messages is made by the Controller, typically the Host
3187 (e.g., Application Processor). The Host is required to initiate a Read Message in order to receive information
3188 from the A-PHY device. The A-PHY device only generates the ACMP Interrupt. The ACMP Interrupt is
3189 discussed in Section 12.3.3.
3190 This specification defines the control and management protocol that runs above the interfaces being used
3191 (e.g., I2C, I3C, etc.).
3192 Applications should make use of the ACMP protocol and its Functional Safety provisioning to perform
3193 control and management tasks. In addition, specific product dependent and proprietary functionalities may
3194 also make use of the ACMP protocol as part of the specified Vendor-Defined Register Space of ACMD.
3195 ACMP defines an additional protocol on top of the interface being used (e.g., I2C, I3C, etc.), as specified in
3196 the following sections.
3197 ACMP defines N+1 optional modes, which are denoted as ACMP-Mn with n ranging from 0 to N:
3198 • ACMP Mode 0 (ACMP-M0) is defined in Section 12.3.1. The ACMP-M0 message format integrates
3199 Functional Safety elements. The overall amount of traffic required for control and management is
3200 slightly increased. Processing of the Functional Safety elements is immediate, and can be validated
3201 by either side (i.e., by the Host side and/or by the Peripheral side).
3202 • ACMP Mode 1 (ACMP-M1) through ACMP Mode N (ACMP-MN) shall be defined by a higher-layer
3203 MIPI protocol specification, or by any other specification explicitly authorized by the MIPI Alliance
3204 Board of Directors.
3205 Any A-PHY Device shall support at least one of the ACMP optional modes.
3206 Example: The MIPI Alliance Camera Services Extensions (CSE) specification [MIPI10] defines ESS-CCI
3207 Mode 1 and ESS-CCI Mode 2 to meet the safety and security goals of the Camera Command Interface (CCI).
3208 ACMP-M1 may be defined as ESS-CCI Mode 1, and ACMP-M2 may be defined as ESS-CCI Mode 2.
3209 Applications (e.g., at the Host) using ACMP should use the ACMP’s Functional Safety related fields to
3210 implement the safety requirements and meet their safety goals.

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12.3.1 ACMP Mode 0 (ACMP-M0) Message Format

3211 ACMP-M0 provides means for Functional Safety provisioning by specifying a Message Format that includes
3212 all the necessary fields (i.e., CRC, MC, etc.).
3213 There are two types of messages, as shown in Figure 122:
3214 • Write Messages
3215 • Read Messages
Address
Header
8-bit
Message
Descriptor
8-bit
BA MSB
8-bit
BA LSB
8-bit
LEN MSB
8-bit
LEN LSB
8-bit
HCRC
8-bit
Data-1
8-bit
... Data-N
8-bit
PCRC
MSB
8-bit
PCRC
LSB
8-bit
Write
Message
Header Part Payload Part
Address
Header
8-bit
Message
Descriptor
8-bit
BA MSB
8-bit
BA LSB
8-bit
LEN MSB
8-bit
LEN LSB
8-bit
HCRC
8-bit
Address
Header
8-bit
Message
Descriptor
8-bit
Data-1
8-bit
... Data-N
8-bit
PCRC
MSB
8-bit
PCRC
LSB
8-bit
Read
Message
Header Part Payload Part
3216
Figure 122 ACMP-M0 Message Format
3217 The Byte Fields that are shown with dashed outlines in Figure 122 are optional, and exist only for certain
3218 Message Formats, as detailed in Table 152 and Table 153.
3219 Transmission Order:
3220 • The bits of the ACMP-M0 Message shall be transferred MSB (most significant bit) first, in field
3221 order (i.e., with Address Header first and PCRC last, from left to right).
3222 • Byte fields shall be transferred MSB first.
3223 • Multi-Byte fields shall be transmitted most significant byte first.
3224 Example: When writing a 16-bit Register value, Data-1 shall convey the most significant byte (i.e.,
3225 the most significant 8 bits) of the Register value, and Data-2 shall convey the least significant byte
3226 (i.e., the least significant 8 bits) of the Register value.

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12.3.1.1 ACMP-M0 Message Header Part

3227 The Header part of the ACMP-M0 Message (shown with purple background in Figure 122) includes the
3228 fields detailed in Table 152.
3229 Table 152 ACMP-M0 Message Header Fields
Field Sub-Field Bits Values Remarks
Address R/W 1 0: Write –
Header b0 1: Read
8 bits
Peripheral 7 0 – 127 Independent of
Address b7:b1 T-Address
Message Message Format 3 0: Short –
Descriptor b2:b0 (up to 32 Payload Bytes)
8 bits 1: Long
(up to 4096 Payload Bytes)
2 – 7: Reserved
2
Reserved 0 –
b4:b3
Message 3 0 – 7: MC value (wrap around)
–
Counter (MC) b7:b5
Base Address High 8 BA MSB Most Significant bits of
Base Address
Base Address Low 8 BA LSB Least Significant bits of
Base Address
Shall only exist on
“Long” Message Format
Length High 8 LEN MSB Most Significant bits of
LEN.
LEN (including its least
significant byte, if
exists) shall represent
the number of Data
bytes in the Payload
(i.e., Data-1 through
Data-N in Figure 123)
Length Low 8 LEN LSB Least Significant bits of
LEN
Shall only exist on
“Long” Message Format
CRC-8 is calculated on
HCRC 8 –
all Header fields
12.3.1.1.1 Header CRC (HCRC) Field

3230 The value of the ACMP-M0 Header CRC (HCRC) field shall be calculated over the ACMP-M0 Header Fields
3231 (i.e., Address Header, Message Descriptor, Base Address High/Low, and Length High/Low), using the CRC-8
3232 algorithm as described in Section 8.2.5.3.
3233 See also Section 12.3.2.1 regarding the ACMP-M0 Message receiver’s responsibilities in the event of an
3234 erroneous value in the HCRC field.

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12.3.1.2 ACMP-M0 Message Payload Part

3235 The Payload part of the ACMP-M0 Message (shown with orange background in Figure 122) includes the
3236 fields detailed in Table 153.
3237 Table 153 ACMP-M0 Message Payload Fields
Field Bits Values Remarks
Only exists in Read Message Payload Part.
Address Header 8 –
Format is as in ACMP-M0 Header Fields.
Only exists in Read Message Payload Part.
Message Descriptor 8 –
Format is as in ACMP-M0 Header Fields.
Data Bytes N*8 – N is the value of the ACMP-M0 Header Length field(s)
PCRC High 8 – Most Significant bits of PCRC
Least Significant bits of PCRC.
PCRC Low 8 –
Shall only exist on “Long” Message Format.
12.3.1.2.1 Payload CRC (PCRC)

3238 The value of the ACMP-M0 Payload CRC (PCRC) shall be calculated over the ACMP-M0 Payload Fields
3239 (i.e., the optional Address Header if it exists, the Message Descriptor if it exists, and all of the Data Bytes).
3240 The PCRC calculation shall use either the CRC-8 algorithm or the CRC-16 algorithm, depending upon the
3241 value of the Message Format sub-field in the message’s ACMP-M0 Header:
3242 • Short: If the Message Format sub-field is set to Short, then the PCRC value shall be calculated
3243 using the CRC-8 polynomial described in Section 8.2.5.3.
3244 • Long: If the Message Format sub-field is set to Long, then the PCRC value shall be calculated
3245 using the following CRC-16 polynomial:
3246 G(x) = x16 + x12 + x5 + 1
3247 See also Section 12.3.2.2 regarding the ACMP-M0 Message receiver’s responsibilities in the event of an
3248 erroneous value in the PCRC field.

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12.3.1.3 ACMP-M0 Message Mapping to I2C

3249 Figure 123 illustrates a simple mapping of ACMP-M0 Messages to I2C transactions. The purple background indicates ACMP-M0 Header fields, and the orange
3250 background indicates ACMP-M0 Payload fields.
3251 The I2C bus conditions that frame transmission of the ACMP-M0 fields are indicated with red and orange blocks:
3252 • S: Start Condition
3253 • rS: Repeated Start Condition
3254 • P: Stop Condition
3255 • A: Ack or NAK
S
Address
+W
8-bit
A
Message
Descriptor
8-bit
A
BA MSB
8-bit
A
BA LSB
8-bit
A
LEN MSB
8-bit
A
LEN LSB
8-bit
A
HCRC
8-bit
A
Data-1
8-bit
A ... Data-N
8-bit
A
PCRC
MSB
8-bit
A
PCRC
LSB
8-bit
A P
Write Message
Mapping to I2C
S
Address
+W
8-bit
A
Message
Descriptor
8-bit
A
BA MSB
8-bit
A
BA LSB
8-bit
A
LEN MSB
8-bit
A
LEN LSB
8-bit
A
HCRC
8-bit
A
r
S
Address
+R
8-bit
A
Message
Descriptor
8-bit
A
Data-1
8-bit
A ... Data-N
8-bit
A
PCRC
MSB
8-bit
A
PCRC
LSB
8-bit
A P
Read Message
Mapping to I2C
3256
Figure 123 ACMP-M0 Message Mapping to I2C

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12.3.2 ACMP-M0 Message Receiver Rules and Responsibilities

3257 ACMP-M0 provides means for Functional Safety provisioning by specifying the rules and sequence of
3258 Messages. The rules in this section apply to the consumer of ACMP-M0 messages, not to any intermediate
3259 entity such as an Adaptation Layer.
12.3.2.1 ACMP-M0 Header CRC (HCRC) Errors
3260 If the received Header CRC (HCRC field) has an incorrect value, then the ACMP-M0 Message shall be
3261 discarded and an ACMP Interrupt (ACMPI) should be issued. The receiver shall not perform any operations
3262 conveyed in such an ACMP-M0 message.
12.3.2.2 ACMP-M0 Payload CRC (PCRC) Errors
3263 If the received Payload CRC (PCRC field) has the wrong value, then the ACMP-M0 Message shall be
3264 discarded and an ACMP Interrupt (ACMPI) should be issued. The receiver shall not perform any write
3265 operations (e.g., Register Write) conveyed in a Short ACMP-M0 Message with an incorrect PCRC value.
12.3.2.3 Message Counter (MC)
3266 The value of the ACMP-M0 Header Message Counter (MC) field shall be considered to be valid only if the
3267 respective HCRC or PCRC values are correct.
3268 The MC sequence shall be maintained per Peripheral Address value within the Address Header (see Table
3269 152). The MC initial value shall be set by the Host, and the MC value shall be incremented with each:
3270 • ACMP-M0 Write Message
3271 • ACMP-M0 Read Message Header Part
3272 • ACMP-M0 Read Message Payload Part
3273 • ACMP-M0 Sequential Read Message
12.3.2.4 Keep-Alive
3274 The Host should issue an ACMP-M0 Message to read a valid ACMD register, at a certain period, according
3275 to its system-level functional safety goals.
12.3.2.5 Message Format Setting
3276 The ACMP-M0 Header Message Format sub-field shall be set to either:
3277 • Long for any Payload Part up to 4096 bytes
3278 • Short for any write to Safety Critical Registers up to 32 bytes
12.3.2.6 Virtual Base Address Maintenance
3279 The Virtual Base Address shall be incremented with each Data Byte. This way, registers can be sequentially
3280 accessed, providing that their BAs are sequential. A virtual BA shall be assigned the BA on reception of a
3281 valid Header Part of a Message (where ‘valid’ means that the Header CRC [HCRC] has the correct value).
12.3.2.7 Accessing Register Data
3282 Register data shall be accessed in its entirety.
3283 All unimplemented Registers with BA within the ACMD space shall be ignored on write, and shall return
3284 zero value on read (where ‘unimplemented’ means both not specified in this specification, and also not
3285 specified in the Vendor-Specific specification).

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12.3.3 ACMP Interrupts

3286 To meet strict Functional Safety goals, response time may be an issue. In such cases, the Controller/Target
3287 polling-based method might not provide a sufficient solution due to its inherent time delay.
3288 A more efficient and higher-performance solution is to implement an Interrupt indication that is generated by
3289 the Peripheral and is sent to the Host on events of Functional Safety issues.
3290 ACMP defines the ACMP-Interrupt (ACMPI) for this purpose.
12.3.3.1 ACMPI in I2C
3291 In I2C, the ACMPI is implemented by using a dedicated GPIO signal referred to as FSRI_IO (Functional
3292 Safety Reserved Interrupt). This signal is configured as an OUTPUT in the Peripheral, and as an INPUT in
3293 the Host.
3294 • Peripheral Output FSRI_O: When ACMPI is enabled at the Peripheral, the Peripheral shall toggle
3295 the FSRI_O signal with a toggle period of FSOKT (where FSOKT should be defined by the Native
3296 Protocol Adaptation Layer), as long as there are no Functional Safety issues. Upon the occurrence of
3297 any Functional Safety issue, the Peripheral shall stop toggling the FSRI_O signal, keeping its current
3298 state unchanged. The Peripheral shall state in its User Manual or Datasheet the exact list of
3299 conditions considered to be Functional Safety issues, and that will trigger the ACMPI (i.e., that will
3300 stop toggling the FSRI_O signal).
3301 • Host Input FSRI_I: The Host is expected to monitor its relevant FSRI_I. When an FSRI_I is
3302 toggling at FSOKT periods, it means there are no Functional Safety issues that the Peripheral can
3303 report. The Host is still free to have its own checking and polling to get to its own conclusions. Upon
3304 the discovery of “Bad” toggling of FSRI_I (e.g., absence of toggling), the Host may immediately
3305 start critical Functional Safety measures and query the Peripheral for more information on the source
3306 or type of the issue.
12.3.3.2 ACMPI in I3C
3307 In I3C, the ACMPI is implemented by using the In-Band Interrupt (IBI) feature.

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Annex A PMD Simplified Implementation Examples (Informative)

3308 This Annex provides informative examples for simplified block diagrams for the different PMDs described
3309 in Section 9.
A.1 Profile 1 G1–2 Source PMD

A.1.1 PMD without External Diplexer (Internal Replica)
P1 G1-2 – Source PMD
Downlink
Line Driver
8B/10B
Replica
PCS
Slicer
+
BPF
Clock
CR
3310
Figure 124 Profile 1 G1–2 Source with Internal Replica
A.1.2 PMD With External Diplexer
P1 G1-2 – Source PMD (Diplexer)
Downlink
Line Driver
8B/10B
PCS
Clock
CR
Slicer
POC
Filter
3311
Figure 125 Profile 1 G1–2 Source with External Diplexer

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A.2 Profile 1 G1–2 Sink PMD
P1 G1-2 – Sink PMD
Uplink
Line Driver
Uplink
LPF TX
8B/10B
PCS
Replica CR
Slicer
+ CTLE +
DFE
3312
Figure 126 Profile 1 G1–2 Sink PMD
A.3 G3–5 Source PMD
G3-5 – Source PMD
Downlink Line
Driver
PAM-X
Downlink
PCS
DAC
Replica
DAC
Uplink BPF
ADC
Hybrid
8B/10B
PCS
Clock Digital Clock

CDR
3313
Figure 127 G3–5 Source PMD

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A.4 G3–5 Sink PMD
Uplink
Line Driver
8B/10B
Uplink Line
PCS
TX LPF
Replica
Slicer
PAM-X
Downlink
PCS
+ FFE +
ADC BPF
Band Pass Filter

+
DFE Gain
+
Cancellers
3314
Figure 128 G3–5 Sink PMD

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Annex B 8B/10B Line Coding (Normative)

3315 All information communicated shall be 8b10b encoded [IBM01] according to the data and control symbol
3316 assignments prescribed in this section.
B.1 Data Symbols

3317 The coding of each byte consists of a 5b6b and a 3b4b sub block encoding. The bits in a data byte are indicated
3318 by the capital letters HGFEDCBA. The five data bits “EDCBA” shall encode into a 6-bit sub block “abcdei”,
3319 according to Table 154. The three data bits “HGF” shall encode into the 4-bit sub block “fghj”, according to
3320 Table 155.
3321 For D.x.7 there is a Primary (D.x.P7) and an Alternate (D.x.A7) coding as shown in the table. The Alternate
3322 encoding shall be selected if the Primary coding combined with the preceding 5b/6b code results in five or
3323 more consecutive zeroes or ones. This implies that D.x.A7 shall only be used for x=17, x=18, and x=20 when
3324 RD= 1, and for x=11, x=13, and x=14 when RD=+1. With x=23, x=27, x=29, and x=30, the Alternate code
3325 represents the control symbol K.x.7. Any other x.A7 code cannot be used, as it would result in chances for
3326 misaligned comma sequences.
3327 Several 5b and 3b sub blocks have two complimentary encoded representations with opposite disparity. The
3328 representation with the disparity sign opposite to the running disparity shall be applied for DC balance. For
3329 more information on disparity control, see Section B.3.1. For selection of the correct 3b4b sub block
3330 representation, the RD shall be evaluated including the preceding 5b6b sub block, which is part of the same
3331 symbol.

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Table 154 5b6b Sub-Block Data Encoding
Input Data RD = −1 RD = +1 Input Data RD = −1 RD = +1
Symbol EDCBA abcdei Symbol EDCBA abcdei
D.00 00000 100111 011000 D.16 10000 011011 100100
D.01 00001 011101 100010 D.17 10001 100011 –
D.02 00010 101101 010010 D.18 10010 010011 –
D.03 00011 110001 – D.19 10011 110010 –
D.04 00100 110101 001010 D.20 10100 001011 –
D.05 00101 101001 – D.21 10101 101010 –
D.06 00110 011001 – D.22 10110 011010 –
D.07 00111 111000 000111 D/K.23 10111 111010 000101
D.08 01000 111001 000110 D.24 11000 110011 001100
D.09 01001 100101 – D.25 11001 100110 –
D.10 01010 010101 – D.26 11010 010110 –
D.11 01011 110100 – D/K.27 11011 110110 001001
D.12 01100 001101 – D.28 11100 001110 –
D.13 01101 101100 – K.28 11100 001111 110000
D.14 01110 011100 – D/K.29 11101 101110 010001
D.15 01111 010111 101000 D/K.30 11110 011110 100001
– – – – D.31 11111 101011 010100

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Table 155 3b4b Sub-Block Data Encoding
Input RD = −1 RD = +1 Input RD = −1 RD = +1
Symbol HGF fghj Symbol HGF fghj
D.x.0 000 1011 0100 K.x.0 000 1011 0100
D.x.1 001 1001 – K.x.11 001 0110 1001
D.x.2 010 0101 – K.x.21 010 1010 0101
D.x.3 011 1100 0011 K.x.3 011 1100 0011
D.x.4 100 1101 0010 K.x.4 100 1101 0010
D.x.5 101 1010 – K.x.51 101 0101 1010
D.x.6 110 0110 – K.x.61 110 1001 0110
D.x.P7 111 1110 0001 – – – –
D.x.A7 111 0111 1000 K.x.71 111 0111 1000
3332 Note:
1. The alternate encoding for the K.x.y codes with disparity 0 allow for K.28.1, K.28.5, and K.28.7 to
be “comma” codes that contain a bit sequence that can't be found elsewhere in the data stream.

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B.2 Control Symbols

3333 Control symbols are special symbols that do not occur in the data symbol set, that can be used for embedded
3334 control features during the 8B/10B byte stream. Table 156 lists all control symbols of the 8b10b code set.
3335 Symbol K28.5 has comma properties, and shall be detected anywhere in the bitstream for symbol alignment.
3336 Details on usage of symbols can be found in Section 8.3.2.2.
Table 156 Control Symbols
Input RD = −1 RD = +1
Symbol HGF EDCBA abcdei fghj abcdei fghj
K.28.0 000 11100 001111 0100 110000 1011
K.28.11 001 11100 001111 1001 110000 0110
K.28.2 010 11100 001111 0101 110000 1010
K.28.3 011 11100 001111 0011 110000 1100
K.28.4 100 11100 001111 0010 110000 1101
K.28.51 101 11100 001111 1010 110000 0101
K.28.6 110 11100 001111 0110 110000 1001
K.28.72 111 11100 001111 1000 110000 0111
K.23.7 111 10111 111010 1000 000101 0111
K.27.7 111 11011 110110 1000 001001 0111
K.29.7 111 11101 101110 1000 010001 0111
K.30.7 111 11110 011110 1000 100001 0111
3337 Note:
1. Within the control symbols, K.28.1, K.28.5 are comma symbols. Comma symbols are used for
synchronization (finding the alignment of the 8b and 10b codes within a bit-stream). K28.7 also has
comma properties, but sets constraints on the symbols around it. Because K.28.7 is not used, the
unique comma sequences 0011111 or 1100000 cannot be found at any bit position within any
combination of normal codes.
2. See note 1 for Table 155.

Confidential
13-Dec-2022
B.3 Running Disparity

3338 The applied 8b10b transmission coding is a DC-balanced coding scheme. The Running Disparity (RD) is the
3339 disparity between the number of ones and zeroes in the transmitted symbols, where each one is counted as
3340 +1 and each zero is counted as −1.
B.3.1 RD Characteristics
3341 In the absence of transmission errors, the RD stays within −3 and +3, while it always equals −1 or +1 at any
3342 of the 6b and 4b sub block boundaries. All sub blocks have a disparity of 0, −2, or +2. Sub blocks with
3343 non-zero disparity have complementary representations with positive and negative disparity. In these cases,
3344 the representation with the disparity polarity opposite to the RD shall be used, such that RD changes from −1
3345 to +1 or vice versa at sub block boundaries, and accumulation of disparity cannot occur. The starting value
3346 of the RD may be +1 or −1 for any symbol.
3347
Figure 129 Running Disparity (RD) State Diagram
B.4 Bit Order and Binary Value

3348 The notation for 8b10b symbols is “abcdeifghj”, where the “a” bit is transmitted first. When 8b10b encoding
3349 is bypassed, the “j” bit is transmitted first.
3350 The notation of binary data values is MSB (Most Significant Bit) to LSB (Least Significant Bit) when reading
3351 from left to right. Data bytes are therefore indicated by “HGFEDCBA” where “H” is the MSB and “A” is
3352 the LSB.

Confidential
13-Dec-2022

Confidential
13-Dec-2022
Participants
The list below includes those persons who participated in the Working Group that developed this Specification and who
consented to appear on this list.
Nadav Banet, Valens Semiconductor Ariel Lasry, Qualcomm Incorporated
Amit Barzilai, InvenSense, Inc. Eyran Lida, Valens Semiconductor
Craig Bezek, Teledyne LeCroy Sirius Lin, MediaTek Inc.
Alexander Brill, Intel Corporation Raj Kumar Nagpal, Synopsys, Inc.
Ned Brush, Protocol Insight, LLC Makoto Nariya, Sony Group Corporation
Tony Carosa, Protocol Insight, LLC Ramesh P E, Tektronix, Inc.
Edo Cohen, Valens Semiconductor Yash Pathak, BitifEye Digital Test Solutions GmbH
Yair Darshan, Valens Semiconductor Bill Simms, NVIDIA
Arno Distel, Valens Semiconductor Joseph Stenger, Molex CVS Dabendorf GmbH
Jatin Domadiya, Tektronix, Inc. Giuseppe Tofanicchio, STMicroelectronics
Katsushi Hanaoka, Sony Group Corporation Shinichi Watanabe, Sony Group Corporation
Eric Hong, Mixel, Inc. Stephen Wong, Intel Corporation
Kevin Kershner, Keysight Technologies Inc. Charles Wu, OmniVision Technologies, Inc.
Mohit Kumar, Intel Corporation Kentaro Yasunaka, Sony Group Corporation
Past Contributors to v1.1:

Afshin Attar Zadeh, BitifEye Digital Test Solutions GmbH Eyran Lida, Valens Semiconductor
Radha Krishna Atukula, NVIDIA Nuno Martins, ON Semiconductor
Nadav Banet, Valens Semiconductor Alexander Mokhoria, Robert Bosch GmbH
Amit Barzilai, InvenSense, Inc. Raj Kumar Nagpal, Synopsys, Inc.
Tony Carosa, Protocol Insight, LLC Josh Pan, MediaTek Inc.
Josue Castillo, Luxshare-ICT, Inc. Ryan Petrarca, InvenSense, Inc.
Géraud Cheenne, STMicroelectronics Parthasarathy Raju, Tektronix, Inc.
Zuhaib Chohan, BitifEye Digital Test Solutions GmbH P E Ramesh, Tektronix, Inc.
Edo Cohen, Valens Semiconductor Fei Ren, Synopsys, Inc.
Jatin Domadiya, Tektronix, Inc. Matthew Ronning, Sony Corporation
Curtis Donahue, University of New Hampshire Mohamed Said, Mixel, Inc.
InterOperability Lab (UNH-IOL) Hugo Santos, Synopsys, Inc.
Mohamed Elgendy, Mixel, Inc. Bill Simms, NVIDIA
Massad Eyal, Valens Semiconductor Ariel Sobelman, Valens Semiconductor
Frank Fan, Synopsys, Inc. Giuseppe Tofanicchio, STMicroelectronics
Marty Gubow, Keysight Technologies Inc. Ayshwarya Venkataramanan, Robert Bosch GmbH
Takayuki Hirama, Sony Corporation Rick Wietfeldt, Qualcomm Incorporated
Henrik Icking, Apple Inc. George Wiley, Qualcomm Incorporated
Hasushi Kentaro, Sony Corporation Stephen Wong, Intel Corporation
Kevin Kershner, Keysight Technologies Inc. Charles Wu, OmniVision Technologies, Inc.
Ariel Lasry, Qualcomm Incorporated Kentaro Yasunaka, Sony Corporation
Lv Liang, Synopsys, Inc. Michel Yeh, MediaTek Inc.
Past Contributors to v1.0:

Afshin Attar Zadeh, BitifEye Digital Test Solutions GmbH Géraud Cheenne, STMicroelectronics
Radha Krishna Atukula, NVIDIA Zuhaib Chohan, BitifEye Digital Test Solutions GmbH
Nadav Banet, Valens Semiconductor Edo Cohen, Valens Semiconductor
Josue Castillo, Luxshare-ICT, Inc. Tomer Cohen, Samsung Electronics, Co.

Confidential
13-Dec-2022
Massad Eyal, Valens Semiconductor Matthew Ronning, Sony Corporation

Frank Fan, Synopsys, Inc. Mohamed Said, Mixel, Inc.
Marty Gubow, Keysight Technologies Inc. Victor Sanchez-Rico, BitifEye Digital Test Solutions
Takayuki Hirama, Sony Corporation GmbH
Henrik Icking, Apple Inc. Hugo Santos, Synopsys, Inc.
Michael Kaindl, BMW AG Fenali Shah, Cadence Design Systems, Inc.
Hasushi Kentaro, Sony Corporation Yon Jun Shin, Samsung Electronics, Co.
Tom Kopet, ON Semiconductor Bill Simms, NVIDIA
Saurabh Kumar, Mentor Graphics Ariel Sobelman, Valens Semiconductor
Ariel Lasry, Toshiba Electronic Devices & Storage Giuseppe Tofanicchio, STMicroelectronics
Corporation Ayshwarya Venkataramanan, Robert Bosch GmbH
Eyran Lida, Valens Semiconductor Rick Wietfeldt, Qualcomm Incorporated
Nuno Martins, ON Semiconductor Craig Wiley, Parade Technologies Ltd.
Alexander Mokhoria, Robert Bosch GmbH George Wiley, Qualcomm Incorporated
Raj Kumar Nagpal, Synopsys, Inc. Stephen Wong, Intel Corporation
Ryan Petrarca, InvenSense, Inc. Kentaro Yasunaka, Sony Corporation
Parthasarathy Raju, Tektronix, Inc. Michel Yeh, MediaTek Inc.
Fei Ren, Synopsys, Inc.

Confidential

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Specification for

Version 1.1.1 – 13 December 2022

MIPI Board Adopted 24 May 2023

defined in the MIPI Membership Agreement and MIPI Bylaws.

Copyright © 2020–2023 MIPI Alliance, Inc.

2 Copyright © 2020–2023 MIPI Alliance, Inc.

MIPI Board Adopted 24 May 2023

Copyright © 2020–2023 MIPI Alliance, Inc.

MIPI Alliance, Inc.

ii Copyright © 2020–2023 MIPI Alliance, Inc.

Copyright © 2020–2023 MIPI Alliance, Inc. iii

6.6.2.4 Coupling Attenuation......................................................................................... 29

iv Copyright © 2020–2023 MIPI Alliance, Inc.

8.2.3.1 Retransmission Request Triggering by the Receiver ......................................... 64

Copyright © 2020–2023 MIPI Alliance, Inc. v

9.1.1.1 LFSR Usage Example ..................................................................................... 123

vi Copyright © 2020–2023 MIPI Alliance, Inc.

10.3.3.4 Stop Transition................................................................................................. 150

Copyright © 2020–2023 MIPI Alliance, Inc. vii

11.5.1.2 Packet Forwarding Stage ................................................................................. 185

viii Copyright © 2020–2023 MIPI Alliance, Inc.

Annex B 8B/10B Line Coding (Normative) .................................................................... 233

Copyright © 2020–2023 MIPI Alliance, Inc. ix

x Copyright © 2020–2023 MIPI Alliance, Inc.

Figure 32 A-PHY P2 G3-G5 Single Lane Architecture.................................................................. 53

Copyright © 2020–2023 MIPI Alliance, Inc. xi

Figure 65 In_Idle Startup Control Sequence ................................................................................ 105

xii Copyright © 2020–2023 MIPI Alliance, Inc.

Figure 98 General Waveform of Main Signals ............................................................................. 157

Copyright © 2020–2023 MIPI Alliance, Inc. xiii

xiv Copyright © 2020–2023 MIPI Alliance, Inc.

Table 32 Actual Byte Period Consumption Per Gear ..................................................................... 73

Copyright © 2020–2023 MIPI Alliance, Inc. xv

Table 65 NRZ PMD Upper PSD Limit ........................................................................................ 128

xvi Copyright © 2020–2023 MIPI Alliance, Inc.

Table 98 Register Base Address (BA) Alignment ........................................................................ 201

Copyright © 2020–2023 MIPI Alliance, Inc. xvii

Table 131 Register PORT_CONFIG ............................................................................................ 214

xviii Copyright © 2020–2023 MIPI Alliance, Inc.

06-Aug-2020 v1.0 Initial Board adopted release.

08-Dec-2021 v1.1 Board adopted release.

24-May-2023 v1.1.1 Board adopted release.

Copyright © 2020–2023 MIPI Alliance, Inc. xix

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xx Copyright © 2020–2023 MIPI Alliance, Inc.

Copyright © 2020–2023 MIPI Alliance, Inc. 1

2 Copyright © 2020–2023 MIPI Alliance, Inc.

2.1 Use of Special Terms

Copyright © 2020–2023 MIPI Alliance, Inc. 3

4 Copyright © 2020–2023 MIPI Alliance, Inc.

131 RX Receive, Receiver

Copyright © 2020–2023 MIPI Alliance, Inc. 5

177 Mbps Megabit Per Second

6 Copyright © 2020–2023 MIPI Alliance, Inc.

3.1 Normative References

3.2 Informative References

Copyright © 2020–2023 MIPI Alliance, Inc. 7