Lecture 47
Wrapper Usage
Wrapped Embedded Cores
Wrapper Operation Modes (I)
Normal Mode Serial Bypass Mode
Wrapper Operation Modes (II)
Serial Internal Test Mode Serial External Test Mode
Wrapper Operation Modes (III)
Parallel Internal Test Mode Parallel External
Test Wrapper Optimization
Priority 1: Balanced Wrapper Scan Chains
Core Core
4 FF
4 FF
8 FF 8 FF
Wrapper Wrapper
Unbalanced Balanced
Minimize length of longest wrapper scan in/out chain
Reducing TAM Width
Priority 2: Minimize wrapper scan chains created
Scan chain – 32 FF
I I 8 FF O
4 Wrapper scan chains
I 8 FF O
I 8 FF
2 Wrapper scan chains
Scan chain – 32 FF
I I I I 8 FF 8 FF 8 FF O O
Two-Priority Wrapper Design Algorithm
1. Minimize length of
longest wrapper scan
in/out chain
2. Minimize number of
Longest wrapper scan chain
wrapper scan chains
Design_wrapper algorithm uses
the BFD heuristic for Bin Design
TAM width
Lecture 48
Test Access Mechanisms
Types of TAMs Multi-
C1 C2 C3
• Multiplexed access plexed
[Immaneni, ITC’90]
• Reuse system bus
[Harrod, ITC’99]
Daisy-
• Transparent paths C1 C2 C3
chain
[Ghosh, DAC’98]
• Isolation rings
[Whetsel, ITC’97]
• Test Bus [Varma, Distri-
C1 C2 C3
ITC’98] bution
• Test Rail
[Marinissen, ITC’98]
Test Bus Architecture
Architecture Schedule: Serial
TAM width
A B
A B
C D E
C D E
F
F
SOC test time
Combination of multiplexing and distribution
Supports only serial schedule
Core-external testing is cumbersome or impossible
TestRail Architecture [Goel ITC’02]
• Combination of Daisy chain and Distribution architectures
• Cores connected to a TestRail can be tested simultaneously as well
as sequentially
• Multiple wrappers can be activated simultaneously for Extest
• TestRails can be either fixed-width or flexible-width
Fixed-width TestRails Flexible-width TestRails
C1 C2 C3
C1 C2 C3
w1
W
C1 C2
C1 C2
w2
Step-by-Step Approach to Wrapper/TAM Co-
optimization
1. PW: Wrapper design
2. PAW: Core assignment + PW
3. PPAW: TAM width partitioning + PAW
4. PNPAW: Number of TAMs + PPAW
W3
W2 TAMs
W1
IP IP IP
Wrapper Wrapper Wrapper
Mathematical Programming Model for TAM
Partitioning
• Variable xij = 1, if core i assigned to TAM j
• Testing time of core i on TAM width wj = Ti(wj)
• Testing time on TAM j = i Ti(wj) xij
• Objective: Minimize T = maxj i Ti(wj) xij
• Constraints
1. i xij = 1, every core connected to exactly one
TAM
2. i wj = W, total TAM width is W
3. wj wmax, maximum width of any TAM is
wmax
TAM Design and Test Scheduling
• Given the test set parameters for the
cores and the total TAM width W
• Assign a part of W to each core, design
a wrapper for each core, and determine
the test schedule,
• Such that
– W is not exceeded at any time and
– Testing time is minimized
Lecture 49
Architectures Determine Schedules
Rectangle Model for Test Buses
Three test buses
Each core on same bus gets equal, fixed TAM width
Bus 1 Core 1 Core 3 Core 9 Core 8
Bus 2 Core 2 Core 4
Bus 3 Core 5 Core 6 Core 7
Test Scheduling
• Test scheduling determines sequence of core tests on
the TAMs
• Avoid test resource conflicts
• Minimize testing time
• Ineffective scheduling can increase tester data volume:
Idle bits
Idle bits
Core 1 Core 5
Schedule
Core 2 Core 4
Time
Rectangle Representation
Set Ri of rectangles
• Testing time Ti(wj) for for Core i
Core i and TAM
Ti(wj)
width j
wj
• Rectangle Rij
• Set of rectangles Ri
Collection R
for each core
• Collection of
rectangles R for SOC
Rectangle Packing Problem
• Given collection R of rectangle sets for the SOC cores,
• Select one rectangle Rij for each Core i
• Pack the selected rectangles into a bin of fixed height,
• Such that bin width is minimized
Width
Collection R
Core 1
Core 3
Core 2
Packed Bin = TAM Design + Test Schedule
Rectangle area = tester Empty space = wasted
memory for core test tester memory
Core 8
Core 5
Core 2
Core 4
Core 7
Core 1
Core 3 Core 6
Bin width = SOC testing time
Preferred TAM Widths
• Only Pareto-optimal
TAM widths are
Preferred considered
TAM width
• Procedure: Tests are
Testing time
scheduled at current
Pareto-optimal
width
time in decreasing
order of preferred TAM
width until no TAM
width remains
TAM width
Non-Preferred Rectangles: Fill Idle Time
Next_time Core 3
Core 3
Core 3-P
Core 2
Core 2-P
Core 2-P
Core 1-P
Core 1
Core 1-P
Current_time
Increasing Current TAM Widths
W_available
• Modify current
rectangle that will
Core 3
Core 3-P benefit the most
Core 4-P
Core 2-P
from an increase
in TAM width
If idle time is inevitable,
Core 1-P advance Current_time and
repeat procedure from
the start
Current_time
Current-Generation ATEs
• Port scalability features
• Digital speeds of up to 2.5 Gbps
• Application flexibility
Every port of a tester, consisting of multiple channels,
can configured at a desired data rate
Virtual TAMs
• Embedded core test frequency is limited by scan
frequency
– Scan frequencies are low to meet power,
routing, and clock skew constraints
• Virtual TAMs allow use of high frequency ATE
pins
• How can we match fast ATE data rates to slow
scan frequencies?
Lecture 50
Bandwidth Matching
High frequency
ATE lines
ATE
Low frequency
ATE lines
ATE pins : WATE= 4
ATE frequency factor : n = 4
High frequency pins U = 2
W ATE f ATE WTAM f TAM
U f ATE (WTAM U) fTAM U n fTAM (WATE U) fTAM
Bandwidth Matching
10 low frequency
Bandwidth lines to the cores
ATE
Matching
ATE pins : WATE= 4 Virtual TAM
ATE frequency factor : n = 4
High frequency pins U = 2
W ( n 1) U W ATE
Implementation of Bandwidth Matching
Low-speed TAM
SOC
U U
Serial-In/ Parallel-In/
Parallel- U U
Embedded Serial-
out U U
ATE core out
Registers U U Registers
U
WATE -U
High-speed TAM
(n = 4)
Low-speed TAM
Selection of U and n
• Testing of SOC is often dominated by the
testing time of bottleneck cores
• Testing time of SOCs containing
bottleneck cores does not decrease for
TAM widths greater than W*
• The lower bound on test time in such
SOCs is T* corresponding to TAM width
W*
SOCs with Bottleneck Cores
SOC W* (bits) cycles)
T* (clock
u226 48 5333
d281 48 3926
g1023 40 14794
p34392 36 544579
t512505 36 5228420
h953 16 119357
f2126 16 335334
q12710 16 2222349
Relationship of U, n and W*
• U and n should be chosen such that total
virtual TAM width W does not exceed W*
*
W W
W nU (W ATE U )
*
U ( n 1) W W ATE
Variation of U with n
U vs n for ITC’02 Benchmarks
SOC p34392
SOC h953
W*=36 W*=16
SOC d281 SOC g1023
W*=48 W*=40
Multiple-Speed TAM Architectures
• Exploit port-scalability of ATEs
• Facilitate efficient use of high data-rate tester channels
• Unlike virtual TAMs, avoid on-chip hardware
overhead
• Reduce testing time of bottleneck cores
I/O pads
fast CPU Self-test
control
core
User-defined logic
Memory DSP
I/O pads
I/O pads
array core
Legacy Interface
core control
IP hard Embedded
core DRAM
ATE SOC
slow 1149.1 TAP controller
Problem Formulation
• Dual-speed optimization problem
Given:
f.r
V
Embedded
ATE r cores
SOC
W-V
Determine the wrapper design, TAM width and test data rate for each
core, and the SOC test schedule such that:
• the total number of TAM wires utilized at any moment does not exceed W
• the number of TAM wires driven at the high data rate does not exceed V
• the SOC testing time is minimized
Selection of Data Rate for a Core
fast
Testing time
Testing time
r f.r
TAM width TAM width
Core 5 in SOC p93791
f =2 V=10 T = 14026.9μs
f =1 W-V=23 T = 11398.9μs
Matching Core Scan Frequencies to ATE Data
Rates
Core A Core B Core C Core D
f = 40MHz f = 80MHz
T = 456 μs
TAM width
Baseline w1= 8
Case 1 A B C
f1= 40MHz
w2= 2, f2= 40MHz
D
Test time
Matching Core Scan Frequencies to ATE Data
Rates
Core A Core B Core C Core D
f = 40MHz f = 80MHz
TAM width
w1= 8
C D
Baseline f1= 80MHz
Case 2
T = 275 μs A B w1= 2, f2= 40MHz
Test time
Matching Core Scan Frequencies to ATE
Data Rates
Core A Core B Core C Core D
f = 40MHz f = 80MHz
w1= 5
C
TAM width
f1= 80MHz
f2= 40MHz
A B D
w1= 5
T = 246 μs Test time
Problem Statement
Given
• Test data parameters for N embedded cores
• Maximum scan frequency fi* for each core i
• SOC-level TAM width W
Determine
• The number of TAM partitions B
• Width wj and scan frequency fj of each TAM partition j
• Assignment of cores to TAM partitions
Such that
• TAM frequency does not exceed the maximum scan frequency of
any core assigned to that TAM partition
• The overall test time is minimized
• The sum of the widths of all the TAM partitions does not exceed W
Solution Techniques
• Lower bound on test time based on geometric
arguments (rectangle packing)
• Integer linear programming
– Exact optimization method, limited to small
problem instances
• Fast heuristic method
– Scalable, close to optimal results
Lecture 51
Conclusions
• Test reuse, test time minimization, and test compression
are necessary to reduce test cost for SOCs
• Wrapper/TAM optimization and test scheduling can
reduce test time for core-based SOCs
• Virtual TAMs offer several advantages for SOC testing
– On-chip TAM wires are not limited by the number of
available pins on the SOC
– Better utilization of high-speed ATE channels reduces
testing times
• TAM architectures can match port-scalable ATE channels
to different scan frequencies of embedded cores
Introduction to Network-On-Chip Testing
• For future SoCs with large number of cores and increased
interconnect delay, traditional point-to-point or bus-based
communication architecture becomes new bottleneck.
• Traditional communication architectures cannot meet system
requirements of bandwidth, latency, and power consumption.
• Integrated switching network has been proposed as an
alternative approach to interconnect cores in SoC.
• Such networks rely on a scalable and reusable
communication platform, called network-on-chip (NoC)
system, to meet two major requirements: reusability and
scalable bandwidth.
Conceptual Architecture of a NoC System
• The figure shown below represents a 2-D mesh NoC.
Core 1 Core 2 Core 3
Router Router Router
Core 4 Core 5 Core 6
Router Router Router
N bits
• Cores are connected to NoC by routers or switches.
• Data are organized by packets and transported through
interconnection links.
• Various network topologies and routing algorithms can be
used to meet requirements of performance, hardware
overhead, power consumption.
Special Features of NoC Testing
• The greatest difference between NoC testing and SoC testing
is on test access mechanism design.
• On-chip-network of a NoC can be reused as a TAM for test
packet delivery. Theoretically, no TAM interconnects are
required to be invested.
• Test time can be reduced by network reuse even under
power constraints, with minimized pin count and area
overhead.
• Generally, more cores can be tested in parallel than TAM-
based SoC testing, due to large NoC channel bandwidth.
