Lunch & Learn

Specifying Efficient Constraints

in
Design Compiler and PrimeTime

Specifying Efficient Constraints

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Synopsys .. 1
Agenda

„ Introduction
„ Static Timing Analysis Basis

„ Timing Constraints

„ Environmental Constraints

„ Timing exceptions

„ Report and Analysis

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What are constraints used for ?

„ Driving the synthesis process

Design Compiler

„ Performing Static Timing Analysis

Design Compiler & PrimeTime

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Synthesis is Constraint-Driven

Large

•
Area
•
•
Small • • •

Fast Speed Slow

You set the goals (through constraints)

Design Compiler optimizes the design to meet your goals

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Static Timing Analysis

A D Q OUTZ

CLK

„ Static Timing Analysis (STA) is a method for determining if a

circuit meets timing constraints

„ STA needs to know your specifications or constraints

„ Does not simulate clock cycles and does not use functional
vectors

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Agenda

„ Introduction

„ Static Timing Analysis Basis

„ Timing Constraints

„ Environmental Constraints

„ Timing exceptions

„ Report and Analysis

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Synopsys Definition: Design Object
Design Cell Net

TOP
U1 U4
Port A U2
A AIN BUS0 INV0 OUT[1:0]
B Q0 INV D0 Q[1:0]
B BIN
C C U3
CIN BUS1
INV
INV1 D1 Pin
D D Q1
DIN
Clock CLK
ENCODER
CLK REGFILE
CLK

Reference and Design

Designs: {TOP, ENCODER, REGFILE}

References: {ENCODER, REGFILE , INV}
Cells: {U1, U2, U3, U4}
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Design Objects: VHDL Perspective
Design
entity TOP is Clock
port (A, B, C, D, CLK: in STD_LOGIC;
Port OUTI: out STD_LOGIC_VECTOR (1 downto 0));
end TOP;
architecture STRUCTURAL of TOP is
...
signal INV1, INV0, BUS1, BUS0: STD_LOGIC;
Pin
begin
U1: ENCODER port map (AIN=>A, . . . Q1=>BUS1); Net
U2: INV port map (A => BUS0, Z => INV0);
Cell U3: INV port map (A => BUS1, Z=> INV1);
U4: REGFILE port map (D0=>INV0, D1=>INV1, . .
CLK=>CLK);
end STRUCTURAL;
Reference

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Design Objects: Verilog Perspective
Design
module TOP (A,B,C,D,CLK,OUT1);
input A, B, C, D, CLK; Clock
output [1:0] OUT1;

Port
wire INV1,INV0,bus1,bus0; Net

ENCODER U1 (.AIN (A), . . . .Q1 (bus1));

Reference
INV U2 (.A (BUS0), .Z( INV0)),
U3 (.A( BUS1), .Z( INV1)); Pin
Cell

REGFILE U4 (.D0 (INV0), .D1 (INV1), .CLK (CLK) );

endmodule

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Visibility of Constraints

„ Constraints are only visible at the current level

„ Synthesis Process
z Only top level constraints (at the 'current_design' level) are
visible during compile
z Set block level constraints using the complete instance path
name or using the 'current_instance' command

„ Static Timing Analysis

z Only top level constraints are visible during STA
z Changing of current_design in PrimeTime is not recommended.
For instance it removes all back-annotated SPEF data.

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Synopsys Definition: Static Timing Analysis

Path X STA is a method for

A D Q OUTZ
determining if a circuit
Path Y
meets timing constraints
CLK Z without having to simulate
th
Pa clock cycles

STA involves three main steps:

5 Design is broken down into sets of timing paths

o Delay of each path is calculated

p All path delays are checked to see if timing constraints

have been met
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Synopsys Definition : Timing path

Path X
A D Q OUTZ
Path Y
CLK Z
th
Pa

„ Each path has a start-point and an end-point

Start-points:
Primary input ports
Clock pins of sequential devices

End-points:
Primary Output ports
Data input pins of sequential devices
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Synopsys Definition : Timing Arc
„ Pin-to-Pin delay is called a delay timing arc

„2 types of delay arcs

z cell delay arc from input pin to output

z net delay arc from cell output pin to next cell input pin

„ How is path delay computed?

z Add up all cell & net delays arcs from a valid startpoint to the
next valid endpoint in the fanout (rising edge on input of path)
z Repeat for falling edge on path input

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Synopsys Definition : Path Groups
MY_DESIGN

CLK1

A path1 D Q path2 D Q path3 Z path1 DEFAULT

FF2 FF3
CLK1 QB QB path3
CLK2 CLK2 path4

path4 path2

Timing Paths Path Groups

„ Paths are grouped according to the clocks controlling their

endpoints

„ Each clock will be associated with a set of paths called a path group

„ The default path group comprises all paths not associated with a
clock
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Timing Path Exercise
How many timing paths do you see?
How many path groups are there?

set_output_delay 4.0 \
-clock CLK_1 OUTY

OUTY

CLK_1
CLK_2

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Solution: Timing Path Exercise
How many timing paths do you see?
How many path groups are there?

set_output_delay 4.0 \
-clock CLK_1 OUTY

OUTY

CLK_1 Clock
CLK_2 Clock Group 1 Clock Group 2 Group 1
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Setup and Hold

din

clk

setup
Setup: Minimum time that a data input hold
pin must be stable before the clock Hold: Minimum time that a
transition data input pin must be stable
after the clock transition

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Recovery and Removal

Recovery:
clearbar
Recovery
Minimum time that an
asynchronous control input pin
clock must be stable before the clock
active-edge transition

Removal:
clearbar
Removal
Minimum time that an
asynchronous control input pin
must be stable after the clock
clock active-edge transition

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Minimum Clock Pulse Width

„ This example shows the minimum active pulse

width for a positive edge triggered flip-flop (FF)

minimum minimum
active inactive
pulse width pulse width

„ Different technologies may have an inactive

pulse width minimum

„ This check determines how errors are reported

and function affected due to clock-line spikes
(and glitches)
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Clock Skew
FF1

CLK CP

TU FF2
TP

CP

TP = clock propagation delay from CLK to FF2/CP TU = clock skew between FF1 and FF2

„ Clock skew is the difference in arrival time of active clock

edges at one or more register clock pins
z It is a function of delay through the clock tree, logical and
physical balancing of the clock tree branches and leaf nodes

„ Differences in skew amongst pins can degrade setup and

hold time margins, in addition to clock pulse widths

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Maximum Clock Skew

„ Is a result of clock tree construction

„ Must be defined to the analyzer (pre-layout)

„ Will be automatically computed (post-layout)

ff1 ff2
clk clk

CLK

ff1.clk
max clock skew
ff2.clk

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Clock Gating Check

ff
E clk

CLK
0 3 6

CLK
glitch due to late
E arrival time of E

ff.clk

Required E

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Typical Timing Analysis Flow
● Set search path, link path
Set up design environment ● Read designs, libraries

● Link

● Set operating conditions, wire load,

port load/drive/transition

● Clock period / waveform /

Specify timing assertions uncertainty / latency
● Input / output delays

● Multicycle paths
Specify timing exceptions ● False paths

● Min/max delays,

segmentation, disabled arcs

● Check timing
Perform analysis; create reports ● Constraint reports

● Timing reports

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Agenda

„ Introduction

„ Static Timing Analysis Basis

„ Timing Constraints
„ Environmental Constraints

„ Timing exceptions

„ Report example

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Timing Goals: Synchronous Designs
„ Synchronous Designs:
z Data arrives from a clocked device

z Data goes to a clocked device

TO_BE_ANALYZED

D Q M N D Q X D Q S T D Q
FF1 FF2 FF3 FF4
QB QB QB QB

Clk

„ Objective is to define the timing constraints for all

paths within a design:
Š all input logic paths
Š the internal (register to register) paths, and
Š all output paths Specifying Efficient Constraints
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Defining a Clock
Path X constrained
by create_clock
TO_BE_ANALYZED

D Q M N D Q X D Q S T D Q
FF1 FF2 FF3 FF4
QB QB

Clk

1 Clock Cycle

dc_shell-t> create_clock -period 10 [get_ports Clk]

dc_shell-t> set_dont_touch_network [get_clocks Clk]

„set_dont_touch_network tells DC not to 'buffer up' the

clock net, even if there are too many Flip-Flops loading it

pt_shell> create_clock -period 10 [get_ports Clk]

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Clock Commands Pre-layout
create_clock create_generated_clock
set_dont_touch_network (DC only) Need to specify its own insertion
delay, CTS latency, skew and clock
Defines the default waveform. transition (pre-layout).
Any latency should be model
with the proper command and
not by shifting the edge of the
waveform. D Q
FF1
/Q

D Q
FF2

set_clock_latency -source set_clock_transition

-early / -late set_clock_latency
Used to model insertion delay. + Only works pre-layout.

Not recommended to use -early / -late to set_clock_uncertainty -hold / -setup Overrides the default '0'
model off-chip jitter apart for advanced transition.
Used if the clock buffers are not present to estimate
tester skew analysis
the delay through the buffers (pre-layout)
Clock uncertainty can model both the Clock Tree Skew
and any off-chip jitter.
Setting latency on a clock object or its physical object
has not the same impact on external delay controlled
by this same clock. Specifying Efficient Constraints
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Clock Commands Post-layout

create_clock create_generated_clock
set_dont_touch_network (DC only)
set_clock_uncertainty -hold / -setup

Clock uncertainty to model

off-chip jitter.
D Q
Typically when the clock FF1
attribute is applied on one /Q

port/pin only the hold

off-chip jitter is “0”.
D Q
FF2

set_clock_latency -source set_propagated_clock

-early / -late
Used to model insertion delay. Used if the clock buffers are present.

Not recommended to use -early / -late Calculates the Clock Tree latency and uncertainty.
to model off-chip jitter apart for
advanced tester skew analysis Any related generated clock will be automatically
propagated.

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Constraining the Input Paths
External Logic TO_BE_ANALYZED
Launch edge M A N
triggers D Q D Q
data

Clk Next edge

Clk
captures data

TClk-q TM TN TSETUP

Clk DC
You specify calculates
how much time how much
Valid new
is used by A data time
external logic... is left for
(TClk-q + TM) (TN + TSETUP) internal logic
(Input Delay)

dc_shell-t> set_input_delay -max 4 -clock Clk [get_ports A]

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Constraining Output Paths of a Design
TO_BE_ANALYZED External Logic External
U3
Launches U3 B
Flip-Flop
S T
Data D Q D Q captures
data
Clk

TClk-q Ts TT TSETUP
Launch Edge Capture Edge
DC calculates
You specify Clk
how much
how much time Valid new data time
B
is needed by is left for
external logic... internal logic
TClk-q + TS TT + TSETUP
(Output Delay)

dc_shell-t> set_output_delay -max 5.4 -clock Clk [get_ports B]

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Complex Constraints - Combo Logic

TO_BE_ANALYZED
A B
Combo Logic

Clk_virtual Clk_virtual

„ The specification for this path is

“the max delay for the combo logic is 12 ns”
„ Use a virtual clock!

dc_shell-t> create_clock -period 20 -name Clk_virtual

dc_shell-t> set_input_delay 0 -clock Clk_virtual [get_ports A]
dc_shell-t> set_output_delay 8 -clock Clk_virtual [get_ports B]

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Complex Constraints - Multiple External Delays

T1 D Q
TO_BE_ANALYZED
U3 S B Clk_vrt
D Q

T2 D Q

Clk1

External Logic

dc_shell-t> create_clock -period 10 [get_ports clk1]

dc_shell-t> create_clock -period 8 -name Clk_vrt
dc_shell-t> set_output_delay 3 -clock Clk1 [get_ports B]
dc_shell-t> set_output_delay 2 -clock Clk_vrt[get_port B] -add_delay

„ Same concept for input external delays

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Complex Constraints - Multiplexed Clocks
CLOCK_GEN
TEST_en

TEST_Clk a
y Int_Clk
Clk
b
U1

dc_shell-t> create_clock -period 10 [get_ports Clk]

dc_shell-t> create_clock -period 100 [get_ports TEST_Clk]

„ The tool does not know which clock to propagate at

the pin CLOCK_GEN/U1/Y
„ Need to help the tool by either manually disabling
the relevant timing arc or propagating a “timing”
constant.
dc_shell-t> set_disable_timing CLK_GEN/U1 -from a -to y

dc_shell-t> set_case_analysis 0 [get_ports TEST_en]

(in DC since 2000.11 - any version of PT)
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Complex Constraints - Derived Clocks
„ Define clock dividers/multiplier, waveform shaping,…
„ New clock is defined in relation to a source clock
„ Post-Layout, the latency from the source clock to the
derived clock will be automatically calculated

dc_shell-t> create_clock -period 10 [get_ports CLK]

dc_shell-t> create_generated_clock -name DIV_CLOCK \
-source U4/CP -divide_by 2 [get_pins U4/Q]

New clock created with

create_generated_clock
Divide-by-two
clock generator U6
D
Source clock pin
U4 CP
D Q U5
Original clock
QN
CLK U1 U2 U3 CP
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Do / Don’t Do
„ Do not set an external input delay on the clock port !

dc_shell-t> create_clock -period 10 [get_ports CLK]

dc_shell-t> set_input_delay 3 -clock CLK [all_inputs]

dc_shell-t> create_clock -period 10 [get_ports CLK]

dc_shell-t> set_input_delay 3 -clock CLK \
[remove_from _collection [all_inputs] [get_ports CLK]]

„ Do not forget the clock controlling a port external

delay! If needed create a virtual clock.

dc_shell-t> set_input_delay 3 [get_ports A]

dc_shell-t> create_clock -period 10 -name VIRT_CLK

dc_shell-t> set_input_delay 3 -clock VIRT_CLK [get_ports A]
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Do / Don’t Do
„ Do not use max/min delays to constraint combo logic!

dc_shell-t> set_max_delay 12 -from [get_ports A] \

-to [get_ports B]

dc_shell-t> create_clock -period 12 -name CLK_VIRT

dc_shell-t> set_input_delay 0 -clock CLK_VIRT [get_ports A]
dc_shell-t> set_output_delay 0 -clock CLK_VIRT [get_ports B]

„ Do not forget to fully specify the constraints!

By default (without -fall/-rise or -max/-min),
commands are symmetric
dc_shell-t> set_input_delay -rise 2 -clock CLK [get_ports A]

dc_shell-t> set_input_delay -fall 3 -clock CLK [get_ports A]

dc_shell-t> set_input_delay -rise 2 -clock CLK [get_ports A]
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Agenda

„ Introduction

„ Static Timing Analysis Basis

„ Timing Constraints

„ Environmental Constraints
„ Timing exceptions

„ Report example

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Specifying an Area Goal (Design Compiler)

z Area optimization is not carried out unless area constraints

are specified - only minimal area recovery is done by default

z Total Negative slack (TNS) is prioritized ahead of area

dc_shell-t> current_design PRGRM_CNT_TOP

dc_shell-t> set_max_area 100

Units are those of target library,

defined by the vendor

z 2-input-NAND-gate
z transistors
z square mils…
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Constraining for Timing - What is missing?

TO_BE_ANALYZED set_output_delay
set_input_delay

N D Q X D Q S
FF2 FF3
QB QB
CLK
create_clock

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Describing Environmental Attributes

set_operating_conditions

set_load

set_driving_cell set_wire_load

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Modeling Output Load
Use set_load to specify a load value on an output port

OUT
1 5 set_load 5 [get_ports OUT1]

Use set_load [load_of lib/cell/pin] to place the load of a gate

from the technology library on the port

OUT1 A
AN2 set_load [load_of CBA/AN2/A] [get_ports OUT1]
B

load_of(lib/cell/pin) can be multiplied by a scaling factor:

A
set_load [expr [load_of CBA/IVA/A] * 3] [get_ports OUT1]
OUT
A
1
A

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Modeling Input Drive Strength
„ In order to accurately calculate the timing of an input circuit,
DC needs to know the transition time of the signal arriving at
the input port

„ set_driving_cell allows the user to specify a realistic

external cell driving the input ports:
z By default, DC assumes that the external signal has a
transition time of 0

TO_BE_SYNTHESIZED

ND2
IN1

dc_shell-t> set_driving_cell -lib_cell ND2 [get_ports IN1]

dc_shell-t> set_driving_cell -lib_cell ND2 -from_pin Y \

[get_ports IN1]
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Setting The Operating Conditions
„ Vendors allow for synthesis of circuits which will not
operate under 'nominal' conditions by embedding
operating condition models in the technology libraries

„ Operating conditions can be placed on your design by

using the set_operating_conditions command
z During synthesis, 'nominal' cell and wire delays will be scaled
based on the operating conditions

dc_shell-t> current_design addtwo

dc_shell-t> set_operating_conditions -max “slow_125_1.62”

worst worst
nominal
Delay nominal Delay Delay worst
best nominal
best
best

Temperature Voltage Process

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Specifying Wire Loads

„ A wire load model is an estimate of a nets parasitics

based on the nets fanout
dc_shell-t> current_design addtwo
dc_shell-t> set_wire_load_model –name tc6a120m2

„ A wire load mode specifies the wire load model to use for
nets that cross hierarchical boundaries.
mode = enclosed mode = top
50X50 50X50
40X40 40X40
20x20 30x30 20X20 30X30

50x50
40x40

dc_shell-t> set auto_wire_load_selection true

dc_shell-t> set_wire_load_mode enclosed
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Typical BASIC Script - Review
my_block_constraints.tcl
# Define clock
create_clock -period 10 [get_ports CLK]
set_dont_touch_network [all_clocks]

# Delay and drive strength on input ports

set all_inputs_but_clk [remove_from_collection [all_inputs] CLK]
set_input_delay $clk_to_q -clock CLK $all_inputs_but_clk
set_driving_cell -lib_cell $my_register $all_inputs_but_clk

# Delay and load on output ports

set_output_delay [expr 10 - $clk_to_q] -clock CLK [all_outputs]
set_load [expr $pessimistic_load * 3] [all_outputs]

# Describe environment
set_operating_conditions WCCOM
set_wire_load_mode top A
B Yout
set auto_wire_load_selection false
set_wire_load_model -name 100k_WLM clk

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Agenda

„ Introduction

„ Static Timing Analysis Basis

„ Timing Constraints

„ Environmental Constraints

„ Timing exceptions
„ Report example

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What are Timing Exceptions?

„ Timing exceptions are used to overrides the default single

cycle behaviour described by create_clock, set_input_delay
and set_output_delay

„ There are three types of timing exception,

z set_false_path - for paths which do not affect the circuit
operation or for path which are asynchronous

z set_multicycle_path - for paths which takes more than one

clock cycle

z set_max_delay / set_min_delay - for paths with a specific

timing delay requirement

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Timing Exceptions

„ We recommend strongly to apply exceptions on

valid timing startpoints and endpoints.

„ What are timing startpoints?

z Primary input ports

z Register (latch, FF) clock pins

„ What are timing endpoints?

z Primary output ports

z Register (latch, FF) data pins

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Timing Exception Impact
„ Timing exceptions make analysis more costly

„ PrimeTime and Design Compiler are optimized for

fully constrained design with default single cycle
behaviour

Complexity of Timing Analysis ~=

Latches + Flip-flops + Timing exceptions + Clocks
dc_shell-t> set_false_path -from U_CONTROL/reg*/CP \
-to U_DATA/reg*/D

If regs are 32 bits, # of exceptions = 32*32 = 1024!

Tools do NOT check if exceptions are valid

Use report_timing_requirements -ignore in DC

and report_exceptions ignore in PT
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Asynchronous paths
TOP
Des_A Des_B
CLKA
(100 Mhz N D Q D Q X D Q
from OSC1)
CLKB
(100 Mhz
from OSC2)

„ If the clocks are Asynchronous (multiple source & sinks), you

MUST use set_false_path to disable timing-based synthesis
and timing analysis
dc_shell-t> create_clock -period 10 [get_ports CLKA]
dc_shell-t> create_clock -period 10 [get_ports CLKB]

dc_shell-t> set_false_path -from [get_clocks CLKA] \

-to [get_clocks CLKB]
dc_shell-t> set_false_path -from [get_clocks CLKB] \
-to [get_clocks CLKA]
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Multi-Cycle Behavior
„ Problem: Not all paths operate at the target frequency of the
circuit

SYSTEM_SYNCH_SET

FF4
U2

64 x 64
DATA FF1
U1 MULTIPLIER FF2
CLK U3

„ Solution:
z Add pipeline stage(s) to divide the logic into single-cycle paths

z Ease off the single-cycle requirement & allow more clock cycles

set_multicycle_path 2 -setup -from [get_pins U1/CP] -to [get_pins U3/D]

set_multicycle_path 1 -hold -from [get_pins U1/CP] -to [get_pins U3/D]

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Timing Checks on Multicycle Paths

„ The hold check is related to the setup check - By

default the hold check is one edge before the setup
dc_shell-t> set_multicycle_path 2 -setup -from A -to B

2-cycle example

0 1 2
setup check
wanted default
hold hold
check check
Tp < delay < 2Tp

„ To bring back the hold check to its wanted location,

you should set the hold multiplier such that
hold_multiplier = setup_multiplier - 1
dc_shell-t> set_multicycle_path 2 -setup -from A -to B
dc_shell-t> set_multicycle_path 1 -hold -from A -to B

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Do / Don't Do
„ Do not use max/min delays to constraint combo logic
dc_shell-t> set_max_delay 12 -from [get_ports A] \
-to [get_ports B]

dc_shell-t> create_clock -period 12 -name CLK_VIRT

dc_shell-t> set_input_delay 0 -clock CLK_VIRT [get_ports A]
dc_shell-t> set_output_delay 0 -clock CLK_VIRT [get_ports B]

„ Do use valid startpoint and endpoint when using -from

and -to switches. Prevents path segmentation

dc_shell-t> set_max_delay -from [get_pins U1/U256/QN]

dc_shell-t> set_max_delay -through [get_pins U1/U256/QN]

or
dc_shell-t> set_max_delay -from [get_pins U1/U256/CP]
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Agenda

„ Introduction

„ Static Timing Analysis Basis

„ Timing Constraints

„ Environmental Constraints

„ Timing exceptions

„ Reports and Analysis

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Checking the constraints - 1

„ report_port -verbose
z Returns all attributes and constraints placed on all input and
output ports

„ report_clock / report_clock -skew

z Returns the source, waveform and period of all clock objects in
current_design

„ report_design
z Returns the current design and environmental attribute such as
operating conditions and wire loads

„ list_libs / report_lib
z The first command list the library in memory while the second
gives some relevant information regarding a given library

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Checking the constraints - 2

„ report_timing_requirements (-ignored) - DC only

report_exceptions (-ignored) - PT only
z Returns all timing exceptions (and 'invalid' timing exceptions)

„ report_disable_timing
z Reports timing arcs which were disabled via set_case_analysis or
set_disable_timing

„ write_script
z Returns a script with ALL the attributes set on the current_design
z Extremely useful for final sanity checks - File can be large!

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Before Detailed Timing analysis

„ check_design (DC only)

z check the design for consistency pre-compile. Warns if
multiple instantiation of the same design exists, if there
are unconnected port…

„ check_timing -verbose
z Check for any timing problem such as unmapped logic,
unconstrained paths, missing clocks...

„ report_analysis_coverage (PT only)

z For each type of check (for example, setup), shows the
number and percentage of checks meeting and violating
constraints, and those that are untested

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The check_timing Command

„ check_timing (-verbose) will check the

following:
z Generic cells in a design (unmapped cells with zero
delay)
z Unconstrained timing endpoints (an endpoint is a
primary output port or a register data input)
z Multiple clocks reaching a register pin

z Missing clocks on register pins

z Missing clock-related delays on input ports

z Combinational feedback loops

z Level-sensitive latches which fanout to themselves

(potentially causing a transparent feedback loop)
z Incorrectly specified generated clocks

z Ignored timing attributes

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check_timing Example

dc_shell-t> check_timing

Warning:
There are 4 register clock pins with no clock.
There are 10 endpoints which are not constrained for maximum delay.
There are timing exceptions which are ignored.
There are max_time_borrow attributes which are ignored.
There are 6 timing loops in the design.

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Static Timing Analysis Commands - 1
„ update_timing
z Updates timing for the current design and prepares the
design for further analysis
z Some commands such as report_timing or report_constraint
automatically call update_timing if needed

„ report_bottleneck (PT only)

z Reports the common point in the design that contributes to
multiple violations

„ report_constraint
z By default will return the synthesis cost function with all
costs, weights and weighted costs
z Can report all violators for max/min timing and DRC

z -verbose switch is not recommended

Specifying Efficient Constraints

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Static Timing Analysis Commands - 2

„ report_timing
z By default shows the worst max path per path group

„ report_delay_calculation
z Shows the delay calculation for a pin-to-pin timing arc

z Library needs to be enabled for delay calculation reports

Specifying Efficient Constraints

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The report_timing command

-max_path 4 Reports the worst 4 paths per path

groups(default= 1)
-nworst 3 Reports 3 paths per endpoint in the
limit of max_path(default = 1)
-delay_type min Select delay type (default = max)
-path_type full_clock Shows the entire clock network

-input Shows input pin with net delay

-transition Shows transition time
-capacitance Shows max (lumped) capacitance
-sig 8 Reports value with 8 significant
digits (default = 2)
-nosplit Prevents line splitting
Specifying Efficient Constraints
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Timing Report, page 1
pt_shell> report_timing
****************************************
Report : timing
-path full Is this a setup or a
-delay max
-max_paths 1 hold time report?
Design : AM2910
Version: 1997.08
Date : Mon Dec 29 10:53:32 1997
****************************************

Startpoint: U3/OUTPUT_reg[12]
(rising edge-triggered flip-flop clocked by CLOCK)
Endpoint: U2/OUTPUT_reg[2]
(rising edge-triggered flip-flop clocked by CLOCK)
Path Group: CLOCK
Path Type: max

Point Incr Path

---------------------------------------------------------------
clock CLOCK (rise edge) 0.00 0.00
clock network delay (ideal) 5.50 5.50
U3/OUTPUT_reg[12]/CP (FD1) 0.00 5.50 r
U3/OUTPUT_reg[12]/Q (FD1) 3.97 9.47 f
U3/U106/Z (OR3) 3.78 13.25 f
...
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Synopsys .. 63
Timing Report, page 2
Point Incr Path
---------------------------------------------------------------
...
U3/U130/Z (ND2I) 0.24 24.34 f
U3/U148/Z (IV) 2.90 27.25 r How can you tell the
U3/ZERO (REGCNT) 0.00 27.25 r
U5/REGCNT_ZERO (CONTROL) 0.00 27.25 r hierarchy that this path
U5/U232/Z (ND2) 0.64 27.88 f
... traverses?
U5/U236/Z (IVA) 0.75 31.15 r
U5/U193/Z (ND4) 1.38 32.53 f
U5/Y_CONTROL[1] (CONTROL) 0.00 32.53 f
U4/OPERATION[1] (Y) 0.00 32.53 f Did the path meet
U4/core/MUXOUT[1] (Y_core) 7.24 39.77 r
U4/MUXOUT[1] (Y) 0.00 39.77 r timing?
U2/DATA[12] (UPC) 0.00 39.77 r
U2/U73/Z (ND2) 0.74 40.51 f
...
U2/U62/Z (AN2) 1.92 58.90 f What is the clock
U2/OUTPUT_reg[2]/D (FD1) 0.01 58.91 f
data arrival time 58.91 period?
clock CLOCK (rise edge) 30.00 30.00
clock network delay (ideal) 5.50 35.50 Where does the clock skew
clock uncertainty -0.50 35.00
U2/OUTPUT_reg[2]/CP (FD1) 35.00 r information show up in the
library setup time -0.80 34.20
data required time 34.20 report?
---------------------------------------------------------------
data required time 34.20
data arrival time -58.91
---------------------------------------------------------------
slack (VIOLATED) -24.71

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Synopsys .. 64
Summary: Timing Checks
Recovery
Removal Setup Out Setup
Hold MY_DESIGN Out Hold

Clk3 Clk4

Clk1
ClkEn U1 Clk Gating Check Setup
Clk Gating Check Hold
Clk2
Timing Model

Max Skew
Min Clk Pulse Width
Min Clk Pulse Width
Data to Data
Setup and Hold

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Summary: Generate Reports

Report all violations

In more detail

Setup/Hold Clock check Clock Network Bottleneck DRC

check reports reports reports reports reports

'What If' Analysis

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Synopsys .. 66
Thank You !!!

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