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Assignment 5

Anonymous

Science Computing

CS 1104-01 - AY2024-T4

Professor Shashank Singth

May 10, 2024

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For the Unit 5 assignment, I want you to assume that you are writing an instructional

paper in which you must describe the processing and interdependencies of the following

components of computer architecture.

ALU (Arithmetic Logic Unit); Instruction Decoder; Clock and Program

Counter; Control Codes; Control Unit.

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Figure 1.

A complex processor.

Figure 2.

The complex processor is not required.

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Figure 3.

The processor required.

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Figure 4.

Control codes
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Processor

ALU (Arithmetic Logic Unit)

ALU is a digital circuitry that provides arithmetic, mathematical and logic operations.

This is the fundamental building part of the central processing unit of a PC. A modern central

processing unit has a powerful ALU and this is complex in design. In addition, to ALU

modern CPU has a control unit and a big as possible set of registers. Most of the operations

are made true by one or more ALUs that upload data from the available input register.

Registers are not many amounts of storage available to the CPU because it makes the

machine expensive. These registers can be very fast. The control unit informs ALU what

operation to do on the data. After performing calculation, the ALU keeps the output in a

memory register.(GeeksforGeeks, 2023).

Instruction Decoder

The process of decoding an instruction consists of taking the 32-bit

instruction and breaking it into groups of data that are then passed on to other

units in the CPU. These groupings fall into the following basic types:

Specific register types (e.g., Rd, Rn, Rm, Rs) that contain the register

number to use for these registers (e.g., 0b0000 for r0, 0b0001 for r1); Numeric

data, such as the Immediate and ShAmt values. Note that the numeric values

in assembly instructions can be different sizes. For example, the ShAmt is a 4-

bit number when it represents a rotation in an Immediate expression, but is a

5-bit number in a Numeric Shift Instruction. The Immediate value can be 4, 8,

or 12 bits depending on the type of instruction. For these values, the maximum

number of bits (5 bits for the ShAmt and 12 bits for the Immediate) will be
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sent to the other CPU units, and those units are responsible for proper

processing the data; Control data, bits that indicate to the CPU the type of

instruction, will be forwarded to the CU, ALU, and barrel shifter to properly

set up the CPU to handle the instruction. While these units are the heart of the

CPU, it is complex, and is a topic separate from assembly language.

In the MSCPU, a Decoder unit will be placed between the Text

Memory, which retrieves the 32- bit instruction from Text Memory, and the

rest of the CPU which will use the parts of the instruction. A black box

Decoder unit is shown in Figure 31. The input is the 32-bit instruction, and the

outputs are the numeric Immediate and ShAmt values, the Rd, Rm, Rn, and Rs

register numbers, and the control information.

Figure 31.

Decoder black box diagram

How the decoding of the instruction is achieved will now be built in

stages. The first iteration will use a splitter to break the instruction into 32
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separate wires and then to create register number output to forward to the

Register Bank.

To start we examine Appendix 3, which gives the machine code

formats of all the Address instructions. The Register Instruction uses all the

registers in a single instruction and is reproduced in Figure 32.

Figure 32.

Register Instruction

This instruction shows where each of the register numbers that occur in

all instructions, generally called Rd, Rm, Rn, and Rs, are located in the

instructions. These registers will sometimes be referred to by other names

(such as Rt for the and str instructions), and some instructions use other

register conventions (such as the instruction that swaps Rd and Rn). However,

these anomalous cases require the CPU to have a knowledge of the

instructions being processed to know how to handle them, and since the

Decoder unit has no way to know the instruction type, the register identifiers

in the register instruction shown above will still be used. The responsibility for

determining any anomalous meaning of the registers will be the responsibility

of the downstream processing units, in this case the Register Bank. The

decoder simply moves 4 bits from a specified position in the instruction to the

4-bit output value. In this case, bits 0-3 are moved to the Rm output, bits 8-11
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are moved to the Rs output, bits 12-15 are moved to the Rd output, and bits

16-19 are moved to the Rn output. This is shown in the first iteration of the

Decoder below.

Figure 33.

Decoder showing the mapping of instruction to register numbers

The next iteration of the decoder will process the output to the

Immediate and the ShAmt. To see where these numeric values occur in a

Register Format, Operand2 with ShAmt and a Load/Store Immediate

Instruction are reproduced in Figures 34 and 35. The maximum ShAmt is

instruction bits 7...11, and the maximum immediate value is instruction bits

0...11.

Figure 35.

Load/Store Immediate Instructions.

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Once again there are anomalous conditions where the ShAmt and

Immediate value are different sizes depending on the instructions. Again, the

largest value is parsed from the input, and the downstream CPU units are

responsible for using the values correctly.

Note that both the ShAmt and Immediate have wires that overlap the

wires for the registers. This does not cause any problems as the overlap occurs

for different instructions, thus the values for the registers and immediate

values are always correct for the instruction being executed. Again, since the

Decoder has no way to determine which instruction is being executed, or how

many bits to put on the output wires, it will always provide the maximum

number of bits to these values, relying on other units to adjust to the proper

number of bits used.

Figure 36.

Decoder with added Immediate and ShAmt values

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Finally, the control information needs to be forwarded. For now, all the

control information is just grouped together and sent to a single output port.

The control information is 15-bits of information, and includes the CondCode,

OpType, OpCode, and ShiftType. This final iteration of the decoder is

presented in the following figure, which represents the final implementation of

the Decoder (Kann, n.d, p. 1).

Figure 37.

Final implementation.

Clock and Program Counter.

The Clock makes sure that a variety of circuits inside a computer work jointly at the

same time. The Clock speed is measured by how many ticks(pulses) per minute it makes. The

hertz (Hz, unit of measurement), which is standardized one cycle per second( University

Information Technology Services, 2003).

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The counter, also known as PC(program counter, not personal computer), is an

important component of a computer's central processing unit. It is a special register. The

program counter is important because it permits the central processing unit to fetch

guidelines from memory in a sequential mode. Keeping track of the current guidelines’

address, the Counter makes sure that the CPU knows which guidelines to fetch next(Lenovo,

n.d).

Control Codes. A computer’s instruction is a binary code which determines the

operations in a for a computer. They are stored in the memory together with information.

Each computer has a specific sequence of instructions.

They can be classified in two elements as operation codes and addresses. Operations

codes specify the operation(surely) for some instructions. An address code determines the

registers or the places that can be used for. It is 12 bits of memory that are needed to define

the address if the memory includes 4096 words. The 15th bit of the guideline determines the

addressing mode (where direct addressing is 0, indirect addressing is 1). Hence, the

instruction includes 12 bits of address and 1 bit for the addressing mode, 3 bits are kept for

Opcodes (TutorialsPoint, 2023).

Control Unit

The control unit informs ALU what operation to do on the data. “Video games,

interactive video installations, virtual reality, and computer-based art.”( Smuts, 2009, p. 2).

“The function of the control unit of an electronic digital computer is to provide the

sequences of pulses, which, when applied to the store, arithmetic unit and other units of the

machine, cause the orders of the programme to be executed. In one group of systems the
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order code is determined by the arrangement of diodes in a diode matrix, and in another by

the appropriate threading of wires through a matrix of ferrite cores”( Wilkes et al, 1958, p.1).

Figure 38.

Required diagram, job of mine.

References
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APA Style. APA 7th Edition Style. APA Style. https://apastyle.apa.org/

APA Style. Headings. APA Style. https://apastyle.apa.org/style-grammar-guidelines/paper-

format/headings

Lenovo(n.d). What is a program counter (PC)? Lenovo.

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%252F%252Fwww.google.com%252F

GeeksforGeeks(Aug 12, 2023). Introduction of ALU and Data Path. GeeksforGeeks.

https://www.geeksforgeeks.org/introduction-of-alu-and-data-path/

Nisan, N., & Schocken, S. (2005). The elements of computing systems. MIT Press.

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Kann W. C.(n.d). 6.1: Decoding a machine code instruction. LibreText Engineering.

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SMUTS, A. (2009). What Is Interactivity? The Journal of Aesthetic Education, 43(4), 53–

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Tarnoff, D. (2007). Computer organization and design fundamentals.

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Tutorialspoint(Nov 3, 2023). What are Instruction Codes and Operands in Computer

Architecture? Tutorialspoint. https://www.tutorialspoint.com/what-are-instruction-

codes-and-operands-in-computer-architecture

Wilkes, V. Renwick, Wheeler D. J. (1958). The design of the control unit of an electronic

digital computer. V 105, I(20).IET Digital Library. DOI: 10.1049/pi-b-1.1958.0267

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University Information Technology Services(Nov. 09, 2003). ARCHIVED: What is a

computer's clock speed? University Information Technology Services.

https://kb.iu.edu/d/aekt