2022 IEEE 3rd Global Conference for Advancement in Technology (GCAT)

Bangalore, India. Oct 7-9, 2022

Development of Verification IP of Physical Layer of

PCIe
Viraj Nitin Vaidya Vaishali Ingale Ashlesha Gokhale
VLSI and Embedded Systems Dept. of E&TC ESCICOMP-INDIA Pvt. Lt.
College of Engineering Pune College of Engineering Pune Pune, India
Pune, India Pune, India ashleshaag@gmail.com
vaidyavn20.extc@coep.ac.in vvi.extc@coep.ac.in

Abstract— PCI Express (Peripheral Component

2022 IEEE 3rd Global Conference for Advancement in Technology (GCAT) | 978-1-6654-6855-8/22/$31.00 ©2022 IEEE | DOI: 10.1109/GCAT55367.2022.9971846

Interconnect) is a point-to-point, high-performance, serial

interconnect protocol. PCIe outperforms older buses and offers
greater bandwidth, making it a fantastic option for a wide range
of applications. PCIe features layered architecture with three
distinct layers. Packets are used to convey information between
these layers. The verification IP of the physical layer in PCI
Express is implemented in this paper. The Universal Verification
Methodology is used for development of VIP of PCIe, which is
written in System Verilog (UVM).

Keywords—PCI Express, PCIe, System Verilog, UVM,

Verification IP

I. INTRODUCTION
The PCI Express architects have taken advantage of latest
advancements in computer design while also carrying over the
most desirable aspects from previous generation bus
architectures. PCI Express, for example, uses the same load-
store mode of communication as PCI and PCI-X. Memory
read, memory write, IO read, IO write, configuration read and
configuration write are all supported by PCI Express. With PCI
and PCI-X, PCI Express is backwards compatible systems in
terms of software. With no changes to present drivers or
application programs, a PCI Express machine will boot an Fig. 1. PCI Express Device Layers
existing OS. PCI Express, like its predecessor buses, offers
chip-to-chip and board-to-board[12]. Transaction Layer Packet (TLP). Information required for
PCI Express is a serial point-to-point interconnect that checking errors at a receiver is added to the packet by Data
allows devices to communicate. Switches are used to connect Link Layer (DLLP). This packet is then scrambled and
several PCI Express devices. Because of point-to-point encoded in the Physical layer and transmitted differentially on
interconnect has a minimal electrical load, transmission and the Link by this Layer's analogue part. The packet is sent to the
reception frequencies can be scaled to much greater numbers. receiving device, which is its neighbour, utilising the available
Serial connectivity between devices results in fewer pins per Lanes of the Link. In the Physical Layer, the receiver device
device, lowering both the cost and the complexity of PCI decodes and descrambles the packet contents and transmits the
Express chip and board design. To connect multiple devices, resulting contents to the top layers[15].
PCI Express uses switch-based technology. A packet-based II. RELATED WORK
communication protocol is used to communicate across the
serial interconnect. This minimizes system cost by keeping the The transaction and data link layers of PCIe are applied
device pin count low[13]. with a novel methodology by Peter B ohm[1]. A sequence of
data modeling phases form the foundation of the technique for
As demonstrated in Figure 1, the PCI Express has a layered developing on-chip protocols, which updates the standard
architecture for device. Transaction Layer, Data Link Layer, modelling as well as validation workflow.
and Physical Layer are the three layers present. Consider a
device's transmit function. The Transaction Layer creates The transactions between the MAC and PHY layers of the
packet contents using information from the device. The packet PCIe Gen5.0 physical layer were verified by Dinesh Mathur
is transmitted to the lower layers. The packet is known as [2]. The RTL is written in the System Verilog, and UVM is
used for verification. The proposed procedure's efficacy is

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 demonstrated by simulation results, which are effectively
displayed in the Synopsys Discovery Visual Environment tool.
Li Jun's paper[3] offers a design and verification of the
PCle based on the Xilinx Spartan-6 FPGA. Without the need
for any extra external chips, a PClexl information connection
interface may be implemented inside the add-in card thanks to
the Sparant-6 FPGA's integrated Endpoint Block and
associated IP-core.
To verify the proposed hardware and software design
strategy, Haiming Cai's research uses a gigabit Ethernet chip
and network bandwidth test automation[4]. The architecture of
this method provides the advantages of a straightforward
structure, potent performance, and simple extension, making it
a competitive solution for future high-performance servers and
substantial PLC systems.
Design and verification of numerous physical layer blocks
of PCIe and USB is included Richard A Prasad's work. RTL is
written in Verilog and verification is done in UVM with
Mentor Graphics' Questasim 10.0c[5].
Chandana K N establishes numerous key jobs in the
LTSSM paper[6]. The Link Training & Status Status Machine
(LTSSM) performs all of these activities by observing the
remote link partner's response as well as the present state and
responding appropriately. Fig. 2. Architecture of Physical Layer
Ravikumar Javali demonstrated how packets are produced
in the PHY layer[7]. The proposed PCIe MAC design operates 1) Data Scrambling: To limit the likelihood of electrical
at five-clock cycle delay to build, scramble, and place a packet resonances on the link, PCI Express uses a method known as
on the bus. data scrambling. The PCI Express specification specifies a
Author Sagar K. implemented Ordered Sets sampling[8]. A linear feedback shift register-based scrambling/descrambling
major task in the Physical layer in PCI Express 3.0 is to method. PCI Express scrambles or descrambles data by
monitor and sample different Ordered sets and Data Packets conducting a serial XOR operation on it with the seed output
that came from various layers. of a synchronised Linear Feedback Shift Register (LFSR).
2) 8-Bit/10-Bit Encoding: The main goal of 8-bit/10-bit
III. ARCHITECTURE OF PHYSICAL LAYER encoding is to incorporate a clock signal into the data stream.
Physical Layer is the lowest architectural layer of PCI This encoding approach eliminates the need for external clock
Express. This layer is in charge of delivering and receiving all signals by incorporating a clock into the data.
of the data that has to be transferred through the link of PCI 3) Packet Framing: Identifying 10-bit special symbols are
Express. The Data Link Layer and the PCI Express link inserted and appended to a previously 8-bit/10-bit encoded data
communicate with the Physical Layer. packet to allow the receiving device know where one packet
A. Logical Sub-Block starts and finishes.
The Physical Layer's logical sub-block is the key decision
maker. The transmit unit and receive unit, respectively, are B. Electrical Sub-Block
independent transmit and receive routes in the logical sub-
block. Both units have the ability to work independently of one The electrical sub-block of the Physical Layer serves as the
another. The transmit unit's main job is to prepare data link delivery mechanism for the physical architecture, while the
packets for transmission after they've been received from the logical sub-block serves as the essential decision maker. The
Data Link Layer. Data scrambling, 8-bit/10-bit encoding, and transmit and receive buffers in the electrical sub-block convert
packet framing are the three main stages of this procedure. The data into electrical signals that can be transferred across the
receive unit works in the same way as the transmit unit, but in link. The PLL circuitry, which supplies internal clocks for the
the opposite direction. The receive unit receives the device, may also be found in the electrical sub-block.
deserialized physical packet that the electrical sub-block has 1) Serial/Parallel Conversion: The electrical sub-transmit
taken off the link, removes the framing, decodes it, and block's buffer translates the encoded/packetized data from the
ultimately descrambles it. logical sub-block to serial format. After serialisation, the data
is directed to a corresponding lane for transmission across the

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 link. The receivers deserialize the data and feed it back to the 8) L2: L2 is the state with the least amount of power.
logical sub-block for additional processing on the receive side. Although main power and clocks aren't guaranteed, but we
2) Clock Extraction: In addition to the parallel-to-serial can use AUX power.
conversion mentioned above, the electrical sub-receive block's 9) Disabled: In disabled mode the transmitter has a high
buffer is responsible for retrieving the data's embedded link electrical impedance state and the receiver is turned on and in
clock. low - resistance mode. When it detects two or even more
3) Lane-to-Lane De-Skew: Before combining serial data successive TS1 OS or TS2 OS which has bit of Disable
into a parallel data packet, the receive buffer in the electrical Link set, this state can be retrieved, or when a device receives
sub-block de-skews data from the various lanes of the link. a command from higher layer.
This is required to account for the 20 nanoseconds of lane-to- 10) Loopback: It's designed for usage in testing and fault
lane skew allowed. isolation. Behaviour of entry and exit is only specified. It
4) Differential Signaling: The transmit and receive buffers might happen on a lane or link that has been configured.
on PCI Express are designed to convert logical data symbols 11) Hot Reset: When it detects two or even more successive
into differential signals. TS1 OS or TS2 OS which has Reset bit set, this state can be
5) PLL (Phase Locked Loop) Circuit: A clock obtained retrieved, or when a device receives a command from Data
from a PLL circuit could be used to give internal clocking to Link Layer.
the PCI Express device. A 100 megahertz differential pair
clock is assigned to each PCI Express device. This clock can
be fed into a PLL circuit, which multiplies it by 25 to get the
2.5 GHz frequency.
6) AC coupling: PCI Express eliminates the DC Common
Mode portion by using AC coupling on the transmit side of
the differential pair. As a result, the PCI Express buffer design
process becomes significantly easier.
7) De-Emphasis: To lessen the impacts of inter-symbol
interference, PCI Express employs a concept known as de-
emphasis.
IV. LINK TRAINING AND STATUS STATE MACHINE
Link training is a Physical Layer procedure which
configures and initialises Link in order for typical packet traffic
to pass over the Link. Without the need of any software. As
shown in Figure 3, the LTSSM is responsible for Link
Initialization and Training process.
1) Detect: When the device is powered on, the data link
layer directs an initial state in which the attached remote
device is detected. Fig. 3. LTSSM State Diagram
2) Polling: Bit and symbol locking also lane data rate and
lane polarity are specified in this state. The device sends out V. UVM TESTBENCH ARCHITECTURE
ordered sets and responds to those that are received. UVM has a number of advantages over past verification
3) Configuration: Transmitter and receiver both are mechanisms. It has class based library which is used for
working at the agreed-upon speed. Link-width, lane-reversal, verification, which is supported by all major simulators[9,10].
lane-ordering, and skew management in lanes are all done in This section describes the various UVM testbench
this state. components (shown in Figure 4) that are used in the testbench
4) Recovery: In recovery state, bit lock and symbol lock as to verify the DUT[11,14].
well as lane-to-lane de-skew are re-established.
1) Sequencer: The purpose of this component is really to
5) L0: This state is the typical operating state of the link
execute variety of sequences transmitted to design utilising
that is used to send and receive TLPs and DLLPs. From this
an interface.
stage, it can enter to all low power states.
2) Driver: It receives the randomised sequences from the
6) L0s: L0s is a power saving mode. It takes little amount
sequencer then it drives the signals which are from interface.
of time to exit L0s and return to L0. There is no need to enter
The DUT and the driver communicate at the pin level.
configuration and recovery state.
7) L1: L1 is state which has less power as compared to
L0s. Power saving is more in L1 than in L0s, in return they
have a longer latency period.

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 Fig. 4. UVM Testbench Architecture
Fig. 6. 8b/10b encoding

3) Monitor: Monitor samples DUT signal using the virtual

interface but it does not drive them, converts DUT signals
collect and provide information for coverages and checkers.
4) Agent: A driver, a sequencer, and a monitor are all
encapsulated in the Agent class. It is of two types, Active and
Passive. The signals are driven to the DUT by active agents,
drivers, and sequencers. Monitor and passive agent merely
monitors activity of DUT.
5) Scoreboard: The scoreboard receives transaction from
the DUT and from monitor, It then compares both of them. It
provides of how many responses were successful and how
many were not.
6) Environment: Depending on the architecture, an
environment is a class that can hold many agents and a Fig. 7. 8b/10b Decoding
scoreboard.
7) Interface: A testbench's interface is a structural
component which has all of the signals required for DUT
communication.
8) DUT: Module which we want to verify is known as
Design Under Test (DUT).
9) Top Testbench: In this the interface is created and the
clock is generated. The interface signals are connected with
the DUT signals.
VI. RESULTS

Fig. 8. Training Set 1/2 Ordered Set Formation

Fig. 5. Data Scrambling

Fig. 9. LTSSM

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