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Cache Problem Solution

The document contains a question about calculating the tag, index, and offset fields for a 16-bit direct-mapped cache with 64 byte blocks and 2KB size. It then provides two memory addresses and indicates whether each access would be a hit or miss. A second question provides 7 64-bit addresses and asks to identify the binary address, tag, index, and offset for a direct-mapped cache with two-word blocks and size of 8 blocks, indicating hits or misses.

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rishikesh shinde
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106 views2 pages

Cache Problem Solution

The document contains a question about calculating the tag, index, and offset fields for a 16-bit direct-mapped cache with 64 byte blocks and 2KB size. It then provides two memory addresses and indicates whether each access would be a hit or miss. A second question provides 7 64-bit addresses and asks to identify the binary address, tag, index, and offset for a direct-mapped cache with two-word blocks and size of 8 blocks, indicating hits or misses.

Uploaded by

rishikesh shinde
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Q.A processor system uses 16-bit memory addresses.

It has a 2K-byte cache organized in a direct-


mapped manner with 64 bytes per cache block. Assume that the size of each memory word is 1 byte.
(A)Calculate the number of bits in each of the Tag, Index, and Offset fields of the memory address.
(B)When a program is executed, the processor reads data sequentially from the following word
addresses: 128, 144.
All the above addresses are shown in decimal values. Assume that the cache is initially empty. For
each of the above addresses, indicate whether the cache access will result in a hit or a miss.

Ans.
Block size = 64 bytes = 26 bytes = 26 words (since 1 word = 1 byte)
Therefore, Number of bits in the Offset field = 6

Cache size = 2K-byte = 211 bytes


Number of cache blocks = Cache size / Block size = 211/26 = 25
Therefore, Number of bits in the Index field = 5

Total number of address bits = 16


Therefore, Number of bits in the Tag field = 16 - 6 - 5 = 5

For a given 16-bit address, the 5 most significant bits represent the Tag, the next 5 bits represent the
Index (Block), and the 6 least significant bits represent the Offset (Word).
Access # 1:
Address = (128)10 = (0000000010000000)2
(Note: Address is shown as a 16-bit number, because the processor uses 16-bit addresses)
For this address, Tag = 00000, Block = 00010, Word = 000000
Since the cache is empty before this access, this will be a cache miss
After this access, Tag field for cache block 00010 is set to 00000
Access # 2:
Address = (144)10 = (0000000010010000)2
For this address, Tag = 00000, Block = 00010, Word = 010000
Since tag field for cache block 00010 is 00000 before this access, this will be a cache hit (because
address tag = block tag)
Q. Caches are important to providing a high-performance memory hierarchy to ARM processors.
Below is a list of 64-bit memory address references, given as word addresses. 0xFFAA0003,
0xFFAA00B4, 0xFFAA002B, 0xFFAA0002, 0xFFAA00BF, 0xDDCC00BE, 0xDDCC00B5.
For each of these references, identify the binary word address, the tag, the index, and the offset given
a direct-mapped cache with two-word blocks and a total size of eight blocks. Also list if each reference
is a hit or a miss, assuming the cache is initially empty. [7]
Ans.
As cache has two word blocks, require offset 1 bit.
Total size is 8 blocks, index is 3 bits.
Remaining bits are Tag bits 64-3-1 = 60 bits.
At first time Tag=0xFFAA000 and Index =1 then it is miss but for second time it matches address tag
and index bit, so it is hit. (address tag = block tag)

Word Address Binary Tag Index Offset Hit/Mis


Address s
0xFFAA0003 0000 0011 0xFFAA000 1 1 M
0xFFAA00B4 1011 0100 0xFFAA00B 2 0 M
0xFFAA002B 0010 1011 0xFFAA002 5 1 M
0xFFAA0002 0000 0010 0xFFAA000 1 0 H
0xFFAA00BF 1011 1111 0xFFAA00B 7 1 M
0xDDCC00BE 1011 1110 0xDDCC00B 7 0 M
0xDDCC00B5 1011 0101 0xDDCC00B 2 1 M

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