16-Sep-23

EEE-342
MICROPROCESSOR SYSTEM AND
INTERFACING

Dr Junaid Ahmed
Associate Professor,
Electrical & Computer Engineering,
COMSATS University Islamabad.

Dr Junaid Ahmed

 Room 127 (1st floor)

 Email: junaid@comsats.edu.pk

 Phone: 051-9049240

 Course material will be made available at

CuOnline or MS Teams

1
 16-Sep-23

 Course Textbook
 The AVR Microcontroller and Embedded Systems: Using
Assembly and C, by Muhammad Ali Mazidi, Sarmad Naimi
Sepehr Naimi.
 Atmel AVR Microcontroller Primer: Programming and
Interfacing. By Steven F. Barrett, Daniel J. Pack. Morgan
and Claypool, 2007.
 Microcontrollers Fundamentals for Engineers and
Scientists. Steven F. Barrett, Daniel J. Pack, 2006.

 Additional recommended books:

 ATMega16 Datasheet.
 Embedded Systems Design with the Atmel AVR
Microcontroller.

https://drive.google.com/drive/folders/1gSjpEY5-
O8jPysb3U5Ab4loT3-UCCUqz

Theory:
Quizzes : 15%
Semester Project : 10%
Midterm Exam : 25%
Terminal Exam : 50%
Total : 100%

Lab:
In-Lab Performance & Lab Reports: 25%
Midterm Exam : 25%
Semester Project : 50%
Total : 100%

2
 16-Sep-23

 In this chapter we are InShaAllah going to study

 0.4: CPU Architecture

3
 16-Sep-23

 Inside CPU

 CPU Registers
1. The CPU uses registers to store information temporarily.
2. The information could be two values to be processed, or the
address of the value needed to be fetched from memory.
3. Registers inside the CPU can be 8-bit, 16-bit, 32-bit, or
even 64-bit registers, depending on the CPU.
4. In general, the more and bigger the registers, the better
the CPU.
5. The disadvantage of more and bigger registers is the
increased cost of such a CPU.

4
 16-Sep-23

 Arithmetic-logic unit (ALU)

 The ALU is responsible for performing arithmetic functions
such as add, subtract, multiply, and divide, and logic
functions such as AND, OR, and NOT.
 Program Counter
 The function of the program counter is to point to the
address of the next instruction to be executed.
 Once an instruction is executed, the program counter is
incremented to point to the address of the next instruction
to be executed.
 The contents of the program counter are placed on the
address bus to find and fetch the desired instruction.
 It is also called Instruction Pointer (IP)

 Instruction Decoder
 It interprets the instruction fetched into the CPU.
 It is a kind of dictionary, storing the meaning of each
instruction and what steps the CPU should take upon
receiving a given instruction.
 Just as a dictionary requires more pages the more words it
defines, a CPU capable of understanding more instructions
requires more transistors to design.

10

5
 16-Sep-23

 Let’s do step-by-step analysis of the process a CPU

would go through to add three numbers (0x21, 0x42,
0x12).
 Assume that an imaginary CPU has registers called A,
B, C, and D. It has an 8-bit data bus and a 16-bit
address bus.
 How many memory locations can the CPU address?
The CPU can access memory from addresses 0x0000 to 0xFFFF,
for a total of 0x10000 = 65536 = 2 locations,.

 The actions to be performed by the CPU are:

 Put hexadecimal value 0x21 into register A,
 Add to register A the values 0x42.
 Add to register A the values 0x12.

11

 Assume that the code for the CPU to move a value to

register A is 1011 0000 (0xB0).
 And the code for adding a value to register A is 0000
0100 (0x04). The necessary steps and code to perform
these operations are as follows.
Action Code Data
Move value 0x21 into register A 0xB0 0x21
Add value 0x42 to register A 0x04 0x42
Add value 0x12 to register A ? 0x04 ? 0x12

12

6
 16-Sep-23

 If the program to perform the actions listed above is

stored in memory locations starting at 0x1400, the
following would represent the contents for each
memory address location:

Memory Contents of memory address

address
1400 (B0) code for moving a value to register A
1401 (21) value to be moved
1402 (04) code for adding a value to register A
1403 (42) value to be added
1404 (04) code for adding a value to register A
1405 (12) value to be added
1406 (F4) code for halt

13

 The actions performed by the CPU to run the program

above would be as follows:
1. The CPU's program counter can have a value between
0x0000 and 0xFFFF. The program counter must be set to
the value 0x 1400 , indicating the address of the first
instruction code to be executed.
2. The CPU puts 0x1400 on the address bus and sends it out.
The memory circuitry finds the location while the CPU
activates the READ signal, indicating to memory that it
wants the byte at location 0x1400. This causes the
contents of memory location 0x1400, which is 0xB0, to be
put on the data bus and brought into the CPU.
3. The CPU decodes the instruction 0xB0 with the help of its
instruction decoder dictionary. When it finds the definition
for that instruction it knows it must bring the byte in the
next memory location into register A of the CPU.

14

7
 16-Sep-23

4. From memory location 0x1402 the CPU fetches code 0x04.

5. After decoding, the CPU knows that it must add the byte sitting at
the next address (0x1403) to the contents of register A.
6. After the CPU brings the value, it provides the contents of register
A along with this value to the ALU to perform the addition.
7. It then takes the result of the addition from the ALU's output and
puts it into register A.
8. Meanwhile the program counter becomes 0x1404, the address of the
next instruction.
9. Address 0x1404 is put on the address bus and the code is fetched
into the CPU, decoded, and executed. This code again is adding a
value to register A. The program counter is updated to 0x1406.
10. Finally, the contents of address 1406 are fetched in and executed.
This HALT instruction tells the CPU to stop incrementing the
program counter and asking for the next instruction. Without the
HALT, the CPU would continue updating the program counter and
fetching instructions.

15

ROM (read-only memory)

 ROM is a type of memory that does not lose its contents
when the power is turned off. For this reason, ROM is
also called nonvolatile memory.
 There are different types of read-only memory, such as
PROM, EPROM, EEPROM, Flash EPROM, and mask
ROM
Mask ROM
 contents are programmed by the IC manufacturer.
 It is not a user-programmable ROM.
 It offers very low cost.
 It is used when the needed volume is high (hundreds of
thousands) and it is absolutely certain that the
contents will not change.

16

8
 16-Sep-23

PROM (programmable ROM) and OTP

 It’s a kind of ROM that the user can bum information once.
 Therefore it is also called One Time Programmable (OTP)
 Programming ROM, also called burning ROM, requires special
equipment called a ROM burner or ROM programmer

EPROM (erasable programmable ROM) and UV-EPROM

 EPROM can be programed and erased thousands of times.
 A widely used EPROM is called UV-EPROM,
 It can be erased by shining UV light for 15-20 minutes.
 It is programmed in an EPROM programmer (burner), and erased
in a separate EPROM erasure equipment.
 It cannot be erased and programmed while it is in the system
board.
 Under UV light individual data segments (bytes) can not be
selected for erasure, instead the whole chip gets erased.

17

EEPROM (Electrically Erasable Programmable ROM)

 It is programmed and erased electrically within seconds.

 It can be programmed and its contents erased while it is still

in the system board. It does not require physical removal of
the memory chip from its socket.
 Cost per bit for EEPROM is much higher than for UV-
EPROM.
Flash memory EPROM
 Similar to EEPROM it can be programmed and erased
electrically in seconds.
 Individual bytes can not be read or written instead data is
read/written block wise.
 It is slower but less expensive than EEPROM.

18

9
 16-Sep-23

RAM (random access memory)

 It is a volatile memory since cutting off power to the IC
results in loss of data.
 There are three major types of RAM: static RAM
(SRAM), NV-RAM (nonvolatile RAM), and dynamic
RAM (DRAM).
SRAM (static RAM)
 Storage cells are made of flip-flops.

 Do not require refreshing in order to keep their data.

 Each cell requires at 4 - 6 transistors to build, and the

cell holds only 1 bit of data.
 Low capacity and therefore relatively expensive

19

NV-RAM (nonvolatile RAM)

 Like other RAMs, it allows the CPU to read and write
to it, but when the power is turned off the contents are
not lost.
 It uses
 extremely power-efficient SRAM cells built out of CMOS
 an internal lithium battery as a backup energy source
 an intelligent control circuitry to switch automatically to its
internal power source when external power source is off.
 It is a very expensive type of RAM.
 It can retain its contents up to ten years after the
power has been turned off and allows one to read and
write in exactly the same way as SRAM.

20

10
 16-Sep-23

DRAM (dynamic RAM)

 It uses a capacitor to store each bit, therefore each cell
occupies a smaller area.
 It requires constant refreshing due to leakage.

 The advantages of DRAM memory are

 high density (capacity),
 cheaper cost per bit,
 lower power consumption per bit.
 The disadvantages are
 it must be refreshed periodically because the capacitor cell
loses its charge
 while DRAM is being refreshed, the data cannot be
accessed.

21

11