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SV Data Types 2 State

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0% found this document useful (0 votes)
21 views2 pages

SV Data Types 2 State

Uploaded by

sadgunanissy662
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Day 3/75 VLSI SYSTEM VERILOG By: Abhishek Sorte

2 State Datatype:

- System Verilog introduces with two state datatypes i.e., these datatypes have only 2
states ‘0’ and ‘1’.
- It we try to drive x (unknown) and z (high impedance) to variables of 2 state
datatype; it will treat it as ‘0’.
- 2 state datatypes helps us to improve simulation performance

What is the need of 2 state datatypes?

- For lot of verification testbench applications unknown (x) and high impedance (z)
values are not necessary, so if we take 4 state data type for such applications, the it
will be more computation time and more memory requirement. That’s why 2 state
datatypes are used.
- For RTL point of view 4 state datatypes are used but for simulation point of view we
do not need unknown (x) or high impedance (z) states as we never drive these values
to DUT.

Two state datatypes are:

NAME DEFAULT SIZE TYPE


bit 1 bit unsigned
byte 8 bits signed
shortint 16 bits signed
int 32 bits signed
longint 64 bits signed

Difference between int and integer datatype.

Integer:

- It is 4 state datatype.
- It supports 4 values 0, 1, x, z.
- Mostly preferred for RTL and TB both

Int:

- It is 2 state datatype.
- It supports only 2 values 0 and 1.
- Mostly preferred for TB only

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Day 3/75 VLSI SYSTEM VERILOG By: Abhishek Sorte

Difference between bit [7:0] and byte.

Both bit [7:0] and byte are of 8 bits each but as we have seen in above table bit is unsigned
data type and byte is signed one.

As bit is unsigned data type it will only hold the positive range of values i.e. bit [7:0] will be
holding the value range from 0 to 255.

Unlikely byte us a signed data type and it can hold the positive as well as negative values too
so byte will be holding the value range from -128 to +127.

Questions from Day 2 post:

1. What is single driven and multi driven?

Ans:

Single-Driven: This term could potentially refer to a system or process that is primarily
influenced or directed by a single factor or driving force. In the context of technology or
mechanics, it might imply a mechanism where a single input or source is responsible for
initiating or controlling the system.

Multi-Driven: Conversely, "multi-driven" could suggest a system that is influenced or


propelled by multiple factors or driving forces. In various contexts, this might be used to
describe a complex system where several inputs or sources contribute to its behavior or
functioning.

2. What is the difference between reg, wire, and logic?

Ans:

- Wire datatype can only be driven in “assign” statement.


- Reg datatype con only be driven in “procedural block”.
- Logic can be driven in both procedural and continuous assignment.

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