Unit 4:
Digital Signal Processor and Development Tools
A Typical DSP Architecture
PM DM
PM Address Address Address DM Address
Program
Memory Generator Generator Data
(PM) Memory
(DM)
Instruc- Program Sequencer
tions & Instruction Cache Data
secondary PM Data DM Data
only
data
Registers DMA Bus
I/O
Multiplier Controller
(DMA)
ALU
Shifter
Input/Output
DMA (Direct Memory Access): Allows bulk data transfer between I/O
and memory without CPU intervention after granted by CPU.
Microcontroller vs. DSP
• Microcontroller • DSP
– Modified Harvard Architecture
– Mostly Harvard Architecture
– VLIW/SIMD (parallel execution
– Single execution unit units)
– Flexible bit-level operations – No bit level operations
– No hardware MACs – Hardware MACs
– Integer operations – Real operations using fixed or
floating point
– Control, Data – Control, Data Communication,
Communication and Networking, Signal Processing
Networking applications applications
A Simplified view of Typical MAC unit
in DSP
n n
A Register B Register
Multiplier
n
n
2n
C Register
Types of multipliers used:
2n 1. Array multipliers
Adder 2. Multipliers based on
2n
2n
modified Booth’s algorithm
D Register
(Accumulator)
2n
An M th order FIR filter implementation
M 1
y ( n) h( k ) x ( n k )
k 0
DAGEN
h[0]
DAGEN
A X[n] B
h[1] X[n-1]
h[2] X[n-2]
MAC
•• ••
•• ••
•• ••
h[M-1] X[n-M+1]
y[n]
Coefficients: Input samples (frame):
Data/Prog. Memory A Data Memory B
Instruction Level Parallelism: Pipelining
• Each instruction execution is split up into a sequence of steps –
different steps can be executed concurrently by different
circuitry.
• Processor speed can be enhanced by having separate hardware
units for the different functional blocks, with buffers between
the successive units.
– The number of unit operations into which the instruction cycle of a
processor can be divided for this purpose defines the number of stages in
the pipeline.
– A processor having an n-stage pipeline would have up to n instructions
simultaneously being processed by the different functional units of the
processor.
• Effective processor speed increases ideally by a factor equal to
the number of pipelining stages.
• In DSP with Harvard architecture, where data and instructions lie
in separate memory spaces, promotes pipelining.
• DSP algorithms are often repetitive but highly structured, making
them well suited to multilevel pipelining.
Example: A Four-stage Pipeline
Data Dependency in Pipelining
If the input data for an instruction depends on the
outcome of the previous instruction, the Write cycle of
the previous instruction has to be over before the
Operate cycle of the next instruction can start. The
pipeline effectively idles through one instruction,
creating a bubble in the pipeline which persists for
several instructions.
F1 D1 O1 W1
F2 D2 idle O2 W2
F3 idle D3 O3 W3
Bubble
ends
here
F4 D4 O4 W4
A 3 + A; B 4 x A Solution:
Can’t perform these two in parallel Compiler Optimization
Circular Buffer Addressing
• After accessing the last co-efficient, h(M-1), the co-
efficient pointer has to wrap around to h(0) for the
next input sample.
• The content of the co-efficient data memory A is static,
but the input sample data memory B changes when
each new input sample arrives.
• Let M=8.
• The input sample x(n-7) is the oldest and it should be
discarded when new sample arrives. To maintain the
same order of storage in memory; all the previous
samples have to shift (move) by one position in
memory and the new sample is stored at first location
in memory. This type of implementation is called linear
buffer based implementation.
Location0 Memory
x(n) Pointer New Sample
Memory Pointer
1 x(n-1)
2 x(n-2)
3 x(n-3)
4 x(n-4)
5 x(n-5)
6 x(n-6)
7 x(n-7)
Discarded
(Oldest
sample)
• To avoid the data shifting while new sample comes, the DSP processor
provides circular buffer addressing in which memory is configured as
circular buffer instead of linear buffer.
• A circular buffer is same as a linear buffer if we consider the two ends of
the linear buffer to be adjacent as shown in figure.
• In the circular buffer, the memory pointer points to the memory location
of the newest input sample, x(n) and previous input samples x(n-1),x(n-
2),--------,x(n-7) are stored in successive locations.
• At each sampling instant, the FIR loop is executed and MAC operation is
performed as in linear buffer case.
• The only difference is that the data samples are not shifted after loop
computation, but the pointer is located at x(n-7), the oldest data sample,
which is overwritten by new incoming sample
Oldest
sample
5 6
5 6 Memory
x(n-5) x(n-6) Pointer
4 7 4 7
Oldest
x(n-4) x(n-7) sample New sample
3 0
Memory 3 0
x(n-3) x(n)
Pointer
2 x(n-2) x(n-1) 1
2 1
COMMONLY USED DSP CHIPS
• Texas Instruments(TI): TMS 320 family
• Analog Devices: ADSP 2100 family, Blackfin family,
SHARC(Super Harvard Architecture Computer) family,
TigerSHARC family
• Motorola: DSP 56000 family
• Lucent Technology: DSP 1600 and 16000 family
• LSI Logic: ZSP 400 family etc.
• The Texas Instruments TMS320 family is most popular
from understanding and application points of view.
TMS320 DSP FAMILIES FROM TI
• TSM320C2000 family - High Performance 16/32-bit Controllers: Digital
Signal Controllers (DSC) Sophisticated Microcontrollers
• Industrial
– Automation and Control
– Drives
• Automotive
– Electronic power steering
– Integrated starter alternator
– Brush less motors and pumps
• Appliances/Heavy Electrical Goods
– Water Pumps
– HVAC Drive motors
– Drive motors
• Others
– Hand-held power tools
– Power Supplies
– Intelligent sensors
• TMS320C5000 family - Power-Efficient DSPs
• 1. Telecommunications:
• Cellular telephones
• Digital switching systems
• Networking devices and modems
• Personal communication systems
• Voice over internet protocol(VOIP)
• 2. Audio processing:
• Surround sound processing
• Graphic equalizers
• Echo cancellations
• Digital hearing aids
• 3. Consumer:
• Digital answering machines
• Digital audio players/MP3 players
• TMS320C6000 family - High Performance DSPs:
• The C6000 DSP platform offers the industry’s highest performance fixed-
and floating-point DSPs ideal for video, imaging, broadband infrastructure
and performance audio applications.
• In this category, C62x and C64X devices are fixed-point,C67x devices are
floating-point DSPs.
• Their architecture is based on VLIW (very long instruction word) standard.
• The major applications are :
1. Graphics and Image processing: 2. Voice/speech processing:
• Digital cameras • Speech enhancement
• Computer vision • Speech synthesis
• Pattern recognition • Speech recognition
• Image compression, enhancement • Voice coders (Vocoders)
and restoration • Text to speech
• Watermarking • Speaker verification
• 3D Graphics 3. Military:
• Medical imaging • Radar and Sonar signal processing
• Navigational aids
• Missile guidance
Example: DSP in Audio
Player/Recorder System
Example: DSP in PC sound card: Audio
Signal Processor
Development Tools:
• Design, Simulation and Prototyping:
MATLAB/SIMULIK, toolboxes, Embedded targets
from Mathworks Inc.
Scilab Open source
• Processor Specific IDE (Integrated Development
Environment): Compiler, Assembler, Debugger,
Simulator, Programmer: Code Composer Studio
(CCS) for TI DSPs
• Hardware Debugger: Emulator
• Hardware Trainer kits (By Spectrum Digital for TI
DSPs)
• Troubleshooting: DSO, Arbitrary Waveform
Generator, Pattern Generator, Spectrum Analyser,
Logic Analyser, Signature Analyser etc.
DSP Application Development Tool
•
Example: EPB_C6748
Designed and Developed by Edutech Learning Solutions Pvt. Ltd.,
Vadodara
• EPB_C6748: Educational Practice Board based on TI DSP chip:
TMS320C6748.
• TMS320C6748 fixed- and floating-point DSP is a low-power
applications processor based on a C674x DSP core - member of the
TMS320C6000™ platform of DSPs.
• C674x DSP core uses a 2-level cache-based architecture.
• The level 1 program cache (L1P) is a 32-KB direct mapped cache, and
the level 1 data cache (L1D) is a 32-KB 2-way, set-associative cache.
• The level 2 program cache (L2P) consists of a 256-KB memory space
that is shared between program and data space. L2 memory can be
configured as mapped memory, cache, or combinations of the two.
TMS320C6748 Block diagram
DSP Code Building Process:
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