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Midterm Exam 2022.2 Course: Ee2130E - Digital System Design Date: 17 / 05 / 2023 Duration: 60 Min

The document is a midterm exam for a digital systems design course. It contains 3 problems: 1) converting decimal numbers to binary and performing binary addition, 2) determining logic levels in a circuit with switches, and 3) designing a combinational logic circuit to control an LED based on a 4-bit input.

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120 views2 pages

Midterm Exam 2022.2 Course: Ee2130E - Digital System Design Date: 17 / 05 / 2023 Duration: 60 Min

The document is a midterm exam for a digital systems design course. It contains 3 problems: 1) converting decimal numbers to binary and performing binary addition, 2) determining logic levels in a circuit with switches, and 3) designing a combinational logic circuit to control an LED based on a 4-bit input.

Uploaded by

Lại Quốc Đạt
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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HANOI UNIVERSITY OF SCIENCE AND TECHNOLOGY MIDTERM EXAM 2022.

2
SCHOOL OF ELECTRONIC & ELECTRICAL Course: EE2130E – DIGITAL SYSTEM DESIGN
ENGINEERING Date: 17 / 05 / 2023
Duration: 60 min
No.: 01 Total page: 2 Allowed to use documents. Submit the exam paper
together with your work.
Signa Teacher(s): Responsible teacher of teaching group:
ture

Note: 1 point is given for presentation


Problem 1 (2 points)
1) Convert decimal number (123) to 8-bits unsigned binary number (0.5 pts)
2) Convert decimal number (-123) to 8-bits signed binary number using 2’s complement (0.5 pts)
3) Two 8-bits binary numbers: (1 pts)
A = 1101 1010 and B = 0111 0011
- Perform the sum of A and B, the result is saved in 8-bit binary number. If A and B are
unsigned binary numbers, is the sum of them overflow? Why?
- Perform the sum of A and B, the result is saved in 8-bit binary number. If A and B are
signed binary numbers (using 2’s complement), is the sum of them overflow? Why?
Problem 2 (3 points)
Knowing the circuit as Figure with Vdd = 5V. All logic gates have these parameters:
VIH Input voltage High level 2V
VIL Input voltage Low level 0.8V
VOH Output voltage High level 2.5V
VOL Output voltage Low level 0.5V
tPLH Propagation delay of the output from 3ns
Low to High level
tPHL Propagation delay of the output from 5ns
High to Low level

(Input and output currents of logic gates are neglected)

1) Determine the output logic Y in the two cases: (2 pts)


a. SWA close, SWB close, SWC open.
b. SWA open, SWB open, SWC close.
2) Determine the propagation of the circuit in the case SWB is open (fixed status), A and C
change corresponding with the status of SWA and SWC (1 pts)

1
Problem 3 (4 pts):
Given the combinational logic circuit as shown in the figure with the following operation:
- It has 4-bit binary number input, in which: A(MSB), D (LSB)
- It has one output Q that controls LED D2
- LED D2 is OFF only when the decimal value of binary input is more than 6. In other
cases, LED D2 is ON
- Supposing that all logic components of this logic circuit are of normal TTL
technology
1) Establish a truth table describing the combinational logic circuit (1pts)
2) Find the logic expression of output Q as the following expression cases:
- Sum of minterms (0.5 pts)
- Product of maxterms (0.5 pts)
3) Design the above combinational logic circuit using AND gates, OR gates, NOT gates (if
necessary) (1pts)
4) Design the above combinational logic circuit using only 2-input NAND gates (1pts)

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